2 * Copyright 2013 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
29 #define SMU__NUM_SCLK_DPM_STATE 8
30 #define SMU__NUM_MCLK_DPM_LEVELS 6
31 #define SMU__NUM_LCLK_DPM_LEVELS 8
32 #define SMU__NUM_PCIE_DPM_LEVELS 8
33 #include "smu7_discrete.h"
35 #define CISLANDS_MAX_HARDWARE_POWERLEVELS 2
37 #define CISLANDS_UNUSED_GPIO_PIN 0x7F
42 enum radeon_pcie_gen pcie_gen
;
47 u16 performance_level_count
;
50 struct ci_pl performance_levels
[CISLANDS_MAX_HARDWARE_POWERLEVELS
];
59 #define CISLAND_MAX_DEEPSLEEP_DIVIDER_ID 5
60 #define MAX_REGULAR_DPM_NUMBER 8
61 #define CISLAND_MINIMUM_ENGINE_CLOCK 800
63 struct ci_single_dpm_table
{
65 struct ci_dpm_level dpm_levels
[MAX_REGULAR_DPM_NUMBER
];
69 struct ci_single_dpm_table sclk_table
;
70 struct ci_single_dpm_table mclk_table
;
71 struct ci_single_dpm_table pcie_speed_table
;
72 struct ci_single_dpm_table vddc_table
;
73 struct ci_single_dpm_table vddci_table
;
74 struct ci_single_dpm_table mvdd_table
;
77 struct ci_mc_reg_entry
{
79 u32 mc_data
[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE
];
82 struct ci_mc_reg_table
{
86 struct ci_mc_reg_entry mc_reg_table_entry
[MAX_AC_TIMING_ENTRIES
];
87 SMU7_Discrete_MCRegisterAddress mc_reg_address
[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE
];
94 u32 volt_change_delay
;
98 #define CISLANDS_MAX_LEAKAGE_COUNT 8
100 struct ci_leakage_voltage
{
102 u16 leakage_id
[CISLANDS_MAX_LEAKAGE_COUNT
];
103 u16 actual_voltage
[CISLANDS_MAX_LEAKAGE_COUNT
];
106 struct ci_dpm_level_enable_mask
{
107 u32 uvd_dpm_enable_mask
;
108 u32 vce_dpm_enable_mask
;
109 u32 acp_dpm_enable_mask
;
110 u32 samu_dpm_enable_mask
;
111 u32 sclk_dpm_enable_mask
;
112 u32 mclk_dpm_enable_mask
;
113 u32 pcie_dpm_enable_mask
;
116 struct ci_vbios_boot_state
118 u16 mvdd_bootup_value
;
119 u16 vddc_bootup_value
;
120 u16 vddci_bootup_value
;
121 u32 sclk_bootup_value
;
122 u32 mclk_bootup_value
;
123 u16 pcie_gen_bootup_value
;
124 u16 pcie_lane_bootup_value
;
127 struct ci_clock_registers
{
128 u32 cg_spll_func_cntl
;
129 u32 cg_spll_func_cntl_2
;
130 u32 cg_spll_func_cntl_3
;
131 u32 cg_spll_func_cntl_4
;
132 u32 cg_spll_spread_spectrum
;
133 u32 cg_spll_spread_spectrum_2
;
135 u32 mclk_pwrmgt_cntl
;
136 u32 mpll_ad_func_cntl
;
137 u32 mpll_dq_func_cntl
;
139 u32 mpll_func_cntl_1
;
140 u32 mpll_func_cntl_2
;
145 struct ci_thermal_temperature_setting
{
147 s32 temperature_high
;
148 s32 temperature_shutdown
;
151 struct ci_pcie_perf_range
{
156 enum ci_pt_config_reg_type
{
157 CISLANDS_CONFIGREG_MMR
= 0,
158 CISLANDS_CONFIGREG_SMC_IND
,
159 CISLANDS_CONFIGREG_DIDT_IND
,
160 CISLANDS_CONFIGREG_CACHE
,
161 CISLANDS_CONFIGREG_MAX
164 #define POWERCONTAINMENT_FEATURE_BAPM 0x00000001
165 #define POWERCONTAINMENT_FEATURE_TDCLimit 0x00000002
166 #define POWERCONTAINMENT_FEATURE_PkgPwrLimit 0x00000004
168 struct ci_pt_config_reg
{
173 enum ci_pt_config_reg_type type
;
176 struct ci_pt_defaults
{
178 u8 svi_load_line_vddc
;
179 u8 tdc_vddc_throttle_release_limit_perc
;
181 u8 tdc_waterfall_ctl
;
182 u8 dte_ambient_temp_base
;
184 u32 bapm_temp_gradient
;
185 u16 bapmti_r
[SMU7_DTE_ITERATIONS
* SMU7_DTE_SOURCES
* SMU7_DTE_SINKS
];
186 u16 bapmti_rc
[SMU7_DTE_ITERATIONS
* SMU7_DTE_SOURCES
* SMU7_DTE_SINKS
];
189 #define DPMTABLE_OD_UPDATE_SCLK 0x00000001
190 #define DPMTABLE_OD_UPDATE_MCLK 0x00000002
191 #define DPMTABLE_UPDATE_SCLK 0x00000004
192 #define DPMTABLE_UPDATE_MCLK 0x00000008
194 struct ci_power_info
{
195 struct ci_dpm_table dpm_table
;
199 u32 active_auto_throttle_sources
;
200 struct ci_clock_registers clock_registers
;
203 enum radeon_pcie_gen force_pcie_gen
;
204 enum radeon_pcie_gen acpi_pcie_gen
;
205 struct ci_leakage_voltage vddc_leakage
;
206 struct ci_leakage_voltage vddci_leakage
;
207 u16 max_vddc_in_pp_table
;
208 u16 min_vddc_in_pp_table
;
209 u16 max_vddci_in_pp_table
;
210 u16 min_vddci_in_pp_table
;
211 u32 mclk_strobe_mode_threshold
;
212 u32 mclk_stutter_mode_threshold
;
213 u32 mclk_edc_enable_threshold
;
214 u32 mclk_edc_wr_enable_threshold
;
215 struct ci_vbios_boot_state vbios_boot_state
;
220 u32 mc_reg_table_start
;
224 SMU7_Discrete_DpmTable smc_state_table
;
225 SMU7_Discrete_MCRegisters smc_mc_reg_table
;
226 SMU7_Discrete_PmFuses smc_powertune_table
;
228 struct ci_mc_reg_table mc_reg_table
;
229 struct atom_voltage_table vddc_voltage_table
;
230 struct atom_voltage_table vddci_voltage_table
;
231 struct atom_voltage_table mvdd_voltage_table
;
232 struct ci_ulv_parm ulv
;
233 u32 power_containment_features
;
234 const struct ci_pt_defaults
*powertune_defaults
;
236 bool vddc_phase_shed_control
;
237 struct ci_thermal_temperature_setting thermal_temp_setting
;
238 struct ci_dpm_level_enable_mask dpm_level_enable_mask
;
239 u32 need_update_smu7_dpm_table
;
240 u32 sclk_dpm_key_disabled
;
241 u32 mclk_dpm_key_disabled
;
242 u32 pcie_dpm_key_disabled
;
243 u32 thermal_sclk_dpm_enabled
;
244 struct ci_pcie_perf_range pcie_gen_performance
;
245 struct ci_pcie_perf_range pcie_lane_performance
;
246 struct ci_pcie_perf_range pcie_gen_powersaving
;
247 struct ci_pcie_perf_range pcie_lane_powersaving
;
248 u32 activity_target
[SMU7_MAX_LEVELS_GRAPHICS
];
249 u32 mclk_activity_target
;
250 u32 low_sclk_interrupt_t
;
251 u32 last_mclk_dpm_enable_mask
;
254 bool caps_power_containment
;
256 bool caps_sq_ramping
;
257 bool caps_db_ramping
;
258 bool caps_td_ramping
;
259 bool caps_tcp_ramping
;
262 bool caps_sclk_ss_support
;
263 bool caps_mclk_ss_support
;
268 bool caps_automatic_dc_transition
;
269 bool caps_sclk_throttle_low_notification
;
270 bool caps_dynamic_ac_timing
;
271 bool caps_od_fuzzy_fan_control_support
;
273 bool thermal_protection
;
274 bool pcie_performance_request
;
280 bool pspp_notify_required
;
282 bool enable_bapm_feature
;
283 bool enable_tdc_limit_feature
;
284 bool enable_pkg_pwr_tracking_feature
;
285 bool use_pcie_performance_levels
;
286 bool use_pcie_powersaving_levels
;
287 bool uvd_power_gated
;
289 struct radeon_ps current_rps
;
290 struct ci_ps current_ps
;
291 struct radeon_ps requested_rps
;
292 struct ci_ps requested_ps
;
294 bool fan_ctrl_is_in_default_mode
;
295 bool fan_is_controlled_by_smc
;
297 u32 fan_ctrl_default_mode
;
300 #define CISLANDS_VOLTAGE_CONTROL_NONE 0x0
301 #define CISLANDS_VOLTAGE_CONTROL_BY_GPIO 0x1
302 #define CISLANDS_VOLTAGE_CONTROL_BY_SVID2 0x2
304 #define CISLANDS_Q88_FORMAT_CONVERSION_UNIT 256
306 #define CISLANDS_VRC_DFLT0 0x3FFFC000
307 #define CISLANDS_VRC_DFLT1 0x000400
308 #define CISLANDS_VRC_DFLT2 0xC00080
309 #define CISLANDS_VRC_DFLT3 0xC00200
310 #define CISLANDS_VRC_DFLT4 0xC01680
311 #define CISLANDS_VRC_DFLT5 0xC00033
312 #define CISLANDS_VRC_DFLT6 0xC00033
313 #define CISLANDS_VRC_DFLT7 0x3FFFC000
315 #define CISLANDS_CGULVPARAMETER_DFLT 0x00040035
316 #define CISLAND_TARGETACTIVITY_DFLT 30
317 #define CISLAND_MCLK_TARGETACTIVITY_DFLT 10
319 #define PCIE_PERF_REQ_REMOVE_REGISTRY 0
320 #define PCIE_PERF_REQ_FORCE_LOWPOWER 1
321 #define PCIE_PERF_REQ_PECI_GEN1 2
322 #define PCIE_PERF_REQ_PECI_GEN2 3
323 #define PCIE_PERF_REQ_PECI_GEN3 4
325 int ci_copy_bytes_to_smc(struct radeon_device
*rdev
,
326 u32 smc_start_address
,
327 const u8
*src
, u32 byte_count
, u32 limit
);
328 void ci_start_smc(struct radeon_device
*rdev
);
329 void ci_reset_smc(struct radeon_device
*rdev
);
330 int ci_program_jump_on_start(struct radeon_device
*rdev
);
331 void ci_stop_smc_clock(struct radeon_device
*rdev
);
332 void ci_start_smc_clock(struct radeon_device
*rdev
);
333 bool ci_is_smc_running(struct radeon_device
*rdev
);
334 PPSMC_Result
ci_wait_for_smc_inactive(struct radeon_device
*rdev
);
335 int ci_load_smc_ucode(struct radeon_device
*rdev
, u32 limit
);
336 int ci_read_smc_sram_dword(struct radeon_device
*rdev
,
337 u32 smc_address
, u32
*value
, u32 limit
);
338 int ci_write_smc_sram_dword(struct radeon_device
*rdev
,
339 u32 smc_address
, u32 value
, u32 limit
);