?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
treewide: remove redundant IS_ERR() before error code check
[linux/fpc-iii.git] / drivers / gpu / drm / radeon / r600_cs.c
blob49e8266461f85222fc0550c60547127e0fe38fbd
1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28 #include <linux/kernel.h>
29
30 #include "radeon.h"
31 #include "radeon_asic.h"
32 #include "r600d.h"
33 #include "r600_reg_safe.h"
34
35 static int r600_nomm;
36 extern void r600_cs_legacy_get_tiling_conf(struct drm_device *dev, u32 *npipes, u32 *nbanks, u32 *group_size);
37
38
39 struct r600_cs_track {
40 /* configuration we miror so that we use same code btw kms/ums */
41 u32 group_size;
42 u32 nbanks;
43 u32 npipes;
44 /* value we track */
45 u32 sq_config;
46 u32 log_nsamples;
47 u32 nsamples;
48 u32 cb_color_base_last[8];
49 struct radeon_bo *cb_color_bo[8];
50 u64 cb_color_bo_mc[8];
51 u64 cb_color_bo_offset[8];
52 struct radeon_bo *cb_color_frag_bo[8];
53 u64 cb_color_frag_offset[8];
54 struct radeon_bo *cb_color_tile_bo[8];
55 u64 cb_color_tile_offset[8];
56 u32 cb_color_mask[8];
57 u32 cb_color_info[8];
58 u32 cb_color_view[8];
59 u32 cb_color_size_idx[8]; /* unused */
60 u32 cb_target_mask;
61 u32 cb_shader_mask; /* unused */
62 bool is_resolve;
63 u32 cb_color_size[8];
64 u32 vgt_strmout_en;
65 u32 vgt_strmout_buffer_en;
66 struct radeon_bo *vgt_strmout_bo[4];
67 u64 vgt_strmout_bo_mc[4]; /* unused */
68 u32 vgt_strmout_bo_offset[4];
69 u32 vgt_strmout_size[4];
70 u32 db_depth_control;
71 u32 db_depth_info;
72 u32 db_depth_size_idx;
73 u32 db_depth_view;
74 u32 db_depth_size;
75 u32 db_offset;
76 struct radeon_bo *db_bo;
77 u64 db_bo_mc;
78 bool sx_misc_kill_all_prims;
79 bool cb_dirty;
80 bool db_dirty;
81 bool streamout_dirty;
82 struct radeon_bo *htile_bo;
83 u64 htile_offset;
84 u32 htile_surface;
85 };
86
87 #define FMT_8_BIT(fmt, vc) [fmt] = { 1, 1, 1, vc, CHIP_R600 }
88 #define FMT_16_BIT(fmt, vc) [fmt] = { 1, 1, 2, vc, CHIP_R600 }
89 #define FMT_24_BIT(fmt) [fmt] = { 1, 1, 4, 0, CHIP_R600 }
90 #define FMT_32_BIT(fmt, vc) [fmt] = { 1, 1, 4, vc, CHIP_R600 }
91 #define FMT_48_BIT(fmt) [fmt] = { 1, 1, 8, 0, CHIP_R600 }
92 #define FMT_64_BIT(fmt, vc) [fmt] = { 1, 1, 8, vc, CHIP_R600 }
93 #define FMT_96_BIT(fmt) [fmt] = { 1, 1, 12, 0, CHIP_R600 }
94 #define FMT_128_BIT(fmt, vc) [fmt] = { 1, 1, 16,vc, CHIP_R600 }
95
96 struct gpu_formats {
97 unsigned blockwidth;
98 unsigned blockheight;
99 unsigned blocksize;
100 unsigned valid_color;
101 enum radeon_family min_family;
102 };
103
104 static const struct gpu_formats color_formats_table[] = {
105 /* 8 bit */
106 FMT_8_BIT(V_038004_COLOR_8, 1),
107 FMT_8_BIT(V_038004_COLOR_4_4, 1),
108 FMT_8_BIT(V_038004_COLOR_3_3_2, 1),
109 FMT_8_BIT(V_038004_FMT_1, 0),
110
111 /* 16-bit */
112 FMT_16_BIT(V_038004_COLOR_16, 1),
113 FMT_16_BIT(V_038004_COLOR_16_FLOAT, 1),
114 FMT_16_BIT(V_038004_COLOR_8_8, 1),
115 FMT_16_BIT(V_038004_COLOR_5_6_5, 1),
116 FMT_16_BIT(V_038004_COLOR_6_5_5, 1),
117 FMT_16_BIT(V_038004_COLOR_1_5_5_5, 1),
118 FMT_16_BIT(V_038004_COLOR_4_4_4_4, 1),
119 FMT_16_BIT(V_038004_COLOR_5_5_5_1, 1),
120
121 /* 24-bit */
122 FMT_24_BIT(V_038004_FMT_8_8_8),
123
124 /* 32-bit */
125 FMT_32_BIT(V_038004_COLOR_32, 1),
126 FMT_32_BIT(V_038004_COLOR_32_FLOAT, 1),
127 FMT_32_BIT(V_038004_COLOR_16_16, 1),
128 FMT_32_BIT(V_038004_COLOR_16_16_FLOAT, 1),
129 FMT_32_BIT(V_038004_COLOR_8_24, 1),
130 FMT_32_BIT(V_038004_COLOR_8_24_FLOAT, 1),
131 FMT_32_BIT(V_038004_COLOR_24_8, 1),
132 FMT_32_BIT(V_038004_COLOR_24_8_FLOAT, 1),
133 FMT_32_BIT(V_038004_COLOR_10_11_11, 1),
134 FMT_32_BIT(V_038004_COLOR_10_11_11_FLOAT, 1),
135 FMT_32_BIT(V_038004_COLOR_11_11_10, 1),
136 FMT_32_BIT(V_038004_COLOR_11_11_10_FLOAT, 1),
137 FMT_32_BIT(V_038004_COLOR_2_10_10_10, 1),
138 FMT_32_BIT(V_038004_COLOR_8_8_8_8, 1),
139 FMT_32_BIT(V_038004_COLOR_10_10_10_2, 1),
140 FMT_32_BIT(V_038004_FMT_5_9_9_9_SHAREDEXP, 0),
141 FMT_32_BIT(V_038004_FMT_32_AS_8, 0),
142 FMT_32_BIT(V_038004_FMT_32_AS_8_8, 0),
143
144 /* 48-bit */
145 FMT_48_BIT(V_038004_FMT_16_16_16),
146 FMT_48_BIT(V_038004_FMT_16_16_16_FLOAT),
147
148 /* 64-bit */
149 FMT_64_BIT(V_038004_COLOR_X24_8_32_FLOAT, 1),
150 FMT_64_BIT(V_038004_COLOR_32_32, 1),
151 FMT_64_BIT(V_038004_COLOR_32_32_FLOAT, 1),
152 FMT_64_BIT(V_038004_COLOR_16_16_16_16, 1),
153 FMT_64_BIT(V_038004_COLOR_16_16_16_16_FLOAT, 1),
154
155 FMT_96_BIT(V_038004_FMT_32_32_32),
156 FMT_96_BIT(V_038004_FMT_32_32_32_FLOAT),
157
158 /* 128-bit */
159 FMT_128_BIT(V_038004_COLOR_32_32_32_32, 1),
160 FMT_128_BIT(V_038004_COLOR_32_32_32_32_FLOAT, 1),
161
162 [V_038004_FMT_GB_GR] = { 2, 1, 4, 0 },
163 [V_038004_FMT_BG_RG] = { 2, 1, 4, 0 },
164
165 /* block compressed formats */
166 [V_038004_FMT_BC1] = { 4, 4, 8, 0 },
167 [V_038004_FMT_BC2] = { 4, 4, 16, 0 },
168 [V_038004_FMT_BC3] = { 4, 4, 16, 0 },
169 [V_038004_FMT_BC4] = { 4, 4, 8, 0 },
170 [V_038004_FMT_BC5] = { 4, 4, 16, 0},
171 [V_038004_FMT_BC6] = { 4, 4, 16, 0, CHIP_CEDAR}, /* Evergreen-only */
172 [V_038004_FMT_BC7] = { 4, 4, 16, 0, CHIP_CEDAR}, /* Evergreen-only */
173
174 /* The other Evergreen formats */
175 [V_038004_FMT_32_AS_32_32_32_32] = { 1, 1, 4, 0, CHIP_CEDAR},
176 };
177
178 bool r600_fmt_is_valid_color(u32 format)
179 {
180 if (format >= ARRAY_SIZE(color_formats_table))
181 return false;
182
183 if (color_formats_table[format].valid_color)
184 return true;
185
186 return false;
187 }
188
189 bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family)
190 {
191 if (format >= ARRAY_SIZE(color_formats_table))
192 return false;
193
194 if (family < color_formats_table[format].min_family)
195 return false;
196
197 if (color_formats_table[format].blockwidth > 0)
198 return true;
199
200 return false;
201 }
202
203 int r600_fmt_get_blocksize(u32 format)
204 {
205 if (format >= ARRAY_SIZE(color_formats_table))
206 return 0;
207
208 return color_formats_table[format].blocksize;
209 }
210
211 int r600_fmt_get_nblocksx(u32 format, u32 w)
212 {
213 unsigned bw;
214
215 if (format >= ARRAY_SIZE(color_formats_table))
216 return 0;
217
218 bw = color_formats_table[format].blockwidth;
219 if (bw == 0)
220 return 0;
221
222 return (w + bw - 1) / bw;
223 }
224
225 int r600_fmt_get_nblocksy(u32 format, u32 h)
226 {
227 unsigned bh;
228
229 if (format >= ARRAY_SIZE(color_formats_table))
230 return 0;
231
232 bh = color_formats_table[format].blockheight;
233 if (bh == 0)
234 return 0;
235
236 return (h + bh - 1) / bh;
237 }
238
239 struct array_mode_checker {
240 int array_mode;
241 u32 group_size;
242 u32 nbanks;
243 u32 npipes;
244 u32 nsamples;
245 u32 blocksize;
246 };
247
248 /* returns alignment in pixels for pitch/height/depth and bytes for base */
249 static int r600_get_array_mode_alignment(struct array_mode_checker *values,
250 u32 *pitch_align,
251 u32 *height_align,
252 u32 *depth_align,
253 u64 *base_align)
254 {
255 u32 tile_width = 8;
256 u32 tile_height = 8;
257 u32 macro_tile_width = values->nbanks;
258 u32 macro_tile_height = values->npipes;
259 u32 tile_bytes = tile_width * tile_height * values->blocksize * values->nsamples;
260 u32 macro_tile_bytes = macro_tile_width * macro_tile_height * tile_bytes;
261
262 switch (values->array_mode) {
263 case ARRAY_LINEAR_GENERAL:
264 /* technically tile_width/_height for pitch/height */
265 *pitch_align = 1; /* tile_width */
266 *height_align = 1; /* tile_height */
267 *depth_align = 1;
268 *base_align = 1;
269 break;
270 case ARRAY_LINEAR_ALIGNED:
271 *pitch_align = max((u32)64, (u32)(values->group_size / values->blocksize));
272 *height_align = 1;
273 *depth_align = 1;
274 *base_align = values->group_size;
275 break;
276 case ARRAY_1D_TILED_THIN1:
277 *pitch_align = max((u32)tile_width,
278 (u32)(values->group_size /
279 (tile_height * values->blocksize * values->nsamples)));
280 *height_align = tile_height;
281 *depth_align = 1;
282 *base_align = values->group_size;
283 break;
284 case ARRAY_2D_TILED_THIN1:
285 *pitch_align = max((u32)macro_tile_width * tile_width,
286 (u32)((values->group_size * values->nbanks) /
287 (values->blocksize * values->nsamples * tile_width)));
288 *height_align = macro_tile_height * tile_height;
289 *depth_align = 1;
290 *base_align = max(macro_tile_bytes,
291 (*pitch_align) * values->blocksize * (*height_align) * values->nsamples);
292 break;
293 default:
294 return -EINVAL;
295 }
296
297 return 0;
298 }
299
300 static void r600_cs_track_init(struct r600_cs_track *track)
301 {
302 int i;
303
304 /* assume DX9 mode */
305 track->sq_config = DX9_CONSTS;
306 for (i = 0; i < 8; i++) {
307 track->cb_color_base_last[i] = 0;
308 track->cb_color_size[i] = 0;
309 track->cb_color_size_idx[i] = 0;
310 track->cb_color_info[i] = 0;
311 track->cb_color_view[i] = 0xFFFFFFFF;
312 track->cb_color_bo[i] = NULL;
313 track->cb_color_bo_offset[i] = 0xFFFFFFFF;
314 track->cb_color_bo_mc[i] = 0xFFFFFFFF;
315 track->cb_color_frag_bo[i] = NULL;
316 track->cb_color_frag_offset[i] = 0xFFFFFFFF;
317 track->cb_color_tile_bo[i] = NULL;
318 track->cb_color_tile_offset[i] = 0xFFFFFFFF;
319 track->cb_color_mask[i] = 0xFFFFFFFF;
320 }
321 track->is_resolve = false;
322 track->nsamples = 16;
323 track->log_nsamples = 4;
324 track->cb_target_mask = 0xFFFFFFFF;
325 track->cb_shader_mask = 0xFFFFFFFF;
326 track->cb_dirty = true;
327 track->db_bo = NULL;
328 track->db_bo_mc = 0xFFFFFFFF;
329 /* assume the biggest format and that htile is enabled */
330 track->db_depth_info = 7 | (1 << 25);
331 track->db_depth_view = 0xFFFFC000;
332 track->db_depth_size = 0xFFFFFFFF;
333 track->db_depth_size_idx = 0;
334 track->db_depth_control = 0xFFFFFFFF;
335 track->db_dirty = true;
336 track->htile_bo = NULL;
337 track->htile_offset = 0xFFFFFFFF;
338 track->htile_surface = 0;
339
340 for (i = 0; i < 4; i++) {
341 track->vgt_strmout_size[i] = 0;
342 track->vgt_strmout_bo[i] = NULL;
343 track->vgt_strmout_bo_offset[i] = 0xFFFFFFFF;
344 track->vgt_strmout_bo_mc[i] = 0xFFFFFFFF;
345 }
346 track->streamout_dirty = true;
347 track->sx_misc_kill_all_prims = false;
348 }
349
350 static int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i)
351 {
352 struct r600_cs_track *track = p->track;
353 u32 slice_tile_max, tmp;
354 u32 height, height_align, pitch, pitch_align, depth_align;
355 u64 base_offset, base_align;
356 struct array_mode_checker array_check;
357 volatile u32 *ib = p->ib.ptr;
358 unsigned array_mode;
359 u32 format;
360 /* When resolve is used, the second colorbuffer has always 1 sample. */
361 unsigned nsamples = track->is_resolve && i == 1 ? 1 : track->nsamples;
362
363 format = G_0280A0_FORMAT(track->cb_color_info[i]);
364 if (!r600_fmt_is_valid_color(format)) {
365 dev_warn(p->dev, "%s:%d cb invalid format %d for %d (0x%08X)\n",
366 __func__, __LINE__, format,
367 i, track->cb_color_info[i]);
368 return -EINVAL;
369 }
370 /* pitch in pixels */
371 pitch = (G_028060_PITCH_TILE_MAX(track->cb_color_size[i]) + 1) * 8;
372 slice_tile_max = G_028060_SLICE_TILE_MAX(track->cb_color_size[i]) + 1;
373 slice_tile_max *= 64;
374 height = slice_tile_max / pitch;
375 if (height > 8192)
376 height = 8192;
377 array_mode = G_0280A0_ARRAY_MODE(track->cb_color_info[i]);
378
379 base_offset = track->cb_color_bo_mc[i] + track->cb_color_bo_offset[i];
380 array_check.array_mode = array_mode;
381 array_check.group_size = track->group_size;
382 array_check.nbanks = track->nbanks;
383 array_check.npipes = track->npipes;
384 array_check.nsamples = nsamples;
385 array_check.blocksize = r600_fmt_get_blocksize(format);
386 if (r600_get_array_mode_alignment(&array_check,
387 &pitch_align, &height_align, &depth_align, &base_align)) {
388 dev_warn(p->dev, "%s invalid tiling %d for %d (0x%08X)\n", __func__,
389 G_0280A0_ARRAY_MODE(track->cb_color_info[i]), i,
390 track->cb_color_info[i]);
391 return -EINVAL;
392 }
393 switch (array_mode) {
394 case V_0280A0_ARRAY_LINEAR_GENERAL:
395 break;
396 case V_0280A0_ARRAY_LINEAR_ALIGNED:
397 break;
398 case V_0280A0_ARRAY_1D_TILED_THIN1:
399 /* avoid breaking userspace */
400 if (height > 7)
401 height &= ~0x7;
402 break;
403 case V_0280A0_ARRAY_2D_TILED_THIN1:
404 break;
405 default:
406 dev_warn(p->dev, "%s invalid tiling %d for %d (0x%08X)\n", __func__,
407 G_0280A0_ARRAY_MODE(track->cb_color_info[i]), i,
408 track->cb_color_info[i]);
409 return -EINVAL;
410 }
411
412 if (!IS_ALIGNED(pitch, pitch_align)) {
413 dev_warn(p->dev, "%s:%d cb pitch (%d, 0x%x, %d) invalid\n",
414 __func__, __LINE__, pitch, pitch_align, array_mode);
415 return -EINVAL;
416 }
417 if (!IS_ALIGNED(height, height_align)) {
418 dev_warn(p->dev, "%s:%d cb height (%d, 0x%x, %d) invalid\n",
419 __func__, __LINE__, height, height_align, array_mode);
420 return -EINVAL;
421 }
422 if (!IS_ALIGNED(base_offset, base_align)) {
423 dev_warn(p->dev, "%s offset[%d] 0x%llx 0x%llx, %d not aligned\n", __func__, i,
424 base_offset, base_align, array_mode);
425 return -EINVAL;
426 }
427
428 /* check offset */
429 tmp = r600_fmt_get_nblocksy(format, height) * r600_fmt_get_nblocksx(format, pitch) *
430 r600_fmt_get_blocksize(format) * nsamples;
431 switch (array_mode) {
432 default:
433 case V_0280A0_ARRAY_LINEAR_GENERAL:
434 case V_0280A0_ARRAY_LINEAR_ALIGNED:
435 tmp += track->cb_color_view[i] & 0xFF;
436 break;
437 case V_0280A0_ARRAY_1D_TILED_THIN1:
438 case V_0280A0_ARRAY_2D_TILED_THIN1:
439 tmp += G_028080_SLICE_MAX(track->cb_color_view[i]) * tmp;
440 break;
441 }
442 if ((tmp + track->cb_color_bo_offset[i]) > radeon_bo_size(track->cb_color_bo[i])) {
443 if (array_mode == V_0280A0_ARRAY_LINEAR_GENERAL) {
444 /* the initial DDX does bad things with the CB size occasionally */
445 /* it rounds up height too far for slice tile max but the BO is smaller */
446 /* r600c,g also seem to flush at bad times in some apps resulting in
447 * bogus values here. So for linear just allow anything to avoid breaking
448 * broken userspace.
449 */
450 } else {
451 dev_warn(p->dev, "%s offset[%d] %d %llu %d %lu too big (%d %d) (%d %d %d)\n",
452 __func__, i, array_mode,
453 track->cb_color_bo_offset[i], tmp,
454 radeon_bo_size(track->cb_color_bo[i]),
455 pitch, height, r600_fmt_get_nblocksx(format, pitch),
456 r600_fmt_get_nblocksy(format, height),
457 r600_fmt_get_blocksize(format));
458 return -EINVAL;
459 }
460 }
461 /* limit max tile */
462 tmp = (height * pitch) >> 6;
463 if (tmp < slice_tile_max)
464 slice_tile_max = tmp;
465 tmp = S_028060_PITCH_TILE_MAX((pitch / 8) - 1) |
466 S_028060_SLICE_TILE_MAX(slice_tile_max - 1);
467 ib[track->cb_color_size_idx[i]] = tmp;
468
469 /* FMASK/CMASK */
470 switch (G_0280A0_TILE_MODE(track->cb_color_info[i])) {
471 case V_0280A0_TILE_DISABLE:
472 break;
473 case V_0280A0_FRAG_ENABLE:
474 if (track->nsamples > 1) {
475 uint32_t tile_max = G_028100_FMASK_TILE_MAX(track->cb_color_mask[i]);
476 /* the tile size is 8x8, but the size is in units of bits.
477 * for bytes, do just * 8. */
478 uint32_t bytes = track->nsamples * track->log_nsamples * 8 * (tile_max + 1);
479
480 if (bytes + track->cb_color_frag_offset[i] >
481 radeon_bo_size(track->cb_color_frag_bo[i])) {
482 dev_warn(p->dev, "%s FMASK_TILE_MAX too large "
483 "(tile_max=%u, bytes=%u, offset=%llu, bo_size=%lu)\n",
484 __func__, tile_max, bytes,
485 track->cb_color_frag_offset[i],
486 radeon_bo_size(track->cb_color_frag_bo[i]));
487 return -EINVAL;
488 }
489 }
490 /* fall through */
491 case V_0280A0_CLEAR_ENABLE:
492 {
493 uint32_t block_max = G_028100_CMASK_BLOCK_MAX(track->cb_color_mask[i]);
494 /* One block = 128x128 pixels, one 8x8 tile has 4 bits..
495 * (128*128) / (8*8) / 2 = 128 bytes per block. */
496 uint32_t bytes = (block_max + 1) * 128;
497
498 if (bytes + track->cb_color_tile_offset[i] >
499 radeon_bo_size(track->cb_color_tile_bo[i])) {
500 dev_warn(p->dev, "%s CMASK_BLOCK_MAX too large "
501 "(block_max=%u, bytes=%u, offset=%llu, bo_size=%lu)\n",
502 __func__, block_max, bytes,
503 track->cb_color_tile_offset[i],
504 radeon_bo_size(track->cb_color_tile_bo[i]));
505 return -EINVAL;
506 }
507 break;
508 }
509 default:
510 dev_warn(p->dev, "%s invalid tile mode\n", __func__);
511 return -EINVAL;
512 }
513 return 0;
514 }
515
516 static int r600_cs_track_validate_db(struct radeon_cs_parser *p)
517 {
518 struct r600_cs_track *track = p->track;
519 u32 nviews, bpe, ntiles, slice_tile_max, tmp;
520 u32 height_align, pitch_align, depth_align;
521 u32 pitch = 8192;
522 u32 height = 8192;
523 u64 base_offset, base_align;
524 struct array_mode_checker array_check;
525 int array_mode;
526 volatile u32 *ib = p->ib.ptr;
527
528
529 if (track->db_bo == NULL) {
530 dev_warn(p->dev, "z/stencil with no depth buffer\n");
531 return -EINVAL;
532 }
533 switch (G_028010_FORMAT(track->db_depth_info)) {
534 case V_028010_DEPTH_16:
535 bpe = 2;
536 break;
537 case V_028010_DEPTH_X8_24:
538 case V_028010_DEPTH_8_24:
539 case V_028010_DEPTH_X8_24_FLOAT:
540 case V_028010_DEPTH_8_24_FLOAT:
541 case V_028010_DEPTH_32_FLOAT:
542 bpe = 4;
543 break;
544 case V_028010_DEPTH_X24_8_32_FLOAT:
545 bpe = 8;
546 break;
547 default:
548 dev_warn(p->dev, "z/stencil with invalid format %d\n", G_028010_FORMAT(track->db_depth_info));
549 return -EINVAL;
550 }
551 if ((track->db_depth_size & 0xFFFFFC00) == 0xFFFFFC00) {
552 if (!track->db_depth_size_idx) {
553 dev_warn(p->dev, "z/stencil buffer size not set\n");
554 return -EINVAL;
555 }
556 tmp = radeon_bo_size(track->db_bo) - track->db_offset;
557 tmp = (tmp / bpe) >> 6;
558 if (!tmp) {
559 dev_warn(p->dev, "z/stencil buffer too small (0x%08X %d %d %ld)\n",
560 track->db_depth_size, bpe, track->db_offset,
561 radeon_bo_size(track->db_bo));
562 return -EINVAL;
563 }
564 ib[track->db_depth_size_idx] = S_028000_SLICE_TILE_MAX(tmp - 1) | (track->db_depth_size & 0x3FF);
565 } else {
566 /* pitch in pixels */
567 pitch = (G_028000_PITCH_TILE_MAX(track->db_depth_size) + 1) * 8;
568 slice_tile_max = G_028000_SLICE_TILE_MAX(track->db_depth_size) + 1;
569 slice_tile_max *= 64;
570 height = slice_tile_max / pitch;
571 if (height > 8192)
572 height = 8192;
573 base_offset = track->db_bo_mc + track->db_offset;
574 array_mode = G_028010_ARRAY_MODE(track->db_depth_info);
575 array_check.array_mode = array_mode;
576 array_check.group_size = track->group_size;
577 array_check.nbanks = track->nbanks;
578 array_check.npipes = track->npipes;
579 array_check.nsamples = track->nsamples;
580 array_check.blocksize = bpe;
581 if (r600_get_array_mode_alignment(&array_check,
582 &pitch_align, &height_align, &depth_align, &base_align)) {
583 dev_warn(p->dev, "%s invalid tiling %d (0x%08X)\n", __func__,
584 G_028010_ARRAY_MODE(track->db_depth_info),
585 track->db_depth_info);
586 return -EINVAL;
587 }
588 switch (array_mode) {
589 case V_028010_ARRAY_1D_TILED_THIN1:
590 /* don't break userspace */
591 height &= ~0x7;
592 break;
593 case V_028010_ARRAY_2D_TILED_THIN1:
594 break;
595 default:
596 dev_warn(p->dev, "%s invalid tiling %d (0x%08X)\n", __func__,
597 G_028010_ARRAY_MODE(track->db_depth_info),
598 track->db_depth_info);
599 return -EINVAL;
600 }
601
602 if (!IS_ALIGNED(pitch, pitch_align)) {
603 dev_warn(p->dev, "%s:%d db pitch (%d, 0x%x, %d) invalid\n",
604 __func__, __LINE__, pitch, pitch_align, array_mode);
605 return -EINVAL;
606 }
607 if (!IS_ALIGNED(height, height_align)) {
608 dev_warn(p->dev, "%s:%d db height (%d, 0x%x, %d) invalid\n",
609 __func__, __LINE__, height, height_align, array_mode);
610 return -EINVAL;
611 }
612 if (!IS_ALIGNED(base_offset, base_align)) {
613 dev_warn(p->dev, "%s offset 0x%llx, 0x%llx, %d not aligned\n", __func__,
614 base_offset, base_align, array_mode);
615 return -EINVAL;
616 }
617
618 ntiles = G_028000_SLICE_TILE_MAX(track->db_depth_size) + 1;
619 nviews = G_028004_SLICE_MAX(track->db_depth_view) + 1;
620 tmp = ntiles * bpe * 64 * nviews * track->nsamples;
621 if ((tmp + track->db_offset) > radeon_bo_size(track->db_bo)) {
622 dev_warn(p->dev, "z/stencil buffer (%d) too small (0x%08X %d %d %d -> %u have %lu)\n",
623 array_mode,
624 track->db_depth_size, ntiles, nviews, bpe, tmp + track->db_offset,
625 radeon_bo_size(track->db_bo));
626 return -EINVAL;
627 }
628 }
629
630 /* hyperz */
631 if (G_028010_TILE_SURFACE_ENABLE(track->db_depth_info)) {
632 unsigned long size;
633 unsigned nbx, nby;
634
635 if (track->htile_bo == NULL) {
636 dev_warn(p->dev, "%s:%d htile enabled without htile surface 0x%08x\n",
637 __func__, __LINE__, track->db_depth_info);
638 return -EINVAL;
639 }
640 if ((track->db_depth_size & 0xFFFFFC00) == 0xFFFFFC00) {
641 dev_warn(p->dev, "%s:%d htile can't be enabled with bogus db_depth_size 0x%08x\n",
642 __func__, __LINE__, track->db_depth_size);
643 return -EINVAL;
644 }
645
646 nbx = pitch;
647 nby = height;
648 if (G_028D24_LINEAR(track->htile_surface)) {
649 /* nbx must be 16 htiles aligned == 16 * 8 pixel aligned */
650 nbx = round_up(nbx, 16 * 8);
651 /* nby is npipes htiles aligned == npipes * 8 pixel aligned */
652 nby = round_up(nby, track->npipes * 8);
653 } else {
654 /* always assume 8x8 htile */
655 /* align is htile align * 8, htile align vary according to
656 * number of pipe and tile width and nby
657 */
658 switch (track->npipes) {
659 case 8:
660 /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/
661 nbx = round_up(nbx, 64 * 8);
662 nby = round_up(nby, 64 * 8);
663 break;
664 case 4:
665 /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/
666 nbx = round_up(nbx, 64 * 8);
667 nby = round_up(nby, 32 * 8);
668 break;
669 case 2:
670 /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/
671 nbx = round_up(nbx, 32 * 8);
672 nby = round_up(nby, 32 * 8);
673 break;
674 case 1:
675 /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/
676 nbx = round_up(nbx, 32 * 8);
677 nby = round_up(nby, 16 * 8);
678 break;
679 default:
680 dev_warn(p->dev, "%s:%d invalid num pipes %d\n",
681 __func__, __LINE__, track->npipes);
682 return -EINVAL;
683 }
684 }
685 /* compute number of htile */
686 nbx = nbx >> 3;
687 nby = nby >> 3;
688 /* size must be aligned on npipes * 2K boundary */
689 size = roundup(nbx * nby * 4, track->npipes * (2 << 10));
690 size += track->htile_offset;
691
692 if (size > radeon_bo_size(track->htile_bo)) {
693 dev_warn(p->dev, "%s:%d htile surface too small %ld for %ld (%d %d)\n",
694 __func__, __LINE__, radeon_bo_size(track->htile_bo),
695 size, nbx, nby);
696 return -EINVAL;
697 }
698 }
699
700 track->db_dirty = false;
701 return 0;
702 }
703
704 static int r600_cs_track_check(struct radeon_cs_parser *p)
705 {
706 struct r600_cs_track *track = p->track;
707 u32 tmp;
708 int r, i;
709
710 /* on legacy kernel we don't perform advanced check */
711 if (p->rdev == NULL)
712 return 0;
713
714 /* check streamout */
715 if (track->streamout_dirty && track->vgt_strmout_en) {
716 for (i = 0; i < 4; i++) {
717 if (track->vgt_strmout_buffer_en & (1 << i)) {
718 if (track->vgt_strmout_bo[i]) {
719 u64 offset = (u64)track->vgt_strmout_bo_offset[i] +
720 (u64)track->vgt_strmout_size[i];
721 if (offset > radeon_bo_size(track->vgt_strmout_bo[i])) {
722 DRM_ERROR("streamout %d bo too small: 0x%llx, 0x%lx\n",
723 i, offset,
724 radeon_bo_size(track->vgt_strmout_bo[i]));
725 return -EINVAL;
726 }
727 } else {
728 dev_warn(p->dev, "No buffer for streamout %d\n", i);
729 return -EINVAL;
730 }
731 }
732 }
733 track->streamout_dirty = false;
734 }
735
736 if (track->sx_misc_kill_all_prims)
737 return 0;
738
739 /* check that we have a cb for each enabled target, we don't check
740 * shader_mask because it seems mesa isn't always setting it :(
741 */
742 if (track->cb_dirty) {
743 tmp = track->cb_target_mask;
744
745 /* We must check both colorbuffers for RESOLVE. */
746 if (track->is_resolve) {
747 tmp |= 0xff;
748 }
749
750 for (i = 0; i < 8; i++) {
751 u32 format = G_0280A0_FORMAT(track->cb_color_info[i]);
752
753 if (format != V_0280A0_COLOR_INVALID &&
754 (tmp >> (i * 4)) & 0xF) {
755 /* at least one component is enabled */
756 if (track->cb_color_bo[i] == NULL) {
757 dev_warn(p->dev, "%s:%d mask 0x%08X | 0x%08X no cb for %d\n",
758 __func__, __LINE__, track->cb_target_mask, track->cb_shader_mask, i);
759 return -EINVAL;
760 }
761 /* perform rewrite of CB_COLOR[0-7]_SIZE */
762 r = r600_cs_track_validate_cb(p, i);
763 if (r)
764 return r;
765 }
766 }
767 track->cb_dirty = false;
768 }
769
770 /* Check depth buffer */
771 if (track->db_dirty &&
772 G_028010_FORMAT(track->db_depth_info) != V_028010_DEPTH_INVALID &&
773 (G_028800_STENCIL_ENABLE(track->db_depth_control) ||
774 G_028800_Z_ENABLE(track->db_depth_control))) {
775 r = r600_cs_track_validate_db(p);
776 if (r)
777 return r;
778 }
779
780 return 0;
781 }
782
783 /**
784 * r600_cs_packet_parse_vline() - parse userspace VLINE packet
785 * @parser: parser structure holding parsing context.
786 *
787 * This is an R600-specific function for parsing VLINE packets.
788 * Real work is done by r600_cs_common_vline_parse function.
789 * Here we just set up ASIC-specific register table and call
790 * the common implementation function.
791 */
792 static int r600_cs_packet_parse_vline(struct radeon_cs_parser *p)
793 {
794 static uint32_t vline_start_end[2] = {AVIVO_D1MODE_VLINE_START_END,
795 AVIVO_D2MODE_VLINE_START_END};
796 static uint32_t vline_status[2] = {AVIVO_D1MODE_VLINE_STATUS,
797 AVIVO_D2MODE_VLINE_STATUS};
798
799 return r600_cs_common_vline_parse(p, vline_start_end, vline_status);
800 }
801
802 /**
803 * r600_cs_common_vline_parse() - common vline parser
804 * @parser: parser structure holding parsing context.
805 * @vline_start_end: table of vline_start_end registers
806 * @vline_status: table of vline_status registers
807 *
808 * Userspace sends a special sequence for VLINE waits.
809 * PACKET0 - VLINE_START_END + value
810 * PACKET3 - WAIT_REG_MEM poll vline status reg
811 * RELOC (P3) - crtc_id in reloc.
812 *
813 * This function parses this and relocates the VLINE START END
814 * and WAIT_REG_MEM packets to the correct crtc.
815 * It also detects a switched off crtc and nulls out the
816 * wait in that case. This function is common for all ASICs that
817 * are R600 and newer. The parsing algorithm is the same, and only
818 * differs in which registers are used.
819 *
820 * Caller is the ASIC-specific function which passes the parser
821 * context and ASIC-specific register table
822 */
823 int r600_cs_common_vline_parse(struct radeon_cs_parser *p,
824 uint32_t *vline_start_end,
825 uint32_t *vline_status)
826 {
827 struct drm_crtc *crtc;
828 struct radeon_crtc *radeon_crtc;
829 struct radeon_cs_packet p3reloc, wait_reg_mem;
830 int crtc_id;
831 int r;
832 uint32_t header, h_idx, reg, wait_reg_mem_info;
833 volatile uint32_t *ib;
834
835 ib = p->ib.ptr;
836
837 /* parse the WAIT_REG_MEM */
838 r = radeon_cs_packet_parse(p, &wait_reg_mem, p->idx);
839 if (r)
840 return r;
841
842 /* check its a WAIT_REG_MEM */
843 if (wait_reg_mem.type != RADEON_PACKET_TYPE3 ||
844 wait_reg_mem.opcode != PACKET3_WAIT_REG_MEM) {
845 DRM_ERROR("vline wait missing WAIT_REG_MEM segment\n");
846 return -EINVAL;
847 }
848
849 wait_reg_mem_info = radeon_get_ib_value(p, wait_reg_mem.idx + 1);
850 /* bit 4 is reg (0) or mem (1) */
851 if (wait_reg_mem_info & 0x10) {
852 DRM_ERROR("vline WAIT_REG_MEM waiting on MEM instead of REG\n");
853 return -EINVAL;
854 }
855 /* bit 8 is me (0) or pfp (1) */
856 if (wait_reg_mem_info & 0x100) {
857 DRM_ERROR("vline WAIT_REG_MEM waiting on PFP instead of ME\n");
858 return -EINVAL;
859 }
860 /* waiting for value to be equal */
861 if ((wait_reg_mem_info & 0x7) != 0x3) {
862 DRM_ERROR("vline WAIT_REG_MEM function not equal\n");
863 return -EINVAL;
864 }
865 if ((radeon_get_ib_value(p, wait_reg_mem.idx + 2) << 2) != vline_status[0]) {
866 DRM_ERROR("vline WAIT_REG_MEM bad reg\n");
867 return -EINVAL;
868 }
869
870 if (radeon_get_ib_value(p, wait_reg_mem.idx + 5) != RADEON_VLINE_STAT) {
871 DRM_ERROR("vline WAIT_REG_MEM bad bit mask\n");
872 return -EINVAL;
873 }
874
875 /* jump over the NOP */
876 r = radeon_cs_packet_parse(p, &p3reloc, p->idx + wait_reg_mem.count + 2);
877 if (r)
878 return r;
879
880 h_idx = p->idx - 2;
881 p->idx += wait_reg_mem.count + 2;
882 p->idx += p3reloc.count + 2;
883
884 header = radeon_get_ib_value(p, h_idx);
885 crtc_id = radeon_get_ib_value(p, h_idx + 2 + 7 + 1);
886 reg = R600_CP_PACKET0_GET_REG(header);
887
888 crtc = drm_crtc_find(p->rdev->ddev, p->filp, crtc_id);
889 if (!crtc) {
890 DRM_ERROR("cannot find crtc %d\n", crtc_id);
891 return -ENOENT;
892 }
893 radeon_crtc = to_radeon_crtc(crtc);
894 crtc_id = radeon_crtc->crtc_id;
895
896 if (!crtc->enabled) {
897 /* CRTC isn't enabled - we need to nop out the WAIT_REG_MEM */
898 ib[h_idx + 2] = PACKET2(0);
899 ib[h_idx + 3] = PACKET2(0);
900 ib[h_idx + 4] = PACKET2(0);
901 ib[h_idx + 5] = PACKET2(0);
902 ib[h_idx + 6] = PACKET2(0);
903 ib[h_idx + 7] = PACKET2(0);
904 ib[h_idx + 8] = PACKET2(0);
905 } else if (reg == vline_start_end[0]) {
906 header &= ~R600_CP_PACKET0_REG_MASK;
907 header |= vline_start_end[crtc_id] >> 2;
908 ib[h_idx] = header;
909 ib[h_idx + 4] = vline_status[crtc_id] >> 2;
910 } else {
911 DRM_ERROR("unknown crtc reloc\n");
912 return -EINVAL;
913 }
914 return 0;
915 }
916
917 static int r600_packet0_check(struct radeon_cs_parser *p,
918 struct radeon_cs_packet *pkt,
919 unsigned idx, unsigned reg)
920 {
921 int r;
922
923 switch (reg) {
924 case AVIVO_D1MODE_VLINE_START_END:
925 r = r600_cs_packet_parse_vline(p);
926 if (r) {
927 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
928 idx, reg);
929 return r;
930 }
931 break;
932 default:
933 pr_err("Forbidden register 0x%04X in cs at %d\n", reg, idx);
934 return -EINVAL;
935 }
936 return 0;
937 }
938
939 static int r600_cs_parse_packet0(struct radeon_cs_parser *p,
940 struct radeon_cs_packet *pkt)
941 {
942 unsigned reg, i;
943 unsigned idx;
944 int r;
945
946 idx = pkt->idx + 1;
947 reg = pkt->reg;
948 for (i = 0; i <= pkt->count; i++, idx++, reg += 4) {
949 r = r600_packet0_check(p, pkt, idx, reg);
950 if (r) {
951 return r;
952 }
953 }
954 return 0;
955 }
956
957 /**
958 * r600_cs_check_reg() - check if register is authorized or not
959 * @parser: parser structure holding parsing context
960 * @reg: register we are testing
961 * @idx: index into the cs buffer
962 *
963 * This function will test against r600_reg_safe_bm and return 0
964 * if register is safe. If register is not flag as safe this function
965 * will test it against a list of register needind special handling.
966 */
967 static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
968 {
969 struct r600_cs_track *track = (struct r600_cs_track *)p->track;
970 struct radeon_bo_list *reloc;
971 u32 m, i, tmp, *ib;
972 int r;
973
974 i = (reg >> 7);
975 if (i >= ARRAY_SIZE(r600_reg_safe_bm)) {
976 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
977 return -EINVAL;
978 }
979 m = 1 << ((reg >> 2) & 31);
980 if (!(r600_reg_safe_bm[i] & m))
981 return 0;
982 ib = p->ib.ptr;
983 switch (reg) {
984 /* force following reg to 0 in an attempt to disable out buffer
985 * which will need us to better understand how it works to perform
986 * security check on it (Jerome)
987 */
988 case R_0288A8_SQ_ESGS_RING_ITEMSIZE:
989 case R_008C44_SQ_ESGS_RING_SIZE:
990 case R_0288B0_SQ_ESTMP_RING_ITEMSIZE:
991 case R_008C54_SQ_ESTMP_RING_SIZE:
992 case R_0288C0_SQ_FBUF_RING_ITEMSIZE:
993 case R_008C74_SQ_FBUF_RING_SIZE:
994 case R_0288B4_SQ_GSTMP_RING_ITEMSIZE:
995 case R_008C5C_SQ_GSTMP_RING_SIZE:
996 case R_0288AC_SQ_GSVS_RING_ITEMSIZE:
997 case R_008C4C_SQ_GSVS_RING_SIZE:
998 case R_0288BC_SQ_PSTMP_RING_ITEMSIZE:
999 case R_008C6C_SQ_PSTMP_RING_SIZE:
1000 case R_0288C4_SQ_REDUC_RING_ITEMSIZE:
1001 case R_008C7C_SQ_REDUC_RING_SIZE:
1002 case R_0288B8_SQ_VSTMP_RING_ITEMSIZE:
1003 case R_008C64_SQ_VSTMP_RING_SIZE:
1004 case R_0288C8_SQ_GS_VERT_ITEMSIZE:
1005 /* get value to populate the IB don't remove */
1006 /*tmp =radeon_get_ib_value(p, idx);
1007 ib[idx] = 0;*/
1008 break;
1009 case SQ_ESGS_RING_BASE:
1010 case SQ_GSVS_RING_BASE:
1011 case SQ_ESTMP_RING_BASE:
1012 case SQ_GSTMP_RING_BASE:
1013 case SQ_PSTMP_RING_BASE:
1014 case SQ_VSTMP_RING_BASE:
1015 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1016 if (r) {
1017 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1018 "0x%04X\n", reg);
1019 return -EINVAL;
1020 }
1021 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
1022 break;
1023 case SQ_CONFIG:
1024 track->sq_config = radeon_get_ib_value(p, idx);
1025 break;
1026 case R_028800_DB_DEPTH_CONTROL:
1027 track->db_depth_control = radeon_get_ib_value(p, idx);
1028 track->db_dirty = true;
1029 break;
1030 case R_028010_DB_DEPTH_INFO:
1031 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS) &&
1032 radeon_cs_packet_next_is_pkt3_nop(p)) {
1033 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
1034 if (r) {
1035 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1036 "0x%04X\n", reg);
1037 return -EINVAL;
1038 }
1039 track->db_depth_info = radeon_get_ib_value(p, idx);
1040 ib[idx] &= C_028010_ARRAY_MODE;
1041 track->db_depth_info &= C_028010_ARRAY_MODE;
1042 if (reloc->tiling_flags & RADEON_TILING_MACRO) {
1043 ib[idx] |= S_028010_ARRAY_MODE(V_028010_ARRAY_2D_TILED_THIN1);
1044 track->db_depth_info |= S_028010_ARRAY_MODE(V_028010_ARRAY_2D_TILED_THIN1);
1045 } else {
1046 ib[idx] |= S_028010_ARRAY_MODE(V_028010_ARRAY_1D_TILED_THIN1);
1047 track->db_depth_info |= S_028010_ARRAY_MODE(V_028010_ARRAY_1D_TILED_THIN1);
1048 }
1049 } else {
1050 track->db_depth_info = radeon_get_ib_value(p, idx);
1051 }
1052 track->db_dirty = true;
1053 break;
1054 case R_028004_DB_DEPTH_VIEW:
1055 track->db_depth_view = radeon_get_ib_value(p, idx);
1056 track->db_dirty = true;
1057 break;
1058 case R_028000_DB_DEPTH_SIZE:
1059 track->db_depth_size = radeon_get_ib_value(p, idx);
1060 track->db_depth_size_idx = idx;
1061 track->db_dirty = true;
1062 break;
1063 case R_028AB0_VGT_STRMOUT_EN:
1064 track->vgt_strmout_en = radeon_get_ib_value(p, idx);
1065 track->streamout_dirty = true;
1066 break;
1067 case R_028B20_VGT_STRMOUT_BUFFER_EN:
1068 track->vgt_strmout_buffer_en = radeon_get_ib_value(p, idx);
1069 track->streamout_dirty = true;
1070 break;
1071 case VGT_STRMOUT_BUFFER_BASE_0:
1072 case VGT_STRMOUT_BUFFER_BASE_1:
1073 case VGT_STRMOUT_BUFFER_BASE_2:
1074 case VGT_STRMOUT_BUFFER_BASE_3:
1075 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
1076 if (r) {
1077 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1078 "0x%04X\n", reg);
1079 return -EINVAL;
1080 }
1081 tmp = (reg - VGT_STRMOUT_BUFFER_BASE_0) / 16;
1082 track->vgt_strmout_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8;
1083 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
1084 track->vgt_strmout_bo[tmp] = reloc->robj;
1085 track->vgt_strmout_bo_mc[tmp] = reloc->gpu_offset;
1086 track->streamout_dirty = true;
1087 break;
1088 case VGT_STRMOUT_BUFFER_SIZE_0:
1089 case VGT_STRMOUT_BUFFER_SIZE_1:
1090 case VGT_STRMOUT_BUFFER_SIZE_2:
1091 case VGT_STRMOUT_BUFFER_SIZE_3:
1092 tmp = (reg - VGT_STRMOUT_BUFFER_SIZE_0) / 16;
1093 /* size in register is DWs, convert to bytes */
1094 track->vgt_strmout_size[tmp] = radeon_get_ib_value(p, idx) * 4;
1095 track->streamout_dirty = true;
1096 break;
1097 case CP_COHER_BASE:
1098 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
1099 if (r) {
1100 dev_warn(p->dev, "missing reloc for CP_COHER_BASE "
1101 "0x%04X\n", reg);
1102 return -EINVAL;
1103 }
1104 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
1105 break;
1106 case R_028238_CB_TARGET_MASK:
1107 track->cb_target_mask = radeon_get_ib_value(p, idx);
1108 track->cb_dirty = true;
1109 break;
1110 case R_02823C_CB_SHADER_MASK:
1111 track->cb_shader_mask = radeon_get_ib_value(p, idx);
1112 break;
1113 case R_028C04_PA_SC_AA_CONFIG:
1114 tmp = G_028C04_MSAA_NUM_SAMPLES(radeon_get_ib_value(p, idx));
1115 track->log_nsamples = tmp;
1116 track->nsamples = 1 << tmp;
1117 track->cb_dirty = true;
1118 break;
1119 case R_028808_CB_COLOR_CONTROL:
1120 tmp = G_028808_SPECIAL_OP(radeon_get_ib_value(p, idx));
1121 track->is_resolve = tmp == V_028808_SPECIAL_RESOLVE_BOX;
1122 track->cb_dirty = true;
1123 break;
1124 case R_0280A0_CB_COLOR0_INFO:
1125 case R_0280A4_CB_COLOR1_INFO:
1126 case R_0280A8_CB_COLOR2_INFO:
1127 case R_0280AC_CB_COLOR3_INFO:
1128 case R_0280B0_CB_COLOR4_INFO:
1129 case R_0280B4_CB_COLOR5_INFO:
1130 case R_0280B8_CB_COLOR6_INFO:
1131 case R_0280BC_CB_COLOR7_INFO:
1132 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS) &&
1133 radeon_cs_packet_next_is_pkt3_nop(p)) {
1134 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
1135 if (r) {
1136 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
1137 return -EINVAL;
1138 }
1139 tmp = (reg - R_0280A0_CB_COLOR0_INFO) / 4;
1140 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);
1141 if (reloc->tiling_flags & RADEON_TILING_MACRO) {
1142 ib[idx] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_2D_TILED_THIN1);
1143 track->cb_color_info[tmp] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_2D_TILED_THIN1);
1144 } else if (reloc->tiling_flags & RADEON_TILING_MICRO) {
1145 ib[idx] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_1D_TILED_THIN1);
1146 track->cb_color_info[tmp] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_1D_TILED_THIN1);
1147 }
1148 } else {
1149 tmp = (reg - R_0280A0_CB_COLOR0_INFO) / 4;
1150 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);
1151 }
1152 track->cb_dirty = true;
1153 break;
1154 case R_028080_CB_COLOR0_VIEW:
1155 case R_028084_CB_COLOR1_VIEW:
1156 case R_028088_CB_COLOR2_VIEW:
1157 case R_02808C_CB_COLOR3_VIEW:
1158 case R_028090_CB_COLOR4_VIEW:
1159 case R_028094_CB_COLOR5_VIEW:
1160 case R_028098_CB_COLOR6_VIEW:
1161 case R_02809C_CB_COLOR7_VIEW:
1162 tmp = (reg - R_028080_CB_COLOR0_VIEW) / 4;
1163 track->cb_color_view[tmp] = radeon_get_ib_value(p, idx);
1164 track->cb_dirty = true;
1165 break;
1166 case R_028060_CB_COLOR0_SIZE:
1167 case R_028064_CB_COLOR1_SIZE:
1168 case R_028068_CB_COLOR2_SIZE:
1169 case R_02806C_CB_COLOR3_SIZE:
1170 case R_028070_CB_COLOR4_SIZE:
1171 case R_028074_CB_COLOR5_SIZE:
1172 case R_028078_CB_COLOR6_SIZE:
1173 case R_02807C_CB_COLOR7_SIZE:
1174 tmp = (reg - R_028060_CB_COLOR0_SIZE) / 4;
1175 track->cb_color_size[tmp] = radeon_get_ib_value(p, idx);
1176 track->cb_color_size_idx[tmp] = idx;
1177 track->cb_dirty = true;
1178 break;
1179 /* This register were added late, there is userspace
1180 * which does provide relocation for those but set
1181 * 0 offset. In order to avoid breaking old userspace
1182 * we detect this and set address to point to last
1183 * CB_COLOR0_BASE, note that if userspace doesn't set
1184 * CB_COLOR0_BASE before this register we will report
1185 * error. Old userspace always set CB_COLOR0_BASE
1186 * before any of this.
1187 */
1188 case R_0280E0_CB_COLOR0_FRAG:
1189 case R_0280E4_CB_COLOR1_FRAG:
1190 case R_0280E8_CB_COLOR2_FRAG:
1191 case R_0280EC_CB_COLOR3_FRAG:
1192 case R_0280F0_CB_COLOR4_FRAG:
1193 case R_0280F4_CB_COLOR5_FRAG:
1194 case R_0280F8_CB_COLOR6_FRAG:
1195 case R_0280FC_CB_COLOR7_FRAG:
1196 tmp = (reg - R_0280E0_CB_COLOR0_FRAG) / 4;
1197 if (!radeon_cs_packet_next_is_pkt3_nop(p)) {
1198 if (!track->cb_color_base_last[tmp]) {
1199 dev_err(p->dev, "Broken old userspace ? no cb_color0_base supplied before trying to write 0x%08X\n", reg);
1200 return -EINVAL;
1201 }
1202 track->cb_color_frag_bo[tmp] = track->cb_color_bo[tmp];
1203 track->cb_color_frag_offset[tmp] = track->cb_color_bo_offset[tmp];
1204 ib[idx] = track->cb_color_base_last[tmp];
1205 } else {
1206 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
1207 if (r) {
1208 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
1209 return -EINVAL;
1210 }
1211 track->cb_color_frag_bo[tmp] = reloc->robj;
1212 track->cb_color_frag_offset[tmp] = (u64)ib[idx] << 8;
1213 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
1214 }
1215 if (G_0280A0_TILE_MODE(track->cb_color_info[tmp])) {
1216 track->cb_dirty = true;
1217 }
1218 break;
1219 case R_0280C0_CB_COLOR0_TILE:
1220 case R_0280C4_CB_COLOR1_TILE:
1221 case R_0280C8_CB_COLOR2_TILE:
1222 case R_0280CC_CB_COLOR3_TILE:
1223 case R_0280D0_CB_COLOR4_TILE:
1224 case R_0280D4_CB_COLOR5_TILE:
1225 case R_0280D8_CB_COLOR6_TILE:
1226 case R_0280DC_CB_COLOR7_TILE:
1227 tmp = (reg - R_0280C0_CB_COLOR0_TILE) / 4;
1228 if (!radeon_cs_packet_next_is_pkt3_nop(p)) {
1229 if (!track->cb_color_base_last[tmp]) {
1230 dev_err(p->dev, "Broken old userspace ? no cb_color0_base supplied before trying to write 0x%08X\n", reg);
1231 return -EINVAL;
1232 }
1233 track->cb_color_tile_bo[tmp] = track->cb_color_bo[tmp];
1234 track->cb_color_tile_offset[tmp] = track->cb_color_bo_offset[tmp];
1235 ib[idx] = track->cb_color_base_last[tmp];
1236 } else {
1237 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
1238 if (r) {
1239 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
1240 return -EINVAL;
1241 }
1242 track->cb_color_tile_bo[tmp] = reloc->robj;
1243 track->cb_color_tile_offset[tmp] = (u64)ib[idx] << 8;
1244 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
1245 }
1246 if (G_0280A0_TILE_MODE(track->cb_color_info[tmp])) {
1247 track->cb_dirty = true;
1248 }
1249 break;
1250 case R_028100_CB_COLOR0_MASK:
1251 case R_028104_CB_COLOR1_MASK:
1252 case R_028108_CB_COLOR2_MASK:
1253 case R_02810C_CB_COLOR3_MASK:
1254 case R_028110_CB_COLOR4_MASK:
1255 case R_028114_CB_COLOR5_MASK:
1256 case R_028118_CB_COLOR6_MASK:
1257 case R_02811C_CB_COLOR7_MASK:
1258 tmp = (reg - R_028100_CB_COLOR0_MASK) / 4;
1259 track->cb_color_mask[tmp] = radeon_get_ib_value(p, idx);
1260 if (G_0280A0_TILE_MODE(track->cb_color_info[tmp])) {
1261 track->cb_dirty = true;
1262 }
1263 break;
1264 case CB_COLOR0_BASE:
1265 case CB_COLOR1_BASE:
1266 case CB_COLOR2_BASE:
1267 case CB_COLOR3_BASE:
1268 case CB_COLOR4_BASE:
1269 case CB_COLOR5_BASE:
1270 case CB_COLOR6_BASE:
1271 case CB_COLOR7_BASE:
1272 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
1273 if (r) {
1274 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1275 "0x%04X\n", reg);
1276 return -EINVAL;
1277 }
1278 tmp = (reg - CB_COLOR0_BASE) / 4;
1279 track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8;
1280 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
1281 track->cb_color_base_last[tmp] = ib[idx];
1282 track->cb_color_bo[tmp] = reloc->robj;
1283 track->cb_color_bo_mc[tmp] = reloc->gpu_offset;
1284 track->cb_dirty = true;
1285 break;
1286 case DB_DEPTH_BASE:
1287 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
1288 if (r) {
1289 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1290 "0x%04X\n", reg);
1291 return -EINVAL;
1292 }
1293 track->db_offset = radeon_get_ib_value(p, idx) << 8;
1294 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
1295 track->db_bo = reloc->robj;
1296 track->db_bo_mc = reloc->gpu_offset;
1297 track->db_dirty = true;
1298 break;
1299 case DB_HTILE_DATA_BASE:
1300 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
1301 if (r) {
1302 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1303 "0x%04X\n", reg);
1304 return -EINVAL;
1305 }
1306 track->htile_offset = radeon_get_ib_value(p, idx) << 8;
1307 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
1308 track->htile_bo = reloc->robj;
1309 track->db_dirty = true;
1310 break;
1311 case DB_HTILE_SURFACE:
1312 track->htile_surface = radeon_get_ib_value(p, idx);
1313 /* force 8x8 htile width and height */
1314 ib[idx] |= 3;
1315 track->db_dirty = true;
1316 break;
1317 case SQ_PGM_START_FS:
1318 case SQ_PGM_START_ES:
1319 case SQ_PGM_START_VS:
1320 case SQ_PGM_START_GS:
1321 case SQ_PGM_START_PS:
1322 case SQ_ALU_CONST_CACHE_GS_0:
1323 case SQ_ALU_CONST_CACHE_GS_1:
1324 case SQ_ALU_CONST_CACHE_GS_2:
1325 case SQ_ALU_CONST_CACHE_GS_3:
1326 case SQ_ALU_CONST_CACHE_GS_4:
1327 case SQ_ALU_CONST_CACHE_GS_5:
1328 case SQ_ALU_CONST_CACHE_GS_6:
1329 case SQ_ALU_CONST_CACHE_GS_7:
1330 case SQ_ALU_CONST_CACHE_GS_8:
1331 case SQ_ALU_CONST_CACHE_GS_9:
1332 case SQ_ALU_CONST_CACHE_GS_10:
1333 case SQ_ALU_CONST_CACHE_GS_11:
1334 case SQ_ALU_CONST_CACHE_GS_12:
1335 case SQ_ALU_CONST_CACHE_GS_13:
1336 case SQ_ALU_CONST_CACHE_GS_14:
1337 case SQ_ALU_CONST_CACHE_GS_15:
1338 case SQ_ALU_CONST_CACHE_PS_0:
1339 case SQ_ALU_CONST_CACHE_PS_1:
1340 case SQ_ALU_CONST_CACHE_PS_2:
1341 case SQ_ALU_CONST_CACHE_PS_3:
1342 case SQ_ALU_CONST_CACHE_PS_4:
1343 case SQ_ALU_CONST_CACHE_PS_5:
1344 case SQ_ALU_CONST_CACHE_PS_6:
1345 case SQ_ALU_CONST_CACHE_PS_7:
1346 case SQ_ALU_CONST_CACHE_PS_8:
1347 case SQ_ALU_CONST_CACHE_PS_9:
1348 case SQ_ALU_CONST_CACHE_PS_10:
1349 case SQ_ALU_CONST_CACHE_PS_11:
1350 case SQ_ALU_CONST_CACHE_PS_12:
1351 case SQ_ALU_CONST_CACHE_PS_13:
1352 case SQ_ALU_CONST_CACHE_PS_14:
1353 case SQ_ALU_CONST_CACHE_PS_15:
1354 case SQ_ALU_CONST_CACHE_VS_0:
1355 case SQ_ALU_CONST_CACHE_VS_1:
1356 case SQ_ALU_CONST_CACHE_VS_2:
1357 case SQ_ALU_CONST_CACHE_VS_3:
1358 case SQ_ALU_CONST_CACHE_VS_4:
1359 case SQ_ALU_CONST_CACHE_VS_5:
1360 case SQ_ALU_CONST_CACHE_VS_6:
1361 case SQ_ALU_CONST_CACHE_VS_7:
1362 case SQ_ALU_CONST_CACHE_VS_8:
1363 case SQ_ALU_CONST_CACHE_VS_9:
1364 case SQ_ALU_CONST_CACHE_VS_10:
1365 case SQ_ALU_CONST_CACHE_VS_11:
1366 case SQ_ALU_CONST_CACHE_VS_12:
1367 case SQ_ALU_CONST_CACHE_VS_13:
1368 case SQ_ALU_CONST_CACHE_VS_14:
1369 case SQ_ALU_CONST_CACHE_VS_15:
1370 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
1371 if (r) {
1372 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1373 "0x%04X\n", reg);
1374 return -EINVAL;
1375 }
1376 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
1377 break;
1378 case SX_MEMORY_EXPORT_BASE:
1379 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
1380 if (r) {
1381 dev_warn(p->dev, "bad SET_CONFIG_REG "
1382 "0x%04X\n", reg);
1383 return -EINVAL;
1384 }
1385 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
1386 break;
1387 case SX_MISC:
1388 track->sx_misc_kill_all_prims = (radeon_get_ib_value(p, idx) & 0x1) != 0;
1389 break;
1390 default:
1391 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
1392 return -EINVAL;
1393 }
1394 return 0;
1395 }
1396
1397 unsigned r600_mip_minify(unsigned size, unsigned level)
1398 {
1399 unsigned val;
1400
1401 val = max(1U, size >> level);
1402 if (level > 0)
1403 val = roundup_pow_of_two(val);
1404 return val;
1405 }
1406
1407 static void r600_texture_size(unsigned nfaces, unsigned blevel, unsigned llevel,
1408 unsigned w0, unsigned h0, unsigned d0, unsigned nsamples, unsigned format,
1409 unsigned block_align, unsigned height_align, unsigned base_align,
1410 unsigned *l0_size, unsigned *mipmap_size)
1411 {
1412 unsigned offset, i, level;
1413 unsigned width, height, depth, size;
1414 unsigned blocksize;
1415 unsigned nbx, nby;
1416 unsigned nlevels = llevel - blevel + 1;
1417
1418 *l0_size = -1;
1419 blocksize = r600_fmt_get_blocksize(format);
1420
1421 w0 = r600_mip_minify(w0, 0);
1422 h0 = r600_mip_minify(h0, 0);
1423 d0 = r600_mip_minify(d0, 0);
1424 for(i = 0, offset = 0, level = blevel; i < nlevels; i++, level++) {
1425 width = r600_mip_minify(w0, i);
1426 nbx = r600_fmt_get_nblocksx(format, width);
1427
1428 nbx = round_up(nbx, block_align);
1429
1430 height = r600_mip_minify(h0, i);
1431 nby = r600_fmt_get_nblocksy(format, height);
1432 nby = round_up(nby, height_align);
1433
1434 depth = r600_mip_minify(d0, i);
1435
1436 size = nbx * nby * blocksize * nsamples;
1437 if (nfaces)
1438 size *= nfaces;
1439 else
1440 size *= depth;
1441
1442 if (i == 0)
1443 *l0_size = size;
1444
1445 if (i == 0 || i == 1)
1446 offset = round_up(offset, base_align);
1447
1448 offset += size;
1449 }
1450 *mipmap_size = offset;
1451 if (llevel == 0)
1452 *mipmap_size = *l0_size;
1453 if (!blevel)
1454 *mipmap_size -= *l0_size;
1455 }
1456
1457 /**
1458 * r600_check_texture_resource() - check if register is authorized or not
1459 * @p: parser structure holding parsing context
1460 * @idx: index into the cs buffer
1461 * @texture: texture's bo structure
1462 * @mipmap: mipmap's bo structure
1463 *
1464 * This function will check that the resource has valid field and that
1465 * the texture and mipmap bo object are big enough to cover this resource.
1466 */
1467 static int r600_check_texture_resource(struct radeon_cs_parser *p, u32 idx,
1468 struct radeon_bo *texture,
1469 struct radeon_bo *mipmap,
1470 u64 base_offset,
1471 u64 mip_offset,
1472 u32 tiling_flags)
1473 {
1474 struct r600_cs_track *track = p->track;
1475 u32 dim, nfaces, llevel, blevel, w0, h0, d0;
1476 u32 word0, word1, l0_size, mipmap_size, word2, word3, word4, word5;
1477 u32 height_align, pitch, pitch_align, depth_align;
1478 u32 barray, larray;
1479 u64 base_align;
1480 struct array_mode_checker array_check;
1481 u32 format;
1482 bool is_array;
1483
1484 /* on legacy kernel we don't perform advanced check */
1485 if (p->rdev == NULL)
1486 return 0;
1487
1488 /* convert to bytes */
1489 base_offset <<= 8;
1490 mip_offset <<= 8;
1491
1492 word0 = radeon_get_ib_value(p, idx + 0);
1493 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1494 if (tiling_flags & RADEON_TILING_MACRO)
1495 word0 |= S_038000_TILE_MODE(V_038000_ARRAY_2D_TILED_THIN1);
1496 else if (tiling_flags & RADEON_TILING_MICRO)
1497 word0 |= S_038000_TILE_MODE(V_038000_ARRAY_1D_TILED_THIN1);
1498 }
1499 word1 = radeon_get_ib_value(p, idx + 1);
1500 word2 = radeon_get_ib_value(p, idx + 2) << 8;
1501 word3 = radeon_get_ib_value(p, idx + 3) << 8;
1502 word4 = radeon_get_ib_value(p, idx + 4);
1503 word5 = radeon_get_ib_value(p, idx + 5);
1504 dim = G_038000_DIM(word0);
1505 w0 = G_038000_TEX_WIDTH(word0) + 1;
1506 pitch = (G_038000_PITCH(word0) + 1) * 8;
1507 h0 = G_038004_TEX_HEIGHT(word1) + 1;
1508 d0 = G_038004_TEX_DEPTH(word1);
1509 format = G_038004_DATA_FORMAT(word1);
1510 blevel = G_038010_BASE_LEVEL(word4);
1511 llevel = G_038014_LAST_LEVEL(word5);
1512 /* pitch in texels */
1513 array_check.array_mode = G_038000_TILE_MODE(word0);
1514 array_check.group_size = track->group_size;
1515 array_check.nbanks = track->nbanks;
1516 array_check.npipes = track->npipes;
1517 array_check.nsamples = 1;
1518 array_check.blocksize = r600_fmt_get_blocksize(format);
1519 nfaces = 1;
1520 is_array = false;
1521 switch (dim) {
1522 case V_038000_SQ_TEX_DIM_1D:
1523 case V_038000_SQ_TEX_DIM_2D:
1524 case V_038000_SQ_TEX_DIM_3D:
1525 break;
1526 case V_038000_SQ_TEX_DIM_CUBEMAP:
1527 if (p->family >= CHIP_RV770)
1528 nfaces = 8;
1529 else
1530 nfaces = 6;
1531 break;
1532 case V_038000_SQ_TEX_DIM_1D_ARRAY:
1533 case V_038000_SQ_TEX_DIM_2D_ARRAY:
1534 is_array = true;
1535 break;
1536 case V_038000_SQ_TEX_DIM_2D_ARRAY_MSAA:
1537 is_array = true;
1538 /* fall through */
1539 case V_038000_SQ_TEX_DIM_2D_MSAA:
1540 array_check.nsamples = 1 << llevel;
1541 llevel = 0;
1542 break;
1543 default:
1544 dev_warn(p->dev, "this kernel doesn't support %d texture dim\n", G_038000_DIM(word0));
1545 return -EINVAL;
1546 }
1547 if (!r600_fmt_is_valid_texture(format, p->family)) {
1548 dev_warn(p->dev, "%s:%d texture invalid format %d\n",
1549 __func__, __LINE__, format);
1550 return -EINVAL;
1551 }
1552
1553 if (r600_get_array_mode_alignment(&array_check,
1554 &pitch_align, &height_align, &depth_align, &base_align)) {
1555 dev_warn(p->dev, "%s:%d tex array mode (%d) invalid\n",
1556 __func__, __LINE__, G_038000_TILE_MODE(word0));
1557 return -EINVAL;
1558 }
1559
1560 /* XXX check height as well... */
1561
1562 if (!IS_ALIGNED(pitch, pitch_align)) {
1563 dev_warn(p->dev, "%s:%d tex pitch (%d, 0x%x, %d) invalid\n",
1564 __func__, __LINE__, pitch, pitch_align, G_038000_TILE_MODE(word0));
1565 return -EINVAL;
1566 }
1567 if (!IS_ALIGNED(base_offset, base_align)) {
1568 dev_warn(p->dev, "%s:%d tex base offset (0x%llx, 0x%llx, %d) invalid\n",
1569 __func__, __LINE__, base_offset, base_align, G_038000_TILE_MODE(word0));
1570 return -EINVAL;
1571 }
1572 if (!IS_ALIGNED(mip_offset, base_align)) {
1573 dev_warn(p->dev, "%s:%d tex mip offset (0x%llx, 0x%llx, %d) invalid\n",
1574 __func__, __LINE__, mip_offset, base_align, G_038000_TILE_MODE(word0));
1575 return -EINVAL;
1576 }
1577
1578 if (blevel > llevel) {
1579 dev_warn(p->dev, "texture blevel %d > llevel %d\n",
1580 blevel, llevel);
1581 }
1582 if (is_array) {
1583 barray = G_038014_BASE_ARRAY(word5);
1584 larray = G_038014_LAST_ARRAY(word5);
1585
1586 nfaces = larray - barray + 1;
1587 }
1588 r600_texture_size(nfaces, blevel, llevel, w0, h0, d0, array_check.nsamples, format,
1589 pitch_align, height_align, base_align,
1590 &l0_size, &mipmap_size);
1591 /* using get ib will give us the offset into the texture bo */
1592 if ((l0_size + word2) > radeon_bo_size(texture)) {
1593 dev_warn(p->dev, "texture bo too small ((%d %d) (%d %d) %d %d %d -> %d have %ld)\n",
1594 w0, h0, pitch_align, height_align,
1595 array_check.array_mode, format, word2,
1596 l0_size, radeon_bo_size(texture));
1597 dev_warn(p->dev, "alignments %d %d %d %lld\n", pitch, pitch_align, height_align, base_align);
1598 return -EINVAL;
1599 }
1600 /* using get ib will give us the offset into the mipmap bo */
1601 if ((mipmap_size + word3) > radeon_bo_size(mipmap)) {
1602 /*dev_warn(p->dev, "mipmap bo too small (%d %d %d %d %d %d -> %d have %ld)\n",
1603 w0, h0, format, blevel, nlevels, word3, mipmap_size, radeon_bo_size(texture));*/
1604 }
1605 return 0;
1606 }
1607
1608 static bool r600_is_safe_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
1609 {
1610 u32 m, i;
1611
1612 i = (reg >> 7);
1613 if (i >= ARRAY_SIZE(r600_reg_safe_bm)) {
1614 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
1615 return false;
1616 }
1617 m = 1 << ((reg >> 2) & 31);
1618 if (!(r600_reg_safe_bm[i] & m))
1619 return true;
1620 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
1621 return false;
1622 }
1623
1624 static int r600_packet3_check(struct radeon_cs_parser *p,
1625 struct radeon_cs_packet *pkt)
1626 {
1627 struct radeon_bo_list *reloc;
1628 struct r600_cs_track *track;
1629 volatile u32 *ib;
1630 unsigned idx;
1631 unsigned i;
1632 unsigned start_reg, end_reg, reg;
1633 int r;
1634 u32 idx_value;
1635
1636 track = (struct r600_cs_track *)p->track;
1637 ib = p->ib.ptr;
1638 idx = pkt->idx + 1;
1639 idx_value = radeon_get_ib_value(p, idx);
1640
1641 switch (pkt->opcode) {
1642 case PACKET3_SET_PREDICATION:
1643 {
1644 int pred_op;
1645 int tmp;
1646 uint64_t offset;
1647
1648 if (pkt->count != 1) {
1649 DRM_ERROR("bad SET PREDICATION\n");
1650 return -EINVAL;
1651 }
1652
1653 tmp = radeon_get_ib_value(p, idx + 1);
1654 pred_op = (tmp >> 16) & 0x7;
1655
1656 /* for the clear predicate operation */
1657 if (pred_op == 0)
1658 return 0;
1659
1660 if (pred_op > 2) {
1661 DRM_ERROR("bad SET PREDICATION operation %d\n", pred_op);
1662 return -EINVAL;
1663 }
1664
1665 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
1666 if (r) {
1667 DRM_ERROR("bad SET PREDICATION\n");
1668 return -EINVAL;
1669 }
1670
1671 offset = reloc->gpu_offset +
1672 (idx_value & 0xfffffff0) +
1673 ((u64)(tmp & 0xff) << 32);
1674
1675 ib[idx + 0] = offset;
1676 ib[idx + 1] = (tmp & 0xffffff00) | (upper_32_bits(offset) & 0xff);
1677 }
1678 break;
1679
1680 case PACKET3_START_3D_CMDBUF:
1681 if (p->family >= CHIP_RV770 || pkt->count) {
1682 DRM_ERROR("bad START_3D\n");
1683 return -EINVAL;
1684 }
1685 break;
1686 case PACKET3_CONTEXT_CONTROL:
1687 if (pkt->count != 1) {
1688 DRM_ERROR("bad CONTEXT_CONTROL\n");
1689 return -EINVAL;
1690 }
1691 break;
1692 case PACKET3_INDEX_TYPE:
1693 case PACKET3_NUM_INSTANCES:
1694 if (pkt->count) {
1695 DRM_ERROR("bad INDEX_TYPE/NUM_INSTANCES\n");
1696 return -EINVAL;
1697 }
1698 break;
1699 case PACKET3_DRAW_INDEX:
1700 {
1701 uint64_t offset;
1702 if (pkt->count != 3) {
1703 DRM_ERROR("bad DRAW_INDEX\n");
1704 return -EINVAL;
1705 }
1706 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
1707 if (r) {
1708 DRM_ERROR("bad DRAW_INDEX\n");
1709 return -EINVAL;
1710 }
1711
1712 offset = reloc->gpu_offset +
1713 idx_value +
1714 ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32);
1715
1716 ib[idx+0] = offset;
1717 ib[idx+1] = upper_32_bits(offset) & 0xff;
1718
1719 r = r600_cs_track_check(p);
1720 if (r) {
1721 dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
1722 return r;
1723 }
1724 break;
1725 }
1726 case PACKET3_DRAW_INDEX_AUTO:
1727 if (pkt->count != 1) {
1728 DRM_ERROR("bad DRAW_INDEX_AUTO\n");
1729 return -EINVAL;
1730 }
1731 r = r600_cs_track_check(p);
1732 if (r) {
1733 dev_warn(p->dev, "%s:%d invalid cmd stream %d\n", __func__, __LINE__, idx);
1734 return r;
1735 }
1736 break;
1737 case PACKET3_DRAW_INDEX_IMMD_BE:
1738 case PACKET3_DRAW_INDEX_IMMD:
1739 if (pkt->count < 2) {
1740 DRM_ERROR("bad DRAW_INDEX_IMMD\n");
1741 return -EINVAL;
1742 }
1743 r = r600_cs_track_check(p);
1744 if (r) {
1745 dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
1746 return r;
1747 }
1748 break;
1749 case PACKET3_WAIT_REG_MEM:
1750 if (pkt->count != 5) {
1751 DRM_ERROR("bad WAIT_REG_MEM\n");
1752 return -EINVAL;
1753 }
1754 /* bit 4 is reg (0) or mem (1) */
1755 if (idx_value & 0x10) {
1756 uint64_t offset;
1757
1758 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
1759 if (r) {
1760 DRM_ERROR("bad WAIT_REG_MEM\n");
1761 return -EINVAL;
1762 }
1763
1764 offset = reloc->gpu_offset +
1765 (radeon_get_ib_value(p, idx+1) & 0xfffffff0) +
1766 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);
1767
1768 ib[idx+1] = (ib[idx+1] & 0x3) | (offset & 0xfffffff0);
1769 ib[idx+2] = upper_32_bits(offset) & 0xff;
1770 } else if (idx_value & 0x100) {
1771 DRM_ERROR("cannot use PFP on REG wait\n");
1772 return -EINVAL;
1773 }
1774 break;
1775 case PACKET3_CP_DMA:
1776 {
1777 u32 command, size;
1778 u64 offset, tmp;
1779 if (pkt->count != 4) {
1780 DRM_ERROR("bad CP DMA\n");
1781 return -EINVAL;
1782 }
1783 command = radeon_get_ib_value(p, idx+4);
1784 size = command & 0x1fffff;
1785 if (command & PACKET3_CP_DMA_CMD_SAS) {
1786 /* src address space is register */
1787 DRM_ERROR("CP DMA SAS not supported\n");
1788 return -EINVAL;
1789 } else {
1790 if (command & PACKET3_CP_DMA_CMD_SAIC) {
1791 DRM_ERROR("CP DMA SAIC only supported for registers\n");
1792 return -EINVAL;
1793 }
1794 /* src address space is memory */
1795 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
1796 if (r) {
1797 DRM_ERROR("bad CP DMA SRC\n");
1798 return -EINVAL;
1799 }
1800
1801 tmp = radeon_get_ib_value(p, idx) +
1802 ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32);
1803
1804 offset = reloc->gpu_offset + tmp;
1805
1806 if ((tmp + size) > radeon_bo_size(reloc->robj)) {
1807 dev_warn(p->dev, "CP DMA src buffer too small (%llu %lu)\n",
1808 tmp + size, radeon_bo_size(reloc->robj));
1809 return -EINVAL;
1810 }
1811
1812 ib[idx] = offset;
1813 ib[idx+1] = (ib[idx+1] & 0xffffff00) | (upper_32_bits(offset) & 0xff);
1814 }
1815 if (command & PACKET3_CP_DMA_CMD_DAS) {
1816 /* dst address space is register */
1817 DRM_ERROR("CP DMA DAS not supported\n");
1818 return -EINVAL;
1819 } else {
1820 /* dst address space is memory */
1821 if (command & PACKET3_CP_DMA_CMD_DAIC) {
1822 DRM_ERROR("CP DMA DAIC only supported for registers\n");
1823 return -EINVAL;
1824 }
1825 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
1826 if (r) {
1827 DRM_ERROR("bad CP DMA DST\n");
1828 return -EINVAL;
1829 }
1830
1831 tmp = radeon_get_ib_value(p, idx+2) +
1832 ((u64)(radeon_get_ib_value(p, idx+3) & 0xff) << 32);
1833
1834 offset = reloc->gpu_offset + tmp;
1835
1836 if ((tmp + size) > radeon_bo_size(reloc->robj)) {
1837 dev_warn(p->dev, "CP DMA dst buffer too small (%llu %lu)\n",
1838 tmp + size, radeon_bo_size(reloc->robj));
1839 return -EINVAL;
1840 }
1841
1842 ib[idx+2] = offset;
1843 ib[idx+3] = upper_32_bits(offset) & 0xff;
1844 }
1845 break;
1846 }
1847 case PACKET3_SURFACE_SYNC:
1848 if (pkt->count != 3) {
1849 DRM_ERROR("bad SURFACE_SYNC\n");
1850 return -EINVAL;
1851 }
1852 /* 0xffffffff/0x0 is flush all cache flag */
1853 if (radeon_get_ib_value(p, idx + 1) != 0xffffffff ||
1854 radeon_get_ib_value(p, idx + 2) != 0) {
1855 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
1856 if (r) {
1857 DRM_ERROR("bad SURFACE_SYNC\n");
1858 return -EINVAL;
1859 }
1860 ib[idx+2] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
1861 }
1862 break;
1863 case PACKET3_EVENT_WRITE:
1864 if (pkt->count != 2 && pkt->count != 0) {
1865 DRM_ERROR("bad EVENT_WRITE\n");
1866 return -EINVAL;
1867 }
1868 if (pkt->count) {
1869 uint64_t offset;
1870
1871 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
1872 if (r) {
1873 DRM_ERROR("bad EVENT_WRITE\n");
1874 return -EINVAL;
1875 }
1876 offset = reloc->gpu_offset +
1877 (radeon_get_ib_value(p, idx+1) & 0xfffffff8) +
1878 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);
1879
1880 ib[idx+1] = offset & 0xfffffff8;
1881 ib[idx+2] = upper_32_bits(offset) & 0xff;
1882 }
1883 break;
1884 case PACKET3_EVENT_WRITE_EOP:
1885 {
1886 uint64_t offset;
1887
1888 if (pkt->count != 4) {
1889 DRM_ERROR("bad EVENT_WRITE_EOP\n");
1890 return -EINVAL;
1891 }
1892 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
1893 if (r) {
1894 DRM_ERROR("bad EVENT_WRITE\n");
1895 return -EINVAL;
1896 }
1897
1898 offset = reloc->gpu_offset +
1899 (radeon_get_ib_value(p, idx+1) & 0xfffffffc) +
1900 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);
1901
1902 ib[idx+1] = offset & 0xfffffffc;
1903 ib[idx+2] = (ib[idx+2] & 0xffffff00) | (upper_32_bits(offset) & 0xff);
1904 break;
1905 }
1906 case PACKET3_SET_CONFIG_REG:
1907 start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_OFFSET;
1908 end_reg = 4 * pkt->count + start_reg - 4;
1909 if ((start_reg < PACKET3_SET_CONFIG_REG_OFFSET) ||
1910 (start_reg >= PACKET3_SET_CONFIG_REG_END) ||
1911 (end_reg >= PACKET3_SET_CONFIG_REG_END)) {
1912 DRM_ERROR("bad PACKET3_SET_CONFIG_REG\n");
1913 return -EINVAL;
1914 }
1915 for (i = 0; i < pkt->count; i++) {
1916 reg = start_reg + (4 * i);
1917 r = r600_cs_check_reg(p, reg, idx+1+i);
1918 if (r)
1919 return r;
1920 }
1921 break;
1922 case PACKET3_SET_CONTEXT_REG:
1923 start_reg = (idx_value << 2) + PACKET3_SET_CONTEXT_REG_OFFSET;
1924 end_reg = 4 * pkt->count + start_reg - 4;
1925 if ((start_reg < PACKET3_SET_CONTEXT_REG_OFFSET) ||
1926 (start_reg >= PACKET3_SET_CONTEXT_REG_END) ||
1927 (end_reg >= PACKET3_SET_CONTEXT_REG_END)) {
1928 DRM_ERROR("bad PACKET3_SET_CONTEXT_REG\n");
1929 return -EINVAL;
1930 }
1931 for (i = 0; i < pkt->count; i++) {
1932 reg = start_reg + (4 * i);
1933 r = r600_cs_check_reg(p, reg, idx+1+i);
1934 if (r)
1935 return r;
1936 }
1937 break;
1938 case PACKET3_SET_RESOURCE:
1939 if (pkt->count % 7) {
1940 DRM_ERROR("bad SET_RESOURCE\n");
1941 return -EINVAL;
1942 }
1943 start_reg = (idx_value << 2) + PACKET3_SET_RESOURCE_OFFSET;
1944 end_reg = 4 * pkt->count + start_reg - 4;
1945 if ((start_reg < PACKET3_SET_RESOURCE_OFFSET) ||
1946 (start_reg >= PACKET3_SET_RESOURCE_END) ||
1947 (end_reg >= PACKET3_SET_RESOURCE_END)) {
1948 DRM_ERROR("bad SET_RESOURCE\n");
1949 return -EINVAL;
1950 }
1951 for (i = 0; i < (pkt->count / 7); i++) {
1952 struct radeon_bo *texture, *mipmap;
1953 u32 size, offset, base_offset, mip_offset;
1954
1955 switch (G__SQ_VTX_CONSTANT_TYPE(radeon_get_ib_value(p, idx+(i*7)+6+1))) {
1956 case SQ_TEX_VTX_VALID_TEXTURE:
1957 /* tex base */
1958 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
1959 if (r) {
1960 DRM_ERROR("bad SET_RESOURCE\n");
1961 return -EINVAL;
1962 }
1963 base_offset = (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
1964 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1965 if (reloc->tiling_flags & RADEON_TILING_MACRO)
1966 ib[idx+1+(i*7)+0] |= S_038000_TILE_MODE(V_038000_ARRAY_2D_TILED_THIN1);
1967 else if (reloc->tiling_flags & RADEON_TILING_MICRO)
1968 ib[idx+1+(i*7)+0] |= S_038000_TILE_MODE(V_038000_ARRAY_1D_TILED_THIN1);
1969 }
1970 texture = reloc->robj;
1971 /* tex mip base */
1972 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
1973 if (r) {
1974 DRM_ERROR("bad SET_RESOURCE\n");
1975 return -EINVAL;
1976 }
1977 mip_offset = (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
1978 mipmap = reloc->robj;
1979 r = r600_check_texture_resource(p, idx+(i*7)+1,
1980 texture, mipmap,
1981 base_offset + radeon_get_ib_value(p, idx+1+(i*7)+2),
1982 mip_offset + radeon_get_ib_value(p, idx+1+(i*7)+3),
1983 reloc->tiling_flags);
1984 if (r)
1985 return r;
1986 ib[idx+1+(i*7)+2] += base_offset;
1987 ib[idx+1+(i*7)+3] += mip_offset;
1988 break;
1989 case SQ_TEX_VTX_VALID_BUFFER:
1990 {
1991 uint64_t offset64;
1992 /* vtx base */
1993 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
1994 if (r) {
1995 DRM_ERROR("bad SET_RESOURCE\n");
1996 return -EINVAL;
1997 }
1998 offset = radeon_get_ib_value(p, idx+1+(i*7)+0);
1999 size = radeon_get_ib_value(p, idx+1+(i*7)+1) + 1;
2000 if (p->rdev && (size + offset) > radeon_bo_size(reloc->robj)) {
2001 /* force size to size of the buffer */
2002 dev_warn(p->dev, "vbo resource seems too big (%d) for the bo (%ld)\n",
2003 size + offset, radeon_bo_size(reloc->robj));
2004 ib[idx+1+(i*7)+1] = radeon_bo_size(reloc->robj) - offset;
2005 }
2006
2007 offset64 = reloc->gpu_offset + offset;
2008 ib[idx+1+(i*8)+0] = offset64;
2009 ib[idx+1+(i*8)+2] = (ib[idx+1+(i*8)+2] & 0xffffff00) |
2010 (upper_32_bits(offset64) & 0xff);
2011 break;
2012 }
2013 case SQ_TEX_VTX_INVALID_TEXTURE:
2014 case SQ_TEX_VTX_INVALID_BUFFER:
2015 default:
2016 DRM_ERROR("bad SET_RESOURCE\n");
2017 return -EINVAL;
2018 }
2019 }
2020 break;
2021 case PACKET3_SET_ALU_CONST:
2022 if (track->sq_config & DX9_CONSTS) {
2023 start_reg = (idx_value << 2) + PACKET3_SET_ALU_CONST_OFFSET;
2024 end_reg = 4 * pkt->count + start_reg - 4;
2025 if ((start_reg < PACKET3_SET_ALU_CONST_OFFSET) ||
2026 (start_reg >= PACKET3_SET_ALU_CONST_END) ||
2027 (end_reg >= PACKET3_SET_ALU_CONST_END)) {
2028 DRM_ERROR("bad SET_ALU_CONST\n");
2029 return -EINVAL;
2030 }
2031 }
2032 break;
2033 case PACKET3_SET_BOOL_CONST:
2034 start_reg = (idx_value << 2) + PACKET3_SET_BOOL_CONST_OFFSET;
2035 end_reg = 4 * pkt->count + start_reg - 4;
2036 if ((start_reg < PACKET3_SET_BOOL_CONST_OFFSET) ||
2037 (start_reg >= PACKET3_SET_BOOL_CONST_END) ||
2038 (end_reg >= PACKET3_SET_BOOL_CONST_END)) {
2039 DRM_ERROR("bad SET_BOOL_CONST\n");
2040 return -EINVAL;
2041 }
2042 break;
2043 case PACKET3_SET_LOOP_CONST:
2044 start_reg = (idx_value << 2) + PACKET3_SET_LOOP_CONST_OFFSET;
2045 end_reg = 4 * pkt->count + start_reg - 4;
2046 if ((start_reg < PACKET3_SET_LOOP_CONST_OFFSET) ||
2047 (start_reg >= PACKET3_SET_LOOP_CONST_END) ||
2048 (end_reg >= PACKET3_SET_LOOP_CONST_END)) {
2049 DRM_ERROR("bad SET_LOOP_CONST\n");
2050 return -EINVAL;
2051 }
2052 break;
2053 case PACKET3_SET_CTL_CONST:
2054 start_reg = (idx_value << 2) + PACKET3_SET_CTL_CONST_OFFSET;
2055 end_reg = 4 * pkt->count + start_reg - 4;
2056 if ((start_reg < PACKET3_SET_CTL_CONST_OFFSET) ||
2057 (start_reg >= PACKET3_SET_CTL_CONST_END) ||
2058 (end_reg >= PACKET3_SET_CTL_CONST_END)) {
2059 DRM_ERROR("bad SET_CTL_CONST\n");
2060 return -EINVAL;
2061 }
2062 break;
2063 case PACKET3_SET_SAMPLER:
2064 if (pkt->count % 3) {
2065 DRM_ERROR("bad SET_SAMPLER\n");
2066 return -EINVAL;
2067 }
2068 start_reg = (idx_value << 2) + PACKET3_SET_SAMPLER_OFFSET;
2069 end_reg = 4 * pkt->count + start_reg - 4;
2070 if ((start_reg < PACKET3_SET_SAMPLER_OFFSET) ||
2071 (start_reg >= PACKET3_SET_SAMPLER_END) ||
2072 (end_reg >= PACKET3_SET_SAMPLER_END)) {
2073 DRM_ERROR("bad SET_SAMPLER\n");
2074 return -EINVAL;
2075 }
2076 break;
2077 case PACKET3_STRMOUT_BASE_UPDATE:
2078 /* RS780 and RS880 also need this */
2079 if (p->family < CHIP_RS780) {
2080 DRM_ERROR("STRMOUT_BASE_UPDATE only supported on 7xx\n");
2081 return -EINVAL;
2082 }
2083 if (pkt->count != 1) {
2084 DRM_ERROR("bad STRMOUT_BASE_UPDATE packet count\n");
2085 return -EINVAL;
2086 }
2087 if (idx_value > 3) {
2088 DRM_ERROR("bad STRMOUT_BASE_UPDATE index\n");
2089 return -EINVAL;
2090 }
2091 {
2092 u64 offset;
2093
2094 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
2095 if (r) {
2096 DRM_ERROR("bad STRMOUT_BASE_UPDATE reloc\n");
2097 return -EINVAL;
2098 }
2099
2100 if (reloc->robj != track->vgt_strmout_bo[idx_value]) {
2101 DRM_ERROR("bad STRMOUT_BASE_UPDATE, bo does not match\n");
2102 return -EINVAL;
2103 }
2104
2105 offset = radeon_get_ib_value(p, idx+1) << 8;
2106 if (offset != track->vgt_strmout_bo_offset[idx_value]) {
2107 DRM_ERROR("bad STRMOUT_BASE_UPDATE, bo offset does not match: 0x%llx, 0x%x\n",
2108 offset, track->vgt_strmout_bo_offset[idx_value]);
2109 return -EINVAL;
2110 }
2111
2112 if ((offset + 4) > radeon_bo_size(reloc->robj)) {
2113 DRM_ERROR("bad STRMOUT_BASE_UPDATE bo too small: 0x%llx, 0x%lx\n",
2114 offset + 4, radeon_bo_size(reloc->robj));
2115 return -EINVAL;
2116 }
2117 ib[idx+1] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
2118 }
2119 break;
2120 case PACKET3_SURFACE_BASE_UPDATE:
2121 if (p->family >= CHIP_RV770 || p->family == CHIP_R600) {
2122 DRM_ERROR("bad SURFACE_BASE_UPDATE\n");
2123 return -EINVAL;
2124 }
2125 if (pkt->count) {
2126 DRM_ERROR("bad SURFACE_BASE_UPDATE\n");
2127 return -EINVAL;
2128 }
2129 break;
2130 case PACKET3_STRMOUT_BUFFER_UPDATE:
2131 if (pkt->count != 4) {
2132 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE (invalid count)\n");
2133 return -EINVAL;
2134 }
2135 /* Updating memory at DST_ADDRESS. */
2136 if (idx_value & 0x1) {
2137 u64 offset;
2138 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
2139 if (r) {
2140 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE (missing dst reloc)\n");
2141 return -EINVAL;
2142 }
2143 offset = radeon_get_ib_value(p, idx+1);
2144 offset += ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32;
2145 if ((offset + 4) > radeon_bo_size(reloc->robj)) {
2146 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE dst bo too small: 0x%llx, 0x%lx\n",
2147 offset + 4, radeon_bo_size(reloc->robj));
2148 return -EINVAL;
2149 }
2150 offset += reloc->gpu_offset;
2151 ib[idx+1] = offset;
2152 ib[idx+2] = upper_32_bits(offset) & 0xff;
2153 }
2154 /* Reading data from SRC_ADDRESS. */
2155 if (((idx_value >> 1) & 0x3) == 2) {
2156 u64 offset;
2157 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
2158 if (r) {
2159 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE (missing src reloc)\n");
2160 return -EINVAL;
2161 }
2162 offset = radeon_get_ib_value(p, idx+3);
2163 offset += ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32;
2164 if ((offset + 4) > radeon_bo_size(reloc->robj)) {
2165 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE src bo too small: 0x%llx, 0x%lx\n",
2166 offset + 4, radeon_bo_size(reloc->robj));
2167 return -EINVAL;
2168 }
2169 offset += reloc->gpu_offset;
2170 ib[idx+3] = offset;
2171 ib[idx+4] = upper_32_bits(offset) & 0xff;
2172 }
2173 break;
2174 case PACKET3_MEM_WRITE:
2175 {
2176 u64 offset;
2177
2178 if (pkt->count != 3) {
2179 DRM_ERROR("bad MEM_WRITE (invalid count)\n");
2180 return -EINVAL;
2181 }
2182 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
2183 if (r) {
2184 DRM_ERROR("bad MEM_WRITE (missing reloc)\n");
2185 return -EINVAL;
2186 }
2187 offset = radeon_get_ib_value(p, idx+0);
2188 offset += ((u64)(radeon_get_ib_value(p, idx+1) & 0xff)) << 32UL;
2189 if (offset & 0x7) {
2190 DRM_ERROR("bad MEM_WRITE (address not qwords aligned)\n");
2191 return -EINVAL;
2192 }
2193 if ((offset + 8) > radeon_bo_size(reloc->robj)) {
2194 DRM_ERROR("bad MEM_WRITE bo too small: 0x%llx, 0x%lx\n",
2195 offset + 8, radeon_bo_size(reloc->robj));
2196 return -EINVAL;
2197 }
2198 offset += reloc->gpu_offset;
2199 ib[idx+0] = offset;
2200 ib[idx+1] = upper_32_bits(offset) & 0xff;
2201 break;
2202 }
2203 case PACKET3_COPY_DW:
2204 if (pkt->count != 4) {
2205 DRM_ERROR("bad COPY_DW (invalid count)\n");
2206 return -EINVAL;
2207 }
2208 if (idx_value & 0x1) {
2209 u64 offset;
2210 /* SRC is memory. */
2211 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
2212 if (r) {
2213 DRM_ERROR("bad COPY_DW (missing src reloc)\n");
2214 return -EINVAL;
2215 }
2216 offset = radeon_get_ib_value(p, idx+1);
2217 offset += ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32;
2218 if ((offset + 4) > radeon_bo_size(reloc->robj)) {
2219 DRM_ERROR("bad COPY_DW src bo too small: 0x%llx, 0x%lx\n",
2220 offset + 4, radeon_bo_size(reloc->robj));
2221 return -EINVAL;
2222 }
2223 offset += reloc->gpu_offset;
2224 ib[idx+1] = offset;
2225 ib[idx+2] = upper_32_bits(offset) & 0xff;
2226 } else {
2227 /* SRC is a reg. */
2228 reg = radeon_get_ib_value(p, idx+1) << 2;
2229 if (!r600_is_safe_reg(p, reg, idx+1))
2230 return -EINVAL;
2231 }
2232 if (idx_value & 0x2) {
2233 u64 offset;
2234 /* DST is memory. */
2235 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
2236 if (r) {
2237 DRM_ERROR("bad COPY_DW (missing dst reloc)\n");
2238 return -EINVAL;
2239 }
2240 offset = radeon_get_ib_value(p, idx+3);
2241 offset += ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32;
2242 if ((offset + 4) > radeon_bo_size(reloc->robj)) {
2243 DRM_ERROR("bad COPY_DW dst bo too small: 0x%llx, 0x%lx\n",
2244 offset + 4, radeon_bo_size(reloc->robj));
2245 return -EINVAL;
2246 }
2247 offset += reloc->gpu_offset;
2248 ib[idx+3] = offset;
2249 ib[idx+4] = upper_32_bits(offset) & 0xff;
2250 } else {
2251 /* DST is a reg. */
2252 reg = radeon_get_ib_value(p, idx+3) << 2;
2253 if (!r600_is_safe_reg(p, reg, idx+3))
2254 return -EINVAL;
2255 }
2256 break;
2257 case PACKET3_NOP:
2258 break;
2259 default:
2260 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
2261 return -EINVAL;
2262 }
2263 return 0;
2264 }
2265
2266 int r600_cs_parse(struct radeon_cs_parser *p)
2267 {
2268 struct radeon_cs_packet pkt;
2269 struct r600_cs_track *track;
2270 int r;
2271
2272 if (p->track == NULL) {
2273 /* initialize tracker, we are in kms */
2274 track = kzalloc(sizeof(*track), GFP_KERNEL);
2275 if (track == NULL)
2276 return -ENOMEM;
2277 r600_cs_track_init(track);
2278 if (p->rdev->family < CHIP_RV770) {
2279 track->npipes = p->rdev->config.r600.tiling_npipes;
2280 track->nbanks = p->rdev->config.r600.tiling_nbanks;
2281 track->group_size = p->rdev->config.r600.tiling_group_size;
2282 } else if (p->rdev->family <= CHIP_RV740) {
2283 track->npipes = p->rdev->config.rv770.tiling_npipes;
2284 track->nbanks = p->rdev->config.rv770.tiling_nbanks;
2285 track->group_size = p->rdev->config.rv770.tiling_group_size;
2286 }
2287 p->track = track;
2288 }
2289 do {
2290 r = radeon_cs_packet_parse(p, &pkt, p->idx);
2291 if (r) {
2292 kfree(p->track);
2293 p->track = NULL;
2294 return r;
2295 }
2296 p->idx += pkt.count + 2;
2297 switch (pkt.type) {
2298 case RADEON_PACKET_TYPE0:
2299 r = r600_cs_parse_packet0(p, &pkt);
2300 break;
2301 case RADEON_PACKET_TYPE2:
2302 break;
2303 case RADEON_PACKET_TYPE3:
2304 r = r600_packet3_check(p, &pkt);
2305 break;
2306 default:
2307 DRM_ERROR("Unknown packet type %d !\n", pkt.type);
2308 kfree(p->track);
2309 p->track = NULL;
2310 return -EINVAL;
2311 }
2312 if (r) {
2313 kfree(p->track);
2314 p->track = NULL;
2315 return r;
2316 }
2317 } while (p->idx < p->chunk_ib->length_dw);
2318 #if 0
2319 for (r = 0; r < p->ib.length_dw; r++) {
2320 pr_info("%05d 0x%08X\n", r, p->ib.ptr[r]);
2321 mdelay(1);
2322 }
2323 #endif
2324 kfree(p->track);
2325 p->track = NULL;
2326 return 0;
2327 }
2328
2329 /*
2330 * DMA
2331 */
2332 /**
2333 * r600_dma_cs_next_reloc() - parse next reloc
2334 * @p: parser structure holding parsing context.
2335 * @cs_reloc: reloc informations
2336 *
2337 * Return the next reloc, do bo validation and compute
2338 * GPU offset using the provided start.
2339 **/
2340 int r600_dma_cs_next_reloc(struct radeon_cs_parser *p,
2341 struct radeon_bo_list **cs_reloc)
2342 {
2343 unsigned idx;
2344
2345 *cs_reloc = NULL;
2346 if (p->chunk_relocs == NULL) {
2347 DRM_ERROR("No relocation chunk !\n");
2348 return -EINVAL;
2349 }
2350 idx = p->dma_reloc_idx;
2351 if (idx >= p->nrelocs) {
2352 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
2353 idx, p->nrelocs);
2354 return -EINVAL;
2355 }
2356 *cs_reloc = &p->relocs[idx];
2357 p->dma_reloc_idx++;
2358 return 0;
2359 }
2360
2361 #define GET_DMA_CMD(h) (((h) & 0xf0000000) >> 28)
2362 #define GET_DMA_COUNT(h) ((h) & 0x0000ffff)
2363 #define GET_DMA_T(h) (((h) & 0x00800000) >> 23)
2364
2365 /**
2366 * r600_dma_cs_parse() - parse the DMA IB
2367 * @p: parser structure holding parsing context.
2368 *
2369 * Parses the DMA IB from the CS ioctl and updates
2370 * the GPU addresses based on the reloc information and
2371 * checks for errors. (R6xx-R7xx)
2372 * Returns 0 for success and an error on failure.
2373 **/
2374 int r600_dma_cs_parse(struct radeon_cs_parser *p)
2375 {
2376 struct radeon_cs_chunk *ib_chunk = p->chunk_ib;
2377 struct radeon_bo_list *src_reloc, *dst_reloc;
2378 u32 header, cmd, count, tiled;
2379 volatile u32 *ib = p->ib.ptr;
2380 u32 idx, idx_value;
2381 u64 src_offset, dst_offset;
2382 int r;
2383
2384 do {
2385 if (p->idx >= ib_chunk->length_dw) {
2386 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
2387 p->idx, ib_chunk->length_dw);
2388 return -EINVAL;
2389 }
2390 idx = p->idx;
2391 header = radeon_get_ib_value(p, idx);
2392 cmd = GET_DMA_CMD(header);
2393 count = GET_DMA_COUNT(header);
2394 tiled = GET_DMA_T(header);
2395
2396 switch (cmd) {
2397 case DMA_PACKET_WRITE:
2398 r = r600_dma_cs_next_reloc(p, &dst_reloc);
2399 if (r) {
2400 DRM_ERROR("bad DMA_PACKET_WRITE\n");
2401 return -EINVAL;
2402 }
2403 if (tiled) {
2404 dst_offset = radeon_get_ib_value(p, idx+1);
2405 dst_offset <<= 8;
2406
2407 ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8);
2408 p->idx += count + 5;
2409 } else {
2410 dst_offset = radeon_get_ib_value(p, idx+1);
2411 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32;
2412
2413 ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc);
2414 ib[idx+2] += upper_32_bits(dst_reloc->gpu_offset) & 0xff;
2415 p->idx += count + 3;
2416 }
2417 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
2418 dev_warn(p->dev, "DMA write buffer too small (%llu %lu)\n",
2419 dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));
2420 return -EINVAL;
2421 }
2422 break;
2423 case DMA_PACKET_COPY:
2424 r = r600_dma_cs_next_reloc(p, &src_reloc);
2425 if (r) {
2426 DRM_ERROR("bad DMA_PACKET_COPY\n");
2427 return -EINVAL;
2428 }
2429 r = r600_dma_cs_next_reloc(p, &dst_reloc);
2430 if (r) {
2431 DRM_ERROR("bad DMA_PACKET_COPY\n");
2432 return -EINVAL;
2433 }
2434 if (tiled) {
2435 idx_value = radeon_get_ib_value(p, idx + 2);
2436 /* detile bit */
2437 if (idx_value & (1 << 31)) {
2438 /* tiled src, linear dst */
2439 src_offset = radeon_get_ib_value(p, idx+1);
2440 src_offset <<= 8;
2441 ib[idx+1] += (u32)(src_reloc->gpu_offset >> 8);
2442
2443 dst_offset = radeon_get_ib_value(p, idx+5);
2444 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+6) & 0xff)) << 32;
2445 ib[idx+5] += (u32)(dst_reloc->gpu_offset & 0xfffffffc);
2446 ib[idx+6] += upper_32_bits(dst_reloc->gpu_offset) & 0xff;
2447 } else {
2448 /* linear src, tiled dst */
2449 src_offset = radeon_get_ib_value(p, idx+5);
2450 src_offset |= ((u64)(radeon_get_ib_value(p, idx+6) & 0xff)) << 32;
2451 ib[idx+5] += (u32)(src_reloc->gpu_offset & 0xfffffffc);
2452 ib[idx+6] += upper_32_bits(src_reloc->gpu_offset) & 0xff;
2453
2454 dst_offset = radeon_get_ib_value(p, idx+1);
2455 dst_offset <<= 8;
2456 ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8);
2457 }
2458 p->idx += 7;
2459 } else {
2460 if (p->family >= CHIP_RV770) {
2461 src_offset = radeon_get_ib_value(p, idx+2);
2462 src_offset |= ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32;
2463 dst_offset = radeon_get_ib_value(p, idx+1);
2464 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff)) << 32;
2465
2466 ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc);
2467 ib[idx+2] += (u32)(src_reloc->gpu_offset & 0xfffffffc);
2468 ib[idx+3] += upper_32_bits(dst_reloc->gpu_offset) & 0xff;
2469 ib[idx+4] += upper_32_bits(src_reloc->gpu_offset) & 0xff;
2470 p->idx += 5;
2471 } else {
2472 src_offset = radeon_get_ib_value(p, idx+2);
2473 src_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff)) << 32;
2474 dst_offset = radeon_get_ib_value(p, idx+1);
2475 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff0000)) << 16;
2476
2477 ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc);
2478 ib[idx+2] += (u32)(src_reloc->gpu_offset & 0xfffffffc);
2479 ib[idx+3] += upper_32_bits(src_reloc->gpu_offset) & 0xff;
2480 ib[idx+3] += (upper_32_bits(dst_reloc->gpu_offset) & 0xff) << 16;
2481 p->idx += 4;
2482 }
2483 }
2484 if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {
2485 dev_warn(p->dev, "DMA copy src buffer too small (%llu %lu)\n",
2486 src_offset + (count * 4), radeon_bo_size(src_reloc->robj));
2487 return -EINVAL;
2488 }
2489 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
2490 dev_warn(p->dev, "DMA write dst buffer too small (%llu %lu)\n",
2491 dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));
2492 return -EINVAL;
2493 }
2494 break;
2495 case DMA_PACKET_CONSTANT_FILL:
2496 if (p->family < CHIP_RV770) {
2497 DRM_ERROR("Constant Fill is 7xx only !\n");
2498 return -EINVAL;
2499 }
2500 r = r600_dma_cs_next_reloc(p, &dst_reloc);
2501 if (r) {
2502 DRM_ERROR("bad DMA_PACKET_WRITE\n");
2503 return -EINVAL;
2504 }
2505 dst_offset = radeon_get_ib_value(p, idx+1);
2506 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0x00ff0000)) << 16;
2507 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
2508 dev_warn(p->dev, "DMA constant fill buffer too small (%llu %lu)\n",
2509 dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));
2510 return -EINVAL;
2511 }
2512 ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc);
2513 ib[idx+3] += (upper_32_bits(dst_reloc->gpu_offset) << 16) & 0x00ff0000;
2514 p->idx += 4;
2515 break;
2516 case DMA_PACKET_NOP:
2517 p->idx += 1;
2518 break;
2519 default:
2520 DRM_ERROR("Unknown packet type %d at %d !\n", cmd, idx);
2521 return -EINVAL;
2522 }
2523 } while (p->idx < p->chunk_ib->length_dw);
2524 #if 0
2525 for (r = 0; r < p->ib->length_dw; r++) {
2526 pr_info("%05d 0x%08X\n", r, p->ib.ptr[r]);
2527 mdelay(1);
2528 }
2529 #endif
2530 return 0;
2531 }
Linux with added FPC-III support