drivers/gpu/drm/radeon/rv730_dpm.c

   1 /*
   2  * Copyright 2011 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Alex Deucher
  23  */
  24
  25 #include "radeon.h"
  26 #include "rv730d.h"
  27 #include "r600_dpm.h"
  28 #include "rv770_dpm.h"
  29 #include "atom.h"
  30
  31 #define MC_CG_ARB_FREQ_F0           0x0a
  32 #define MC_CG_ARB_FREQ_F1           0x0b
  33 #define MC_CG_ARB_FREQ_F2           0x0c
  34 #define MC_CG_ARB_FREQ_F3           0x0d
  35
  36 struct rv7xx_ps *rv770_get_ps(struct radeon_ps *rps);
  37 struct rv7xx_power_info *rv770_get_pi(struct radeon_device *rdev);
  38
  39 int rv730_populate_sclk_value(struct radeon_device *rdev,
  40                               u32 engine_clock,
  41                               RV770_SMC_SCLK_VALUE *sclk)
  42 {
  43         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
  44         struct atom_clock_dividers dividers;
  45         u32 spll_func_cntl = pi->clk_regs.rv730.cg_spll_func_cntl;
  46         u32 spll_func_cntl_2 = pi->clk_regs.rv730.cg_spll_func_cntl_2;
  47         u32 spll_func_cntl_3 = pi->clk_regs.rv730.cg_spll_func_cntl_3;
  48         u32 cg_spll_spread_spectrum = pi->clk_regs.rv730.cg_spll_spread_spectrum;
  49         u32 cg_spll_spread_spectrum_2 = pi->clk_regs.rv730.cg_spll_spread_spectrum_2;
  50         u64 tmp;
  51         u32 reference_clock = rdev->clock.spll.reference_freq;
  52         u32 reference_divider, post_divider;
  53         u32 fbdiv;
  54         int ret;
  55
  56         ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
  57                                              engine_clock, false, &dividers);
  58         if (ret)
  59                 return ret;
  60
  61         reference_divider = 1 + dividers.ref_div;
  62
  63         if (dividers.enable_post_div)
  64                 post_divider = ((dividers.post_div >> 4) & 0xf) +
  65                         (dividers.post_div & 0xf) + 2;
  66         else
  67                 post_divider = 1;
  68
  69         tmp = (u64) engine_clock * reference_divider * post_divider * 16384;
  70         do_div(tmp, reference_clock);
  71         fbdiv = (u32) tmp;
  72
  73         /* set up registers */
  74         if (dividers.enable_post_div)
  75                 spll_func_cntl |= SPLL_DIVEN;
  76         else
  77                 spll_func_cntl &= ~SPLL_DIVEN;
  78         spll_func_cntl &= ~(SPLL_HILEN_MASK | SPLL_LOLEN_MASK | SPLL_REF_DIV_MASK);
  79         spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div);
  80         spll_func_cntl |= SPLL_HILEN((dividers.post_div >> 4) & 0xf);
  81         spll_func_cntl |= SPLL_LOLEN(dividers.post_div & 0xf);
  82
  83         spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
  84         spll_func_cntl_2 |= SCLK_MUX_SEL(2);
  85
  86         spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK;
  87         spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv);
  88         spll_func_cntl_3 |= SPLL_DITHEN;
  89
  90         if (pi->sclk_ss) {
  91                 struct radeon_atom_ss ss;
  92                 u32 vco_freq = engine_clock * post_divider;
  93
  94                 if (radeon_atombios_get_asic_ss_info(rdev, &ss,
  95                                                      ASIC_INTERNAL_ENGINE_SS, vco_freq)) {
  96                         u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate);
  97                         u32 clk_v = ss.percentage * fbdiv / (clk_s * 10000);
  98
  99                         cg_spll_spread_spectrum &= ~CLK_S_MASK;
 100                         cg_spll_spread_spectrum |= CLK_S(clk_s);
 101                         cg_spll_spread_spectrum |= SSEN;
 102
 103                         cg_spll_spread_spectrum_2 &= ~CLK_V_MASK;
 104                         cg_spll_spread_spectrum_2 |= CLK_V(clk_v);
 105                 }
 106         }
 107
 108         sclk->sclk_value = cpu_to_be32(engine_clock);
 109         sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl);
 110         sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(spll_func_cntl_2);
 111         sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(spll_func_cntl_3);
 112         sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(cg_spll_spread_spectrum);
 113         sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(cg_spll_spread_spectrum_2);
 114
 115         return 0;
 116 }
 117
 118 int rv730_populate_mclk_value(struct radeon_device *rdev,
 119                               u32 engine_clock, u32 memory_clock,
 120                               LPRV7XX_SMC_MCLK_VALUE mclk)
 121 {
 122         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
 123         u32 mclk_pwrmgt_cntl = pi->clk_regs.rv730.mclk_pwrmgt_cntl;
 124         u32 dll_cntl = pi->clk_regs.rv730.dll_cntl;
 125         u32 mpll_func_cntl = pi->clk_regs.rv730.mpll_func_cntl;
 126         u32 mpll_func_cntl_2 = pi->clk_regs.rv730.mpll_func_cntl2;
 127         u32 mpll_func_cntl_3 = pi->clk_regs.rv730.mpll_func_cntl3;
 128         u32 mpll_ss = pi->clk_regs.rv730.mpll_ss;
 129         u32 mpll_ss2 = pi->clk_regs.rv730.mpll_ss2;
 130         struct atom_clock_dividers dividers;
 131         u32 post_divider, reference_divider;
 132         int ret;
 133
 134         ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_MEMORY_PLL_PARAM,
 135                                              memory_clock, false, &dividers);
 136         if (ret)
 137                 return ret;
 138
 139         reference_divider = dividers.ref_div + 1;
 140
 141         if (dividers.enable_post_div)
 142                 post_divider = ((dividers.post_div >> 4) & 0xf) +
 143                         (dividers.post_div & 0xf) + 2;
 144         else
 145                 post_divider = 1;
 146
 147         /* setup the registers */
 148         if (dividers.enable_post_div)
 149                 mpll_func_cntl |= MPLL_DIVEN;
 150         else
 151                 mpll_func_cntl &= ~MPLL_DIVEN;
 152
 153         mpll_func_cntl &= ~(MPLL_REF_DIV_MASK | MPLL_HILEN_MASK | MPLL_LOLEN_MASK);
 154         mpll_func_cntl |= MPLL_REF_DIV(dividers.ref_div);
 155         mpll_func_cntl |= MPLL_HILEN((dividers.post_div >> 4) & 0xf);
 156         mpll_func_cntl |= MPLL_LOLEN(dividers.post_div & 0xf);
 157
 158         mpll_func_cntl_3 &= ~MPLL_FB_DIV_MASK;
 159         mpll_func_cntl_3 |= MPLL_FB_DIV(dividers.fb_div);
 160         if (dividers.enable_dithen)
 161                 mpll_func_cntl_3 |= MPLL_DITHEN;
 162         else
 163                 mpll_func_cntl_3 &= ~MPLL_DITHEN;
 164
 165         if (pi->mclk_ss) {
 166                 struct radeon_atom_ss ss;
 167                 u32 vco_freq = memory_clock * post_divider;
 168
 169                 if (radeon_atombios_get_asic_ss_info(rdev, &ss,
 170                                                      ASIC_INTERNAL_MEMORY_SS, vco_freq)) {
 171                         u32 reference_clock = rdev->clock.mpll.reference_freq;
 172                         u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate);
 173                         u32 clk_v = ss.percentage * dividers.fb_div / (clk_s * 10000);
 174
 175                         mpll_ss &= ~CLK_S_MASK;
 176                         mpll_ss |= CLK_S(clk_s);
 177                         mpll_ss |= SSEN;
 178
 179                         mpll_ss2 &= ~CLK_V_MASK;
 180                         mpll_ss |= CLK_V(clk_v);
 181                 }
 182         }
 183
 184
 185         mclk->mclk730.vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl);
 186         mclk->mclk730.vDLL_CNTL = cpu_to_be32(dll_cntl);
 187         mclk->mclk730.mclk_value = cpu_to_be32(memory_clock);
 188         mclk->mclk730.vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl);
 189         mclk->mclk730.vMPLL_FUNC_CNTL2 = cpu_to_be32(mpll_func_cntl_2);
 190         mclk->mclk730.vMPLL_FUNC_CNTL3 = cpu_to_be32(mpll_func_cntl_3);
 191         mclk->mclk730.vMPLL_SS = cpu_to_be32(mpll_ss);
 192         mclk->mclk730.vMPLL_SS2 = cpu_to_be32(mpll_ss2);
 193
 194         return 0;
 195 }
 196
 197 void rv730_read_clock_registers(struct radeon_device *rdev)
 198 {
 199         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
 200
 201         pi->clk_regs.rv730.cg_spll_func_cntl =
 202                 RREG32(CG_SPLL_FUNC_CNTL);
 203         pi->clk_regs.rv730.cg_spll_func_cntl_2 =
 204                 RREG32(CG_SPLL_FUNC_CNTL_2);
 205         pi->clk_regs.rv730.cg_spll_func_cntl_3 =
 206                 RREG32(CG_SPLL_FUNC_CNTL_3);
 207         pi->clk_regs.rv730.cg_spll_spread_spectrum =
 208                 RREG32(CG_SPLL_SPREAD_SPECTRUM);
 209         pi->clk_regs.rv730.cg_spll_spread_spectrum_2 =
 210                 RREG32(CG_SPLL_SPREAD_SPECTRUM_2);
 211
 212         pi->clk_regs.rv730.mclk_pwrmgt_cntl =
 213                 RREG32(TCI_MCLK_PWRMGT_CNTL);
 214         pi->clk_regs.rv730.dll_cntl =
 215                 RREG32(TCI_DLL_CNTL);
 216         pi->clk_regs.rv730.mpll_func_cntl =
 217                 RREG32(CG_MPLL_FUNC_CNTL);
 218         pi->clk_regs.rv730.mpll_func_cntl2 =
 219                 RREG32(CG_MPLL_FUNC_CNTL_2);
 220         pi->clk_regs.rv730.mpll_func_cntl3 =
 221                 RREG32(CG_MPLL_FUNC_CNTL_3);
 222         pi->clk_regs.rv730.mpll_ss =
 223                 RREG32(CG_TCI_MPLL_SPREAD_SPECTRUM);
 224         pi->clk_regs.rv730.mpll_ss2 =
 225                 RREG32(CG_TCI_MPLL_SPREAD_SPECTRUM_2);
 226 }
 227
 228 int rv730_populate_smc_acpi_state(struct radeon_device *rdev,
 229                                   RV770_SMC_STATETABLE *table)
 230 {
 231         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
 232         u32 mpll_func_cntl = 0;
 233         u32 mpll_func_cntl_2 = 0 ;
 234         u32 mpll_func_cntl_3 = 0;
 235         u32 mclk_pwrmgt_cntl;
 236         u32 dll_cntl;
 237         u32 spll_func_cntl;
 238         u32 spll_func_cntl_2;
 239         u32 spll_func_cntl_3;
 240
 241         table->ACPIState = table->initialState;
 242         table->ACPIState.flags &= ~PPSMC_SWSTATE_FLAG_DC;
 243
 244         if (pi->acpi_vddc) {
 245                 rv770_populate_vddc_value(rdev, pi->acpi_vddc,
 246                                           &table->ACPIState.levels[0].vddc);
 247                 table->ACPIState.levels[0].gen2PCIE = pi->pcie_gen2 ?
 248                         pi->acpi_pcie_gen2 : 0;
 249                 table->ACPIState.levels[0].gen2XSP =
 250                         pi->acpi_pcie_gen2;
 251         } else {
 252                 rv770_populate_vddc_value(rdev, pi->min_vddc_in_table,
 253                                           &table->ACPIState.levels[0].vddc);
 254                 table->ACPIState.levels[0].gen2PCIE = 0;
 255         }
 256
 257         mpll_func_cntl = pi->clk_regs.rv730.mpll_func_cntl;
 258         mpll_func_cntl_2 = pi->clk_regs.rv730.mpll_func_cntl2;
 259         mpll_func_cntl_3 = pi->clk_regs.rv730.mpll_func_cntl3;
 260
 261         mpll_func_cntl |= MPLL_RESET | MPLL_BYPASS_EN;
 262         mpll_func_cntl &= ~MPLL_SLEEP;
 263
 264         mpll_func_cntl_2 &= ~MCLK_MUX_SEL_MASK;
 265         mpll_func_cntl_2 |= MCLK_MUX_SEL(1);
 266
 267         mclk_pwrmgt_cntl = (MRDCKA_RESET |
 268                             MRDCKB_RESET |
 269                             MRDCKC_RESET |
 270                             MRDCKD_RESET |
 271                             MRDCKE_RESET |
 272                             MRDCKF_RESET |
 273                             MRDCKG_RESET |
 274                             MRDCKH_RESET |
 275                             MRDCKA_SLEEP |
 276                             MRDCKB_SLEEP |
 277                             MRDCKC_SLEEP |
 278                             MRDCKD_SLEEP |
 279                             MRDCKE_SLEEP |
 280                             MRDCKF_SLEEP |
 281                             MRDCKG_SLEEP |
 282                             MRDCKH_SLEEP);
 283
 284         dll_cntl = 0xff000000;
 285
 286         spll_func_cntl = pi->clk_regs.rv730.cg_spll_func_cntl;
 287         spll_func_cntl_2 = pi->clk_regs.rv730.cg_spll_func_cntl_2;
 288         spll_func_cntl_3 = pi->clk_regs.rv730.cg_spll_func_cntl_3;
 289
 290         spll_func_cntl |= SPLL_RESET | SPLL_BYPASS_EN;
 291         spll_func_cntl &= ~SPLL_SLEEP;
 292
 293         spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
 294         spll_func_cntl_2 |= SCLK_MUX_SEL(4);
 295
 296         table->ACPIState.levels[0].mclk.mclk730.vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl);
 297         table->ACPIState.levels[0].mclk.mclk730.vMPLL_FUNC_CNTL2 = cpu_to_be32(mpll_func_cntl_2);
 298         table->ACPIState.levels[0].mclk.mclk730.vMPLL_FUNC_CNTL3 = cpu_to_be32(mpll_func_cntl_3);
 299         table->ACPIState.levels[0].mclk.mclk730.vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl);
 300         table->ACPIState.levels[0].mclk.mclk730.vDLL_CNTL = cpu_to_be32(dll_cntl);
 301
 302         table->ACPIState.levels[0].mclk.mclk730.mclk_value = 0;
 303
 304         table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl);
 305         table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(spll_func_cntl_2);
 306         table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(spll_func_cntl_3);
 307
 308         table->ACPIState.levels[0].sclk.sclk_value = 0;
 309
 310         rv770_populate_mvdd_value(rdev, 0, &table->ACPIState.levels[0].mvdd);
 311
 312         table->ACPIState.levels[1] = table->ACPIState.levels[0];
 313         table->ACPIState.levels[2] = table->ACPIState.levels[0];
 314
 315         return 0;
 316 }
 317
 318 int rv730_populate_smc_initial_state(struct radeon_device *rdev,
 319                                      struct radeon_ps *radeon_state,
 320                                      RV770_SMC_STATETABLE *table)
 321 {
 322         struct rv7xx_ps *initial_state = rv770_get_ps(radeon_state);
 323         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
 324         u32 a_t;
 325
 326         table->initialState.levels[0].mclk.mclk730.vMPLL_FUNC_CNTL =
 327                 cpu_to_be32(pi->clk_regs.rv730.mpll_func_cntl);
 328         table->initialState.levels[0].mclk.mclk730.vMPLL_FUNC_CNTL2 =
 329                 cpu_to_be32(pi->clk_regs.rv730.mpll_func_cntl2);
 330         table->initialState.levels[0].mclk.mclk730.vMPLL_FUNC_CNTL3 =
 331                 cpu_to_be32(pi->clk_regs.rv730.mpll_func_cntl3);
 332         table->initialState.levels[0].mclk.mclk730.vMCLK_PWRMGT_CNTL =
 333                 cpu_to_be32(pi->clk_regs.rv730.mclk_pwrmgt_cntl);
 334         table->initialState.levels[0].mclk.mclk730.vDLL_CNTL =
 335                 cpu_to_be32(pi->clk_regs.rv730.dll_cntl);
 336         table->initialState.levels[0].mclk.mclk730.vMPLL_SS =
 337                 cpu_to_be32(pi->clk_regs.rv730.mpll_ss);
 338         table->initialState.levels[0].mclk.mclk730.vMPLL_SS2 =
 339                 cpu_to_be32(pi->clk_regs.rv730.mpll_ss2);
 340
 341         table->initialState.levels[0].mclk.mclk730.mclk_value =
 342                 cpu_to_be32(initial_state->low.mclk);
 343
 344         table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
 345                 cpu_to_be32(pi->clk_regs.rv730.cg_spll_func_cntl);
 346         table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
 347                 cpu_to_be32(pi->clk_regs.rv730.cg_spll_func_cntl_2);
 348         table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
 349                 cpu_to_be32(pi->clk_regs.rv730.cg_spll_func_cntl_3);
 350         table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM =
 351                 cpu_to_be32(pi->clk_regs.rv730.cg_spll_spread_spectrum);
 352         table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM_2 =
 353                 cpu_to_be32(pi->clk_regs.rv730.cg_spll_spread_spectrum_2);
 354
 355         table->initialState.levels[0].sclk.sclk_value =
 356                 cpu_to_be32(initial_state->low.sclk);
 357
 358         table->initialState.levels[0].arbValue = MC_CG_ARB_FREQ_F0;
 359
 360         table->initialState.levels[0].seqValue =
 361                 rv770_get_seq_value(rdev, &initial_state->low);
 362
 363         rv770_populate_vddc_value(rdev,
 364                                   initial_state->low.vddc,
 365                                   &table->initialState.levels[0].vddc);
 366         rv770_populate_initial_mvdd_value(rdev,
 367                                           &table->initialState.levels[0].mvdd);
 368
 369         a_t = CG_R(0xffff) | CG_L(0);
 370
 371         table->initialState.levels[0].aT = cpu_to_be32(a_t);
 372
 373         table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp);
 374
 375         if (pi->boot_in_gen2)
 376                 table->initialState.levels[0].gen2PCIE = 1;
 377         else
 378                 table->initialState.levels[0].gen2PCIE = 0;
 379         if (initial_state->low.flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2)
 380                 table->initialState.levels[0].gen2XSP = 1;
 381         else
 382                 table->initialState.levels[0].gen2XSP = 0;
 383
 384         table->initialState.levels[1] = table->initialState.levels[0];
 385         table->initialState.levels[2] = table->initialState.levels[0];
 386
 387         table->initialState.flags |= PPSMC_SWSTATE_FLAG_DC;
 388
 389         return 0;
 390 }
 391
 392 void rv730_program_memory_timing_parameters(struct radeon_device *rdev,
 393                                             struct radeon_ps *radeon_state)
 394 {
 395         struct rv7xx_ps *state = rv770_get_ps(radeon_state);
 396         u32 arb_refresh_rate = 0;
 397         u32 dram_timing = 0;
 398         u32 dram_timing2 = 0;
 399         u32 old_dram_timing = 0;
 400         u32 old_dram_timing2 = 0;
 401
 402         arb_refresh_rate = RREG32(MC_ARB_RFSH_RATE) &
 403                 ~(POWERMODE1_MASK | POWERMODE2_MASK | POWERMODE3_MASK);
 404         arb_refresh_rate |=
 405                 (POWERMODE1(rv770_calculate_memory_refresh_rate(rdev, state->low.sclk)) |
 406                  POWERMODE2(rv770_calculate_memory_refresh_rate(rdev, state->medium.sclk)) |
 407                  POWERMODE3(rv770_calculate_memory_refresh_rate(rdev, state->high.sclk)));
 408         WREG32(MC_ARB_RFSH_RATE, arb_refresh_rate);
 409
 410         /* save the boot dram timings */
 411         old_dram_timing = RREG32(MC_ARB_DRAM_TIMING);
 412         old_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
 413
 414         radeon_atom_set_engine_dram_timings(rdev,
 415                                             state->high.sclk,
 416                                             state->high.mclk);
 417
 418         dram_timing = RREG32(MC_ARB_DRAM_TIMING);
 419         dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
 420
 421         WREG32(MC_ARB_DRAM_TIMING_3, dram_timing);
 422         WREG32(MC_ARB_DRAM_TIMING2_3, dram_timing2);
 423
 424         radeon_atom_set_engine_dram_timings(rdev,
 425                                             state->medium.sclk,
 426                                             state->medium.mclk);
 427
 428         dram_timing = RREG32(MC_ARB_DRAM_TIMING);
 429         dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
 430
 431         WREG32(MC_ARB_DRAM_TIMING_2, dram_timing);
 432         WREG32(MC_ARB_DRAM_TIMING2_2, dram_timing2);
 433
 434         radeon_atom_set_engine_dram_timings(rdev,
 435                                             state->low.sclk,
 436                                             state->low.mclk);
 437
 438         dram_timing = RREG32(MC_ARB_DRAM_TIMING);
 439         dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
 440
 441         WREG32(MC_ARB_DRAM_TIMING_1, dram_timing);
 442         WREG32(MC_ARB_DRAM_TIMING2_1, dram_timing2);
 443
 444         /* restore the boot dram timings */
 445         WREG32(MC_ARB_DRAM_TIMING, old_dram_timing);
 446         WREG32(MC_ARB_DRAM_TIMING2, old_dram_timing2);
 447
 448 }
 449
 450 void rv730_start_dpm(struct radeon_device *rdev)
 451 {
 452         WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF);
 453
 454         WREG32_P(TCI_MCLK_PWRMGT_CNTL, 0, ~MPLL_PWRMGT_OFF);
 455
 456         WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN);
 457 }
 458
 459 void rv730_stop_dpm(struct radeon_device *rdev)
 460 {
 461         PPSMC_Result result;
 462
 463         result = rv770_send_msg_to_smc(rdev, PPSMC_MSG_TwoLevelsDisabled);
 464
 465         if (result != PPSMC_Result_OK)
 466                 DRM_DEBUG("Could not force DPM to low\n");
 467
 468         WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN);
 469
 470         WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF);
 471
 472         WREG32_P(TCI_MCLK_PWRMGT_CNTL, MPLL_PWRMGT_OFF, ~MPLL_PWRMGT_OFF);
 473 }
 474
 475 void rv730_program_dcodt(struct radeon_device *rdev, bool use_dcodt)
 476 {
 477         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
 478         u32 i = use_dcodt ? 0 : 1;
 479         u32 mc4_io_pad_cntl;
 480
 481         mc4_io_pad_cntl = RREG32(MC4_IO_DQ_PAD_CNTL_D0_I0);
 482         mc4_io_pad_cntl &= 0xFFFFFF00;
 483         mc4_io_pad_cntl |= pi->odt_value_0[i];
 484         WREG32(MC4_IO_DQ_PAD_CNTL_D0_I0, mc4_io_pad_cntl);
 485         WREG32(MC4_IO_DQ_PAD_CNTL_D0_I1, mc4_io_pad_cntl);
 486
 487         mc4_io_pad_cntl = RREG32(MC4_IO_QS_PAD_CNTL_D0_I0);
 488         mc4_io_pad_cntl &= 0xFFFFFF00;
 489         mc4_io_pad_cntl |= pi->odt_value_1[i];
 490         WREG32(MC4_IO_QS_PAD_CNTL_D0_I0, mc4_io_pad_cntl);
 491         WREG32(MC4_IO_QS_PAD_CNTL_D0_I1, mc4_io_pad_cntl);
 492 }
 493
 494 void rv730_get_odt_values(struct radeon_device *rdev)
 495 {
 496         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
 497         u32 mc4_io_pad_cntl;
 498
 499         pi->odt_value_0[0] = (u8)0;
 500         pi->odt_value_1[0] = (u8)0x80;
 501
 502         mc4_io_pad_cntl = RREG32(MC4_IO_DQ_PAD_CNTL_D0_I0);
 503         pi->odt_value_0[1] = (u8)(mc4_io_pad_cntl & 0xff);
 504
 505         mc4_io_pad_cntl = RREG32(MC4_IO_QS_PAD_CNTL_D0_I0);
 506         pi->odt_value_1[1] = (u8)(mc4_io_pad_cntl & 0xff);
 507 }