drivers/gpu/drm/rcar-du/rcar_du_drv.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * rcar_du_drv.c  --  R-Car Display Unit DRM driver
   4  *
   5  * Copyright (C) 2013-2015 Renesas Electronics Corporation
   6  *
   7  * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
   8  */
   9
  10 #include <linux/clk.h>
  11 #include <linux/io.h>
  12 #include <linux/mm.h>
  13 #include <linux/module.h>
  14 #include <linux/of_device.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/pm.h>
  17 #include <linux/slab.h>
  18 #include <linux/wait.h>
  19
  20 #include <drm/drm_atomic_helper.h>
  21 #include <drm/drm_fb_cma_helper.h>
  22 #include <drm/drm_fb_helper.h>
  23 #include <drm/drm_drv.h>
  24 #include <drm/drm_gem_cma_helper.h>
  25 #include <drm/drm_probe_helper.h>
  26
  27 #include "rcar_du_drv.h"
  28 #include "rcar_du_kms.h"
  29 #include "rcar_du_of.h"
  30 #include "rcar_du_regs.h"
  31
  32 /* -----------------------------------------------------------------------------
  33  * Device Information
  34  */
  35
  36 static const struct rcar_du_device_info rzg1_du_r8a7743_info = {
  37         .gen = 2,
  38         .features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK
  39                   | RCAR_DU_FEATURE_INTERLACED
  40                   | RCAR_DU_FEATURE_TVM_SYNC,
  41         .channels_mask = BIT(1) | BIT(0),
  42         .routes = {
  43                 /*
  44                  * R8A774[34] has one RGB output and one LVDS output
  45                  */
  46                 [RCAR_DU_OUTPUT_DPAD0] = {
  47                         .possible_crtcs = BIT(1) | BIT(0),
  48                         .port = 0,
  49                 },
  50                 [RCAR_DU_OUTPUT_LVDS0] = {
  51                         .possible_crtcs = BIT(0),
  52                         .port = 1,
  53                 },
  54         },
  55         .num_lvds = 1,
  56 };
  57
  58 static const struct rcar_du_device_info rzg1_du_r8a7745_info = {
  59         .gen = 2,
  60         .features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK
  61                   | RCAR_DU_FEATURE_INTERLACED
  62                   | RCAR_DU_FEATURE_TVM_SYNC,
  63         .channels_mask = BIT(1) | BIT(0),
  64         .routes = {
  65                 /*
  66                  * R8A7745 has two RGB outputs
  67                  */
  68                 [RCAR_DU_OUTPUT_DPAD0] = {
  69                         .possible_crtcs = BIT(0),
  70                         .port = 0,
  71                 },
  72                 [RCAR_DU_OUTPUT_DPAD1] = {
  73                         .possible_crtcs = BIT(1),
  74                         .port = 1,
  75                 },
  76         },
  77 };
  78
  79 static const struct rcar_du_device_info rzg1_du_r8a77470_info = {
  80         .gen = 2,
  81         .features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK
  82                   | RCAR_DU_FEATURE_INTERLACED
  83                   | RCAR_DU_FEATURE_TVM_SYNC,
  84         .channels_mask = BIT(1) | BIT(0),
  85         .routes = {
  86                 /*
  87                  * R8A77470 has two RGB outputs, one LVDS output, and
  88                  * one (currently unsupported) analog video output
  89                  */
  90                 [RCAR_DU_OUTPUT_DPAD0] = {
  91                         .possible_crtcs = BIT(0),
  92                         .port = 0,
  93                 },
  94                 [RCAR_DU_OUTPUT_DPAD1] = {
  95                         .possible_crtcs = BIT(1),
  96                         .port = 1,
  97                 },
  98                 [RCAR_DU_OUTPUT_LVDS0] = {
  99                         .possible_crtcs = BIT(0) | BIT(1),
 100                         .port = 2,
 101                 },
 102         },
 103 };
 104
 105 static const struct rcar_du_device_info rcar_du_r8a774a1_info = {
 106         .gen = 3,
 107         .features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK
 108                   | RCAR_DU_FEATURE_VSP1_SOURCE
 109                   | RCAR_DU_FEATURE_INTERLACED
 110                   | RCAR_DU_FEATURE_TVM_SYNC,
 111         .channels_mask = BIT(2) | BIT(1) | BIT(0),
 112         .routes = {
 113                 /*
 114                  * R8A774A1 has one RGB output, one LVDS output and one HDMI
 115                  * output.
 116                  */
 117                 [RCAR_DU_OUTPUT_DPAD0] = {
 118                         .possible_crtcs = BIT(2),
 119                         .port = 0,
 120                 },
 121                 [RCAR_DU_OUTPUT_HDMI0] = {
 122                         .possible_crtcs = BIT(1),
 123                         .port = 1,
 124                 },
 125                 [RCAR_DU_OUTPUT_LVDS0] = {
 126                         .possible_crtcs = BIT(0),
 127                         .port = 2,
 128                 },
 129         },
 130         .num_lvds = 1,
 131         .dpll_mask =  BIT(1),
 132 };
 133
 134 static const struct rcar_du_device_info rcar_du_r8a774b1_info = {
 135         .gen = 3,
 136         .features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK
 137                   | RCAR_DU_FEATURE_VSP1_SOURCE
 138                   | RCAR_DU_FEATURE_INTERLACED
 139                   | RCAR_DU_FEATURE_TVM_SYNC,
 140         .channels_mask = BIT(3) | BIT(1) | BIT(0),
 141         .routes = {
 142                 /*
 143                  * R8A774B1 has one RGB output, one LVDS output and one HDMI
 144                  * output.
 145                  */
 146                 [RCAR_DU_OUTPUT_DPAD0] = {
 147                         .possible_crtcs = BIT(2),
 148                         .port = 0,
 149                 },
 150                 [RCAR_DU_OUTPUT_HDMI0] = {
 151                         .possible_crtcs = BIT(1),
 152                         .port = 1,
 153                 },
 154                 [RCAR_DU_OUTPUT_LVDS0] = {
 155                         .possible_crtcs = BIT(0),
 156                         .port = 2,
 157                 },
 158         },
 159         .num_lvds = 1,
 160         .dpll_mask =  BIT(1),
 161 };
 162
 163 static const struct rcar_du_device_info rcar_du_r8a774c0_info = {
 164         .gen = 3,
 165         .features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK
 166                   | RCAR_DU_FEATURE_VSP1_SOURCE,
 167         .channels_mask = BIT(1) | BIT(0),
 168         .routes = {
 169                 /*
 170                  * R8A774C0 has one RGB output and two LVDS outputs
 171                  */
 172                 [RCAR_DU_OUTPUT_DPAD0] = {
 173                         .possible_crtcs = BIT(0) | BIT(1),
 174                         .port = 0,
 175                 },
 176                 [RCAR_DU_OUTPUT_LVDS0] = {
 177                         .possible_crtcs = BIT(0),
 178                         .port = 1,
 179                 },
 180                 [RCAR_DU_OUTPUT_LVDS1] = {
 181                         .possible_crtcs = BIT(1),
 182                         .port = 2,
 183                 },
 184         },
 185         .num_lvds = 2,
 186         .lvds_clk_mask =  BIT(1) | BIT(0),
 187 };
 188
 189 static const struct rcar_du_device_info rcar_du_r8a7779_info = {
 190         .gen = 1,
 191         .features = RCAR_DU_FEATURE_INTERLACED
 192                   | RCAR_DU_FEATURE_TVM_SYNC,
 193         .channels_mask = BIT(1) | BIT(0),
 194         .routes = {
 195                 /*
 196                  * R8A7779 has two RGB outputs and one (currently unsupported)
 197                  * TCON output.
 198                  */
 199                 [RCAR_DU_OUTPUT_DPAD0] = {
 200                         .possible_crtcs = BIT(0),
 201                         .port = 0,
 202                 },
 203                 [RCAR_DU_OUTPUT_DPAD1] = {
 204                         .possible_crtcs = BIT(1) | BIT(0),
 205                         .port = 1,
 206                 },
 207         },
 208 };
 209
 210 static const struct rcar_du_device_info rcar_du_r8a7790_info = {
 211         .gen = 2,
 212         .features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK
 213                   | RCAR_DU_FEATURE_INTERLACED
 214                   | RCAR_DU_FEATURE_TVM_SYNC,
 215         .quirks = RCAR_DU_QUIRK_ALIGN_128B,
 216         .channels_mask = BIT(2) | BIT(1) | BIT(0),
 217         .routes = {
 218                 /*
 219                  * R8A7790 has one RGB output, two LVDS outputs and one
 220                  * (currently unsupported) TCON output.
 221                  */
 222                 [RCAR_DU_OUTPUT_DPAD0] = {
 223                         .possible_crtcs = BIT(2) | BIT(1) | BIT(0),
 224                         .port = 0,
 225                 },
 226                 [RCAR_DU_OUTPUT_LVDS0] = {
 227                         .possible_crtcs = BIT(0),
 228                         .port = 1,
 229                 },
 230                 [RCAR_DU_OUTPUT_LVDS1] = {
 231                         .possible_crtcs = BIT(2) | BIT(1),
 232                         .port = 2,
 233                 },
 234         },
 235         .num_lvds = 2,
 236 };
 237
 238 /* M2-W (r8a7791) and M2-N (r8a7793) are identical */
 239 static const struct rcar_du_device_info rcar_du_r8a7791_info = {
 240         .gen = 2,
 241         .features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK
 242                   | RCAR_DU_FEATURE_INTERLACED
 243                   | RCAR_DU_FEATURE_TVM_SYNC,
 244         .channels_mask = BIT(1) | BIT(0),
 245         .routes = {
 246                 /*
 247                  * R8A779[13] has one RGB output, one LVDS output and one
 248                  * (currently unsupported) TCON output.
 249                  */
 250                 [RCAR_DU_OUTPUT_DPAD0] = {
 251                         .possible_crtcs = BIT(1) | BIT(0),
 252                         .port = 0,
 253                 },
 254                 [RCAR_DU_OUTPUT_LVDS0] = {
 255                         .possible_crtcs = BIT(0),
 256                         .port = 1,
 257                 },
 258         },
 259         .num_lvds = 1,
 260 };
 261
 262 static const struct rcar_du_device_info rcar_du_r8a7792_info = {
 263         .gen = 2,
 264         .features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK
 265                   | RCAR_DU_FEATURE_INTERLACED
 266                   | RCAR_DU_FEATURE_TVM_SYNC,
 267         .channels_mask = BIT(1) | BIT(0),
 268         .routes = {
 269                 /* R8A7792 has two RGB outputs. */
 270                 [RCAR_DU_OUTPUT_DPAD0] = {
 271                         .possible_crtcs = BIT(0),
 272                         .port = 0,
 273                 },
 274                 [RCAR_DU_OUTPUT_DPAD1] = {
 275                         .possible_crtcs = BIT(1),
 276                         .port = 1,
 277                 },
 278         },
 279 };
 280
 281 static const struct rcar_du_device_info rcar_du_r8a7794_info = {
 282         .gen = 2,
 283         .features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK
 284                   | RCAR_DU_FEATURE_INTERLACED
 285                   | RCAR_DU_FEATURE_TVM_SYNC,
 286         .channels_mask = BIT(1) | BIT(0),
 287         .routes = {
 288                 /*
 289                  * R8A7794 has two RGB outputs and one (currently unsupported)
 290                  * TCON output.
 291                  */
 292                 [RCAR_DU_OUTPUT_DPAD0] = {
 293                         .possible_crtcs = BIT(0),
 294                         .port = 0,
 295                 },
 296                 [RCAR_DU_OUTPUT_DPAD1] = {
 297                         .possible_crtcs = BIT(1),
 298                         .port = 1,
 299                 },
 300         },
 301 };
 302
 303 static const struct rcar_du_device_info rcar_du_r8a7795_info = {
 304         .gen = 3,
 305         .features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK
 306                   | RCAR_DU_FEATURE_VSP1_SOURCE
 307                   | RCAR_DU_FEATURE_INTERLACED
 308                   | RCAR_DU_FEATURE_TVM_SYNC,
 309         .channels_mask = BIT(3) | BIT(2) | BIT(1) | BIT(0),
 310         .routes = {
 311                 /*
 312                  * R8A7795 has one RGB output, two HDMI outputs and one
 313                  * LVDS output.
 314                  */
 315                 [RCAR_DU_OUTPUT_DPAD0] = {
 316                         .possible_crtcs = BIT(3),
 317                         .port = 0,
 318                 },
 319                 [RCAR_DU_OUTPUT_HDMI0] = {
 320                         .possible_crtcs = BIT(1),
 321                         .port = 1,
 322                 },
 323                 [RCAR_DU_OUTPUT_HDMI1] = {
 324                         .possible_crtcs = BIT(2),
 325                         .port = 2,
 326                 },
 327                 [RCAR_DU_OUTPUT_LVDS0] = {
 328                         .possible_crtcs = BIT(0),
 329                         .port = 3,
 330                 },
 331         },
 332         .num_lvds = 1,
 333         .dpll_mask =  BIT(2) | BIT(1),
 334 };
 335
 336 static const struct rcar_du_device_info rcar_du_r8a7796_info = {
 337         .gen = 3,
 338         .features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK
 339                   | RCAR_DU_FEATURE_VSP1_SOURCE
 340                   | RCAR_DU_FEATURE_INTERLACED
 341                   | RCAR_DU_FEATURE_TVM_SYNC,
 342         .channels_mask = BIT(2) | BIT(1) | BIT(0),
 343         .routes = {
 344                 /*
 345                  * R8A7796 has one RGB output, one LVDS output and one HDMI
 346                  * output.
 347                  */
 348                 [RCAR_DU_OUTPUT_DPAD0] = {
 349                         .possible_crtcs = BIT(2),
 350                         .port = 0,
 351                 },
 352                 [RCAR_DU_OUTPUT_HDMI0] = {
 353                         .possible_crtcs = BIT(1),
 354                         .port = 1,
 355                 },
 356                 [RCAR_DU_OUTPUT_LVDS0] = {
 357                         .possible_crtcs = BIT(0),
 358                         .port = 2,
 359                 },
 360         },
 361         .num_lvds = 1,
 362         .dpll_mask =  BIT(1),
 363 };
 364
 365 static const struct rcar_du_device_info rcar_du_r8a77965_info = {
 366         .gen = 3,
 367         .features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK
 368                   | RCAR_DU_FEATURE_VSP1_SOURCE
 369                   | RCAR_DU_FEATURE_INTERLACED
 370                   | RCAR_DU_FEATURE_TVM_SYNC,
 371         .channels_mask = BIT(3) | BIT(1) | BIT(0),
 372         .routes = {
 373                 /*
 374                  * R8A77965 has one RGB output, one LVDS output and one HDMI
 375                  * output.
 376                  */
 377                 [RCAR_DU_OUTPUT_DPAD0] = {
 378                         .possible_crtcs = BIT(2),
 379                         .port = 0,
 380                 },
 381                 [RCAR_DU_OUTPUT_HDMI0] = {
 382                         .possible_crtcs = BIT(1),
 383                         .port = 1,
 384                 },
 385                 [RCAR_DU_OUTPUT_LVDS0] = {
 386                         .possible_crtcs = BIT(0),
 387                         .port = 2,
 388                 },
 389         },
 390         .num_lvds = 1,
 391         .dpll_mask =  BIT(1),
 392 };
 393
 394 static const struct rcar_du_device_info rcar_du_r8a77970_info = {
 395         .gen = 3,
 396         .features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK
 397                   | RCAR_DU_FEATURE_VSP1_SOURCE
 398                   | RCAR_DU_FEATURE_INTERLACED
 399                   | RCAR_DU_FEATURE_TVM_SYNC,
 400         .channels_mask = BIT(0),
 401         .routes = {
 402                 /*
 403                  * R8A77970 and R8A77980 have one RGB output and one LVDS
 404                  * output.
 405                  */
 406                 [RCAR_DU_OUTPUT_DPAD0] = {
 407                         .possible_crtcs = BIT(0),
 408                         .port = 0,
 409                 },
 410                 [RCAR_DU_OUTPUT_LVDS0] = {
 411                         .possible_crtcs = BIT(0),
 412                         .port = 1,
 413                 },
 414         },
 415         .num_lvds = 1,
 416 };
 417
 418 static const struct rcar_du_device_info rcar_du_r8a7799x_info = {
 419         .gen = 3,
 420         .features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK
 421                   | RCAR_DU_FEATURE_VSP1_SOURCE,
 422         .channels_mask = BIT(1) | BIT(0),
 423         .routes = {
 424                 /*
 425                  * R8A77990 and R8A77995 have one RGB output and two LVDS
 426                  * outputs.
 427                  */
 428                 [RCAR_DU_OUTPUT_DPAD0] = {
 429                         .possible_crtcs = BIT(0) | BIT(1),
 430                         .port = 0,
 431                 },
 432                 [RCAR_DU_OUTPUT_LVDS0] = {
 433                         .possible_crtcs = BIT(0),
 434                         .port = 1,
 435                 },
 436                 [RCAR_DU_OUTPUT_LVDS1] = {
 437                         .possible_crtcs = BIT(1),
 438                         .port = 2,
 439                 },
 440         },
 441         .num_lvds = 2,
 442         .lvds_clk_mask =  BIT(1) | BIT(0),
 443 };
 444
 445 static const struct of_device_id rcar_du_of_table[] = {
 446         { .compatible = "renesas,du-r8a7743", .data = &rzg1_du_r8a7743_info },
 447         { .compatible = "renesas,du-r8a7744", .data = &rzg1_du_r8a7743_info },
 448         { .compatible = "renesas,du-r8a7745", .data = &rzg1_du_r8a7745_info },
 449         { .compatible = "renesas,du-r8a77470", .data = &rzg1_du_r8a77470_info },
 450         { .compatible = "renesas,du-r8a774a1", .data = &rcar_du_r8a774a1_info },
 451         { .compatible = "renesas,du-r8a774b1", .data = &rcar_du_r8a774b1_info },
 452         { .compatible = "renesas,du-r8a774c0", .data = &rcar_du_r8a774c0_info },
 453         { .compatible = "renesas,du-r8a7779", .data = &rcar_du_r8a7779_info },
 454         { .compatible = "renesas,du-r8a7790", .data = &rcar_du_r8a7790_info },
 455         { .compatible = "renesas,du-r8a7791", .data = &rcar_du_r8a7791_info },
 456         { .compatible = "renesas,du-r8a7792", .data = &rcar_du_r8a7792_info },
 457         { .compatible = "renesas,du-r8a7793", .data = &rcar_du_r8a7791_info },
 458         { .compatible = "renesas,du-r8a7794", .data = &rcar_du_r8a7794_info },
 459         { .compatible = "renesas,du-r8a7795", .data = &rcar_du_r8a7795_info },
 460         { .compatible = "renesas,du-r8a7796", .data = &rcar_du_r8a7796_info },
 461         { .compatible = "renesas,du-r8a77965", .data = &rcar_du_r8a77965_info },
 462         { .compatible = "renesas,du-r8a77970", .data = &rcar_du_r8a77970_info },
 463         { .compatible = "renesas,du-r8a77980", .data = &rcar_du_r8a77970_info },
 464         { .compatible = "renesas,du-r8a77990", .data = &rcar_du_r8a7799x_info },
 465         { .compatible = "renesas,du-r8a77995", .data = &rcar_du_r8a7799x_info },
 466         { }
 467 };
 468
 469 MODULE_DEVICE_TABLE(of, rcar_du_of_table);
 470
 471 /* -----------------------------------------------------------------------------
 472  * DRM operations
 473  */
 474
 475 DEFINE_DRM_GEM_CMA_FOPS(rcar_du_fops);
 476
 477 static struct drm_driver rcar_du_driver = {
 478         .driver_features        = DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC,
 479         .gem_free_object_unlocked = drm_gem_cma_free_object,
 480         .gem_vm_ops             = &drm_gem_cma_vm_ops,
 481         .prime_handle_to_fd     = drm_gem_prime_handle_to_fd,
 482         .prime_fd_to_handle     = drm_gem_prime_fd_to_handle,
 483         .gem_prime_get_sg_table = drm_gem_cma_prime_get_sg_table,
 484         .gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table,
 485         .gem_prime_vmap         = drm_gem_cma_prime_vmap,
 486         .gem_prime_vunmap       = drm_gem_cma_prime_vunmap,
 487         .gem_prime_mmap         = drm_gem_cma_prime_mmap,
 488         .dumb_create            = rcar_du_dumb_create,
 489         .fops                   = &rcar_du_fops,
 490         .name                   = "rcar-du",
 491         .desc                   = "Renesas R-Car Display Unit",
 492         .date                   = "20130110",
 493         .major                  = 1,
 494         .minor                  = 0,
 495 };
 496
 497 /* -----------------------------------------------------------------------------
 498  * Power management
 499  */
 500
 501 #ifdef CONFIG_PM_SLEEP
 502 static int rcar_du_pm_suspend(struct device *dev)
 503 {
 504         struct rcar_du_device *rcdu = dev_get_drvdata(dev);
 505
 506         return drm_mode_config_helper_suspend(rcdu->ddev);
 507 }
 508
 509 static int rcar_du_pm_resume(struct device *dev)
 510 {
 511         struct rcar_du_device *rcdu = dev_get_drvdata(dev);
 512
 513         return drm_mode_config_helper_resume(rcdu->ddev);
 514 }
 515 #endif
 516
 517 static const struct dev_pm_ops rcar_du_pm_ops = {
 518         SET_SYSTEM_SLEEP_PM_OPS(rcar_du_pm_suspend, rcar_du_pm_resume)
 519 };
 520
 521 /* -----------------------------------------------------------------------------
 522  * Platform driver
 523  */
 524
 525 static int rcar_du_remove(struct platform_device *pdev)
 526 {
 527         struct rcar_du_device *rcdu = platform_get_drvdata(pdev);
 528         struct drm_device *ddev = rcdu->ddev;
 529
 530         drm_dev_unregister(ddev);
 531
 532         drm_kms_helper_poll_fini(ddev);
 533         drm_mode_config_cleanup(ddev);
 534
 535         drm_dev_put(ddev);
 536
 537         return 0;
 538 }
 539
 540 static int rcar_du_probe(struct platform_device *pdev)
 541 {
 542         struct rcar_du_device *rcdu;
 543         struct drm_device *ddev;
 544         struct resource *mem;
 545         int ret;
 546
 547         /* Allocate and initialize the R-Car device structure. */
 548         rcdu = devm_kzalloc(&pdev->dev, sizeof(*rcdu), GFP_KERNEL);
 549         if (rcdu == NULL)
 550                 return -ENOMEM;
 551
 552         rcdu->dev = &pdev->dev;
 553         rcdu->info = of_device_get_match_data(rcdu->dev);
 554
 555         platform_set_drvdata(pdev, rcdu);
 556
 557         /* I/O resources */
 558         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 559         rcdu->mmio = devm_ioremap_resource(&pdev->dev, mem);
 560         if (IS_ERR(rcdu->mmio))
 561                 return PTR_ERR(rcdu->mmio);
 562
 563         /* DRM/KMS objects */
 564         ddev = drm_dev_alloc(&rcar_du_driver, &pdev->dev);
 565         if (IS_ERR(ddev))
 566                 return PTR_ERR(ddev);
 567
 568         rcdu->ddev = ddev;
 569         ddev->dev_private = rcdu;
 570
 571         ret = rcar_du_modeset_init(rcdu);
 572         if (ret < 0) {
 573                 if (ret != -EPROBE_DEFER)
 574                         dev_err(&pdev->dev,
 575                                 "failed to initialize DRM/KMS (%d)\n", ret);
 576                 goto error;
 577         }
 578
 579         ddev->irq_enabled = 1;
 580
 581         /*
 582          * Register the DRM device with the core and the connectors with
 583          * sysfs.
 584          */
 585         ret = drm_dev_register(ddev, 0);
 586         if (ret)
 587                 goto error;
 588
 589         DRM_INFO("Device %s probed\n", dev_name(&pdev->dev));
 590
 591         drm_fbdev_generic_setup(ddev, 32);
 592
 593         return 0;
 594
 595 error:
 596         rcar_du_remove(pdev);
 597
 598         return ret;
 599 }
 600
 601 static struct platform_driver rcar_du_platform_driver = {
 602         .probe          = rcar_du_probe,
 603         .remove         = rcar_du_remove,
 604         .driver         = {
 605                 .name   = "rcar-du",
 606                 .pm     = &rcar_du_pm_ops,
 607                 .of_match_table = rcar_du_of_table,
 608         },
 609 };
 610
 611 static int __init rcar_du_init(void)
 612 {
 613         rcar_du_of_init(rcar_du_of_table);
 614
 615         return platform_driver_register(&rcar_du_platform_driver);
 616 }
 617 module_init(rcar_du_init);
 618
 619 static void __exit rcar_du_exit(void)
 620 {
 621         platform_driver_unregister(&rcar_du_platform_driver);
 622 }
 623 module_exit(rcar_du_exit);
 624
 625 MODULE_AUTHOR("Laurent Pinchart <laurent.pinchart@ideasonboard.com>");
 626 MODULE_DESCRIPTION("Renesas R-Car Display Unit DRM Driver");
 627 MODULE_LICENSE("GPL");