1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) STMicroelectronics SA 2014
4 * Authors: Benjamin Gaignard <benjamin.gaignard@st.com>
5 * Fabien Dessenne <fabien.dessenne@st.com>
6 * for STMicroelectronics.
9 #include <linux/dma-mapping.h>
10 #include <linux/seq_file.h>
12 #include <drm/drm_atomic.h>
13 #include <drm/drm_device.h>
14 #include <drm/drm_fb_cma_helper.h>
15 #include <drm/drm_fourcc.h>
16 #include <drm/drm_gem_cma_helper.h>
18 #include "sti_compositor.h"
20 #include "sti_plane.h"
23 #define ALPHASWITCH BIT(6)
24 #define ENA_COLOR_FILL BIT(8)
25 #define BIGNOTLITTLE BIT(23)
26 #define WAIT_NEXT_VSYNC BIT(31)
28 /* GDP color formats */
29 #define GDP_RGB565 0x00
30 #define GDP_RGB888 0x01
31 #define GDP_RGB888_32 0x02
32 #define GDP_XBGR8888 (GDP_RGB888_32 | BIGNOTLITTLE | ALPHASWITCH)
33 #define GDP_ARGB8565 0x04
34 #define GDP_ARGB8888 0x05
35 #define GDP_ABGR8888 (GDP_ARGB8888 | BIGNOTLITTLE | ALPHASWITCH)
36 #define GDP_ARGB1555 0x06
37 #define GDP_ARGB4444 0x07
39 #define GDP2STR(fmt) { GDP_ ## fmt, #fmt }
41 static struct gdp_format_to_str
{
44 } gdp_format_to_str
[] = {
56 #define GAM_GDP_CTL_OFFSET 0x00
57 #define GAM_GDP_AGC_OFFSET 0x04
58 #define GAM_GDP_VPO_OFFSET 0x0C
59 #define GAM_GDP_VPS_OFFSET 0x10
60 #define GAM_GDP_PML_OFFSET 0x14
61 #define GAM_GDP_PMP_OFFSET 0x18
62 #define GAM_GDP_SIZE_OFFSET 0x1C
63 #define GAM_GDP_NVN_OFFSET 0x24
64 #define GAM_GDP_KEY1_OFFSET 0x28
65 #define GAM_GDP_KEY2_OFFSET 0x2C
66 #define GAM_GDP_PPT_OFFSET 0x34
67 #define GAM_GDP_CML_OFFSET 0x3C
68 #define GAM_GDP_MST_OFFSET 0x68
70 #define GAM_GDP_ALPHARANGE_255 BIT(5)
71 #define GAM_GDP_AGC_FULL_RANGE 0x00808080
72 #define GAM_GDP_PPT_IGNORE (BIT(1) | BIT(0))
74 #define GAM_GDP_SIZE_MAX_WIDTH 3840
75 #define GAM_GDP_SIZE_MAX_HEIGHT 2160
77 #define GDP_NODE_NB_BANK 2
78 #define GDP_NODE_PER_FIELD 2
99 struct sti_gdp_node_list
{
100 struct sti_gdp_node
*top_field
;
101 dma_addr_t top_field_paddr
;
102 struct sti_gdp_node
*btm_field
;
103 dma_addr_t btm_field_paddr
;
109 * @sti_plane: sti_plane structure
110 * @dev: driver device
111 * @regs: gdp registers
112 * @clk_pix: pixel clock for the current gdp
113 * @clk_main_parent: gdp parent clock if main path used
114 * @clk_aux_parent: gdp parent clock if aux path used
115 * @vtg_field_nb: callback for VTG FIELD (top or bottom) notification
116 * @is_curr_top: true if the current node processed is the top field
117 * @node_list: array of node list
118 * @vtg: registered vtg
121 struct sti_plane plane
;
125 struct clk
*clk_main_parent
;
126 struct clk
*clk_aux_parent
;
127 struct notifier_block vtg_field_nb
;
129 struct sti_gdp_node_list node_list
[GDP_NODE_NB_BANK
];
133 #define to_sti_gdp(x) container_of(x, struct sti_gdp, plane)
135 static const uint32_t gdp_supported_formats
[] = {
146 #define DBGFS_DUMP(reg) seq_printf(s, "\n %-25s 0x%08X", #reg, \
147 readl(gdp->regs + reg ## _OFFSET))
149 static void gdp_dbg_ctl(struct seq_file
*s
, int val
)
153 seq_puts(s
, "\tColor:");
154 for (i
= 0; i
< ARRAY_SIZE(gdp_format_to_str
); i
++) {
155 if (gdp_format_to_str
[i
].format
== (val
& 0x1F)) {
156 seq_puts(s
, gdp_format_to_str
[i
].name
);
160 if (i
== ARRAY_SIZE(gdp_format_to_str
))
161 seq_puts(s
, "<UNKNOWN>");
163 seq_printf(s
, "\tWaitNextVsync:%d", val
& WAIT_NEXT_VSYNC
? 1 : 0);
166 static void gdp_dbg_vpo(struct seq_file
*s
, int val
)
168 seq_printf(s
, "\txdo:%4d\tydo:%4d", val
& 0xFFFF, (val
>> 16) & 0xFFFF);
171 static void gdp_dbg_vps(struct seq_file
*s
, int val
)
173 seq_printf(s
, "\txds:%4d\tyds:%4d", val
& 0xFFFF, (val
>> 16) & 0xFFFF);
176 static void gdp_dbg_size(struct seq_file
*s
, int val
)
178 seq_printf(s
, "\t%d x %d", val
& 0xFFFF, (val
>> 16) & 0xFFFF);
181 static void gdp_dbg_nvn(struct seq_file
*s
, struct sti_gdp
*gdp
, int val
)
186 for (i
= 0; i
< GDP_NODE_NB_BANK
; i
++) {
187 if (gdp
->node_list
[i
].top_field_paddr
== val
) {
188 base
= gdp
->node_list
[i
].top_field
;
191 if (gdp
->node_list
[i
].btm_field_paddr
== val
) {
192 base
= gdp
->node_list
[i
].btm_field
;
198 seq_printf(s
, "\tVirt @: %p", base
);
201 static void gdp_dbg_ppt(struct seq_file
*s
, int val
)
203 if (val
& GAM_GDP_PPT_IGNORE
)
204 seq_puts(s
, "\tNot displayed on mixer!");
207 static void gdp_dbg_mst(struct seq_file
*s
, int val
)
210 seq_puts(s
, "\tBUFFER UNDERFLOW!");
213 static int gdp_dbg_show(struct seq_file
*s
, void *data
)
215 struct drm_info_node
*node
= s
->private;
216 struct sti_gdp
*gdp
= (struct sti_gdp
*)node
->info_ent
->data
;
217 struct drm_plane
*drm_plane
= &gdp
->plane
.drm_plane
;
218 struct drm_crtc
*crtc
;
220 drm_modeset_lock(&drm_plane
->mutex
, NULL
);
221 crtc
= drm_plane
->state
->crtc
;
222 drm_modeset_unlock(&drm_plane
->mutex
);
224 seq_printf(s
, "%s: (vaddr = 0x%p)",
225 sti_plane_to_str(&gdp
->plane
), gdp
->regs
);
227 DBGFS_DUMP(GAM_GDP_CTL
);
228 gdp_dbg_ctl(s
, readl(gdp
->regs
+ GAM_GDP_CTL_OFFSET
));
229 DBGFS_DUMP(GAM_GDP_AGC
);
230 DBGFS_DUMP(GAM_GDP_VPO
);
231 gdp_dbg_vpo(s
, readl(gdp
->regs
+ GAM_GDP_VPO_OFFSET
));
232 DBGFS_DUMP(GAM_GDP_VPS
);
233 gdp_dbg_vps(s
, readl(gdp
->regs
+ GAM_GDP_VPS_OFFSET
));
234 DBGFS_DUMP(GAM_GDP_PML
);
235 DBGFS_DUMP(GAM_GDP_PMP
);
236 DBGFS_DUMP(GAM_GDP_SIZE
);
237 gdp_dbg_size(s
, readl(gdp
->regs
+ GAM_GDP_SIZE_OFFSET
));
238 DBGFS_DUMP(GAM_GDP_NVN
);
239 gdp_dbg_nvn(s
, gdp
, readl(gdp
->regs
+ GAM_GDP_NVN_OFFSET
));
240 DBGFS_DUMP(GAM_GDP_KEY1
);
241 DBGFS_DUMP(GAM_GDP_KEY2
);
242 DBGFS_DUMP(GAM_GDP_PPT
);
243 gdp_dbg_ppt(s
, readl(gdp
->regs
+ GAM_GDP_PPT_OFFSET
));
244 DBGFS_DUMP(GAM_GDP_CML
);
245 DBGFS_DUMP(GAM_GDP_MST
);
246 gdp_dbg_mst(s
, readl(gdp
->regs
+ GAM_GDP_MST_OFFSET
));
250 seq_puts(s
, " Not connected to any DRM CRTC\n");
252 seq_printf(s
, " Connected to DRM CRTC #%d (%s)\n",
253 crtc
->base
.id
, sti_mixer_to_str(to_sti_mixer(crtc
)));
258 static void gdp_node_dump_node(struct seq_file
*s
, struct sti_gdp_node
*node
)
260 seq_printf(s
, "\t@:0x%p", node
);
261 seq_printf(s
, "\n\tCTL 0x%08X", node
->gam_gdp_ctl
);
262 gdp_dbg_ctl(s
, node
->gam_gdp_ctl
);
263 seq_printf(s
, "\n\tAGC 0x%08X", node
->gam_gdp_agc
);
264 seq_printf(s
, "\n\tVPO 0x%08X", node
->gam_gdp_vpo
);
265 gdp_dbg_vpo(s
, node
->gam_gdp_vpo
);
266 seq_printf(s
, "\n\tVPS 0x%08X", node
->gam_gdp_vps
);
267 gdp_dbg_vps(s
, node
->gam_gdp_vps
);
268 seq_printf(s
, "\n\tPML 0x%08X", node
->gam_gdp_pml
);
269 seq_printf(s
, "\n\tPMP 0x%08X", node
->gam_gdp_pmp
);
270 seq_printf(s
, "\n\tSIZE 0x%08X", node
->gam_gdp_size
);
271 gdp_dbg_size(s
, node
->gam_gdp_size
);
272 seq_printf(s
, "\n\tNVN 0x%08X", node
->gam_gdp_nvn
);
273 seq_printf(s
, "\n\tKEY1 0x%08X", node
->gam_gdp_key1
);
274 seq_printf(s
, "\n\tKEY2 0x%08X", node
->gam_gdp_key2
);
275 seq_printf(s
, "\n\tPPT 0x%08X", node
->gam_gdp_ppt
);
276 gdp_dbg_ppt(s
, node
->gam_gdp_ppt
);
277 seq_printf(s
, "\n\tCML 0x%08X\n", node
->gam_gdp_cml
);
280 static int gdp_node_dbg_show(struct seq_file
*s
, void *arg
)
282 struct drm_info_node
*node
= s
->private;
283 struct sti_gdp
*gdp
= (struct sti_gdp
*)node
->info_ent
->data
;
286 for (b
= 0; b
< GDP_NODE_NB_BANK
; b
++) {
287 seq_printf(s
, "\n%s[%d].top", sti_plane_to_str(&gdp
->plane
), b
);
288 gdp_node_dump_node(s
, gdp
->node_list
[b
].top_field
);
289 seq_printf(s
, "\n%s[%d].btm", sti_plane_to_str(&gdp
->plane
), b
);
290 gdp_node_dump_node(s
, gdp
->node_list
[b
].btm_field
);
296 static struct drm_info_list gdp0_debugfs_files
[] = {
297 { "gdp0", gdp_dbg_show
, 0, NULL
},
298 { "gdp0_node", gdp_node_dbg_show
, 0, NULL
},
301 static struct drm_info_list gdp1_debugfs_files
[] = {
302 { "gdp1", gdp_dbg_show
, 0, NULL
},
303 { "gdp1_node", gdp_node_dbg_show
, 0, NULL
},
306 static struct drm_info_list gdp2_debugfs_files
[] = {
307 { "gdp2", gdp_dbg_show
, 0, NULL
},
308 { "gdp2_node", gdp_node_dbg_show
, 0, NULL
},
311 static struct drm_info_list gdp3_debugfs_files
[] = {
312 { "gdp3", gdp_dbg_show
, 0, NULL
},
313 { "gdp3_node", gdp_node_dbg_show
, 0, NULL
},
316 static int gdp_debugfs_init(struct sti_gdp
*gdp
, struct drm_minor
*minor
)
319 struct drm_info_list
*gdp_debugfs_files
;
322 switch (gdp
->plane
.desc
) {
324 gdp_debugfs_files
= gdp0_debugfs_files
;
325 nb_files
= ARRAY_SIZE(gdp0_debugfs_files
);
328 gdp_debugfs_files
= gdp1_debugfs_files
;
329 nb_files
= ARRAY_SIZE(gdp1_debugfs_files
);
332 gdp_debugfs_files
= gdp2_debugfs_files
;
333 nb_files
= ARRAY_SIZE(gdp2_debugfs_files
);
336 gdp_debugfs_files
= gdp3_debugfs_files
;
337 nb_files
= ARRAY_SIZE(gdp3_debugfs_files
);
343 for (i
= 0; i
< nb_files
; i
++)
344 gdp_debugfs_files
[i
].data
= gdp
;
346 return drm_debugfs_create_files(gdp_debugfs_files
,
348 minor
->debugfs_root
, minor
);
351 static int sti_gdp_fourcc2format(int fourcc
)
354 case DRM_FORMAT_XRGB8888
:
355 return GDP_RGB888_32
;
356 case DRM_FORMAT_XBGR8888
:
358 case DRM_FORMAT_ARGB8888
:
360 case DRM_FORMAT_ABGR8888
:
362 case DRM_FORMAT_ARGB4444
:
364 case DRM_FORMAT_ARGB1555
:
366 case DRM_FORMAT_RGB565
:
368 case DRM_FORMAT_RGB888
:
374 static int sti_gdp_get_alpharange(int format
)
380 return GAM_GDP_ALPHARANGE_255
;
386 * sti_gdp_get_free_nodes
389 * Look for a GDP node list that is not currently read by the HW.
392 * Pointer to the free GDP node list
394 static struct sti_gdp_node_list
*sti_gdp_get_free_nodes(struct sti_gdp
*gdp
)
399 hw_nvn
= readl(gdp
->regs
+ GAM_GDP_NVN_OFFSET
);
403 for (i
= 0; i
< GDP_NODE_NB_BANK
; i
++)
404 if ((hw_nvn
!= gdp
->node_list
[i
].btm_field_paddr
) &&
405 (hw_nvn
!= gdp
->node_list
[i
].top_field_paddr
))
406 return &gdp
->node_list
[i
];
408 /* in hazardious cases restart with the first node */
409 DRM_ERROR("inconsistent NVN for %s: 0x%08X\n",
410 sti_plane_to_str(&gdp
->plane
), hw_nvn
);
413 return &gdp
->node_list
[0];
417 * sti_gdp_get_current_nodes
420 * Look for GDP nodes that are currently read by the HW.
423 * Pointer to the current GDP node list
426 struct sti_gdp_node_list
*sti_gdp_get_current_nodes(struct sti_gdp
*gdp
)
431 hw_nvn
= readl(gdp
->regs
+ GAM_GDP_NVN_OFFSET
);
435 for (i
= 0; i
< GDP_NODE_NB_BANK
; i
++)
436 if ((hw_nvn
== gdp
->node_list
[i
].btm_field_paddr
) ||
437 (hw_nvn
== gdp
->node_list
[i
].top_field_paddr
))
438 return &gdp
->node_list
[i
];
441 DRM_DEBUG_DRIVER("Warning, NVN 0x%08X for %s does not match any node\n",
442 hw_nvn
, sti_plane_to_str(&gdp
->plane
));
453 static void sti_gdp_disable(struct sti_gdp
*gdp
)
457 DRM_DEBUG_DRIVER("%s\n", sti_plane_to_str(&gdp
->plane
));
459 /* Set the nodes as 'to be ignored on mixer' */
460 for (i
= 0; i
< GDP_NODE_NB_BANK
; i
++) {
461 gdp
->node_list
[i
].top_field
->gam_gdp_ppt
|= GAM_GDP_PPT_IGNORE
;
462 gdp
->node_list
[i
].btm_field
->gam_gdp_ppt
|= GAM_GDP_PPT_IGNORE
;
465 if (sti_vtg_unregister_client(gdp
->vtg
, &gdp
->vtg_field_nb
))
466 DRM_DEBUG_DRIVER("Warning: cannot unregister VTG notifier\n");
469 clk_disable_unprepare(gdp
->clk_pix
);
471 gdp
->plane
.status
= STI_PLANE_DISABLED
;
477 * @nb: notifier block
478 * @event: event message
479 * @data: private data
481 * Handle VTG top field and bottom field event.
486 static int sti_gdp_field_cb(struct notifier_block
*nb
,
487 unsigned long event
, void *data
)
489 struct sti_gdp
*gdp
= container_of(nb
, struct sti_gdp
, vtg_field_nb
);
491 if (gdp
->plane
.status
== STI_PLANE_FLUSHING
) {
492 /* disable need to be synchronize on vsync event */
493 DRM_DEBUG_DRIVER("Vsync event received => disable %s\n",
494 sti_plane_to_str(&gdp
->plane
));
496 sti_gdp_disable(gdp
);
500 case VTG_TOP_FIELD_EVENT
:
501 gdp
->is_curr_top
= true;
503 case VTG_BOTTOM_FIELD_EVENT
:
504 gdp
->is_curr_top
= false;
507 DRM_ERROR("unsupported event: %lu\n", event
);
514 static void sti_gdp_init(struct sti_gdp
*gdp
)
516 struct device_node
*np
= gdp
->dev
->of_node
;
519 unsigned int i
, size
;
521 /* Allocate all the nodes within a single memory page */
522 size
= sizeof(struct sti_gdp_node
) *
523 GDP_NODE_PER_FIELD
* GDP_NODE_NB_BANK
;
524 base
= dma_alloc_wc(gdp
->dev
, size
, &dma_addr
, GFP_KERNEL
);
527 DRM_ERROR("Failed to allocate memory for GDP node\n");
530 memset(base
, 0, size
);
532 for (i
= 0; i
< GDP_NODE_NB_BANK
; i
++) {
533 if (dma_addr
& 0xF) {
534 DRM_ERROR("Mem alignment failed\n");
537 gdp
->node_list
[i
].top_field
= base
;
538 gdp
->node_list
[i
].top_field_paddr
= dma_addr
;
540 DRM_DEBUG_DRIVER("node[%d].top_field=%p\n", i
, base
);
541 base
+= sizeof(struct sti_gdp_node
);
542 dma_addr
+= sizeof(struct sti_gdp_node
);
544 if (dma_addr
& 0xF) {
545 DRM_ERROR("Mem alignment failed\n");
548 gdp
->node_list
[i
].btm_field
= base
;
549 gdp
->node_list
[i
].btm_field_paddr
= dma_addr
;
550 DRM_DEBUG_DRIVER("node[%d].btm_field=%p\n", i
, base
);
551 base
+= sizeof(struct sti_gdp_node
);
552 dma_addr
+= sizeof(struct sti_gdp_node
);
555 if (of_device_is_compatible(np
, "st,stih407-compositor")) {
556 /* GDP of STiH407 chip have its own pixel clock */
559 switch (gdp
->plane
.desc
) {
561 clk_name
= "pix_gdp1";
564 clk_name
= "pix_gdp2";
567 clk_name
= "pix_gdp3";
570 clk_name
= "pix_gdp4";
573 DRM_ERROR("GDP id not recognized\n");
577 gdp
->clk_pix
= devm_clk_get(gdp
->dev
, clk_name
);
578 if (IS_ERR(gdp
->clk_pix
))
579 DRM_ERROR("Cannot get %s clock\n", clk_name
);
581 gdp
->clk_main_parent
= devm_clk_get(gdp
->dev
, "main_parent");
582 if (IS_ERR(gdp
->clk_main_parent
))
583 DRM_ERROR("Cannot get main_parent clock\n");
585 gdp
->clk_aux_parent
= devm_clk_get(gdp
->dev
, "aux_parent");
586 if (IS_ERR(gdp
->clk_aux_parent
))
587 DRM_ERROR("Cannot get aux_parent clock\n");
594 * @dst: requested destination size
597 * Return the cropped / clamped destination size
600 * cropped / clamped destination size
602 static int sti_gdp_get_dst(struct device
*dev
, int dst
, int src
)
608 dev_dbg(dev
, "WARNING: GDP scale not supported, will crop\n");
612 dev_dbg(dev
, "WARNING: GDP scale not supported, will clamp\n");
616 static int sti_gdp_atomic_check(struct drm_plane
*drm_plane
,
617 struct drm_plane_state
*state
)
619 struct sti_plane
*plane
= to_sti_plane(drm_plane
);
620 struct sti_gdp
*gdp
= to_sti_gdp(plane
);
621 struct drm_crtc
*crtc
= state
->crtc
;
622 struct drm_framebuffer
*fb
= state
->fb
;
623 struct drm_crtc_state
*crtc_state
;
624 struct sti_mixer
*mixer
;
625 struct drm_display_mode
*mode
;
626 int dst_x
, dst_y
, dst_w
, dst_h
;
627 int src_x
, src_y
, src_w
, src_h
;
630 /* no need for further checks if the plane is being disabled */
634 mixer
= to_sti_mixer(crtc
);
635 crtc_state
= drm_atomic_get_crtc_state(state
->state
, crtc
);
636 mode
= &crtc_state
->mode
;
637 dst_x
= state
->crtc_x
;
638 dst_y
= state
->crtc_y
;
639 dst_w
= clamp_val(state
->crtc_w
, 0, mode
->hdisplay
- dst_x
);
640 dst_h
= clamp_val(state
->crtc_h
, 0, mode
->vdisplay
- dst_y
);
641 /* src_x are in 16.16 format */
642 src_x
= state
->src_x
>> 16;
643 src_y
= state
->src_y
>> 16;
644 src_w
= clamp_val(state
->src_w
>> 16, 0, GAM_GDP_SIZE_MAX_WIDTH
);
645 src_h
= clamp_val(state
->src_h
>> 16, 0, GAM_GDP_SIZE_MAX_HEIGHT
);
647 format
= sti_gdp_fourcc2format(fb
->format
->format
);
649 DRM_ERROR("Format not supported by GDP %.4s\n",
650 (char *)&fb
->format
->format
);
654 if (!drm_fb_cma_get_gem_obj(fb
, 0)) {
655 DRM_ERROR("Can't get CMA GEM object for fb\n");
660 if (mode
->clock
&& gdp
->clk_pix
) {
662 int rate
= mode
->clock
* 1000;
666 * According to the mixer used, the gdp pixel clock
667 * should have a different parent clock.
669 if (mixer
->id
== STI_MIXER_MAIN
)
670 clkp
= gdp
->clk_main_parent
;
672 clkp
= gdp
->clk_aux_parent
;
675 clk_set_parent(gdp
->clk_pix
, clkp
);
677 res
= clk_set_rate(gdp
->clk_pix
, rate
);
679 DRM_ERROR("Cannot set rate (%dHz) for gdp\n",
685 DRM_DEBUG_KMS("CRTC:%d (%s) drm plane:%d (%s)\n",
686 crtc
->base
.id
, sti_mixer_to_str(mixer
),
687 drm_plane
->base
.id
, sti_plane_to_str(plane
));
688 DRM_DEBUG_KMS("%s dst=(%dx%d)@(%d,%d) - src=(%dx%d)@(%d,%d)\n",
689 sti_plane_to_str(plane
),
690 dst_w
, dst_h
, dst_x
, dst_y
,
691 src_w
, src_h
, src_x
, src_y
);
696 static void sti_gdp_atomic_update(struct drm_plane
*drm_plane
,
697 struct drm_plane_state
*oldstate
)
699 struct drm_plane_state
*state
= drm_plane
->state
;
700 struct sti_plane
*plane
= to_sti_plane(drm_plane
);
701 struct sti_gdp
*gdp
= to_sti_gdp(plane
);
702 struct drm_crtc
*crtc
= state
->crtc
;
703 struct drm_framebuffer
*fb
= state
->fb
;
704 struct drm_display_mode
*mode
;
705 int dst_x
, dst_y
, dst_w
, dst_h
;
706 int src_x
, src_y
, src_w
, src_h
;
707 struct drm_gem_cma_object
*cma_obj
;
708 struct sti_gdp_node_list
*list
;
709 struct sti_gdp_node_list
*curr_list
;
710 struct sti_gdp_node
*top_field
, *btm_field
;
715 u32 ydo
, xdo
, yds
, xds
;
720 if ((oldstate
->fb
== state
->fb
) &&
721 (oldstate
->crtc_x
== state
->crtc_x
) &&
722 (oldstate
->crtc_y
== state
->crtc_y
) &&
723 (oldstate
->crtc_w
== state
->crtc_w
) &&
724 (oldstate
->crtc_h
== state
->crtc_h
) &&
725 (oldstate
->src_x
== state
->src_x
) &&
726 (oldstate
->src_y
== state
->src_y
) &&
727 (oldstate
->src_w
== state
->src_w
) &&
728 (oldstate
->src_h
== state
->src_h
)) {
729 /* No change since last update, do not post cmd */
730 DRM_DEBUG_DRIVER("No change, not posting cmd\n");
731 plane
->status
= STI_PLANE_UPDATED
;
736 struct sti_compositor
*compo
= dev_get_drvdata(gdp
->dev
);
737 struct sti_mixer
*mixer
= to_sti_mixer(crtc
);
739 /* Register gdp callback */
740 gdp
->vtg
= compo
->vtg
[mixer
->id
];
741 sti_vtg_register_client(gdp
->vtg
, &gdp
->vtg_field_nb
, crtc
);
742 clk_prepare_enable(gdp
->clk_pix
);
746 dst_x
= state
->crtc_x
;
747 dst_y
= state
->crtc_y
;
748 dst_w
= clamp_val(state
->crtc_w
, 0, mode
->hdisplay
- dst_x
);
749 dst_h
= clamp_val(state
->crtc_h
, 0, mode
->vdisplay
- dst_y
);
750 /* src_x are in 16.16 format */
751 src_x
= state
->src_x
>> 16;
752 src_y
= state
->src_y
>> 16;
753 src_w
= clamp_val(state
->src_w
>> 16, 0, GAM_GDP_SIZE_MAX_WIDTH
);
754 src_h
= clamp_val(state
->src_h
>> 16, 0, GAM_GDP_SIZE_MAX_HEIGHT
);
756 list
= sti_gdp_get_free_nodes(gdp
);
757 top_field
= list
->top_field
;
758 btm_field
= list
->btm_field
;
760 dev_dbg(gdp
->dev
, "%s %s top_node:0x%p btm_node:0x%p\n", __func__
,
761 sti_plane_to_str(plane
), top_field
, btm_field
);
763 /* build the top field */
764 top_field
->gam_gdp_agc
= GAM_GDP_AGC_FULL_RANGE
;
765 top_field
->gam_gdp_ctl
= WAIT_NEXT_VSYNC
;
766 format
= sti_gdp_fourcc2format(fb
->format
->format
);
767 top_field
->gam_gdp_ctl
|= format
;
768 top_field
->gam_gdp_ctl
|= sti_gdp_get_alpharange(format
);
769 top_field
->gam_gdp_ppt
&= ~GAM_GDP_PPT_IGNORE
;
771 cma_obj
= drm_fb_cma_get_gem_obj(fb
, 0);
773 DRM_DEBUG_DRIVER("drm FB:%d format:%.4s phys@:0x%lx\n", fb
->base
.id
,
774 (char *)&fb
->format
->format
,
775 (unsigned long)cma_obj
->paddr
);
777 /* pixel memory location */
778 bpp
= fb
->format
->cpp
[0];
779 top_field
->gam_gdp_pml
= (u32
)cma_obj
->paddr
+ fb
->offsets
[0];
780 top_field
->gam_gdp_pml
+= src_x
* bpp
;
781 top_field
->gam_gdp_pml
+= src_y
* fb
->pitches
[0];
783 /* output parameters (clamped / cropped) */
784 dst_w
= sti_gdp_get_dst(gdp
->dev
, dst_w
, src_w
);
785 dst_h
= sti_gdp_get_dst(gdp
->dev
, dst_h
, src_h
);
786 ydo
= sti_vtg_get_line_number(*mode
, dst_y
);
787 yds
= sti_vtg_get_line_number(*mode
, dst_y
+ dst_h
- 1);
788 xdo
= sti_vtg_get_pixel_number(*mode
, dst_x
);
789 xds
= sti_vtg_get_pixel_number(*mode
, dst_x
+ dst_w
- 1);
790 top_field
->gam_gdp_vpo
= (ydo
<< 16) | xdo
;
791 top_field
->gam_gdp_vps
= (yds
<< 16) | xds
;
793 /* input parameters */
795 top_field
->gam_gdp_pmp
= fb
->pitches
[0];
796 top_field
->gam_gdp_size
= src_h
<< 16 | src_w
;
798 /* Same content and chained together */
799 memcpy(btm_field
, top_field
, sizeof(*btm_field
));
800 top_field
->gam_gdp_nvn
= list
->btm_field_paddr
;
801 btm_field
->gam_gdp_nvn
= list
->top_field_paddr
;
803 /* Interlaced mode */
804 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
805 btm_field
->gam_gdp_pml
= top_field
->gam_gdp_pml
+
808 /* Update the NVN field of the 'right' field of the current GDP node
809 * (being used by the HW) with the address of the updated ('free') top
811 * - In interlaced mode the 'right' field is the bottom field as we
812 * update frames starting from their top field
813 * - In progressive mode, we update both bottom and top fields which
815 * At the next VSYNC, the updated node list will be used by the HW.
817 curr_list
= sti_gdp_get_current_nodes(gdp
);
818 dma_updated_top
= list
->top_field_paddr
;
819 dma_updated_btm
= list
->btm_field_paddr
;
821 dev_dbg(gdp
->dev
, "Current NVN:0x%X\n",
822 readl(gdp
->regs
+ GAM_GDP_NVN_OFFSET
));
823 dev_dbg(gdp
->dev
, "Posted buff: %lx current buff: %x\n",
824 (unsigned long)cma_obj
->paddr
,
825 readl(gdp
->regs
+ GAM_GDP_PML_OFFSET
));
828 /* First update or invalid node should directly write in the
830 DRM_DEBUG_DRIVER("%s first update (or invalid node)\n",
831 sti_plane_to_str(plane
));
833 writel(gdp
->is_curr_top
?
834 dma_updated_btm
: dma_updated_top
,
835 gdp
->regs
+ GAM_GDP_NVN_OFFSET
);
839 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
840 if (gdp
->is_curr_top
) {
841 /* Do not update in the middle of the frame, but
842 * postpone the update after the bottom field has
844 curr_list
->btm_field
->gam_gdp_nvn
= dma_updated_top
;
846 /* Direct update to avoid one frame delay */
847 writel(dma_updated_top
,
848 gdp
->regs
+ GAM_GDP_NVN_OFFSET
);
851 /* Direct update for progressive to avoid one frame delay */
852 writel(dma_updated_top
, gdp
->regs
+ GAM_GDP_NVN_OFFSET
);
856 sti_plane_update_fps(plane
, true, false);
858 plane
->status
= STI_PLANE_UPDATED
;
861 static void sti_gdp_atomic_disable(struct drm_plane
*drm_plane
,
862 struct drm_plane_state
*oldstate
)
864 struct sti_plane
*plane
= to_sti_plane(drm_plane
);
866 if (!oldstate
->crtc
) {
867 DRM_DEBUG_DRIVER("drm plane:%d not enabled\n",
872 DRM_DEBUG_DRIVER("CRTC:%d (%s) drm plane:%d (%s)\n",
873 oldstate
->crtc
->base
.id
,
874 sti_mixer_to_str(to_sti_mixer(oldstate
->crtc
)),
875 drm_plane
->base
.id
, sti_plane_to_str(plane
));
877 plane
->status
= STI_PLANE_DISABLING
;
880 static const struct drm_plane_helper_funcs sti_gdp_helpers_funcs
= {
881 .atomic_check
= sti_gdp_atomic_check
,
882 .atomic_update
= sti_gdp_atomic_update
,
883 .atomic_disable
= sti_gdp_atomic_disable
,
886 static void sti_gdp_destroy(struct drm_plane
*drm_plane
)
888 DRM_DEBUG_DRIVER("\n");
890 drm_plane_cleanup(drm_plane
);
893 static int sti_gdp_late_register(struct drm_plane
*drm_plane
)
895 struct sti_plane
*plane
= to_sti_plane(drm_plane
);
896 struct sti_gdp
*gdp
= to_sti_gdp(plane
);
898 return gdp_debugfs_init(gdp
, drm_plane
->dev
->primary
);
901 static const struct drm_plane_funcs sti_gdp_plane_helpers_funcs
= {
902 .update_plane
= drm_atomic_helper_update_plane
,
903 .disable_plane
= drm_atomic_helper_disable_plane
,
904 .destroy
= sti_gdp_destroy
,
905 .reset
= sti_plane_reset
,
906 .atomic_duplicate_state
= drm_atomic_helper_plane_duplicate_state
,
907 .atomic_destroy_state
= drm_atomic_helper_plane_destroy_state
,
908 .late_register
= sti_gdp_late_register
,
911 struct drm_plane
*sti_gdp_create(struct drm_device
*drm_dev
,
912 struct device
*dev
, int desc
,
913 void __iomem
*baseaddr
,
914 unsigned int possible_crtcs
,
915 enum drm_plane_type type
)
920 gdp
= devm_kzalloc(dev
, sizeof(*gdp
), GFP_KERNEL
);
922 DRM_ERROR("Failed to allocate memory for GDP\n");
927 gdp
->regs
= baseaddr
;
928 gdp
->plane
.desc
= desc
;
929 gdp
->plane
.status
= STI_PLANE_DISABLED
;
931 gdp
->vtg_field_nb
.notifier_call
= sti_gdp_field_cb
;
935 res
= drm_universal_plane_init(drm_dev
, &gdp
->plane
.drm_plane
,
937 &sti_gdp_plane_helpers_funcs
,
938 gdp_supported_formats
,
939 ARRAY_SIZE(gdp_supported_formats
),
942 DRM_ERROR("Failed to initialize universal plane\n");
946 drm_plane_helper_add(&gdp
->plane
.drm_plane
, &sti_gdp_helpers_funcs
);
948 sti_plane_init_property(&gdp
->plane
, type
);
950 return &gdp
->plane
.drm_plane
;
953 devm_kfree(dev
, gdp
);