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treewide: remove redundant IS_ERR() before error code check
[linux/fpc-iii.git] / drivers / gpu / drm / stm / ltdc.c
blobc2815e8ae1da2a2301f00f5586514e5decdc18e6
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) STMicroelectronics SA 2017
4 *
5 * Authors: Philippe Cornu <philippe.cornu@st.com>
6 * Yannick Fertre <yannick.fertre@st.com>
7 * Fabien Dessenne <fabien.dessenne@st.com>
8 * Mickael Reulier <mickael.reulier@st.com>
9 */
10
11 #include <linux/clk.h>
12 #include <linux/component.h>
13 #include <linux/delay.h>
14 #include <linux/interrupt.h>
15 #include <linux/module.h>
16 #include <linux/of_address.h>
17 #include <linux/of_graph.h>
18 #include <linux/pinctrl/consumer.h>
19 #include <linux/platform_device.h>
20 #include <linux/pm_runtime.h>
21 #include <linux/reset.h>
22
23 #include <drm/drm_atomic.h>
24 #include <drm/drm_atomic_helper.h>
25 #include <drm/drm_bridge.h>
26 #include <drm/drm_device.h>
27 #include <drm/drm_fb_cma_helper.h>
28 #include <drm/drm_fourcc.h>
29 #include <drm/drm_gem_cma_helper.h>
30 #include <drm/drm_gem_framebuffer_helper.h>
31 #include <drm/drm_of.h>
32 #include <drm/drm_plane_helper.h>
33 #include <drm/drm_probe_helper.h>
34 #include <drm/drm_vblank.h>
35
36 #include <video/videomode.h>
37
38 #include "ltdc.h"
39
40 #define NB_CRTC 1
41 #define CRTC_MASK GENMASK(NB_CRTC - 1, 0)
42
43 #define MAX_IRQ 4
44
45 #define MAX_ENDPOINTS 2
46
47 #define HWVER_10200 0x010200
48 #define HWVER_10300 0x010300
49 #define HWVER_20101 0x020101
50
51 /*
52 * The address of some registers depends on the HW version: such registers have
53 * an extra offset specified with reg_ofs.
54 */
55 #define REG_OFS_NONE 0
56 #define REG_OFS_4 4 /* Insertion of "Layer Conf. 2" reg */
57 #define REG_OFS (ldev->caps.reg_ofs)
58 #define LAY_OFS 0x80 /* Register Offset between 2 layers */
59
60 /* Global register offsets */
61 #define LTDC_IDR 0x0000 /* IDentification */
62 #define LTDC_LCR 0x0004 /* Layer Count */
63 #define LTDC_SSCR 0x0008 /* Synchronization Size Configuration */
64 #define LTDC_BPCR 0x000C /* Back Porch Configuration */
65 #define LTDC_AWCR 0x0010 /* Active Width Configuration */
66 #define LTDC_TWCR 0x0014 /* Total Width Configuration */
67 #define LTDC_GCR 0x0018 /* Global Control */
68 #define LTDC_GC1R 0x001C /* Global Configuration 1 */
69 #define LTDC_GC2R 0x0020 /* Global Configuration 2 */
70 #define LTDC_SRCR 0x0024 /* Shadow Reload Configuration */
71 #define LTDC_GACR 0x0028 /* GAmma Correction */
72 #define LTDC_BCCR 0x002C /* Background Color Configuration */
73 #define LTDC_IER 0x0034 /* Interrupt Enable */
74 #define LTDC_ISR 0x0038 /* Interrupt Status */
75 #define LTDC_ICR 0x003C /* Interrupt Clear */
76 #define LTDC_LIPCR 0x0040 /* Line Interrupt Position Conf. */
77 #define LTDC_CPSR 0x0044 /* Current Position Status */
78 #define LTDC_CDSR 0x0048 /* Current Display Status */
79
80 /* Layer register offsets */
81 #define LTDC_L1LC1R (0x80) /* L1 Layer Configuration 1 */
82 #define LTDC_L1LC2R (0x84) /* L1 Layer Configuration 2 */
83 #define LTDC_L1CR (0x84 + REG_OFS)/* L1 Control */
84 #define LTDC_L1WHPCR (0x88 + REG_OFS)/* L1 Window Hor Position Config */
85 #define LTDC_L1WVPCR (0x8C + REG_OFS)/* L1 Window Vert Position Config */
86 #define LTDC_L1CKCR (0x90 + REG_OFS)/* L1 Color Keying Configuration */
87 #define LTDC_L1PFCR (0x94 + REG_OFS)/* L1 Pixel Format Configuration */
88 #define LTDC_L1CACR (0x98 + REG_OFS)/* L1 Constant Alpha Config */
89 #define LTDC_L1DCCR (0x9C + REG_OFS)/* L1 Default Color Configuration */
90 #define LTDC_L1BFCR (0xA0 + REG_OFS)/* L1 Blend Factors Configuration */
91 #define LTDC_L1FBBCR (0xA4 + REG_OFS)/* L1 FrameBuffer Bus Control */
92 #define LTDC_L1AFBCR (0xA8 + REG_OFS)/* L1 AuxFB Control */
93 #define LTDC_L1CFBAR (0xAC + REG_OFS)/* L1 Color FrameBuffer Address */
94 #define LTDC_L1CFBLR (0xB0 + REG_OFS)/* L1 Color FrameBuffer Length */
95 #define LTDC_L1CFBLNR (0xB4 + REG_OFS)/* L1 Color FrameBuffer Line Nb */
96 #define LTDC_L1AFBAR (0xB8 + REG_OFS)/* L1 AuxFB Address */
97 #define LTDC_L1AFBLR (0xBC + REG_OFS)/* L1 AuxFB Length */
98 #define LTDC_L1AFBLNR (0xC0 + REG_OFS)/* L1 AuxFB Line Number */
99 #define LTDC_L1CLUTWR (0xC4 + REG_OFS)/* L1 CLUT Write */
100 #define LTDC_L1YS1R (0xE0 + REG_OFS)/* L1 YCbCr Scale 1 */
101 #define LTDC_L1YS2R (0xE4 + REG_OFS)/* L1 YCbCr Scale 2 */
102
103 /* Bit definitions */
104 #define SSCR_VSH GENMASK(10, 0) /* Vertical Synchronization Height */
105 #define SSCR_HSW GENMASK(27, 16) /* Horizontal Synchronization Width */
106
107 #define BPCR_AVBP GENMASK(10, 0) /* Accumulated Vertical Back Porch */
108 #define BPCR_AHBP GENMASK(27, 16) /* Accumulated Horizontal Back Porch */
109
110 #define AWCR_AAH GENMASK(10, 0) /* Accumulated Active Height */
111 #define AWCR_AAW GENMASK(27, 16) /* Accumulated Active Width */
112
113 #define TWCR_TOTALH GENMASK(10, 0) /* TOTAL Height */
114 #define TWCR_TOTALW GENMASK(27, 16) /* TOTAL Width */
115
116 #define GCR_LTDCEN BIT(0) /* LTDC ENable */
117 #define GCR_DEN BIT(16) /* Dither ENable */
118 #define GCR_PCPOL BIT(28) /* Pixel Clock POLarity-Inverted */
119 #define GCR_DEPOL BIT(29) /* Data Enable POLarity-High */
120 #define GCR_VSPOL BIT(30) /* Vertical Synchro POLarity-High */
121 #define GCR_HSPOL BIT(31) /* Horizontal Synchro POLarity-High */
122
123 #define GC1R_WBCH GENMASK(3, 0) /* Width of Blue CHannel output */
124 #define GC1R_WGCH GENMASK(7, 4) /* Width of Green Channel output */
125 #define GC1R_WRCH GENMASK(11, 8) /* Width of Red Channel output */
126 #define GC1R_PBEN BIT(12) /* Precise Blending ENable */
127 #define GC1R_DT GENMASK(15, 14) /* Dithering Technique */
128 #define GC1R_GCT GENMASK(19, 17) /* Gamma Correction Technique */
129 #define GC1R_SHREN BIT(21) /* SHadow Registers ENabled */
130 #define GC1R_BCP BIT(22) /* Background Colour Programmable */
131 #define GC1R_BBEN BIT(23) /* Background Blending ENabled */
132 #define GC1R_LNIP BIT(24) /* Line Number IRQ Position */
133 #define GC1R_TP BIT(25) /* Timing Programmable */
134 #define GC1R_IPP BIT(26) /* IRQ Polarity Programmable */
135 #define GC1R_SPP BIT(27) /* Sync Polarity Programmable */
136 #define GC1R_DWP BIT(28) /* Dither Width Programmable */
137 #define GC1R_STREN BIT(29) /* STatus Registers ENabled */
138 #define GC1R_BMEN BIT(31) /* Blind Mode ENabled */
139
140 #define GC2R_EDCA BIT(0) /* External Display Control Ability */
141 #define GC2R_STSAEN BIT(1) /* Slave Timing Sync Ability ENabled */
142 #define GC2R_DVAEN BIT(2) /* Dual-View Ability ENabled */
143 #define GC2R_DPAEN BIT(3) /* Dual-Port Ability ENabled */
144 #define GC2R_BW GENMASK(6, 4) /* Bus Width (log2 of nb of bytes) */
145 #define GC2R_EDCEN BIT(7) /* External Display Control ENabled */
146
147 #define SRCR_IMR BIT(0) /* IMmediate Reload */
148 #define SRCR_VBR BIT(1) /* Vertical Blanking Reload */
149
150 #define BCCR_BCBLACK 0x00 /* Background Color BLACK */
151 #define BCCR_BCBLUE GENMASK(7, 0) /* Background Color BLUE */
152 #define BCCR_BCGREEN GENMASK(15, 8) /* Background Color GREEN */
153 #define BCCR_BCRED GENMASK(23, 16) /* Background Color RED */
154 #define BCCR_BCWHITE GENMASK(23, 0) /* Background Color WHITE */
155
156 #define IER_LIE BIT(0) /* Line Interrupt Enable */
157 #define IER_FUIE BIT(1) /* Fifo Underrun Interrupt Enable */
158 #define IER_TERRIE BIT(2) /* Transfer ERRor Interrupt Enable */
159 #define IER_RRIE BIT(3) /* Register Reload Interrupt enable */
160
161 #define CPSR_CYPOS GENMASK(15, 0) /* Current Y position */
162
163 #define ISR_LIF BIT(0) /* Line Interrupt Flag */
164 #define ISR_FUIF BIT(1) /* Fifo Underrun Interrupt Flag */
165 #define ISR_TERRIF BIT(2) /* Transfer ERRor Interrupt Flag */
166 #define ISR_RRIF BIT(3) /* Register Reload Interrupt Flag */
167
168 #define LXCR_LEN BIT(0) /* Layer ENable */
169 #define LXCR_COLKEN BIT(1) /* Color Keying Enable */
170 #define LXCR_CLUTEN BIT(4) /* Color Look-Up Table ENable */
171
172 #define LXWHPCR_WHSTPOS GENMASK(11, 0) /* Window Horizontal StarT POSition */
173 #define LXWHPCR_WHSPPOS GENMASK(27, 16) /* Window Horizontal StoP POSition */
174
175 #define LXWVPCR_WVSTPOS GENMASK(10, 0) /* Window Vertical StarT POSition */
176 #define LXWVPCR_WVSPPOS GENMASK(26, 16) /* Window Vertical StoP POSition */
177
178 #define LXPFCR_PF GENMASK(2, 0) /* Pixel Format */
179
180 #define LXCACR_CONSTA GENMASK(7, 0) /* CONSTant Alpha */
181
182 #define LXBFCR_BF2 GENMASK(2, 0) /* Blending Factor 2 */
183 #define LXBFCR_BF1 GENMASK(10, 8) /* Blending Factor 1 */
184
185 #define LXCFBLR_CFBLL GENMASK(12, 0) /* Color Frame Buffer Line Length */
186 #define LXCFBLR_CFBP GENMASK(28, 16) /* Color Frame Buffer Pitch in bytes */
187
188 #define LXCFBLNR_CFBLN GENMASK(10, 0) /* Color Frame Buffer Line Number */
189
190 #define CLUT_SIZE 256
191
192 #define CONSTA_MAX 0xFF /* CONSTant Alpha MAX= 1.0 */
193 #define BF1_PAXCA 0x600 /* Pixel Alpha x Constant Alpha */
194 #define BF1_CA 0x400 /* Constant Alpha */
195 #define BF2_1PAXCA 0x007 /* 1 - (Pixel Alpha x Constant Alpha) */
196 #define BF2_1CA 0x005 /* 1 - Constant Alpha */
197
198 #define NB_PF 8 /* Max nb of HW pixel format */
199
200 enum ltdc_pix_fmt {
201 PF_NONE,
202 /* RGB formats */
203 PF_ARGB8888, /* ARGB [32 bits] */
204 PF_RGBA8888, /* RGBA [32 bits] */
205 PF_RGB888, /* RGB [24 bits] */
206 PF_RGB565, /* RGB [16 bits] */
207 PF_ARGB1555, /* ARGB A:1 bit RGB:15 bits [16 bits] */
208 PF_ARGB4444, /* ARGB A:4 bits R/G/B: 4 bits each [16 bits] */
209 /* Indexed formats */
210 PF_L8, /* Indexed 8 bits [8 bits] */
211 PF_AL44, /* Alpha:4 bits + indexed 4 bits [8 bits] */
212 PF_AL88 /* Alpha:8 bits + indexed 8 bits [16 bits] */
213 };
214
215 /* The index gives the encoding of the pixel format for an HW version */
216 static const enum ltdc_pix_fmt ltdc_pix_fmt_a0[NB_PF] = {
217 PF_ARGB8888, /* 0x00 */
218 PF_RGB888, /* 0x01 */
219 PF_RGB565, /* 0x02 */
220 PF_ARGB1555, /* 0x03 */
221 PF_ARGB4444, /* 0x04 */
222 PF_L8, /* 0x05 */
223 PF_AL44, /* 0x06 */
224 PF_AL88 /* 0x07 */
225 };
226
227 static const enum ltdc_pix_fmt ltdc_pix_fmt_a1[NB_PF] = {
228 PF_ARGB8888, /* 0x00 */
229 PF_RGB888, /* 0x01 */
230 PF_RGB565, /* 0x02 */
231 PF_RGBA8888, /* 0x03 */
232 PF_AL44, /* 0x04 */
233 PF_L8, /* 0x05 */
234 PF_ARGB1555, /* 0x06 */
235 PF_ARGB4444 /* 0x07 */
236 };
237
238 static const u64 ltdc_format_modifiers[] = {
239 DRM_FORMAT_MOD_LINEAR,
240 DRM_FORMAT_MOD_INVALID
241 };
242
243 static inline u32 reg_read(void __iomem *base, u32 reg)
244 {
245 return readl_relaxed(base + reg);
246 }
247
248 static inline void reg_write(void __iomem *base, u32 reg, u32 val)
249 {
250 writel_relaxed(val, base + reg);
251 }
252
253 static inline void reg_set(void __iomem *base, u32 reg, u32 mask)
254 {
255 reg_write(base, reg, reg_read(base, reg) | mask);
256 }
257
258 static inline void reg_clear(void __iomem *base, u32 reg, u32 mask)
259 {
260 reg_write(base, reg, reg_read(base, reg) & ~mask);
261 }
262
263 static inline void reg_update_bits(void __iomem *base, u32 reg, u32 mask,
264 u32 val)
265 {
266 reg_write(base, reg, (reg_read(base, reg) & ~mask) | val);
267 }
268
269 static inline struct ltdc_device *crtc_to_ltdc(struct drm_crtc *crtc)
270 {
271 return (struct ltdc_device *)crtc->dev->dev_private;
272 }
273
274 static inline struct ltdc_device *plane_to_ltdc(struct drm_plane *plane)
275 {
276 return (struct ltdc_device *)plane->dev->dev_private;
277 }
278
279 static inline struct ltdc_device *encoder_to_ltdc(struct drm_encoder *enc)
280 {
281 return (struct ltdc_device *)enc->dev->dev_private;
282 }
283
284 static inline enum ltdc_pix_fmt to_ltdc_pixelformat(u32 drm_fmt)
285 {
286 enum ltdc_pix_fmt pf;
287
288 switch (drm_fmt) {
289 case DRM_FORMAT_ARGB8888:
290 case DRM_FORMAT_XRGB8888:
291 pf = PF_ARGB8888;
292 break;
293 case DRM_FORMAT_RGBA8888:
294 case DRM_FORMAT_RGBX8888:
295 pf = PF_RGBA8888;
296 break;
297 case DRM_FORMAT_RGB888:
298 pf = PF_RGB888;
299 break;
300 case DRM_FORMAT_RGB565:
301 pf = PF_RGB565;
302 break;
303 case DRM_FORMAT_ARGB1555:
304 case DRM_FORMAT_XRGB1555:
305 pf = PF_ARGB1555;
306 break;
307 case DRM_FORMAT_ARGB4444:
308 case DRM_FORMAT_XRGB4444:
309 pf = PF_ARGB4444;
310 break;
311 case DRM_FORMAT_C8:
312 pf = PF_L8;
313 break;
314 default:
315 pf = PF_NONE;
316 break;
317 /* Note: There are no DRM_FORMAT for AL44 and AL88 */
318 }
319
320 return pf;
321 }
322
323 static inline u32 to_drm_pixelformat(enum ltdc_pix_fmt pf)
324 {
325 switch (pf) {
326 case PF_ARGB8888:
327 return DRM_FORMAT_ARGB8888;
328 case PF_RGBA8888:
329 return DRM_FORMAT_RGBA8888;
330 case PF_RGB888:
331 return DRM_FORMAT_RGB888;
332 case PF_RGB565:
333 return DRM_FORMAT_RGB565;
334 case PF_ARGB1555:
335 return DRM_FORMAT_ARGB1555;
336 case PF_ARGB4444:
337 return DRM_FORMAT_ARGB4444;
338 case PF_L8:
339 return DRM_FORMAT_C8;
340 case PF_AL44: /* No DRM support */
341 case PF_AL88: /* No DRM support */
342 case PF_NONE:
343 default:
344 return 0;
345 }
346 }
347
348 static inline u32 get_pixelformat_without_alpha(u32 drm)
349 {
350 switch (drm) {
351 case DRM_FORMAT_ARGB4444:
352 return DRM_FORMAT_XRGB4444;
353 case DRM_FORMAT_RGBA4444:
354 return DRM_FORMAT_RGBX4444;
355 case DRM_FORMAT_ARGB1555:
356 return DRM_FORMAT_XRGB1555;
357 case DRM_FORMAT_RGBA5551:
358 return DRM_FORMAT_RGBX5551;
359 case DRM_FORMAT_ARGB8888:
360 return DRM_FORMAT_XRGB8888;
361 case DRM_FORMAT_RGBA8888:
362 return DRM_FORMAT_RGBX8888;
363 default:
364 return 0;
365 }
366 }
367
368 static irqreturn_t ltdc_irq_thread(int irq, void *arg)
369 {
370 struct drm_device *ddev = arg;
371 struct ltdc_device *ldev = ddev->dev_private;
372 struct drm_crtc *crtc = drm_crtc_from_index(ddev, 0);
373
374 /* Line IRQ : trigger the vblank event */
375 if (ldev->irq_status & ISR_LIF)
376 drm_crtc_handle_vblank(crtc);
377
378 /* Save FIFO Underrun & Transfer Error status */
379 mutex_lock(&ldev->err_lock);
380 if (ldev->irq_status & ISR_FUIF)
381 ldev->error_status |= ISR_FUIF;
382 if (ldev->irq_status & ISR_TERRIF)
383 ldev->error_status |= ISR_TERRIF;
384 mutex_unlock(&ldev->err_lock);
385
386 return IRQ_HANDLED;
387 }
388
389 static irqreturn_t ltdc_irq(int irq, void *arg)
390 {
391 struct drm_device *ddev = arg;
392 struct ltdc_device *ldev = ddev->dev_private;
393
394 /* Read & Clear the interrupt status */
395 ldev->irq_status = reg_read(ldev->regs, LTDC_ISR);
396 reg_write(ldev->regs, LTDC_ICR, ldev->irq_status);
397
398 return IRQ_WAKE_THREAD;
399 }
400
401 /*
402 * DRM_CRTC
403 */
404
405 static void ltdc_crtc_update_clut(struct drm_crtc *crtc)
406 {
407 struct ltdc_device *ldev = crtc_to_ltdc(crtc);
408 struct drm_color_lut *lut;
409 u32 val;
410 int i;
411
412 if (!crtc->state->color_mgmt_changed || !crtc->state->gamma_lut)
413 return;
414
415 lut = (struct drm_color_lut *)crtc->state->gamma_lut->data;
416
417 for (i = 0; i < CLUT_SIZE; i++, lut++) {
418 val = ((lut->red << 8) & 0xff0000) | (lut->green & 0xff00) |
419 (lut->blue >> 8) | (i << 24);
420 reg_write(ldev->regs, LTDC_L1CLUTWR, val);
421 }
422 }
423
424 static void ltdc_crtc_atomic_enable(struct drm_crtc *crtc,
425 struct drm_crtc_state *old_state)
426 {
427 struct ltdc_device *ldev = crtc_to_ltdc(crtc);
428
429 DRM_DEBUG_DRIVER("\n");
430
431 /* Sets the background color value */
432 reg_write(ldev->regs, LTDC_BCCR, BCCR_BCBLACK);
433
434 /* Enable IRQ */
435 reg_set(ldev->regs, LTDC_IER, IER_RRIE | IER_FUIE | IER_TERRIE);
436
437 /* Commit shadow registers = update planes at next vblank */
438 reg_set(ldev->regs, LTDC_SRCR, SRCR_VBR);
439
440 drm_crtc_vblank_on(crtc);
441 }
442
443 static void ltdc_crtc_atomic_disable(struct drm_crtc *crtc,
444 struct drm_crtc_state *old_state)
445 {
446 struct ltdc_device *ldev = crtc_to_ltdc(crtc);
447 struct drm_device *ddev = crtc->dev;
448
449 DRM_DEBUG_DRIVER("\n");
450
451 drm_crtc_vblank_off(crtc);
452
453 /* disable IRQ */
454 reg_clear(ldev->regs, LTDC_IER, IER_RRIE | IER_FUIE | IER_TERRIE);
455
456 /* immediately commit disable of layers before switching off LTDC */
457 reg_set(ldev->regs, LTDC_SRCR, SRCR_IMR);
458
459 pm_runtime_put_sync(ddev->dev);
460 }
461
462 #define CLK_TOLERANCE_HZ 50
463
464 static enum drm_mode_status
465 ltdc_crtc_mode_valid(struct drm_crtc *crtc,
466 const struct drm_display_mode *mode)
467 {
468 struct ltdc_device *ldev = crtc_to_ltdc(crtc);
469 int target = mode->clock * 1000;
470 int target_min = target - CLK_TOLERANCE_HZ;
471 int target_max = target + CLK_TOLERANCE_HZ;
472 int result;
473
474 result = clk_round_rate(ldev->pixel_clk, target);
475
476 DRM_DEBUG_DRIVER("clk rate target %d, available %d\n", target, result);
477
478 /* Filter modes according to the max frequency supported by the pads */
479 if (result > ldev->caps.pad_max_freq_hz)
480 return MODE_CLOCK_HIGH;
481
482 /*
483 * Accept all "preferred" modes:
484 * - this is important for panels because panel clock tolerances are
485 * bigger than hdmi ones and there is no reason to not accept them
486 * (the fps may vary a little but it is not a problem).
487 * - the hdmi preferred mode will be accepted too, but userland will
488 * be able to use others hdmi "valid" modes if necessary.
489 */
490 if (mode->type & DRM_MODE_TYPE_PREFERRED)
491 return MODE_OK;
492
493 /*
494 * Filter modes according to the clock value, particularly useful for
495 * hdmi modes that require precise pixel clocks.
496 */
497 if (result < target_min || result > target_max)
498 return MODE_CLOCK_RANGE;
499
500 return MODE_OK;
501 }
502
503 static bool ltdc_crtc_mode_fixup(struct drm_crtc *crtc,
504 const struct drm_display_mode *mode,
505 struct drm_display_mode *adjusted_mode)
506 {
507 struct ltdc_device *ldev = crtc_to_ltdc(crtc);
508 struct drm_device *ddev = crtc->dev;
509 int rate = mode->clock * 1000;
510 bool runtime_active;
511 int ret;
512
513 runtime_active = pm_runtime_active(ddev->dev);
514
515 if (runtime_active)
516 pm_runtime_put_sync(ddev->dev);
517
518 if (clk_set_rate(ldev->pixel_clk, rate) < 0) {
519 DRM_ERROR("Cannot set rate (%dHz) for pixel clk\n", rate);
520 return false;
521 }
522
523 adjusted_mode->clock = clk_get_rate(ldev->pixel_clk) / 1000;
524
525 if (runtime_active) {
526 ret = pm_runtime_get_sync(ddev->dev);
527 if (ret) {
528 DRM_ERROR("Failed to fixup mode, cannot get sync\n");
529 return false;
530 }
531 }
532
533 DRM_DEBUG_DRIVER("requested clock %dkHz, adjusted clock %dkHz\n",
534 mode->clock, adjusted_mode->clock);
535
536 return true;
537 }
538
539 static void ltdc_crtc_mode_set_nofb(struct drm_crtc *crtc)
540 {
541 struct ltdc_device *ldev = crtc_to_ltdc(crtc);
542 struct drm_device *ddev = crtc->dev;
543 struct drm_display_mode *mode = &crtc->state->adjusted_mode;
544 struct videomode vm;
545 u32 hsync, vsync, accum_hbp, accum_vbp, accum_act_w, accum_act_h;
546 u32 total_width, total_height;
547 u32 val;
548 int ret;
549
550 if (!pm_runtime_active(ddev->dev)) {
551 ret = pm_runtime_get_sync(ddev->dev);
552 if (ret) {
553 DRM_ERROR("Failed to set mode, cannot get sync\n");
554 return;
555 }
556 }
557
558 drm_display_mode_to_videomode(mode, &vm);
559
560 DRM_DEBUG_DRIVER("CRTC:%d mode:%s\n", crtc->base.id, mode->name);
561 DRM_DEBUG_DRIVER("Video mode: %dx%d", vm.hactive, vm.vactive);
562 DRM_DEBUG_DRIVER(" hfp %d hbp %d hsl %d vfp %d vbp %d vsl %d\n",
563 vm.hfront_porch, vm.hback_porch, vm.hsync_len,
564 vm.vfront_porch, vm.vback_porch, vm.vsync_len);
565
566 /* Convert video timings to ltdc timings */
567 hsync = vm.hsync_len - 1;
568 vsync = vm.vsync_len - 1;
569 accum_hbp = hsync + vm.hback_porch;
570 accum_vbp = vsync + vm.vback_porch;
571 accum_act_w = accum_hbp + vm.hactive;
572 accum_act_h = accum_vbp + vm.vactive;
573 total_width = accum_act_w + vm.hfront_porch;
574 total_height = accum_act_h + vm.vfront_porch;
575
576 /* Configures the HS, VS, DE and PC polarities. Default Active Low */
577 val = 0;
578
579 if (vm.flags & DISPLAY_FLAGS_HSYNC_HIGH)
580 val |= GCR_HSPOL;
581
582 if (vm.flags & DISPLAY_FLAGS_VSYNC_HIGH)
583 val |= GCR_VSPOL;
584
585 if (vm.flags & DISPLAY_FLAGS_DE_LOW)
586 val |= GCR_DEPOL;
587
588 if (vm.flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE)
589 val |= GCR_PCPOL;
590
591 reg_update_bits(ldev->regs, LTDC_GCR,
592 GCR_HSPOL | GCR_VSPOL | GCR_DEPOL | GCR_PCPOL, val);
593
594 /* Set Synchronization size */
595 val = (hsync << 16) | vsync;
596 reg_update_bits(ldev->regs, LTDC_SSCR, SSCR_VSH | SSCR_HSW, val);
597
598 /* Set Accumulated Back porch */
599 val = (accum_hbp << 16) | accum_vbp;
600 reg_update_bits(ldev->regs, LTDC_BPCR, BPCR_AVBP | BPCR_AHBP, val);
601
602 /* Set Accumulated Active Width */
603 val = (accum_act_w << 16) | accum_act_h;
604 reg_update_bits(ldev->regs, LTDC_AWCR, AWCR_AAW | AWCR_AAH, val);
605
606 /* Set total width & height */
607 val = (total_width << 16) | total_height;
608 reg_update_bits(ldev->regs, LTDC_TWCR, TWCR_TOTALH | TWCR_TOTALW, val);
609
610 reg_write(ldev->regs, LTDC_LIPCR, (accum_act_h + 1));
611 }
612
613 static void ltdc_crtc_atomic_flush(struct drm_crtc *crtc,
614 struct drm_crtc_state *old_crtc_state)
615 {
616 struct ltdc_device *ldev = crtc_to_ltdc(crtc);
617 struct drm_device *ddev = crtc->dev;
618 struct drm_pending_vblank_event *event = crtc->state->event;
619
620 DRM_DEBUG_ATOMIC("\n");
621
622 ltdc_crtc_update_clut(crtc);
623
624 /* Commit shadow registers = update planes at next vblank */
625 reg_set(ldev->regs, LTDC_SRCR, SRCR_VBR);
626
627 if (event) {
628 crtc->state->event = NULL;
629
630 spin_lock_irq(&ddev->event_lock);
631 if (drm_crtc_vblank_get(crtc) == 0)
632 drm_crtc_arm_vblank_event(crtc, event);
633 else
634 drm_crtc_send_vblank_event(crtc, event);
635 spin_unlock_irq(&ddev->event_lock);
636 }
637 }
638
639 static const struct drm_crtc_helper_funcs ltdc_crtc_helper_funcs = {
640 .mode_valid = ltdc_crtc_mode_valid,
641 .mode_fixup = ltdc_crtc_mode_fixup,
642 .mode_set_nofb = ltdc_crtc_mode_set_nofb,
643 .atomic_flush = ltdc_crtc_atomic_flush,
644 .atomic_enable = ltdc_crtc_atomic_enable,
645 .atomic_disable = ltdc_crtc_atomic_disable,
646 };
647
648 static int ltdc_crtc_enable_vblank(struct drm_crtc *crtc)
649 {
650 struct ltdc_device *ldev = crtc_to_ltdc(crtc);
651
652 DRM_DEBUG_DRIVER("\n");
653 reg_set(ldev->regs, LTDC_IER, IER_LIE);
654
655 return 0;
656 }
657
658 static void ltdc_crtc_disable_vblank(struct drm_crtc *crtc)
659 {
660 struct ltdc_device *ldev = crtc_to_ltdc(crtc);
661
662 DRM_DEBUG_DRIVER("\n");
663 reg_clear(ldev->regs, LTDC_IER, IER_LIE);
664 }
665
666 bool ltdc_crtc_scanoutpos(struct drm_device *ddev, unsigned int pipe,
667 bool in_vblank_irq, int *vpos, int *hpos,
668 ktime_t *stime, ktime_t *etime,
669 const struct drm_display_mode *mode)
670 {
671 struct ltdc_device *ldev = ddev->dev_private;
672 int line, vactive_start, vactive_end, vtotal;
673
674 if (stime)
675 *stime = ktime_get();
676
677 /* The active area starts after vsync + front porch and ends
678 * at vsync + front porc + display size.
679 * The total height also include back porch.
680 * We have 3 possible cases to handle:
681 * - line < vactive_start: vpos = line - vactive_start and will be
682 * negative
683 * - vactive_start < line < vactive_end: vpos = line - vactive_start
684 * and will be positive
685 * - line > vactive_end: vpos = line - vtotal - vactive_start
686 * and will negative
687 *
688 * Computation for the two first cases are identical so we can
689 * simplify the code and only test if line > vactive_end
690 */
691 if (pm_runtime_active(ddev->dev)) {
692 line = reg_read(ldev->regs, LTDC_CPSR) & CPSR_CYPOS;
693 vactive_start = reg_read(ldev->regs, LTDC_BPCR) & BPCR_AVBP;
694 vactive_end = reg_read(ldev->regs, LTDC_AWCR) & AWCR_AAH;
695 vtotal = reg_read(ldev->regs, LTDC_TWCR) & TWCR_TOTALH;
696
697 if (line > vactive_end)
698 *vpos = line - vtotal - vactive_start;
699 else
700 *vpos = line - vactive_start;
701 } else {
702 *vpos = 0;
703 }
704
705 *hpos = 0;
706
707 if (etime)
708 *etime = ktime_get();
709
710 return true;
711 }
712
713 static const struct drm_crtc_funcs ltdc_crtc_funcs = {
714 .destroy = drm_crtc_cleanup,
715 .set_config = drm_atomic_helper_set_config,
716 .page_flip = drm_atomic_helper_page_flip,
717 .reset = drm_atomic_helper_crtc_reset,
718 .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
719 .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
720 .enable_vblank = ltdc_crtc_enable_vblank,
721 .disable_vblank = ltdc_crtc_disable_vblank,
722 .gamma_set = drm_atomic_helper_legacy_gamma_set,
723 };
724
725 /*
726 * DRM_PLANE
727 */
728
729 static int ltdc_plane_atomic_check(struct drm_plane *plane,
730 struct drm_plane_state *state)
731 {
732 struct drm_framebuffer *fb = state->fb;
733 u32 src_w, src_h;
734
735 DRM_DEBUG_DRIVER("\n");
736
737 if (!fb)
738 return 0;
739
740 /* convert src_ from 16:16 format */
741 src_w = state->src_w >> 16;
742 src_h = state->src_h >> 16;
743
744 /* Reject scaling */
745 if (src_w != state->crtc_w || src_h != state->crtc_h) {
746 DRM_ERROR("Scaling is not supported");
747 return -EINVAL;
748 }
749
750 return 0;
751 }
752
753 static void ltdc_plane_atomic_update(struct drm_plane *plane,
754 struct drm_plane_state *oldstate)
755 {
756 struct ltdc_device *ldev = plane_to_ltdc(plane);
757 struct drm_plane_state *state = plane->state;
758 struct drm_framebuffer *fb = state->fb;
759 u32 lofs = plane->index * LAY_OFS;
760 u32 x0 = state->crtc_x;
761 u32 x1 = state->crtc_x + state->crtc_w - 1;
762 u32 y0 = state->crtc_y;
763 u32 y1 = state->crtc_y + state->crtc_h - 1;
764 u32 src_x, src_y, src_w, src_h;
765 u32 val, pitch_in_bytes, line_length, paddr, ahbp, avbp, bpcr;
766 enum ltdc_pix_fmt pf;
767
768 if (!state->crtc || !fb) {
769 DRM_DEBUG_DRIVER("fb or crtc NULL");
770 return;
771 }
772
773 /* convert src_ from 16:16 format */
774 src_x = state->src_x >> 16;
775 src_y = state->src_y >> 16;
776 src_w = state->src_w >> 16;
777 src_h = state->src_h >> 16;
778
779 DRM_DEBUG_DRIVER("plane:%d fb:%d (%dx%d)@(%d,%d) -> (%dx%d)@(%d,%d)\n",
780 plane->base.id, fb->base.id,
781 src_w, src_h, src_x, src_y,
782 state->crtc_w, state->crtc_h,
783 state->crtc_x, state->crtc_y);
784
785 bpcr = reg_read(ldev->regs, LTDC_BPCR);
786 ahbp = (bpcr & BPCR_AHBP) >> 16;
787 avbp = bpcr & BPCR_AVBP;
788
789 /* Configures the horizontal start and stop position */
790 val = ((x1 + 1 + ahbp) << 16) + (x0 + 1 + ahbp);
791 reg_update_bits(ldev->regs, LTDC_L1WHPCR + lofs,
792 LXWHPCR_WHSTPOS | LXWHPCR_WHSPPOS, val);
793
794 /* Configures the vertical start and stop position */
795 val = ((y1 + 1 + avbp) << 16) + (y0 + 1 + avbp);
796 reg_update_bits(ldev->regs, LTDC_L1WVPCR + lofs,
797 LXWVPCR_WVSTPOS | LXWVPCR_WVSPPOS, val);
798
799 /* Specifies the pixel format */
800 pf = to_ltdc_pixelformat(fb->format->format);
801 for (val = 0; val < NB_PF; val++)
802 if (ldev->caps.pix_fmt_hw[val] == pf)
803 break;
804
805 if (val == NB_PF) {
806 DRM_ERROR("Pixel format %.4s not supported\n",
807 (char *)&fb->format->format);
808 val = 0; /* set by default ARGB 32 bits */
809 }
810 reg_update_bits(ldev->regs, LTDC_L1PFCR + lofs, LXPFCR_PF, val);
811
812 /* Configures the color frame buffer pitch in bytes & line length */
813 pitch_in_bytes = fb->pitches[0];
814 line_length = fb->format->cpp[0] *
815 (x1 - x0 + 1) + (ldev->caps.bus_width >> 3) - 1;
816 val = ((pitch_in_bytes << 16) | line_length);
817 reg_update_bits(ldev->regs, LTDC_L1CFBLR + lofs,
818 LXCFBLR_CFBLL | LXCFBLR_CFBP, val);
819
820 /* Specifies the constant alpha value */
821 val = CONSTA_MAX;
822 reg_update_bits(ldev->regs, LTDC_L1CACR + lofs, LXCACR_CONSTA, val);
823
824 /* Specifies the blending factors */
825 val = BF1_PAXCA | BF2_1PAXCA;
826 if (!fb->format->has_alpha)
827 val = BF1_CA | BF2_1CA;
828
829 /* Manage hw-specific capabilities */
830 if (ldev->caps.non_alpha_only_l1 &&
831 plane->type != DRM_PLANE_TYPE_PRIMARY)
832 val = BF1_PAXCA | BF2_1PAXCA;
833
834 reg_update_bits(ldev->regs, LTDC_L1BFCR + lofs,
835 LXBFCR_BF2 | LXBFCR_BF1, val);
836
837 /* Configures the frame buffer line number */
838 val = y1 - y0 + 1;
839 reg_update_bits(ldev->regs, LTDC_L1CFBLNR + lofs, LXCFBLNR_CFBLN, val);
840
841 /* Sets the FB address */
842 paddr = (u32)drm_fb_cma_get_gem_addr(fb, state, 0);
843
844 DRM_DEBUG_DRIVER("fb: phys 0x%08x", paddr);
845 reg_write(ldev->regs, LTDC_L1CFBAR + lofs, paddr);
846
847 /* Enable layer and CLUT if needed */
848 val = fb->format->format == DRM_FORMAT_C8 ? LXCR_CLUTEN : 0;
849 val |= LXCR_LEN;
850 reg_update_bits(ldev->regs, LTDC_L1CR + lofs,
851 LXCR_LEN | LXCR_CLUTEN, val);
852
853 ldev->plane_fpsi[plane->index].counter++;
854
855 mutex_lock(&ldev->err_lock);
856 if (ldev->error_status & ISR_FUIF) {
857 DRM_WARN("ltdc fifo underrun: please verify display mode\n");
858 ldev->error_status &= ~ISR_FUIF;
859 }
860 if (ldev->error_status & ISR_TERRIF) {
861 DRM_WARN("ltdc transfer error\n");
862 ldev->error_status &= ~ISR_TERRIF;
863 }
864 mutex_unlock(&ldev->err_lock);
865 }
866
867 static void ltdc_plane_atomic_disable(struct drm_plane *plane,
868 struct drm_plane_state *oldstate)
869 {
870 struct ltdc_device *ldev = plane_to_ltdc(plane);
871 u32 lofs = plane->index * LAY_OFS;
872
873 /* disable layer */
874 reg_clear(ldev->regs, LTDC_L1CR + lofs, LXCR_LEN);
875
876 DRM_DEBUG_DRIVER("CRTC:%d plane:%d\n",
877 oldstate->crtc->base.id, plane->base.id);
878 }
879
880 static void ltdc_plane_atomic_print_state(struct drm_printer *p,
881 const struct drm_plane_state *state)
882 {
883 struct drm_plane *plane = state->plane;
884 struct ltdc_device *ldev = plane_to_ltdc(plane);
885 struct fps_info *fpsi = &ldev->plane_fpsi[plane->index];
886 int ms_since_last;
887 ktime_t now;
888
889 now = ktime_get();
890 ms_since_last = ktime_to_ms(ktime_sub(now, fpsi->last_timestamp));
891
892 drm_printf(p, "\tuser_updates=%dfps\n",
893 DIV_ROUND_CLOSEST(fpsi->counter * 1000, ms_since_last));
894
895 fpsi->last_timestamp = now;
896 fpsi->counter = 0;
897 }
898
899 static bool ltdc_plane_format_mod_supported(struct drm_plane *plane,
900 u32 format,
901 u64 modifier)
902 {
903 if (modifier == DRM_FORMAT_MOD_LINEAR)
904 return true;
905
906 return false;
907 }
908
909 static const struct drm_plane_funcs ltdc_plane_funcs = {
910 .update_plane = drm_atomic_helper_update_plane,
911 .disable_plane = drm_atomic_helper_disable_plane,
912 .destroy = drm_plane_cleanup,
913 .reset = drm_atomic_helper_plane_reset,
914 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
915 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
916 .atomic_print_state = ltdc_plane_atomic_print_state,
917 .format_mod_supported = ltdc_plane_format_mod_supported,
918 };
919
920 static const struct drm_plane_helper_funcs ltdc_plane_helper_funcs = {
921 .prepare_fb = drm_gem_fb_prepare_fb,
922 .atomic_check = ltdc_plane_atomic_check,
923 .atomic_update = ltdc_plane_atomic_update,
924 .atomic_disable = ltdc_plane_atomic_disable,
925 };
926
927 static struct drm_plane *ltdc_plane_create(struct drm_device *ddev,
928 enum drm_plane_type type)
929 {
930 unsigned long possible_crtcs = CRTC_MASK;
931 struct ltdc_device *ldev = ddev->dev_private;
932 struct device *dev = ddev->dev;
933 struct drm_plane *plane;
934 unsigned int i, nb_fmt = 0;
935 u32 formats[NB_PF * 2];
936 u32 drm_fmt, drm_fmt_no_alpha;
937 const u64 *modifiers = ltdc_format_modifiers;
938 int ret;
939
940 /* Get supported pixel formats */
941 for (i = 0; i < NB_PF; i++) {
942 drm_fmt = to_drm_pixelformat(ldev->caps.pix_fmt_hw[i]);
943 if (!drm_fmt)
944 continue;
945 formats[nb_fmt++] = drm_fmt;
946
947 /* Add the no-alpha related format if any & supported */
948 drm_fmt_no_alpha = get_pixelformat_without_alpha(drm_fmt);
949 if (!drm_fmt_no_alpha)
950 continue;
951
952 /* Manage hw-specific capabilities */
953 if (ldev->caps.non_alpha_only_l1 &&
954 type != DRM_PLANE_TYPE_PRIMARY)
955 continue;
956
957 formats[nb_fmt++] = drm_fmt_no_alpha;
958 }
959
960 plane = devm_kzalloc(dev, sizeof(*plane), GFP_KERNEL);
961 if (!plane)
962 return NULL;
963
964 ret = drm_universal_plane_init(ddev, plane, possible_crtcs,
965 &ltdc_plane_funcs, formats, nb_fmt,
966 modifiers, type, NULL);
967 if (ret < 0)
968 return NULL;
969
970 drm_plane_helper_add(plane, &ltdc_plane_helper_funcs);
971
972 DRM_DEBUG_DRIVER("plane:%d created\n", plane->base.id);
973
974 return plane;
975 }
976
977 static void ltdc_plane_destroy_all(struct drm_device *ddev)
978 {
979 struct drm_plane *plane, *plane_temp;
980
981 list_for_each_entry_safe(plane, plane_temp,
982 &ddev->mode_config.plane_list, head)
983 drm_plane_cleanup(plane);
984 }
985
986 static int ltdc_crtc_init(struct drm_device *ddev, struct drm_crtc *crtc)
987 {
988 struct ltdc_device *ldev = ddev->dev_private;
989 struct drm_plane *primary, *overlay;
990 unsigned int i;
991 int ret;
992
993 primary = ltdc_plane_create(ddev, DRM_PLANE_TYPE_PRIMARY);
994 if (!primary) {
995 DRM_ERROR("Can not create primary plane\n");
996 return -EINVAL;
997 }
998
999 ret = drm_crtc_init_with_planes(ddev, crtc, primary, NULL,
1000 &ltdc_crtc_funcs, NULL);
1001 if (ret) {
1002 DRM_ERROR("Can not initialize CRTC\n");
1003 goto cleanup;
1004 }
1005
1006 drm_crtc_helper_add(crtc, &ltdc_crtc_helper_funcs);
1007
1008 drm_mode_crtc_set_gamma_size(crtc, CLUT_SIZE);
1009 drm_crtc_enable_color_mgmt(crtc, 0, false, CLUT_SIZE);
1010
1011 DRM_DEBUG_DRIVER("CRTC:%d created\n", crtc->base.id);
1012
1013 /* Add planes. Note : the first layer is used by primary plane */
1014 for (i = 1; i < ldev->caps.nb_layers; i++) {
1015 overlay = ltdc_plane_create(ddev, DRM_PLANE_TYPE_OVERLAY);
1016 if (!overlay) {
1017 ret = -ENOMEM;
1018 DRM_ERROR("Can not create overlay plane %d\n", i);
1019 goto cleanup;
1020 }
1021 }
1022
1023 return 0;
1024
1025 cleanup:
1026 ltdc_plane_destroy_all(ddev);
1027 return ret;
1028 }
1029
1030 /*
1031 * DRM_ENCODER
1032 */
1033
1034 static const struct drm_encoder_funcs ltdc_encoder_funcs = {
1035 .destroy = drm_encoder_cleanup,
1036 };
1037
1038 static void ltdc_encoder_disable(struct drm_encoder *encoder)
1039 {
1040 struct drm_device *ddev = encoder->dev;
1041 struct ltdc_device *ldev = ddev->dev_private;
1042
1043 DRM_DEBUG_DRIVER("\n");
1044
1045 /* Disable LTDC */
1046 reg_clear(ldev->regs, LTDC_GCR, GCR_LTDCEN);
1047
1048 /* Set to sleep state the pinctrl whatever type of encoder */
1049 pinctrl_pm_select_sleep_state(ddev->dev);
1050 }
1051
1052 static void ltdc_encoder_enable(struct drm_encoder *encoder)
1053 {
1054 struct drm_device *ddev = encoder->dev;
1055 struct ltdc_device *ldev = ddev->dev_private;
1056
1057 DRM_DEBUG_DRIVER("\n");
1058
1059 /* Enable LTDC */
1060 reg_set(ldev->regs, LTDC_GCR, GCR_LTDCEN);
1061 }
1062
1063 static void ltdc_encoder_mode_set(struct drm_encoder *encoder,
1064 struct drm_display_mode *mode,
1065 struct drm_display_mode *adjusted_mode)
1066 {
1067 struct drm_device *ddev = encoder->dev;
1068
1069 DRM_DEBUG_DRIVER("\n");
1070
1071 /*
1072 * Set to default state the pinctrl only with DPI type.
1073 * Others types like DSI, don't need pinctrl due to
1074 * internal bridge (the signals do not come out of the chipset).
1075 */
1076 if (encoder->encoder_type == DRM_MODE_ENCODER_DPI)
1077 pinctrl_pm_select_default_state(ddev->dev);
1078 }
1079
1080 static const struct drm_encoder_helper_funcs ltdc_encoder_helper_funcs = {
1081 .disable = ltdc_encoder_disable,
1082 .enable = ltdc_encoder_enable,
1083 .mode_set = ltdc_encoder_mode_set,
1084 };
1085
1086 static int ltdc_encoder_init(struct drm_device *ddev, struct drm_bridge *bridge)
1087 {
1088 struct drm_encoder *encoder;
1089 int ret;
1090
1091 encoder = devm_kzalloc(ddev->dev, sizeof(*encoder), GFP_KERNEL);
1092 if (!encoder)
1093 return -ENOMEM;
1094
1095 encoder->possible_crtcs = CRTC_MASK;
1096 encoder->possible_clones = 0; /* No cloning support */
1097
1098 drm_encoder_init(ddev, encoder, &ltdc_encoder_funcs,
1099 DRM_MODE_ENCODER_DPI, NULL);
1100
1101 drm_encoder_helper_add(encoder, &ltdc_encoder_helper_funcs);
1102
1103 ret = drm_bridge_attach(encoder, bridge, NULL);
1104 if (ret) {
1105 drm_encoder_cleanup(encoder);
1106 return -EINVAL;
1107 }
1108
1109 DRM_DEBUG_DRIVER("Bridge encoder:%d created\n", encoder->base.id);
1110
1111 return 0;
1112 }
1113
1114 static int ltdc_get_caps(struct drm_device *ddev)
1115 {
1116 struct ltdc_device *ldev = ddev->dev_private;
1117 u32 bus_width_log2, lcr, gc2r;
1118
1119 /*
1120 * at least 1 layer must be managed & the number of layers
1121 * must not exceed LTDC_MAX_LAYER
1122 */
1123 lcr = reg_read(ldev->regs, LTDC_LCR);
1124
1125 ldev->caps.nb_layers = clamp((int)lcr, 1, LTDC_MAX_LAYER);
1126
1127 /* set data bus width */
1128 gc2r = reg_read(ldev->regs, LTDC_GC2R);
1129 bus_width_log2 = (gc2r & GC2R_BW) >> 4;
1130 ldev->caps.bus_width = 8 << bus_width_log2;
1131 ldev->caps.hw_version = reg_read(ldev->regs, LTDC_IDR);
1132
1133 switch (ldev->caps.hw_version) {
1134 case HWVER_10200:
1135 case HWVER_10300:
1136 ldev->caps.reg_ofs = REG_OFS_NONE;
1137 ldev->caps.pix_fmt_hw = ltdc_pix_fmt_a0;
1138 /*
1139 * Hw older versions support non-alpha color formats derived
1140 * from native alpha color formats only on the primary layer.
1141 * For instance, RG16 native format without alpha works fine
1142 * on 2nd layer but XR24 (derived color format from AR24)
1143 * does not work on 2nd layer.
1144 */
1145 ldev->caps.non_alpha_only_l1 = true;
1146 ldev->caps.pad_max_freq_hz = 90000000;
1147 if (ldev->caps.hw_version == HWVER_10200)
1148 ldev->caps.pad_max_freq_hz = 65000000;
1149 break;
1150 case HWVER_20101:
1151 ldev->caps.reg_ofs = REG_OFS_4;
1152 ldev->caps.pix_fmt_hw = ltdc_pix_fmt_a1;
1153 ldev->caps.non_alpha_only_l1 = false;
1154 ldev->caps.pad_max_freq_hz = 150000000;
1155 break;
1156 default:
1157 return -ENODEV;
1158 }
1159
1160 return 0;
1161 }
1162
1163 void ltdc_suspend(struct drm_device *ddev)
1164 {
1165 struct ltdc_device *ldev = ddev->dev_private;
1166
1167 DRM_DEBUG_DRIVER("\n");
1168 clk_disable_unprepare(ldev->pixel_clk);
1169 }
1170
1171 int ltdc_resume(struct drm_device *ddev)
1172 {
1173 struct ltdc_device *ldev = ddev->dev_private;
1174 int ret;
1175
1176 DRM_DEBUG_DRIVER("\n");
1177
1178 ret = clk_prepare_enable(ldev->pixel_clk);
1179 if (ret) {
1180 DRM_ERROR("failed to enable pixel clock (%d)\n", ret);
1181 return ret;
1182 }
1183
1184 return 0;
1185 }
1186
1187 int ltdc_load(struct drm_device *ddev)
1188 {
1189 struct platform_device *pdev = to_platform_device(ddev->dev);
1190 struct ltdc_device *ldev = ddev->dev_private;
1191 struct device *dev = ddev->dev;
1192 struct device_node *np = dev->of_node;
1193 struct drm_bridge *bridge[MAX_ENDPOINTS] = {NULL};
1194 struct drm_panel *panel[MAX_ENDPOINTS] = {NULL};
1195 struct drm_crtc *crtc;
1196 struct reset_control *rstc;
1197 struct resource *res;
1198 int irq, ret, i, endpoint_not_ready = -ENODEV;
1199
1200 DRM_DEBUG_DRIVER("\n");
1201
1202 /* Get endpoints if any */
1203 for (i = 0; i < MAX_ENDPOINTS; i++) {
1204 ret = drm_of_find_panel_or_bridge(np, 0, i, &panel[i],
1205 &bridge[i]);
1206
1207 /*
1208 * If at least one endpoint is -EPROBE_DEFER, defer probing,
1209 * else if at least one endpoint is ready, continue probing.
1210 */
1211 if (ret == -EPROBE_DEFER)
1212 return ret;
1213 else if (!ret)
1214 endpoint_not_ready = 0;
1215 }
1216
1217 if (endpoint_not_ready)
1218 return endpoint_not_ready;
1219
1220 rstc = devm_reset_control_get_exclusive(dev, NULL);
1221
1222 mutex_init(&ldev->err_lock);
1223
1224 ldev->pixel_clk = devm_clk_get(dev, "lcd");
1225 if (IS_ERR(ldev->pixel_clk)) {
1226 if (PTR_ERR(ldev->pixel_clk) != -EPROBE_DEFER)
1227 DRM_ERROR("Unable to get lcd clock\n");
1228 return PTR_ERR(ldev->pixel_clk);
1229 }
1230
1231 if (clk_prepare_enable(ldev->pixel_clk)) {
1232 DRM_ERROR("Unable to prepare pixel clock\n");
1233 return -ENODEV;
1234 }
1235
1236 if (!IS_ERR(rstc)) {
1237 reset_control_assert(rstc);
1238 usleep_range(10, 20);
1239 reset_control_deassert(rstc);
1240 }
1241
1242 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1243 ldev->regs = devm_ioremap_resource(dev, res);
1244 if (IS_ERR(ldev->regs)) {
1245 DRM_ERROR("Unable to get ltdc registers\n");
1246 ret = PTR_ERR(ldev->regs);
1247 goto err;
1248 }
1249
1250 /* Disable interrupts */
1251 reg_clear(ldev->regs, LTDC_IER,
1252 IER_LIE | IER_RRIE | IER_FUIE | IER_TERRIE);
1253
1254 for (i = 0; i < MAX_IRQ; i++) {
1255 irq = platform_get_irq(pdev, i);
1256 if (irq == -EPROBE_DEFER)
1257 goto err;
1258
1259 if (irq < 0)
1260 continue;
1261
1262 ret = devm_request_threaded_irq(dev, irq, ltdc_irq,
1263 ltdc_irq_thread, IRQF_ONESHOT,
1264 dev_name(dev), ddev);
1265 if (ret) {
1266 DRM_ERROR("Failed to register LTDC interrupt\n");
1267 goto err;
1268 }
1269 }
1270
1271
1272 ret = ltdc_get_caps(ddev);
1273 if (ret) {
1274 DRM_ERROR("hardware identifier (0x%08x) not supported!\n",
1275 ldev->caps.hw_version);
1276 goto err;
1277 }
1278
1279 DRM_DEBUG_DRIVER("ltdc hw version 0x%08x\n", ldev->caps.hw_version);
1280
1281 /* Add endpoints panels or bridges if any */
1282 for (i = 0; i < MAX_ENDPOINTS; i++) {
1283 if (panel[i]) {
1284 bridge[i] = drm_panel_bridge_add_typed(panel[i],
1285 DRM_MODE_CONNECTOR_DPI);
1286 if (IS_ERR(bridge[i])) {
1287 DRM_ERROR("panel-bridge endpoint %d\n", i);
1288 ret = PTR_ERR(bridge[i]);
1289 goto err;
1290 }
1291 }
1292
1293 if (bridge[i]) {
1294 ret = ltdc_encoder_init(ddev, bridge[i]);
1295 if (ret) {
1296 DRM_ERROR("init encoder endpoint %d\n", i);
1297 goto err;
1298 }
1299 }
1300 }
1301
1302 crtc = devm_kzalloc(dev, sizeof(*crtc), GFP_KERNEL);
1303 if (!crtc) {
1304 DRM_ERROR("Failed to allocate crtc\n");
1305 ret = -ENOMEM;
1306 goto err;
1307 }
1308
1309 ddev->mode_config.allow_fb_modifiers = true;
1310
1311 ret = ltdc_crtc_init(ddev, crtc);
1312 if (ret) {
1313 DRM_ERROR("Failed to init crtc\n");
1314 goto err;
1315 }
1316
1317 ret = drm_vblank_init(ddev, NB_CRTC);
1318 if (ret) {
1319 DRM_ERROR("Failed calling drm_vblank_init()\n");
1320 goto err;
1321 }
1322
1323 /* Allow usage of vblank without having to call drm_irq_install */
1324 ddev->irq_enabled = 1;
1325
1326 clk_disable_unprepare(ldev->pixel_clk);
1327
1328 pinctrl_pm_select_sleep_state(ddev->dev);
1329
1330 pm_runtime_enable(ddev->dev);
1331
1332 return 0;
1333 err:
1334 for (i = 0; i < MAX_ENDPOINTS; i++)
1335 drm_panel_bridge_remove(bridge[i]);
1336
1337 clk_disable_unprepare(ldev->pixel_clk);
1338
1339 return ret;
1340 }
1341
1342 void ltdc_unload(struct drm_device *ddev)
1343 {
1344 int i;
1345
1346 DRM_DEBUG_DRIVER("\n");
1347
1348 for (i = 0; i < MAX_ENDPOINTS; i++)
1349 drm_of_panel_bridge_remove(ddev->dev->of_node, 0, i);
1350
1351 pm_runtime_disable(ddev->dev);
1352 }
1353
1354 MODULE_AUTHOR("Philippe Cornu <philippe.cornu@st.com>");
1355 MODULE_AUTHOR("Yannick Fertre <yannick.fertre@st.com>");
1356 MODULE_AUTHOR("Fabien Dessenne <fabien.dessenne@st.com>");
1357 MODULE_AUTHOR("Mickael Reulier <mickael.reulier@st.com>");
1358 MODULE_DESCRIPTION("STMicroelectronics ST DRM LTDC driver");
1359 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support