drivers/gpu/drm/sun4i/sun8i_mixer.h

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2 /*
   3  * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
   4  */
   5
   6 #ifndef _SUN8I_MIXER_H_
   7 #define _SUN8I_MIXER_H_
   8
   9 #include <linux/clk.h>
  10 #include <linux/regmap.h>
  11 #include <linux/reset.h>
  12
  13 #include "sun8i_csc.h"
  14 #include "sunxi_engine.h"
  15
  16 #define SUN8I_MIXER_SIZE(w, h)                  (((h) - 1) << 16 | ((w) - 1))
  17 #define SUN8I_MIXER_COORD(x, y)                 ((y) << 16 | (x))
  18
  19 #define SUN8I_MIXER_GLOBAL_CTL                  0x0
  20 #define SUN8I_MIXER_GLOBAL_STATUS               0x4
  21 #define SUN8I_MIXER_GLOBAL_DBUFF                0x8
  22 #define SUN8I_MIXER_GLOBAL_SIZE                 0xc
  23
  24 #define SUN8I_MIXER_GLOBAL_CTL_RT_EN            BIT(0)
  25
  26 #define SUN8I_MIXER_GLOBAL_DBUFF_ENABLE         BIT(0)
  27
  28 #define DE2_MIXER_UNIT_SIZE                     0x6000
  29 #define DE3_MIXER_UNIT_SIZE                     0x3000
  30
  31 #define DE2_BLD_BASE                            0x1000
  32 #define DE2_CH_BASE                             0x2000
  33 #define DE2_CH_SIZE                             0x1000
  34
  35 #define DE3_BLD_BASE                            0x0800
  36 #define DE3_CH_BASE                             0x1000
  37 #define DE3_CH_SIZE                             0x0800
  38
  39 #define SUN8I_MIXER_BLEND_PIPE_CTL(base)        ((base) + 0)
  40 #define SUN8I_MIXER_BLEND_ATTR_FCOLOR(base, x)  ((base) + 0x4 + 0x10 * (x))
  41 #define SUN8I_MIXER_BLEND_ATTR_INSIZE(base, x)  ((base) + 0x8 + 0x10 * (x))
  42 #define SUN8I_MIXER_BLEND_ATTR_COORD(base, x)   ((base) + 0xc + 0x10 * (x))
  43 #define SUN8I_MIXER_BLEND_ROUTE(base)           ((base) + 0x80)
  44 #define SUN8I_MIXER_BLEND_PREMULTIPLY(base)     ((base) + 0x84)
  45 #define SUN8I_MIXER_BLEND_BKCOLOR(base)         ((base) + 0x88)
  46 #define SUN8I_MIXER_BLEND_OUTSIZE(base)         ((base) + 0x8c)
  47 #define SUN8I_MIXER_BLEND_MODE(base, x)         ((base) + 0x90 + 0x04 * (x))
  48 #define SUN8I_MIXER_BLEND_CK_CTL(base)          ((base) + 0xb0)
  49 #define SUN8I_MIXER_BLEND_CK_CFG(base)          ((base) + 0xb4)
  50 #define SUN8I_MIXER_BLEND_CK_MAX(base, x)       ((base) + 0xc0 + 0x04 * (x))
  51 #define SUN8I_MIXER_BLEND_CK_MIN(base, x)       ((base) + 0xe0 + 0x04 * (x))
  52 #define SUN8I_MIXER_BLEND_OUTCTL(base)          ((base) + 0xfc)
  53 #define SUN50I_MIXER_BLEND_CSC_CTL(base)        ((base) + 0x100)
  54 #define SUN50I_MIXER_BLEND_CSC_COEFF(base, layer, x, y) \
  55         ((base) + 0x110 + (layer) * 0x30 +  (x) * 0x10 + 4 * (y))
  56 #define SUN50I_MIXER_BLEND_CSC_CONST(base, layer, i) \
  57         ((base) + 0x110 + (layer) * 0x30 +  (i) * 0x10 + 0x0c)
  58
  59 #define SUN8I_MIXER_BLEND_PIPE_CTL_EN_MSK       GENMASK(12, 8)
  60 #define SUN8I_MIXER_BLEND_PIPE_CTL_EN(pipe)     BIT(8 + pipe)
  61 #define SUN8I_MIXER_BLEND_PIPE_CTL_FC_EN(pipe)  BIT(pipe)
  62
  63 /* colors are always in AARRGGBB format */
  64 #define SUN8I_MIXER_BLEND_COLOR_BLACK           0xff000000
  65 /* The following numbers are some still unknown magic numbers */
  66 #define SUN8I_MIXER_BLEND_MODE_DEF              0x03010301
  67
  68 #define SUN8I_MIXER_BLEND_ROUTE_PIPE_MSK(n)     (0xf << ((n) << 2))
  69 #define SUN8I_MIXER_BLEND_ROUTE_PIPE_SHIFT(n)   ((n) << 2)
  70
  71 #define SUN8I_MIXER_BLEND_OUTCTL_INTERLACED     BIT(1)
  72
  73 #define SUN50I_MIXER_BLEND_CSC_CTL_EN(ch)       BIT(ch)
  74 #define SUN50I_MIXER_BLEND_CSC_CONST_VAL(d, c)  (((d) << 16) | ((c) & 0xffff))
  75
  76 #define SUN8I_MIXER_FBFMT_ARGB8888      0
  77 #define SUN8I_MIXER_FBFMT_ABGR8888      1
  78 #define SUN8I_MIXER_FBFMT_RGBA8888      2
  79 #define SUN8I_MIXER_FBFMT_BGRA8888      3
  80 #define SUN8I_MIXER_FBFMT_XRGB8888      4
  81 #define SUN8I_MIXER_FBFMT_XBGR8888      5
  82 #define SUN8I_MIXER_FBFMT_RGBX8888      6
  83 #define SUN8I_MIXER_FBFMT_BGRX8888      7
  84 #define SUN8I_MIXER_FBFMT_RGB888        8
  85 #define SUN8I_MIXER_FBFMT_BGR888        9
  86 #define SUN8I_MIXER_FBFMT_RGB565        10
  87 #define SUN8I_MIXER_FBFMT_BGR565        11
  88 #define SUN8I_MIXER_FBFMT_ARGB4444      12
  89 #define SUN8I_MIXER_FBFMT_ABGR4444      13
  90 #define SUN8I_MIXER_FBFMT_RGBA4444      14
  91 #define SUN8I_MIXER_FBFMT_BGRA4444      15
  92 #define SUN8I_MIXER_FBFMT_ARGB1555      16
  93 #define SUN8I_MIXER_FBFMT_ABGR1555      17
  94 #define SUN8I_MIXER_FBFMT_RGBA5551      18
  95 #define SUN8I_MIXER_FBFMT_BGRA5551      19
  96
  97 #define SUN8I_MIXER_FBFMT_YUYV          0
  98 #define SUN8I_MIXER_FBFMT_UYVY          1
  99 #define SUN8I_MIXER_FBFMT_YVYU          2
 100 #define SUN8I_MIXER_FBFMT_VYUY          3
 101 #define SUN8I_MIXER_FBFMT_NV16          4
 102 #define SUN8I_MIXER_FBFMT_NV61          5
 103 #define SUN8I_MIXER_FBFMT_YUV422        6
 104 /* format 7 doesn't exist */
 105 #define SUN8I_MIXER_FBFMT_NV12          8
 106 #define SUN8I_MIXER_FBFMT_NV21          9
 107 #define SUN8I_MIXER_FBFMT_YUV420        10
 108 /* format 11 doesn't exist */
 109 /* format 12 is semi-planar YUV411 UVUV */
 110 /* format 13 is semi-planar YUV411 VUVU */
 111 #define SUN8I_MIXER_FBFMT_YUV411        14
 112
 113 /*
 114  * Sub-engines listed bellow are unused for now. The EN registers are here only
 115  * to be used to disable these sub-engines.
 116  */
 117 #define SUN8I_MIXER_FCE_EN                      0xa0000
 118 #define SUN8I_MIXER_BWS_EN                      0xa2000
 119 #define SUN8I_MIXER_LTI_EN                      0xa4000
 120 #define SUN8I_MIXER_PEAK_EN                     0xa6000
 121 #define SUN8I_MIXER_ASE_EN                      0xa8000
 122 #define SUN8I_MIXER_FCC_EN                      0xaa000
 123 #define SUN8I_MIXER_DCSC_EN                     0xb0000
 124
 125 #define SUN50I_MIXER_FCE_EN                     0x70000
 126 #define SUN50I_MIXER_PEAK_EN                    0x70800
 127 #define SUN50I_MIXER_LCTI_EN                    0x71000
 128 #define SUN50I_MIXER_BLS_EN                     0x71800
 129 #define SUN50I_MIXER_FCC_EN                     0x72000
 130 #define SUN50I_MIXER_DNS_EN                     0x80000
 131 #define SUN50I_MIXER_DRC_EN                     0xa0000
 132 #define SUN50I_MIXER_FMT_EN                     0xa8000
 133 #define SUN50I_MIXER_CDC0_EN                    0xd0000
 134 #define SUN50I_MIXER_CDC1_EN                    0xd8000
 135
 136 struct de2_fmt_info {
 137         u32                     drm_fmt;
 138         u32                     de2_fmt;
 139         bool                    rgb;
 140         enum sun8i_csc_mode     csc;
 141 };
 142
 143 /**
 144  * struct sun8i_mixer_cfg - mixer HW configuration
 145  * @vi_num: number of VI channels
 146  * @ui_num: number of UI channels
 147  * @scaler_mask: bitmask which tells which channel supports scaling
 148  *      First, scaler supports for VI channels is defined and after that, scaler
 149  *      support for UI channels. For example, if mixer has 2 VI channels without
 150  *      scaler and 2 UI channels with scaler, bitmask would be 0xC.
 151  * @ccsc: select set of CCSC base addresses
 152  *      Set value to 0 if this is first mixer or second mixer with VEP support.
 153  *      Set value to 1 if this is second mixer without VEP support. Other values
 154  *      are invalid.
 155  * @mod_rate: module clock rate that needs to be set in order to have
 156  *      a functional block.
 157  * @is_de3: true, if this is next gen display engine 3.0, false otherwise.
 158  * @scaline_yuv: size of a scanline for VI scaler for YUV formats.
 159  */
 160 struct sun8i_mixer_cfg {
 161         int             vi_num;
 162         int             ui_num;
 163         int             scaler_mask;
 164         int             ccsc;
 165         unsigned long   mod_rate;
 166         unsigned int    is_de3 : 1;
 167         unsigned int    scanline_yuv;
 168 };
 169
 170 struct sun8i_mixer {
 171         struct sunxi_engine             engine;
 172
 173         const struct sun8i_mixer_cfg    *cfg;
 174
 175         struct reset_control            *reset;
 176
 177         struct clk                      *bus_clk;
 178         struct clk                      *mod_clk;
 179 };
 180
 181 static inline struct sun8i_mixer *
 182 engine_to_sun8i_mixer(struct sunxi_engine *engine)
 183 {
 184         return container_of(engine, struct sun8i_mixer, engine);
 185 }
 186
 187 static inline u32
 188 sun8i_blender_base(struct sun8i_mixer *mixer)
 189 {
 190         return mixer->cfg->is_de3 ? DE3_BLD_BASE : DE2_BLD_BASE;
 191 }
 192
 193 static inline u32
 194 sun8i_channel_base(struct sun8i_mixer *mixer, int channel)
 195 {
 196         if (mixer->cfg->is_de3)
 197                 return DE3_CH_BASE + channel * DE3_CH_SIZE;
 198         else
 199                 return DE2_CH_BASE + channel * DE2_CH_SIZE;
 200 }
 201
 202 const struct de2_fmt_info *sun8i_mixer_format_info(u32 format);
 203 #endif /* _SUN8I_MIXER_H_ */