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treewide: remove redundant IS_ERR() before error code check
[linux/fpc-iii.git] / drivers / gpu / drm / tegra / dc.c
blob7c70fd31a4c248ab495a9f130c36d5bd2cc7865f
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2012 Avionic Design GmbH
4 * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
5 */
6
7 #include <linux/clk.h>
8 #include <linux/debugfs.h>
9 #include <linux/delay.h>
10 #include <linux/iommu.h>
11 #include <linux/module.h>
12 #include <linux/of_device.h>
13 #include <linux/pm_runtime.h>
14 #include <linux/reset.h>
15
16 #include <soc/tegra/pmc.h>
17
18 #include <drm/drm_atomic.h>
19 #include <drm/drm_atomic_helper.h>
20 #include <drm/drm_debugfs.h>
21 #include <drm/drm_fourcc.h>
22 #include <drm/drm_plane_helper.h>
23 #include <drm/drm_vblank.h>
24
25 #include "dc.h"
26 #include "drm.h"
27 #include "gem.h"
28 #include "hub.h"
29 #include "plane.h"
30
31 static void tegra_crtc_atomic_destroy_state(struct drm_crtc *crtc,
32 struct drm_crtc_state *state);
33
34 static void tegra_dc_stats_reset(struct tegra_dc_stats *stats)
35 {
36 stats->frames = 0;
37 stats->vblank = 0;
38 stats->underflow = 0;
39 stats->overflow = 0;
40 }
41
42 /* Reads the active copy of a register. */
43 static u32 tegra_dc_readl_active(struct tegra_dc *dc, unsigned long offset)
44 {
45 u32 value;
46
47 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS);
48 value = tegra_dc_readl(dc, offset);
49 tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS);
50
51 return value;
52 }
53
54 static inline unsigned int tegra_plane_offset(struct tegra_plane *plane,
55 unsigned int offset)
56 {
57 if (offset >= 0x500 && offset <= 0x638) {
58 offset = 0x000 + (offset - 0x500);
59 return plane->offset + offset;
60 }
61
62 if (offset >= 0x700 && offset <= 0x719) {
63 offset = 0x180 + (offset - 0x700);
64 return plane->offset + offset;
65 }
66
67 if (offset >= 0x800 && offset <= 0x839) {
68 offset = 0x1c0 + (offset - 0x800);
69 return plane->offset + offset;
70 }
71
72 dev_WARN(plane->dc->dev, "invalid offset: %x\n", offset);
73
74 return plane->offset + offset;
75 }
76
77 static inline u32 tegra_plane_readl(struct tegra_plane *plane,
78 unsigned int offset)
79 {
80 return tegra_dc_readl(plane->dc, tegra_plane_offset(plane, offset));
81 }
82
83 static inline void tegra_plane_writel(struct tegra_plane *plane, u32 value,
84 unsigned int offset)
85 {
86 tegra_dc_writel(plane->dc, value, tegra_plane_offset(plane, offset));
87 }
88
89 bool tegra_dc_has_output(struct tegra_dc *dc, struct device *dev)
90 {
91 struct device_node *np = dc->dev->of_node;
92 struct of_phandle_iterator it;
93 int err;
94
95 of_for_each_phandle(&it, err, np, "nvidia,outputs", NULL, 0)
96 if (it.node == dev->of_node)
97 return true;
98
99 return false;
100 }
101
102 /*
103 * Double-buffered registers have two copies: ASSEMBLY and ACTIVE. When the
104 * *_ACT_REQ bits are set the ASSEMBLY copy is latched into the ACTIVE copy.
105 * Latching happens mmediately if the display controller is in STOP mode or
106 * on the next frame boundary otherwise.
107 *
108 * Triple-buffered registers have three copies: ASSEMBLY, ARM and ACTIVE. The
109 * ASSEMBLY copy is latched into the ARM copy immediately after *_UPDATE bits
110 * are written. When the *_ACT_REQ bits are written, the ARM copy is latched
111 * into the ACTIVE copy, either immediately if the display controller is in
112 * STOP mode, or at the next frame boundary otherwise.
113 */
114 void tegra_dc_commit(struct tegra_dc *dc)
115 {
116 tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
117 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
118 }
119
120 static inline u32 compute_dda_inc(unsigned int in, unsigned int out, bool v,
121 unsigned int bpp)
122 {
123 fixed20_12 outf = dfixed_init(out);
124 fixed20_12 inf = dfixed_init(in);
125 u32 dda_inc;
126 int max;
127
128 if (v)
129 max = 15;
130 else {
131 switch (bpp) {
132 case 2:
133 max = 8;
134 break;
135
136 default:
137 WARN_ON_ONCE(1);
138 /* fallthrough */
139 case 4:
140 max = 4;
141 break;
142 }
143 }
144
145 outf.full = max_t(u32, outf.full - dfixed_const(1), dfixed_const(1));
146 inf.full -= dfixed_const(1);
147
148 dda_inc = dfixed_div(inf, outf);
149 dda_inc = min_t(u32, dda_inc, dfixed_const(max));
150
151 return dda_inc;
152 }
153
154 static inline u32 compute_initial_dda(unsigned int in)
155 {
156 fixed20_12 inf = dfixed_init(in);
157 return dfixed_frac(inf);
158 }
159
160 static void tegra_plane_setup_blending_legacy(struct tegra_plane *plane)
161 {
162 u32 background[3] = {
163 BLEND_WEIGHT1(0) | BLEND_WEIGHT0(0) | BLEND_COLOR_KEY_NONE,
164 BLEND_WEIGHT1(0) | BLEND_WEIGHT0(0) | BLEND_COLOR_KEY_NONE,
165 BLEND_WEIGHT1(0) | BLEND_WEIGHT0(0) | BLEND_COLOR_KEY_NONE,
166 };
167 u32 foreground = BLEND_WEIGHT1(255) | BLEND_WEIGHT0(255) |
168 BLEND_COLOR_KEY_NONE;
169 u32 blendnokey = BLEND_WEIGHT1(255) | BLEND_WEIGHT0(255);
170 struct tegra_plane_state *state;
171 u32 blending[2];
172 unsigned int i;
173
174 /* disable blending for non-overlapping case */
175 tegra_plane_writel(plane, blendnokey, DC_WIN_BLEND_NOKEY);
176 tegra_plane_writel(plane, foreground, DC_WIN_BLEND_1WIN);
177
178 state = to_tegra_plane_state(plane->base.state);
179
180 if (state->opaque) {
181 /*
182 * Since custom fix-weight blending isn't utilized and weight
183 * of top window is set to max, we can enforce dependent
184 * blending which in this case results in transparent bottom
185 * window if top window is opaque and if top window enables
186 * alpha blending, then bottom window is getting alpha value
187 * of 1 minus the sum of alpha components of the overlapping
188 * plane.
189 */
190 background[0] |= BLEND_CONTROL_DEPENDENT;
191 background[1] |= BLEND_CONTROL_DEPENDENT;
192
193 /*
194 * The region where three windows overlap is the intersection
195 * of the two regions where two windows overlap. It contributes
196 * to the area if all of the windows on top of it have an alpha
197 * component.
198 */
199 switch (state->base.normalized_zpos) {
200 case 0:
201 if (state->blending[0].alpha &&
202 state->blending[1].alpha)
203 background[2] |= BLEND_CONTROL_DEPENDENT;
204 break;
205
206 case 1:
207 background[2] |= BLEND_CONTROL_DEPENDENT;
208 break;
209 }
210 } else {
211 /*
212 * Enable alpha blending if pixel format has an alpha
213 * component.
214 */
215 foreground |= BLEND_CONTROL_ALPHA;
216
217 /*
218 * If any of the windows on top of this window is opaque, it
219 * will completely conceal this window within that area. If
220 * top window has an alpha component, it is blended over the
221 * bottom window.
222 */
223 for (i = 0; i < 2; i++) {
224 if (state->blending[i].alpha &&
225 state->blending[i].top)
226 background[i] |= BLEND_CONTROL_DEPENDENT;
227 }
228
229 switch (state->base.normalized_zpos) {
230 case 0:
231 if (state->blending[0].alpha &&
232 state->blending[1].alpha)
233 background[2] |= BLEND_CONTROL_DEPENDENT;
234 break;
235
236 case 1:
237 /*
238 * When both middle and topmost windows have an alpha,
239 * these windows a mixed together and then the result
240 * is blended over the bottom window.
241 */
242 if (state->blending[0].alpha &&
243 state->blending[0].top)
244 background[2] |= BLEND_CONTROL_ALPHA;
245
246 if (state->blending[1].alpha &&
247 state->blending[1].top)
248 background[2] |= BLEND_CONTROL_ALPHA;
249 break;
250 }
251 }
252
253 switch (state->base.normalized_zpos) {
254 case 0:
255 tegra_plane_writel(plane, background[0], DC_WIN_BLEND_2WIN_X);
256 tegra_plane_writel(plane, background[1], DC_WIN_BLEND_2WIN_Y);
257 tegra_plane_writel(plane, background[2], DC_WIN_BLEND_3WIN_XY);
258 break;
259
260 case 1:
261 /*
262 * If window B / C is topmost, then X / Y registers are
263 * matching the order of blending[...] state indices,
264 * otherwise a swap is required.
265 */
266 if (!state->blending[0].top && state->blending[1].top) {
267 blending[0] = foreground;
268 blending[1] = background[1];
269 } else {
270 blending[0] = background[0];
271 blending[1] = foreground;
272 }
273
274 tegra_plane_writel(plane, blending[0], DC_WIN_BLEND_2WIN_X);
275 tegra_plane_writel(plane, blending[1], DC_WIN_BLEND_2WIN_Y);
276 tegra_plane_writel(plane, background[2], DC_WIN_BLEND_3WIN_XY);
277 break;
278
279 case 2:
280 tegra_plane_writel(plane, foreground, DC_WIN_BLEND_2WIN_X);
281 tegra_plane_writel(plane, foreground, DC_WIN_BLEND_2WIN_Y);
282 tegra_plane_writel(plane, foreground, DC_WIN_BLEND_3WIN_XY);
283 break;
284 }
285 }
286
287 static void tegra_plane_setup_blending(struct tegra_plane *plane,
288 const struct tegra_dc_window *window)
289 {
290 u32 value;
291
292 value = BLEND_FACTOR_DST_ALPHA_ZERO | BLEND_FACTOR_SRC_ALPHA_K2 |
293 BLEND_FACTOR_DST_COLOR_NEG_K1_TIMES_SRC |
294 BLEND_FACTOR_SRC_COLOR_K1_TIMES_SRC;
295 tegra_plane_writel(plane, value, DC_WIN_BLEND_MATCH_SELECT);
296
297 value = BLEND_FACTOR_DST_ALPHA_ZERO | BLEND_FACTOR_SRC_ALPHA_K2 |
298 BLEND_FACTOR_DST_COLOR_NEG_K1_TIMES_SRC |
299 BLEND_FACTOR_SRC_COLOR_K1_TIMES_SRC;
300 tegra_plane_writel(plane, value, DC_WIN_BLEND_NOMATCH_SELECT);
301
302 value = K2(255) | K1(255) | WINDOW_LAYER_DEPTH(255 - window->zpos);
303 tegra_plane_writel(plane, value, DC_WIN_BLEND_LAYER_CONTROL);
304 }
305
306 static bool
307 tegra_plane_use_horizontal_filtering(struct tegra_plane *plane,
308 const struct tegra_dc_window *window)
309 {
310 struct tegra_dc *dc = plane->dc;
311
312 if (window->src.w == window->dst.w)
313 return false;
314
315 if (plane->index == 0 && dc->soc->has_win_a_without_filters)
316 return false;
317
318 return true;
319 }
320
321 static bool
322 tegra_plane_use_vertical_filtering(struct tegra_plane *plane,
323 const struct tegra_dc_window *window)
324 {
325 struct tegra_dc *dc = plane->dc;
326
327 if (window->src.h == window->dst.h)
328 return false;
329
330 if (plane->index == 0 && dc->soc->has_win_a_without_filters)
331 return false;
332
333 if (plane->index == 2 && dc->soc->has_win_c_without_vert_filter)
334 return false;
335
336 return true;
337 }
338
339 static void tegra_dc_setup_window(struct tegra_plane *plane,
340 const struct tegra_dc_window *window)
341 {
342 unsigned h_offset, v_offset, h_size, v_size, h_dda, v_dda, bpp;
343 struct tegra_dc *dc = plane->dc;
344 bool yuv, planar;
345 u32 value;
346
347 /*
348 * For YUV planar modes, the number of bytes per pixel takes into
349 * account only the luma component and therefore is 1.
350 */
351 yuv = tegra_plane_format_is_yuv(window->format, &planar);
352 if (!yuv)
353 bpp = window->bits_per_pixel / 8;
354 else
355 bpp = planar ? 1 : 2;
356
357 tegra_plane_writel(plane, window->format, DC_WIN_COLOR_DEPTH);
358 tegra_plane_writel(plane, window->swap, DC_WIN_BYTE_SWAP);
359
360 value = V_POSITION(window->dst.y) | H_POSITION(window->dst.x);
361 tegra_plane_writel(plane, value, DC_WIN_POSITION);
362
363 value = V_SIZE(window->dst.h) | H_SIZE(window->dst.w);
364 tegra_plane_writel(plane, value, DC_WIN_SIZE);
365
366 h_offset = window->src.x * bpp;
367 v_offset = window->src.y;
368 h_size = window->src.w * bpp;
369 v_size = window->src.h;
370
371 value = V_PRESCALED_SIZE(v_size) | H_PRESCALED_SIZE(h_size);
372 tegra_plane_writel(plane, value, DC_WIN_PRESCALED_SIZE);
373
374 /*
375 * For DDA computations the number of bytes per pixel for YUV planar
376 * modes needs to take into account all Y, U and V components.
377 */
378 if (yuv && planar)
379 bpp = 2;
380
381 h_dda = compute_dda_inc(window->src.w, window->dst.w, false, bpp);
382 v_dda = compute_dda_inc(window->src.h, window->dst.h, true, bpp);
383
384 value = V_DDA_INC(v_dda) | H_DDA_INC(h_dda);
385 tegra_plane_writel(plane, value, DC_WIN_DDA_INC);
386
387 h_dda = compute_initial_dda(window->src.x);
388 v_dda = compute_initial_dda(window->src.y);
389
390 tegra_plane_writel(plane, h_dda, DC_WIN_H_INITIAL_DDA);
391 tegra_plane_writel(plane, v_dda, DC_WIN_V_INITIAL_DDA);
392
393 tegra_plane_writel(plane, 0, DC_WIN_UV_BUF_STRIDE);
394 tegra_plane_writel(plane, 0, DC_WIN_BUF_STRIDE);
395
396 tegra_plane_writel(plane, window->base[0], DC_WINBUF_START_ADDR);
397
398 if (yuv && planar) {
399 tegra_plane_writel(plane, window->base[1], DC_WINBUF_START_ADDR_U);
400 tegra_plane_writel(plane, window->base[2], DC_WINBUF_START_ADDR_V);
401 value = window->stride[1] << 16 | window->stride[0];
402 tegra_plane_writel(plane, value, DC_WIN_LINE_STRIDE);
403 } else {
404 tegra_plane_writel(plane, window->stride[0], DC_WIN_LINE_STRIDE);
405 }
406
407 if (window->bottom_up)
408 v_offset += window->src.h - 1;
409
410 tegra_plane_writel(plane, h_offset, DC_WINBUF_ADDR_H_OFFSET);
411 tegra_plane_writel(plane, v_offset, DC_WINBUF_ADDR_V_OFFSET);
412
413 if (dc->soc->supports_block_linear) {
414 unsigned long height = window->tiling.value;
415
416 switch (window->tiling.mode) {
417 case TEGRA_BO_TILING_MODE_PITCH:
418 value = DC_WINBUF_SURFACE_KIND_PITCH;
419 break;
420
421 case TEGRA_BO_TILING_MODE_TILED:
422 value = DC_WINBUF_SURFACE_KIND_TILED;
423 break;
424
425 case TEGRA_BO_TILING_MODE_BLOCK:
426 value = DC_WINBUF_SURFACE_KIND_BLOCK_HEIGHT(height) |
427 DC_WINBUF_SURFACE_KIND_BLOCK;
428 break;
429 }
430
431 tegra_plane_writel(plane, value, DC_WINBUF_SURFACE_KIND);
432 } else {
433 switch (window->tiling.mode) {
434 case TEGRA_BO_TILING_MODE_PITCH:
435 value = DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV |
436 DC_WIN_BUFFER_ADDR_MODE_LINEAR;
437 break;
438
439 case TEGRA_BO_TILING_MODE_TILED:
440 value = DC_WIN_BUFFER_ADDR_MODE_TILE_UV |
441 DC_WIN_BUFFER_ADDR_MODE_TILE;
442 break;
443
444 case TEGRA_BO_TILING_MODE_BLOCK:
445 /*
446 * No need to handle this here because ->atomic_check
447 * will already have filtered it out.
448 */
449 break;
450 }
451
452 tegra_plane_writel(plane, value, DC_WIN_BUFFER_ADDR_MODE);
453 }
454
455 value = WIN_ENABLE;
456
457 if (yuv) {
458 /* setup default colorspace conversion coefficients */
459 tegra_plane_writel(plane, 0x00f0, DC_WIN_CSC_YOF);
460 tegra_plane_writel(plane, 0x012a, DC_WIN_CSC_KYRGB);
461 tegra_plane_writel(plane, 0x0000, DC_WIN_CSC_KUR);
462 tegra_plane_writel(plane, 0x0198, DC_WIN_CSC_KVR);
463 tegra_plane_writel(plane, 0x039b, DC_WIN_CSC_KUG);
464 tegra_plane_writel(plane, 0x032f, DC_WIN_CSC_KVG);
465 tegra_plane_writel(plane, 0x0204, DC_WIN_CSC_KUB);
466 tegra_plane_writel(plane, 0x0000, DC_WIN_CSC_KVB);
467
468 value |= CSC_ENABLE;
469 } else if (window->bits_per_pixel < 24) {
470 value |= COLOR_EXPAND;
471 }
472
473 if (window->bottom_up)
474 value |= V_DIRECTION;
475
476 if (tegra_plane_use_horizontal_filtering(plane, window)) {
477 /*
478 * Enable horizontal 6-tap filter and set filtering
479 * coefficients to the default values defined in TRM.
480 */
481 tegra_plane_writel(plane, 0x00008000, DC_WIN_H_FILTER_P(0));
482 tegra_plane_writel(plane, 0x3e087ce1, DC_WIN_H_FILTER_P(1));
483 tegra_plane_writel(plane, 0x3b117ac1, DC_WIN_H_FILTER_P(2));
484 tegra_plane_writel(plane, 0x591b73aa, DC_WIN_H_FILTER_P(3));
485 tegra_plane_writel(plane, 0x57256d9a, DC_WIN_H_FILTER_P(4));
486 tegra_plane_writel(plane, 0x552f668b, DC_WIN_H_FILTER_P(5));
487 tegra_plane_writel(plane, 0x73385e8b, DC_WIN_H_FILTER_P(6));
488 tegra_plane_writel(plane, 0x72435583, DC_WIN_H_FILTER_P(7));
489 tegra_plane_writel(plane, 0x714c4c8b, DC_WIN_H_FILTER_P(8));
490 tegra_plane_writel(plane, 0x70554393, DC_WIN_H_FILTER_P(9));
491 tegra_plane_writel(plane, 0x715e389b, DC_WIN_H_FILTER_P(10));
492 tegra_plane_writel(plane, 0x71662faa, DC_WIN_H_FILTER_P(11));
493 tegra_plane_writel(plane, 0x536d25ba, DC_WIN_H_FILTER_P(12));
494 tegra_plane_writel(plane, 0x55731bca, DC_WIN_H_FILTER_P(13));
495 tegra_plane_writel(plane, 0x387a11d9, DC_WIN_H_FILTER_P(14));
496 tegra_plane_writel(plane, 0x3c7c08f1, DC_WIN_H_FILTER_P(15));
497
498 value |= H_FILTER;
499 }
500
501 if (tegra_plane_use_vertical_filtering(plane, window)) {
502 unsigned int i, k;
503
504 /*
505 * Enable vertical 2-tap filter and set filtering
506 * coefficients to the default values defined in TRM.
507 */
508 for (i = 0, k = 128; i < 16; i++, k -= 8)
509 tegra_plane_writel(plane, k, DC_WIN_V_FILTER_P(i));
510
511 value |= V_FILTER;
512 }
513
514 tegra_plane_writel(plane, value, DC_WIN_WIN_OPTIONS);
515
516 if (dc->soc->has_legacy_blending)
517 tegra_plane_setup_blending_legacy(plane);
518 else
519 tegra_plane_setup_blending(plane, window);
520 }
521
522 static const u32 tegra20_primary_formats[] = {
523 DRM_FORMAT_ARGB4444,
524 DRM_FORMAT_ARGB1555,
525 DRM_FORMAT_RGB565,
526 DRM_FORMAT_RGBA5551,
527 DRM_FORMAT_ABGR8888,
528 DRM_FORMAT_ARGB8888,
529 /* non-native formats */
530 DRM_FORMAT_XRGB1555,
531 DRM_FORMAT_RGBX5551,
532 DRM_FORMAT_XBGR8888,
533 DRM_FORMAT_XRGB8888,
534 };
535
536 static const u64 tegra20_modifiers[] = {
537 DRM_FORMAT_MOD_LINEAR,
538 DRM_FORMAT_MOD_NVIDIA_TEGRA_TILED,
539 DRM_FORMAT_MOD_INVALID
540 };
541
542 static const u32 tegra114_primary_formats[] = {
543 DRM_FORMAT_ARGB4444,
544 DRM_FORMAT_ARGB1555,
545 DRM_FORMAT_RGB565,
546 DRM_FORMAT_RGBA5551,
547 DRM_FORMAT_ABGR8888,
548 DRM_FORMAT_ARGB8888,
549 /* new on Tegra114 */
550 DRM_FORMAT_ABGR4444,
551 DRM_FORMAT_ABGR1555,
552 DRM_FORMAT_BGRA5551,
553 DRM_FORMAT_XRGB1555,
554 DRM_FORMAT_RGBX5551,
555 DRM_FORMAT_XBGR1555,
556 DRM_FORMAT_BGRX5551,
557 DRM_FORMAT_BGR565,
558 DRM_FORMAT_BGRA8888,
559 DRM_FORMAT_RGBA8888,
560 DRM_FORMAT_XRGB8888,
561 DRM_FORMAT_XBGR8888,
562 };
563
564 static const u32 tegra124_primary_formats[] = {
565 DRM_FORMAT_ARGB4444,
566 DRM_FORMAT_ARGB1555,
567 DRM_FORMAT_RGB565,
568 DRM_FORMAT_RGBA5551,
569 DRM_FORMAT_ABGR8888,
570 DRM_FORMAT_ARGB8888,
571 /* new on Tegra114 */
572 DRM_FORMAT_ABGR4444,
573 DRM_FORMAT_ABGR1555,
574 DRM_FORMAT_BGRA5551,
575 DRM_FORMAT_XRGB1555,
576 DRM_FORMAT_RGBX5551,
577 DRM_FORMAT_XBGR1555,
578 DRM_FORMAT_BGRX5551,
579 DRM_FORMAT_BGR565,
580 DRM_FORMAT_BGRA8888,
581 DRM_FORMAT_RGBA8888,
582 DRM_FORMAT_XRGB8888,
583 DRM_FORMAT_XBGR8888,
584 /* new on Tegra124 */
585 DRM_FORMAT_RGBX8888,
586 DRM_FORMAT_BGRX8888,
587 };
588
589 static const u64 tegra124_modifiers[] = {
590 DRM_FORMAT_MOD_LINEAR,
591 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(0),
592 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(1),
593 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(2),
594 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(3),
595 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(4),
596 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(5),
597 DRM_FORMAT_MOD_INVALID
598 };
599
600 static int tegra_plane_atomic_check(struct drm_plane *plane,
601 struct drm_plane_state *state)
602 {
603 struct tegra_plane_state *plane_state = to_tegra_plane_state(state);
604 unsigned int rotation = DRM_MODE_ROTATE_0 | DRM_MODE_REFLECT_Y;
605 struct tegra_bo_tiling *tiling = &plane_state->tiling;
606 struct tegra_plane *tegra = to_tegra_plane(plane);
607 struct tegra_dc *dc = to_tegra_dc(state->crtc);
608 int err;
609
610 /* no need for further checks if the plane is being disabled */
611 if (!state->crtc)
612 return 0;
613
614 err = tegra_plane_format(state->fb->format->format,
615 &plane_state->format,
616 &plane_state->swap);
617 if (err < 0)
618 return err;
619
620 /*
621 * Tegra20 and Tegra30 are special cases here because they support
622 * only variants of specific formats with an alpha component, but not
623 * the corresponding opaque formats. However, the opaque formats can
624 * be emulated by disabling alpha blending for the plane.
625 */
626 if (dc->soc->has_legacy_blending) {
627 err = tegra_plane_setup_legacy_state(tegra, plane_state);
628 if (err < 0)
629 return err;
630 }
631
632 err = tegra_fb_get_tiling(state->fb, tiling);
633 if (err < 0)
634 return err;
635
636 if (tiling->mode == TEGRA_BO_TILING_MODE_BLOCK &&
637 !dc->soc->supports_block_linear) {
638 DRM_ERROR("hardware doesn't support block linear mode\n");
639 return -EINVAL;
640 }
641
642 rotation = drm_rotation_simplify(state->rotation, rotation);
643
644 if (rotation & DRM_MODE_REFLECT_Y)
645 plane_state->bottom_up = true;
646 else
647 plane_state->bottom_up = false;
648
649 /*
650 * Tegra doesn't support different strides for U and V planes so we
651 * error out if the user tries to display a framebuffer with such a
652 * configuration.
653 */
654 if (state->fb->format->num_planes > 2) {
655 if (state->fb->pitches[2] != state->fb->pitches[1]) {
656 DRM_ERROR("unsupported UV-plane configuration\n");
657 return -EINVAL;
658 }
659 }
660
661 err = tegra_plane_state_add(tegra, state);
662 if (err < 0)
663 return err;
664
665 return 0;
666 }
667
668 static void tegra_plane_atomic_disable(struct drm_plane *plane,
669 struct drm_plane_state *old_state)
670 {
671 struct tegra_plane *p = to_tegra_plane(plane);
672 u32 value;
673
674 /* rien ne va plus */
675 if (!old_state || !old_state->crtc)
676 return;
677
678 value = tegra_plane_readl(p, DC_WIN_WIN_OPTIONS);
679 value &= ~WIN_ENABLE;
680 tegra_plane_writel(p, value, DC_WIN_WIN_OPTIONS);
681 }
682
683 static void tegra_plane_atomic_update(struct drm_plane *plane,
684 struct drm_plane_state *old_state)
685 {
686 struct tegra_plane_state *state = to_tegra_plane_state(plane->state);
687 struct drm_framebuffer *fb = plane->state->fb;
688 struct tegra_plane *p = to_tegra_plane(plane);
689 struct tegra_dc_window window;
690 unsigned int i;
691
692 /* rien ne va plus */
693 if (!plane->state->crtc || !plane->state->fb)
694 return;
695
696 if (!plane->state->visible)
697 return tegra_plane_atomic_disable(plane, old_state);
698
699 memset(&window, 0, sizeof(window));
700 window.src.x = plane->state->src.x1 >> 16;
701 window.src.y = plane->state->src.y1 >> 16;
702 window.src.w = drm_rect_width(&plane->state->src) >> 16;
703 window.src.h = drm_rect_height(&plane->state->src) >> 16;
704 window.dst.x = plane->state->dst.x1;
705 window.dst.y = plane->state->dst.y1;
706 window.dst.w = drm_rect_width(&plane->state->dst);
707 window.dst.h = drm_rect_height(&plane->state->dst);
708 window.bits_per_pixel = fb->format->cpp[0] * 8;
709 window.bottom_up = tegra_fb_is_bottom_up(fb) || state->bottom_up;
710
711 /* copy from state */
712 window.zpos = plane->state->normalized_zpos;
713 window.tiling = state->tiling;
714 window.format = state->format;
715 window.swap = state->swap;
716
717 for (i = 0; i < fb->format->num_planes; i++) {
718 window.base[i] = state->iova[i] + fb->offsets[i];
719
720 /*
721 * Tegra uses a shared stride for UV planes. Framebuffers are
722 * already checked for this in the tegra_plane_atomic_check()
723 * function, so it's safe to ignore the V-plane pitch here.
724 */
725 if (i < 2)
726 window.stride[i] = fb->pitches[i];
727 }
728
729 tegra_dc_setup_window(p, &window);
730 }
731
732 static const struct drm_plane_helper_funcs tegra_plane_helper_funcs = {
733 .prepare_fb = tegra_plane_prepare_fb,
734 .cleanup_fb = tegra_plane_cleanup_fb,
735 .atomic_check = tegra_plane_atomic_check,
736 .atomic_disable = tegra_plane_atomic_disable,
737 .atomic_update = tegra_plane_atomic_update,
738 };
739
740 static unsigned long tegra_plane_get_possible_crtcs(struct drm_device *drm)
741 {
742 /*
743 * Ideally this would use drm_crtc_mask(), but that would require the
744 * CRTC to already be in the mode_config's list of CRTCs. However, it
745 * will only be added to that list in the drm_crtc_init_with_planes()
746 * (in tegra_dc_init()), which in turn requires registration of these
747 * planes. So we have ourselves a nice little chicken and egg problem
748 * here.
749 *
750 * We work around this by manually creating the mask from the number
751 * of CRTCs that have been registered, and should therefore always be
752 * the same as drm_crtc_index() after registration.
753 */
754 return 1 << drm->mode_config.num_crtc;
755 }
756
757 static struct drm_plane *tegra_primary_plane_create(struct drm_device *drm,
758 struct tegra_dc *dc)
759 {
760 unsigned long possible_crtcs = tegra_plane_get_possible_crtcs(drm);
761 enum drm_plane_type type = DRM_PLANE_TYPE_PRIMARY;
762 struct tegra_plane *plane;
763 unsigned int num_formats;
764 const u64 *modifiers;
765 const u32 *formats;
766 int err;
767
768 plane = kzalloc(sizeof(*plane), GFP_KERNEL);
769 if (!plane)
770 return ERR_PTR(-ENOMEM);
771
772 /* Always use window A as primary window */
773 plane->offset = 0xa00;
774 plane->index = 0;
775 plane->dc = dc;
776
777 num_formats = dc->soc->num_primary_formats;
778 formats = dc->soc->primary_formats;
779 modifiers = dc->soc->modifiers;
780
781 err = drm_universal_plane_init(drm, &plane->base, possible_crtcs,
782 &tegra_plane_funcs, formats,
783 num_formats, modifiers, type, NULL);
784 if (err < 0) {
785 kfree(plane);
786 return ERR_PTR(err);
787 }
788
789 drm_plane_helper_add(&plane->base, &tegra_plane_helper_funcs);
790 drm_plane_create_zpos_property(&plane->base, plane->index, 0, 255);
791
792 err = drm_plane_create_rotation_property(&plane->base,
793 DRM_MODE_ROTATE_0,
794 DRM_MODE_ROTATE_0 |
795 DRM_MODE_REFLECT_Y);
796 if (err < 0)
797 dev_err(dc->dev, "failed to create rotation property: %d\n",
798 err);
799
800 return &plane->base;
801 }
802
803 static const u32 tegra_cursor_plane_formats[] = {
804 DRM_FORMAT_RGBA8888,
805 };
806
807 static int tegra_cursor_atomic_check(struct drm_plane *plane,
808 struct drm_plane_state *state)
809 {
810 struct tegra_plane *tegra = to_tegra_plane(plane);
811 int err;
812
813 /* no need for further checks if the plane is being disabled */
814 if (!state->crtc)
815 return 0;
816
817 /* scaling not supported for cursor */
818 if ((state->src_w >> 16 != state->crtc_w) ||
819 (state->src_h >> 16 != state->crtc_h))
820 return -EINVAL;
821
822 /* only square cursors supported */
823 if (state->src_w != state->src_h)
824 return -EINVAL;
825
826 if (state->crtc_w != 32 && state->crtc_w != 64 &&
827 state->crtc_w != 128 && state->crtc_w != 256)
828 return -EINVAL;
829
830 err = tegra_plane_state_add(tegra, state);
831 if (err < 0)
832 return err;
833
834 return 0;
835 }
836
837 static void tegra_cursor_atomic_update(struct drm_plane *plane,
838 struct drm_plane_state *old_state)
839 {
840 struct tegra_plane_state *state = to_tegra_plane_state(plane->state);
841 struct tegra_dc *dc = to_tegra_dc(plane->state->crtc);
842 u32 value = CURSOR_CLIP_DISPLAY;
843
844 /* rien ne va plus */
845 if (!plane->state->crtc || !plane->state->fb)
846 return;
847
848 switch (plane->state->crtc_w) {
849 case 32:
850 value |= CURSOR_SIZE_32x32;
851 break;
852
853 case 64:
854 value |= CURSOR_SIZE_64x64;
855 break;
856
857 case 128:
858 value |= CURSOR_SIZE_128x128;
859 break;
860
861 case 256:
862 value |= CURSOR_SIZE_256x256;
863 break;
864
865 default:
866 WARN(1, "cursor size %ux%u not supported\n",
867 plane->state->crtc_w, plane->state->crtc_h);
868 return;
869 }
870
871 value |= (state->iova[0] >> 10) & 0x3fffff;
872 tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR);
873
874 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
875 value = (state->iova[0] >> 32) & 0x3;
876 tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR_HI);
877 #endif
878
879 /* enable cursor and set blend mode */
880 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
881 value |= CURSOR_ENABLE;
882 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
883
884 value = tegra_dc_readl(dc, DC_DISP_BLEND_CURSOR_CONTROL);
885 value &= ~CURSOR_DST_BLEND_MASK;
886 value &= ~CURSOR_SRC_BLEND_MASK;
887 value |= CURSOR_MODE_NORMAL;
888 value |= CURSOR_DST_BLEND_NEG_K1_TIMES_SRC;
889 value |= CURSOR_SRC_BLEND_K1_TIMES_SRC;
890 value |= CURSOR_ALPHA;
891 tegra_dc_writel(dc, value, DC_DISP_BLEND_CURSOR_CONTROL);
892
893 /* position the cursor */
894 value = (plane->state->crtc_y & 0x3fff) << 16 |
895 (plane->state->crtc_x & 0x3fff);
896 tegra_dc_writel(dc, value, DC_DISP_CURSOR_POSITION);
897 }
898
899 static void tegra_cursor_atomic_disable(struct drm_plane *plane,
900 struct drm_plane_state *old_state)
901 {
902 struct tegra_dc *dc;
903 u32 value;
904
905 /* rien ne va plus */
906 if (!old_state || !old_state->crtc)
907 return;
908
909 dc = to_tegra_dc(old_state->crtc);
910
911 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
912 value &= ~CURSOR_ENABLE;
913 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
914 }
915
916 static const struct drm_plane_helper_funcs tegra_cursor_plane_helper_funcs = {
917 .prepare_fb = tegra_plane_prepare_fb,
918 .cleanup_fb = tegra_plane_cleanup_fb,
919 .atomic_check = tegra_cursor_atomic_check,
920 .atomic_update = tegra_cursor_atomic_update,
921 .atomic_disable = tegra_cursor_atomic_disable,
922 };
923
924 static struct drm_plane *tegra_dc_cursor_plane_create(struct drm_device *drm,
925 struct tegra_dc *dc)
926 {
927 unsigned long possible_crtcs = tegra_plane_get_possible_crtcs(drm);
928 struct tegra_plane *plane;
929 unsigned int num_formats;
930 const u32 *formats;
931 int err;
932
933 plane = kzalloc(sizeof(*plane), GFP_KERNEL);
934 if (!plane)
935 return ERR_PTR(-ENOMEM);
936
937 /*
938 * This index is kind of fake. The cursor isn't a regular plane, but
939 * its update and activation request bits in DC_CMD_STATE_CONTROL do
940 * use the same programming. Setting this fake index here allows the
941 * code in tegra_add_plane_state() to do the right thing without the
942 * need to special-casing the cursor plane.
943 */
944 plane->index = 6;
945 plane->dc = dc;
946
947 num_formats = ARRAY_SIZE(tegra_cursor_plane_formats);
948 formats = tegra_cursor_plane_formats;
949
950 err = drm_universal_plane_init(drm, &plane->base, possible_crtcs,
951 &tegra_plane_funcs, formats,
952 num_formats, NULL,
953 DRM_PLANE_TYPE_CURSOR, NULL);
954 if (err < 0) {
955 kfree(plane);
956 return ERR_PTR(err);
957 }
958
959 drm_plane_helper_add(&plane->base, &tegra_cursor_plane_helper_funcs);
960
961 return &plane->base;
962 }
963
964 static const u32 tegra20_overlay_formats[] = {
965 DRM_FORMAT_ARGB4444,
966 DRM_FORMAT_ARGB1555,
967 DRM_FORMAT_RGB565,
968 DRM_FORMAT_RGBA5551,
969 DRM_FORMAT_ABGR8888,
970 DRM_FORMAT_ARGB8888,
971 /* non-native formats */
972 DRM_FORMAT_XRGB1555,
973 DRM_FORMAT_RGBX5551,
974 DRM_FORMAT_XBGR8888,
975 DRM_FORMAT_XRGB8888,
976 /* planar formats */
977 DRM_FORMAT_UYVY,
978 DRM_FORMAT_YUYV,
979 DRM_FORMAT_YUV420,
980 DRM_FORMAT_YUV422,
981 };
982
983 static const u32 tegra114_overlay_formats[] = {
984 DRM_FORMAT_ARGB4444,
985 DRM_FORMAT_ARGB1555,
986 DRM_FORMAT_RGB565,
987 DRM_FORMAT_RGBA5551,
988 DRM_FORMAT_ABGR8888,
989 DRM_FORMAT_ARGB8888,
990 /* new on Tegra114 */
991 DRM_FORMAT_ABGR4444,
992 DRM_FORMAT_ABGR1555,
993 DRM_FORMAT_BGRA5551,
994 DRM_FORMAT_XRGB1555,
995 DRM_FORMAT_RGBX5551,
996 DRM_FORMAT_XBGR1555,
997 DRM_FORMAT_BGRX5551,
998 DRM_FORMAT_BGR565,
999 DRM_FORMAT_BGRA8888,
1000 DRM_FORMAT_RGBA8888,
1001 DRM_FORMAT_XRGB8888,
1002 DRM_FORMAT_XBGR8888,
1003 /* planar formats */
1004 DRM_FORMAT_UYVY,
1005 DRM_FORMAT_YUYV,
1006 DRM_FORMAT_YUV420,
1007 DRM_FORMAT_YUV422,
1008 };
1009
1010 static const u32 tegra124_overlay_formats[] = {
1011 DRM_FORMAT_ARGB4444,
1012 DRM_FORMAT_ARGB1555,
1013 DRM_FORMAT_RGB565,
1014 DRM_FORMAT_RGBA5551,
1015 DRM_FORMAT_ABGR8888,
1016 DRM_FORMAT_ARGB8888,
1017 /* new on Tegra114 */
1018 DRM_FORMAT_ABGR4444,
1019 DRM_FORMAT_ABGR1555,
1020 DRM_FORMAT_BGRA5551,
1021 DRM_FORMAT_XRGB1555,
1022 DRM_FORMAT_RGBX5551,
1023 DRM_FORMAT_XBGR1555,
1024 DRM_FORMAT_BGRX5551,
1025 DRM_FORMAT_BGR565,
1026 DRM_FORMAT_BGRA8888,
1027 DRM_FORMAT_RGBA8888,
1028 DRM_FORMAT_XRGB8888,
1029 DRM_FORMAT_XBGR8888,
1030 /* new on Tegra124 */
1031 DRM_FORMAT_RGBX8888,
1032 DRM_FORMAT_BGRX8888,
1033 /* planar formats */
1034 DRM_FORMAT_UYVY,
1035 DRM_FORMAT_YUYV,
1036 DRM_FORMAT_YUV420,
1037 DRM_FORMAT_YUV422,
1038 };
1039
1040 static struct drm_plane *tegra_dc_overlay_plane_create(struct drm_device *drm,
1041 struct tegra_dc *dc,
1042 unsigned int index,
1043 bool cursor)
1044 {
1045 unsigned long possible_crtcs = tegra_plane_get_possible_crtcs(drm);
1046 struct tegra_plane *plane;
1047 unsigned int num_formats;
1048 enum drm_plane_type type;
1049 const u32 *formats;
1050 int err;
1051
1052 plane = kzalloc(sizeof(*plane), GFP_KERNEL);
1053 if (!plane)
1054 return ERR_PTR(-ENOMEM);
1055
1056 plane->offset = 0xa00 + 0x200 * index;
1057 plane->index = index;
1058 plane->dc = dc;
1059
1060 num_formats = dc->soc->num_overlay_formats;
1061 formats = dc->soc->overlay_formats;
1062
1063 if (!cursor)
1064 type = DRM_PLANE_TYPE_OVERLAY;
1065 else
1066 type = DRM_PLANE_TYPE_CURSOR;
1067
1068 err = drm_universal_plane_init(drm, &plane->base, possible_crtcs,
1069 &tegra_plane_funcs, formats,
1070 num_formats, NULL, type, NULL);
1071 if (err < 0) {
1072 kfree(plane);
1073 return ERR_PTR(err);
1074 }
1075
1076 drm_plane_helper_add(&plane->base, &tegra_plane_helper_funcs);
1077 drm_plane_create_zpos_property(&plane->base, plane->index, 0, 255);
1078
1079 err = drm_plane_create_rotation_property(&plane->base,
1080 DRM_MODE_ROTATE_0,
1081 DRM_MODE_ROTATE_0 |
1082 DRM_MODE_REFLECT_Y);
1083 if (err < 0)
1084 dev_err(dc->dev, "failed to create rotation property: %d\n",
1085 err);
1086
1087 return &plane->base;
1088 }
1089
1090 static struct drm_plane *tegra_dc_add_shared_planes(struct drm_device *drm,
1091 struct tegra_dc *dc)
1092 {
1093 struct drm_plane *plane, *primary = NULL;
1094 unsigned int i, j;
1095
1096 for (i = 0; i < dc->soc->num_wgrps; i++) {
1097 const struct tegra_windowgroup_soc *wgrp = &dc->soc->wgrps[i];
1098
1099 if (wgrp->dc == dc->pipe) {
1100 for (j = 0; j < wgrp->num_windows; j++) {
1101 unsigned int index = wgrp->windows[j];
1102
1103 plane = tegra_shared_plane_create(drm, dc,
1104 wgrp->index,
1105 index);
1106 if (IS_ERR(plane))
1107 return plane;
1108
1109 /*
1110 * Choose the first shared plane owned by this
1111 * head as the primary plane.
1112 */
1113 if (!primary) {
1114 plane->type = DRM_PLANE_TYPE_PRIMARY;
1115 primary = plane;
1116 }
1117 }
1118 }
1119 }
1120
1121 return primary;
1122 }
1123
1124 static struct drm_plane *tegra_dc_add_planes(struct drm_device *drm,
1125 struct tegra_dc *dc)
1126 {
1127 struct drm_plane *planes[2], *primary;
1128 unsigned int planes_num;
1129 unsigned int i;
1130 int err;
1131
1132 primary = tegra_primary_plane_create(drm, dc);
1133 if (IS_ERR(primary))
1134 return primary;
1135
1136 if (dc->soc->supports_cursor)
1137 planes_num = 2;
1138 else
1139 planes_num = 1;
1140
1141 for (i = 0; i < planes_num; i++) {
1142 planes[i] = tegra_dc_overlay_plane_create(drm, dc, 1 + i,
1143 false);
1144 if (IS_ERR(planes[i])) {
1145 err = PTR_ERR(planes[i]);
1146
1147 while (i--)
1148 tegra_plane_funcs.destroy(planes[i]);
1149
1150 tegra_plane_funcs.destroy(primary);
1151 return ERR_PTR(err);
1152 }
1153 }
1154
1155 return primary;
1156 }
1157
1158 static void tegra_dc_destroy(struct drm_crtc *crtc)
1159 {
1160 drm_crtc_cleanup(crtc);
1161 }
1162
1163 static void tegra_crtc_reset(struct drm_crtc *crtc)
1164 {
1165 struct tegra_dc_state *state = kzalloc(sizeof(*state), GFP_KERNEL);
1166
1167 if (crtc->state)
1168 tegra_crtc_atomic_destroy_state(crtc, crtc->state);
1169
1170 __drm_atomic_helper_crtc_reset(crtc, &state->base);
1171 drm_crtc_vblank_reset(crtc);
1172 }
1173
1174 static struct drm_crtc_state *
1175 tegra_crtc_atomic_duplicate_state(struct drm_crtc *crtc)
1176 {
1177 struct tegra_dc_state *state = to_dc_state(crtc->state);
1178 struct tegra_dc_state *copy;
1179
1180 copy = kmalloc(sizeof(*copy), GFP_KERNEL);
1181 if (!copy)
1182 return NULL;
1183
1184 __drm_atomic_helper_crtc_duplicate_state(crtc, &copy->base);
1185 copy->clk = state->clk;
1186 copy->pclk = state->pclk;
1187 copy->div = state->div;
1188 copy->planes = state->planes;
1189
1190 return &copy->base;
1191 }
1192
1193 static void tegra_crtc_atomic_destroy_state(struct drm_crtc *crtc,
1194 struct drm_crtc_state *state)
1195 {
1196 __drm_atomic_helper_crtc_destroy_state(state);
1197 kfree(state);
1198 }
1199
1200 #define DEBUGFS_REG32(_name) { .name = #_name, .offset = _name }
1201
1202 static const struct debugfs_reg32 tegra_dc_regs[] = {
1203 DEBUGFS_REG32(DC_CMD_GENERAL_INCR_SYNCPT),
1204 DEBUGFS_REG32(DC_CMD_GENERAL_INCR_SYNCPT_CNTRL),
1205 DEBUGFS_REG32(DC_CMD_GENERAL_INCR_SYNCPT_ERROR),
1206 DEBUGFS_REG32(DC_CMD_WIN_A_INCR_SYNCPT),
1207 DEBUGFS_REG32(DC_CMD_WIN_A_INCR_SYNCPT_CNTRL),
1208 DEBUGFS_REG32(DC_CMD_WIN_A_INCR_SYNCPT_ERROR),
1209 DEBUGFS_REG32(DC_CMD_WIN_B_INCR_SYNCPT),
1210 DEBUGFS_REG32(DC_CMD_WIN_B_INCR_SYNCPT_CNTRL),
1211 DEBUGFS_REG32(DC_CMD_WIN_B_INCR_SYNCPT_ERROR),
1212 DEBUGFS_REG32(DC_CMD_WIN_C_INCR_SYNCPT),
1213 DEBUGFS_REG32(DC_CMD_WIN_C_INCR_SYNCPT_CNTRL),
1214 DEBUGFS_REG32(DC_CMD_WIN_C_INCR_SYNCPT_ERROR),
1215 DEBUGFS_REG32(DC_CMD_CONT_SYNCPT_VSYNC),
1216 DEBUGFS_REG32(DC_CMD_DISPLAY_COMMAND_OPTION0),
1217 DEBUGFS_REG32(DC_CMD_DISPLAY_COMMAND),
1218 DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE),
1219 DEBUGFS_REG32(DC_CMD_DISPLAY_POWER_CONTROL),
1220 DEBUGFS_REG32(DC_CMD_INT_STATUS),
1221 DEBUGFS_REG32(DC_CMD_INT_MASK),
1222 DEBUGFS_REG32(DC_CMD_INT_ENABLE),
1223 DEBUGFS_REG32(DC_CMD_INT_TYPE),
1224 DEBUGFS_REG32(DC_CMD_INT_POLARITY),
1225 DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE1),
1226 DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE2),
1227 DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE3),
1228 DEBUGFS_REG32(DC_CMD_STATE_ACCESS),
1229 DEBUGFS_REG32(DC_CMD_STATE_CONTROL),
1230 DEBUGFS_REG32(DC_CMD_DISPLAY_WINDOW_HEADER),
1231 DEBUGFS_REG32(DC_CMD_REG_ACT_CONTROL),
1232 DEBUGFS_REG32(DC_COM_CRC_CONTROL),
1233 DEBUGFS_REG32(DC_COM_CRC_CHECKSUM),
1234 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(0)),
1235 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(1)),
1236 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(2)),
1237 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(3)),
1238 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(0)),
1239 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(1)),
1240 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(2)),
1241 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(3)),
1242 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(0)),
1243 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(1)),
1244 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(2)),
1245 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(3)),
1246 DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(0)),
1247 DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(1)),
1248 DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(2)),
1249 DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(3)),
1250 DEBUGFS_REG32(DC_COM_PIN_INPUT_DATA(0)),
1251 DEBUGFS_REG32(DC_COM_PIN_INPUT_DATA(1)),
1252 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(0)),
1253 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(1)),
1254 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(2)),
1255 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(3)),
1256 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(4)),
1257 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(5)),
1258 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(6)),
1259 DEBUGFS_REG32(DC_COM_PIN_MISC_CONTROL),
1260 DEBUGFS_REG32(DC_COM_PIN_PM0_CONTROL),
1261 DEBUGFS_REG32(DC_COM_PIN_PM0_DUTY_CYCLE),
1262 DEBUGFS_REG32(DC_COM_PIN_PM1_CONTROL),
1263 DEBUGFS_REG32(DC_COM_PIN_PM1_DUTY_CYCLE),
1264 DEBUGFS_REG32(DC_COM_SPI_CONTROL),
1265 DEBUGFS_REG32(DC_COM_SPI_START_BYTE),
1266 DEBUGFS_REG32(DC_COM_HSPI_WRITE_DATA_AB),
1267 DEBUGFS_REG32(DC_COM_HSPI_WRITE_DATA_CD),
1268 DEBUGFS_REG32(DC_COM_HSPI_CS_DC),
1269 DEBUGFS_REG32(DC_COM_SCRATCH_REGISTER_A),
1270 DEBUGFS_REG32(DC_COM_SCRATCH_REGISTER_B),
1271 DEBUGFS_REG32(DC_COM_GPIO_CTRL),
1272 DEBUGFS_REG32(DC_COM_GPIO_DEBOUNCE_COUNTER),
1273 DEBUGFS_REG32(DC_COM_CRC_CHECKSUM_LATCHED),
1274 DEBUGFS_REG32(DC_DISP_DISP_SIGNAL_OPTIONS0),
1275 DEBUGFS_REG32(DC_DISP_DISP_SIGNAL_OPTIONS1),
1276 DEBUGFS_REG32(DC_DISP_DISP_WIN_OPTIONS),
1277 DEBUGFS_REG32(DC_DISP_DISP_MEM_HIGH_PRIORITY),
1278 DEBUGFS_REG32(DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER),
1279 DEBUGFS_REG32(DC_DISP_DISP_TIMING_OPTIONS),
1280 DEBUGFS_REG32(DC_DISP_REF_TO_SYNC),
1281 DEBUGFS_REG32(DC_DISP_SYNC_WIDTH),
1282 DEBUGFS_REG32(DC_DISP_BACK_PORCH),
1283 DEBUGFS_REG32(DC_DISP_ACTIVE),
1284 DEBUGFS_REG32(DC_DISP_FRONT_PORCH),
1285 DEBUGFS_REG32(DC_DISP_H_PULSE0_CONTROL),
1286 DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_A),
1287 DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_B),
1288 DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_C),
1289 DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_D),
1290 DEBUGFS_REG32(DC_DISP_H_PULSE1_CONTROL),
1291 DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_A),
1292 DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_B),
1293 DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_C),
1294 DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_D),
1295 DEBUGFS_REG32(DC_DISP_H_PULSE2_CONTROL),
1296 DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_A),
1297 DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_B),
1298 DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_C),
1299 DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_D),
1300 DEBUGFS_REG32(DC_DISP_V_PULSE0_CONTROL),
1301 DEBUGFS_REG32(DC_DISP_V_PULSE0_POSITION_A),
1302 DEBUGFS_REG32(DC_DISP_V_PULSE0_POSITION_B),
1303 DEBUGFS_REG32(DC_DISP_V_PULSE0_POSITION_C),
1304 DEBUGFS_REG32(DC_DISP_V_PULSE1_CONTROL),
1305 DEBUGFS_REG32(DC_DISP_V_PULSE1_POSITION_A),
1306 DEBUGFS_REG32(DC_DISP_V_PULSE1_POSITION_B),
1307 DEBUGFS_REG32(DC_DISP_V_PULSE1_POSITION_C),
1308 DEBUGFS_REG32(DC_DISP_V_PULSE2_CONTROL),
1309 DEBUGFS_REG32(DC_DISP_V_PULSE2_POSITION_A),
1310 DEBUGFS_REG32(DC_DISP_V_PULSE3_CONTROL),
1311 DEBUGFS_REG32(DC_DISP_V_PULSE3_POSITION_A),
1312 DEBUGFS_REG32(DC_DISP_M0_CONTROL),
1313 DEBUGFS_REG32(DC_DISP_M1_CONTROL),
1314 DEBUGFS_REG32(DC_DISP_DI_CONTROL),
1315 DEBUGFS_REG32(DC_DISP_PP_CONTROL),
1316 DEBUGFS_REG32(DC_DISP_PP_SELECT_A),
1317 DEBUGFS_REG32(DC_DISP_PP_SELECT_B),
1318 DEBUGFS_REG32(DC_DISP_PP_SELECT_C),
1319 DEBUGFS_REG32(DC_DISP_PP_SELECT_D),
1320 DEBUGFS_REG32(DC_DISP_DISP_CLOCK_CONTROL),
1321 DEBUGFS_REG32(DC_DISP_DISP_INTERFACE_CONTROL),
1322 DEBUGFS_REG32(DC_DISP_DISP_COLOR_CONTROL),
1323 DEBUGFS_REG32(DC_DISP_SHIFT_CLOCK_OPTIONS),
1324 DEBUGFS_REG32(DC_DISP_DATA_ENABLE_OPTIONS),
1325 DEBUGFS_REG32(DC_DISP_SERIAL_INTERFACE_OPTIONS),
1326 DEBUGFS_REG32(DC_DISP_LCD_SPI_OPTIONS),
1327 DEBUGFS_REG32(DC_DISP_BORDER_COLOR),
1328 DEBUGFS_REG32(DC_DISP_COLOR_KEY0_LOWER),
1329 DEBUGFS_REG32(DC_DISP_COLOR_KEY0_UPPER),
1330 DEBUGFS_REG32(DC_DISP_COLOR_KEY1_LOWER),
1331 DEBUGFS_REG32(DC_DISP_COLOR_KEY1_UPPER),
1332 DEBUGFS_REG32(DC_DISP_CURSOR_FOREGROUND),
1333 DEBUGFS_REG32(DC_DISP_CURSOR_BACKGROUND),
1334 DEBUGFS_REG32(DC_DISP_CURSOR_START_ADDR),
1335 DEBUGFS_REG32(DC_DISP_CURSOR_START_ADDR_NS),
1336 DEBUGFS_REG32(DC_DISP_CURSOR_POSITION),
1337 DEBUGFS_REG32(DC_DISP_CURSOR_POSITION_NS),
1338 DEBUGFS_REG32(DC_DISP_INIT_SEQ_CONTROL),
1339 DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_A),
1340 DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_B),
1341 DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_C),
1342 DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_D),
1343 DEBUGFS_REG32(DC_DISP_DC_MCCIF_FIFOCTRL),
1344 DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY0A_HYST),
1345 DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY0B_HYST),
1346 DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY1A_HYST),
1347 DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY1B_HYST),
1348 DEBUGFS_REG32(DC_DISP_DAC_CRT_CTRL),
1349 DEBUGFS_REG32(DC_DISP_DISP_MISC_CONTROL),
1350 DEBUGFS_REG32(DC_DISP_SD_CONTROL),
1351 DEBUGFS_REG32(DC_DISP_SD_CSC_COEFF),
1352 DEBUGFS_REG32(DC_DISP_SD_LUT(0)),
1353 DEBUGFS_REG32(DC_DISP_SD_LUT(1)),
1354 DEBUGFS_REG32(DC_DISP_SD_LUT(2)),
1355 DEBUGFS_REG32(DC_DISP_SD_LUT(3)),
1356 DEBUGFS_REG32(DC_DISP_SD_LUT(4)),
1357 DEBUGFS_REG32(DC_DISP_SD_LUT(5)),
1358 DEBUGFS_REG32(DC_DISP_SD_LUT(6)),
1359 DEBUGFS_REG32(DC_DISP_SD_LUT(7)),
1360 DEBUGFS_REG32(DC_DISP_SD_LUT(8)),
1361 DEBUGFS_REG32(DC_DISP_SD_FLICKER_CONTROL),
1362 DEBUGFS_REG32(DC_DISP_DC_PIXEL_COUNT),
1363 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(0)),
1364 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(1)),
1365 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(2)),
1366 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(3)),
1367 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(4)),
1368 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(5)),
1369 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(6)),
1370 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(7)),
1371 DEBUGFS_REG32(DC_DISP_SD_BL_TF(0)),
1372 DEBUGFS_REG32(DC_DISP_SD_BL_TF(1)),
1373 DEBUGFS_REG32(DC_DISP_SD_BL_TF(2)),
1374 DEBUGFS_REG32(DC_DISP_SD_BL_TF(3)),
1375 DEBUGFS_REG32(DC_DISP_SD_BL_CONTROL),
1376 DEBUGFS_REG32(DC_DISP_SD_HW_K_VALUES),
1377 DEBUGFS_REG32(DC_DISP_SD_MAN_K_VALUES),
1378 DEBUGFS_REG32(DC_DISP_CURSOR_START_ADDR_HI),
1379 DEBUGFS_REG32(DC_DISP_BLEND_CURSOR_CONTROL),
1380 DEBUGFS_REG32(DC_WIN_WIN_OPTIONS),
1381 DEBUGFS_REG32(DC_WIN_BYTE_SWAP),
1382 DEBUGFS_REG32(DC_WIN_BUFFER_CONTROL),
1383 DEBUGFS_REG32(DC_WIN_COLOR_DEPTH),
1384 DEBUGFS_REG32(DC_WIN_POSITION),
1385 DEBUGFS_REG32(DC_WIN_SIZE),
1386 DEBUGFS_REG32(DC_WIN_PRESCALED_SIZE),
1387 DEBUGFS_REG32(DC_WIN_H_INITIAL_DDA),
1388 DEBUGFS_REG32(DC_WIN_V_INITIAL_DDA),
1389 DEBUGFS_REG32(DC_WIN_DDA_INC),
1390 DEBUGFS_REG32(DC_WIN_LINE_STRIDE),
1391 DEBUGFS_REG32(DC_WIN_BUF_STRIDE),
1392 DEBUGFS_REG32(DC_WIN_UV_BUF_STRIDE),
1393 DEBUGFS_REG32(DC_WIN_BUFFER_ADDR_MODE),
1394 DEBUGFS_REG32(DC_WIN_DV_CONTROL),
1395 DEBUGFS_REG32(DC_WIN_BLEND_NOKEY),
1396 DEBUGFS_REG32(DC_WIN_BLEND_1WIN),
1397 DEBUGFS_REG32(DC_WIN_BLEND_2WIN_X),
1398 DEBUGFS_REG32(DC_WIN_BLEND_2WIN_Y),
1399 DEBUGFS_REG32(DC_WIN_BLEND_3WIN_XY),
1400 DEBUGFS_REG32(DC_WIN_HP_FETCH_CONTROL),
1401 DEBUGFS_REG32(DC_WINBUF_START_ADDR),
1402 DEBUGFS_REG32(DC_WINBUF_START_ADDR_NS),
1403 DEBUGFS_REG32(DC_WINBUF_START_ADDR_U),
1404 DEBUGFS_REG32(DC_WINBUF_START_ADDR_U_NS),
1405 DEBUGFS_REG32(DC_WINBUF_START_ADDR_V),
1406 DEBUGFS_REG32(DC_WINBUF_START_ADDR_V_NS),
1407 DEBUGFS_REG32(DC_WINBUF_ADDR_H_OFFSET),
1408 DEBUGFS_REG32(DC_WINBUF_ADDR_H_OFFSET_NS),
1409 DEBUGFS_REG32(DC_WINBUF_ADDR_V_OFFSET),
1410 DEBUGFS_REG32(DC_WINBUF_ADDR_V_OFFSET_NS),
1411 DEBUGFS_REG32(DC_WINBUF_UFLOW_STATUS),
1412 DEBUGFS_REG32(DC_WINBUF_AD_UFLOW_STATUS),
1413 DEBUGFS_REG32(DC_WINBUF_BD_UFLOW_STATUS),
1414 DEBUGFS_REG32(DC_WINBUF_CD_UFLOW_STATUS),
1415 };
1416
1417 static int tegra_dc_show_regs(struct seq_file *s, void *data)
1418 {
1419 struct drm_info_node *node = s->private;
1420 struct tegra_dc *dc = node->info_ent->data;
1421 unsigned int i;
1422 int err = 0;
1423
1424 drm_modeset_lock(&dc->base.mutex, NULL);
1425
1426 if (!dc->base.state->active) {
1427 err = -EBUSY;
1428 goto unlock;
1429 }
1430
1431 for (i = 0; i < ARRAY_SIZE(tegra_dc_regs); i++) {
1432 unsigned int offset = tegra_dc_regs[i].offset;
1433
1434 seq_printf(s, "%-40s %#05x %08x\n", tegra_dc_regs[i].name,
1435 offset, tegra_dc_readl(dc, offset));
1436 }
1437
1438 unlock:
1439 drm_modeset_unlock(&dc->base.mutex);
1440 return err;
1441 }
1442
1443 static int tegra_dc_show_crc(struct seq_file *s, void *data)
1444 {
1445 struct drm_info_node *node = s->private;
1446 struct tegra_dc *dc = node->info_ent->data;
1447 int err = 0;
1448 u32 value;
1449
1450 drm_modeset_lock(&dc->base.mutex, NULL);
1451
1452 if (!dc->base.state->active) {
1453 err = -EBUSY;
1454 goto unlock;
1455 }
1456
1457 value = DC_COM_CRC_CONTROL_ACTIVE_DATA | DC_COM_CRC_CONTROL_ENABLE;
1458 tegra_dc_writel(dc, value, DC_COM_CRC_CONTROL);
1459 tegra_dc_commit(dc);
1460
1461 drm_crtc_wait_one_vblank(&dc->base);
1462 drm_crtc_wait_one_vblank(&dc->base);
1463
1464 value = tegra_dc_readl(dc, DC_COM_CRC_CHECKSUM);
1465 seq_printf(s, "%08x\n", value);
1466
1467 tegra_dc_writel(dc, 0, DC_COM_CRC_CONTROL);
1468
1469 unlock:
1470 drm_modeset_unlock(&dc->base.mutex);
1471 return err;
1472 }
1473
1474 static int tegra_dc_show_stats(struct seq_file *s, void *data)
1475 {
1476 struct drm_info_node *node = s->private;
1477 struct tegra_dc *dc = node->info_ent->data;
1478
1479 seq_printf(s, "frames: %lu\n", dc->stats.frames);
1480 seq_printf(s, "vblank: %lu\n", dc->stats.vblank);
1481 seq_printf(s, "underflow: %lu\n", dc->stats.underflow);
1482 seq_printf(s, "overflow: %lu\n", dc->stats.overflow);
1483
1484 return 0;
1485 }
1486
1487 static struct drm_info_list debugfs_files[] = {
1488 { "regs", tegra_dc_show_regs, 0, NULL },
1489 { "crc", tegra_dc_show_crc, 0, NULL },
1490 { "stats", tegra_dc_show_stats, 0, NULL },
1491 };
1492
1493 static int tegra_dc_late_register(struct drm_crtc *crtc)
1494 {
1495 unsigned int i, count = ARRAY_SIZE(debugfs_files);
1496 struct drm_minor *minor = crtc->dev->primary;
1497 struct dentry *root;
1498 struct tegra_dc *dc = to_tegra_dc(crtc);
1499 int err;
1500
1501 #ifdef CONFIG_DEBUG_FS
1502 root = crtc->debugfs_entry;
1503 #else
1504 root = NULL;
1505 #endif
1506
1507 dc->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
1508 GFP_KERNEL);
1509 if (!dc->debugfs_files)
1510 return -ENOMEM;
1511
1512 for (i = 0; i < count; i++)
1513 dc->debugfs_files[i].data = dc;
1514
1515 err = drm_debugfs_create_files(dc->debugfs_files, count, root, minor);
1516 if (err < 0)
1517 goto free;
1518
1519 return 0;
1520
1521 free:
1522 kfree(dc->debugfs_files);
1523 dc->debugfs_files = NULL;
1524
1525 return err;
1526 }
1527
1528 static void tegra_dc_early_unregister(struct drm_crtc *crtc)
1529 {
1530 unsigned int count = ARRAY_SIZE(debugfs_files);
1531 struct drm_minor *minor = crtc->dev->primary;
1532 struct tegra_dc *dc = to_tegra_dc(crtc);
1533
1534 drm_debugfs_remove_files(dc->debugfs_files, count, minor);
1535 kfree(dc->debugfs_files);
1536 dc->debugfs_files = NULL;
1537 }
1538
1539 static u32 tegra_dc_get_vblank_counter(struct drm_crtc *crtc)
1540 {
1541 struct tegra_dc *dc = to_tegra_dc(crtc);
1542
1543 /* XXX vblank syncpoints don't work with nvdisplay yet */
1544 if (dc->syncpt && !dc->soc->has_nvdisplay)
1545 return host1x_syncpt_read(dc->syncpt);
1546
1547 /* fallback to software emulated VBLANK counter */
1548 return (u32)drm_crtc_vblank_count(&dc->base);
1549 }
1550
1551 static int tegra_dc_enable_vblank(struct drm_crtc *crtc)
1552 {
1553 struct tegra_dc *dc = to_tegra_dc(crtc);
1554 u32 value;
1555
1556 value = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1557 value |= VBLANK_INT;
1558 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
1559
1560 return 0;
1561 }
1562
1563 static void tegra_dc_disable_vblank(struct drm_crtc *crtc)
1564 {
1565 struct tegra_dc *dc = to_tegra_dc(crtc);
1566 u32 value;
1567
1568 value = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1569 value &= ~VBLANK_INT;
1570 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
1571 }
1572
1573 static const struct drm_crtc_funcs tegra_crtc_funcs = {
1574 .page_flip = drm_atomic_helper_page_flip,
1575 .set_config = drm_atomic_helper_set_config,
1576 .destroy = tegra_dc_destroy,
1577 .reset = tegra_crtc_reset,
1578 .atomic_duplicate_state = tegra_crtc_atomic_duplicate_state,
1579 .atomic_destroy_state = tegra_crtc_atomic_destroy_state,
1580 .late_register = tegra_dc_late_register,
1581 .early_unregister = tegra_dc_early_unregister,
1582 .get_vblank_counter = tegra_dc_get_vblank_counter,
1583 .enable_vblank = tegra_dc_enable_vblank,
1584 .disable_vblank = tegra_dc_disable_vblank,
1585 };
1586
1587 static int tegra_dc_set_timings(struct tegra_dc *dc,
1588 struct drm_display_mode *mode)
1589 {
1590 unsigned int h_ref_to_sync = 1;
1591 unsigned int v_ref_to_sync = 1;
1592 unsigned long value;
1593
1594 if (!dc->soc->has_nvdisplay) {
1595 tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS);
1596
1597 value = (v_ref_to_sync << 16) | h_ref_to_sync;
1598 tegra_dc_writel(dc, value, DC_DISP_REF_TO_SYNC);
1599 }
1600
1601 value = ((mode->vsync_end - mode->vsync_start) << 16) |
1602 ((mode->hsync_end - mode->hsync_start) << 0);
1603 tegra_dc_writel(dc, value, DC_DISP_SYNC_WIDTH);
1604
1605 value = ((mode->vtotal - mode->vsync_end) << 16) |
1606 ((mode->htotal - mode->hsync_end) << 0);
1607 tegra_dc_writel(dc, value, DC_DISP_BACK_PORCH);
1608
1609 value = ((mode->vsync_start - mode->vdisplay) << 16) |
1610 ((mode->hsync_start - mode->hdisplay) << 0);
1611 tegra_dc_writel(dc, value, DC_DISP_FRONT_PORCH);
1612
1613 value = (mode->vdisplay << 16) | mode->hdisplay;
1614 tegra_dc_writel(dc, value, DC_DISP_ACTIVE);
1615
1616 return 0;
1617 }
1618
1619 /**
1620 * tegra_dc_state_setup_clock - check clock settings and store them in atomic
1621 * state
1622 * @dc: display controller
1623 * @crtc_state: CRTC atomic state
1624 * @clk: parent clock for display controller
1625 * @pclk: pixel clock
1626 * @div: shift clock divider
1627 *
1628 * Returns:
1629 * 0 on success or a negative error-code on failure.
1630 */
1631 int tegra_dc_state_setup_clock(struct tegra_dc *dc,
1632 struct drm_crtc_state *crtc_state,
1633 struct clk *clk, unsigned long pclk,
1634 unsigned int div)
1635 {
1636 struct tegra_dc_state *state = to_dc_state(crtc_state);
1637
1638 if (!clk_has_parent(dc->clk, clk))
1639 return -EINVAL;
1640
1641 state->clk = clk;
1642 state->pclk = pclk;
1643 state->div = div;
1644
1645 return 0;
1646 }
1647
1648 static void tegra_dc_commit_state(struct tegra_dc *dc,
1649 struct tegra_dc_state *state)
1650 {
1651 u32 value;
1652 int err;
1653
1654 err = clk_set_parent(dc->clk, state->clk);
1655 if (err < 0)
1656 dev_err(dc->dev, "failed to set parent clock: %d\n", err);
1657
1658 /*
1659 * Outputs may not want to change the parent clock rate. This is only
1660 * relevant to Tegra20 where only a single display PLL is available.
1661 * Since that PLL would typically be used for HDMI, an internal LVDS
1662 * panel would need to be driven by some other clock such as PLL_P
1663 * which is shared with other peripherals. Changing the clock rate
1664 * should therefore be avoided.
1665 */
1666 if (state->pclk > 0) {
1667 err = clk_set_rate(state->clk, state->pclk);
1668 if (err < 0)
1669 dev_err(dc->dev,
1670 "failed to set clock rate to %lu Hz\n",
1671 state->pclk);
1672 }
1673
1674 DRM_DEBUG_KMS("rate: %lu, div: %u\n", clk_get_rate(dc->clk),
1675 state->div);
1676 DRM_DEBUG_KMS("pclk: %lu\n", state->pclk);
1677
1678 if (!dc->soc->has_nvdisplay) {
1679 value = SHIFT_CLK_DIVIDER(state->div) | PIXEL_CLK_DIVIDER_PCD1;
1680 tegra_dc_writel(dc, value, DC_DISP_DISP_CLOCK_CONTROL);
1681 }
1682
1683 err = clk_set_rate(dc->clk, state->pclk);
1684 if (err < 0)
1685 dev_err(dc->dev, "failed to set clock %pC to %lu Hz: %d\n",
1686 dc->clk, state->pclk, err);
1687 }
1688
1689 static void tegra_dc_stop(struct tegra_dc *dc)
1690 {
1691 u32 value;
1692
1693 /* stop the display controller */
1694 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
1695 value &= ~DISP_CTRL_MODE_MASK;
1696 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
1697
1698 tegra_dc_commit(dc);
1699 }
1700
1701 static bool tegra_dc_idle(struct tegra_dc *dc)
1702 {
1703 u32 value;
1704
1705 value = tegra_dc_readl_active(dc, DC_CMD_DISPLAY_COMMAND);
1706
1707 return (value & DISP_CTRL_MODE_MASK) == 0;
1708 }
1709
1710 static int tegra_dc_wait_idle(struct tegra_dc *dc, unsigned long timeout)
1711 {
1712 timeout = jiffies + msecs_to_jiffies(timeout);
1713
1714 while (time_before(jiffies, timeout)) {
1715 if (tegra_dc_idle(dc))
1716 return 0;
1717
1718 usleep_range(1000, 2000);
1719 }
1720
1721 dev_dbg(dc->dev, "timeout waiting for DC to become idle\n");
1722 return -ETIMEDOUT;
1723 }
1724
1725 static void tegra_crtc_atomic_disable(struct drm_crtc *crtc,
1726 struct drm_crtc_state *old_state)
1727 {
1728 struct tegra_dc *dc = to_tegra_dc(crtc);
1729 u32 value;
1730 int err;
1731
1732 if (!tegra_dc_idle(dc)) {
1733 tegra_dc_stop(dc);
1734
1735 /*
1736 * Ignore the return value, there isn't anything useful to do
1737 * in case this fails.
1738 */
1739 tegra_dc_wait_idle(dc, 100);
1740 }
1741
1742 /*
1743 * This should really be part of the RGB encoder driver, but clearing
1744 * these bits has the side-effect of stopping the display controller.
1745 * When that happens no VBLANK interrupts will be raised. At the same
1746 * time the encoder is disabled before the display controller, so the
1747 * above code is always going to timeout waiting for the controller
1748 * to go idle.
1749 *
1750 * Given the close coupling between the RGB encoder and the display
1751 * controller doing it here is still kind of okay. None of the other
1752 * encoder drivers require these bits to be cleared.
1753 *
1754 * XXX: Perhaps given that the display controller is switched off at
1755 * this point anyway maybe clearing these bits isn't even useful for
1756 * the RGB encoder?
1757 */
1758 if (dc->rgb) {
1759 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
1760 value &= ~(PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
1761 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE);
1762 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
1763 }
1764
1765 tegra_dc_stats_reset(&dc->stats);
1766 drm_crtc_vblank_off(crtc);
1767
1768 spin_lock_irq(&crtc->dev->event_lock);
1769
1770 if (crtc->state->event) {
1771 drm_crtc_send_vblank_event(crtc, crtc->state->event);
1772 crtc->state->event = NULL;
1773 }
1774
1775 spin_unlock_irq(&crtc->dev->event_lock);
1776
1777 err = host1x_client_suspend(&dc->client);
1778 if (err < 0)
1779 dev_err(dc->dev, "failed to suspend: %d\n", err);
1780 }
1781
1782 static void tegra_crtc_atomic_enable(struct drm_crtc *crtc,
1783 struct drm_crtc_state *old_state)
1784 {
1785 struct drm_display_mode *mode = &crtc->state->adjusted_mode;
1786 struct tegra_dc_state *state = to_dc_state(crtc->state);
1787 struct tegra_dc *dc = to_tegra_dc(crtc);
1788 u32 value;
1789 int err;
1790
1791 err = host1x_client_resume(&dc->client);
1792 if (err < 0) {
1793 dev_err(dc->dev, "failed to resume: %d\n", err);
1794 return;
1795 }
1796
1797 /* initialize display controller */
1798 if (dc->syncpt) {
1799 u32 syncpt = host1x_syncpt_id(dc->syncpt), enable;
1800
1801 if (dc->soc->has_nvdisplay)
1802 enable = 1 << 31;
1803 else
1804 enable = 1 << 8;
1805
1806 value = SYNCPT_CNTRL_NO_STALL;
1807 tegra_dc_writel(dc, value, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
1808
1809 value = enable | syncpt;
1810 tegra_dc_writel(dc, value, DC_CMD_CONT_SYNCPT_VSYNC);
1811 }
1812
1813 if (dc->soc->has_nvdisplay) {
1814 value = DSC_TO_UF_INT | DSC_BBUF_UF_INT | DSC_RBUF_UF_INT |
1815 DSC_OBUF_UF_INT;
1816 tegra_dc_writel(dc, value, DC_CMD_INT_TYPE);
1817
1818 value = DSC_TO_UF_INT | DSC_BBUF_UF_INT | DSC_RBUF_UF_INT |
1819 DSC_OBUF_UF_INT | SD3_BUCKET_WALK_DONE_INT |
1820 HEAD_UF_INT | MSF_INT | REG_TMOUT_INT |
1821 REGION_CRC_INT | V_PULSE2_INT | V_PULSE3_INT |
1822 VBLANK_INT | FRAME_END_INT;
1823 tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY);
1824
1825 value = SD3_BUCKET_WALK_DONE_INT | HEAD_UF_INT | VBLANK_INT |
1826 FRAME_END_INT;
1827 tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE);
1828
1829 value = HEAD_UF_INT | REG_TMOUT_INT | FRAME_END_INT;
1830 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
1831
1832 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS);
1833 } else {
1834 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1835 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
1836 tegra_dc_writel(dc, value, DC_CMD_INT_TYPE);
1837
1838 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1839 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
1840 tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY);
1841
1842 /* initialize timer */
1843 value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(0x20) |
1844 WINDOW_B_THRESHOLD(0x20) | WINDOW_C_THRESHOLD(0x20);
1845 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY);
1846
1847 value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(1) |
1848 WINDOW_B_THRESHOLD(1) | WINDOW_C_THRESHOLD(1);
1849 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);
1850
1851 value = VBLANK_INT | WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1852 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
1853 tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE);
1854
1855 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1856 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
1857 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
1858 }
1859
1860 if (dc->soc->supports_background_color)
1861 tegra_dc_writel(dc, 0, DC_DISP_BLEND_BACKGROUND_COLOR);
1862 else
1863 tegra_dc_writel(dc, 0, DC_DISP_BORDER_COLOR);
1864
1865 /* apply PLL and pixel clock changes */
1866 tegra_dc_commit_state(dc, state);
1867
1868 /* program display mode */
1869 tegra_dc_set_timings(dc, mode);
1870
1871 /* interlacing isn't supported yet, so disable it */
1872 if (dc->soc->supports_interlacing) {
1873 value = tegra_dc_readl(dc, DC_DISP_INTERLACE_CONTROL);
1874 value &= ~INTERLACE_ENABLE;
1875 tegra_dc_writel(dc, value, DC_DISP_INTERLACE_CONTROL);
1876 }
1877
1878 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
1879 value &= ~DISP_CTRL_MODE_MASK;
1880 value |= DISP_CTRL_MODE_C_DISPLAY;
1881 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
1882
1883 if (!dc->soc->has_nvdisplay) {
1884 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
1885 value |= PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
1886 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE;
1887 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
1888 }
1889
1890 /* enable underflow reporting and display red for missing pixels */
1891 if (dc->soc->has_nvdisplay) {
1892 value = UNDERFLOW_MODE_RED | UNDERFLOW_REPORT_ENABLE;
1893 tegra_dc_writel(dc, value, DC_COM_RG_UNDERFLOW);
1894 }
1895
1896 tegra_dc_commit(dc);
1897
1898 drm_crtc_vblank_on(crtc);
1899 }
1900
1901 static void tegra_crtc_atomic_begin(struct drm_crtc *crtc,
1902 struct drm_crtc_state *old_crtc_state)
1903 {
1904 unsigned long flags;
1905
1906 if (crtc->state->event) {
1907 spin_lock_irqsave(&crtc->dev->event_lock, flags);
1908
1909 if (drm_crtc_vblank_get(crtc) != 0)
1910 drm_crtc_send_vblank_event(crtc, crtc->state->event);
1911 else
1912 drm_crtc_arm_vblank_event(crtc, crtc->state->event);
1913
1914 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
1915
1916 crtc->state->event = NULL;
1917 }
1918 }
1919
1920 static void tegra_crtc_atomic_flush(struct drm_crtc *crtc,
1921 struct drm_crtc_state *old_crtc_state)
1922 {
1923 struct tegra_dc_state *state = to_dc_state(crtc->state);
1924 struct tegra_dc *dc = to_tegra_dc(crtc);
1925 u32 value;
1926
1927 value = state->planes << 8 | GENERAL_UPDATE;
1928 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
1929 value = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
1930
1931 value = state->planes | GENERAL_ACT_REQ;
1932 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
1933 value = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
1934 }
1935
1936 static const struct drm_crtc_helper_funcs tegra_crtc_helper_funcs = {
1937 .atomic_begin = tegra_crtc_atomic_begin,
1938 .atomic_flush = tegra_crtc_atomic_flush,
1939 .atomic_enable = tegra_crtc_atomic_enable,
1940 .atomic_disable = tegra_crtc_atomic_disable,
1941 };
1942
1943 static irqreturn_t tegra_dc_irq(int irq, void *data)
1944 {
1945 struct tegra_dc *dc = data;
1946 unsigned long status;
1947
1948 status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
1949 tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);
1950
1951 if (status & FRAME_END_INT) {
1952 /*
1953 dev_dbg(dc->dev, "%s(): frame end\n", __func__);
1954 */
1955 dc->stats.frames++;
1956 }
1957
1958 if (status & VBLANK_INT) {
1959 /*
1960 dev_dbg(dc->dev, "%s(): vertical blank\n", __func__);
1961 */
1962 drm_crtc_handle_vblank(&dc->base);
1963 dc->stats.vblank++;
1964 }
1965
1966 if (status & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT)) {
1967 /*
1968 dev_dbg(dc->dev, "%s(): underflow\n", __func__);
1969 */
1970 dc->stats.underflow++;
1971 }
1972
1973 if (status & (WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT)) {
1974 /*
1975 dev_dbg(dc->dev, "%s(): overflow\n", __func__);
1976 */
1977 dc->stats.overflow++;
1978 }
1979
1980 if (status & HEAD_UF_INT) {
1981 dev_dbg_ratelimited(dc->dev, "%s(): head underflow\n", __func__);
1982 dc->stats.underflow++;
1983 }
1984
1985 return IRQ_HANDLED;
1986 }
1987
1988 static bool tegra_dc_has_window_groups(struct tegra_dc *dc)
1989 {
1990 unsigned int i;
1991
1992 if (!dc->soc->wgrps)
1993 return true;
1994
1995 for (i = 0; i < dc->soc->num_wgrps; i++) {
1996 const struct tegra_windowgroup_soc *wgrp = &dc->soc->wgrps[i];
1997
1998 if (wgrp->dc == dc->pipe && wgrp->num_windows > 0)
1999 return true;
2000 }
2001
2002 return false;
2003 }
2004
2005 static int tegra_dc_init(struct host1x_client *client)
2006 {
2007 struct drm_device *drm = dev_get_drvdata(client->host);
2008 unsigned long flags = HOST1X_SYNCPT_CLIENT_MANAGED;
2009 struct tegra_dc *dc = host1x_client_to_dc(client);
2010 struct tegra_drm *tegra = drm->dev_private;
2011 struct drm_plane *primary = NULL;
2012 struct drm_plane *cursor = NULL;
2013 int err;
2014
2015 /*
2016 * XXX do not register DCs with no window groups because we cannot
2017 * assign a primary plane to them, which in turn will cause KMS to
2018 * crash.
2019 */
2020 if (!tegra_dc_has_window_groups(dc))
2021 return 0;
2022
2023 /*
2024 * Set the display hub as the host1x client parent for the display
2025 * controller. This is needed for the runtime reference counting that
2026 * ensures the display hub is always powered when any of the display
2027 * controllers are.
2028 */
2029 if (dc->soc->has_nvdisplay)
2030 client->parent = &tegra->hub->client;
2031
2032 dc->syncpt = host1x_syncpt_request(client, flags);
2033 if (!dc->syncpt)
2034 dev_warn(dc->dev, "failed to allocate syncpoint\n");
2035
2036 err = host1x_client_iommu_attach(client);
2037 if (err < 0 && err != -ENODEV) {
2038 dev_err(client->dev, "failed to attach to domain: %d\n", err);
2039 return err;
2040 }
2041
2042 if (dc->soc->wgrps)
2043 primary = tegra_dc_add_shared_planes(drm, dc);
2044 else
2045 primary = tegra_dc_add_planes(drm, dc);
2046
2047 if (IS_ERR(primary)) {
2048 err = PTR_ERR(primary);
2049 goto cleanup;
2050 }
2051
2052 if (dc->soc->supports_cursor) {
2053 cursor = tegra_dc_cursor_plane_create(drm, dc);
2054 if (IS_ERR(cursor)) {
2055 err = PTR_ERR(cursor);
2056 goto cleanup;
2057 }
2058 } else {
2059 /* dedicate one overlay to mouse cursor */
2060 cursor = tegra_dc_overlay_plane_create(drm, dc, 2, true);
2061 if (IS_ERR(cursor)) {
2062 err = PTR_ERR(cursor);
2063 goto cleanup;
2064 }
2065 }
2066
2067 err = drm_crtc_init_with_planes(drm, &dc->base, primary, cursor,
2068 &tegra_crtc_funcs, NULL);
2069 if (err < 0)
2070 goto cleanup;
2071
2072 drm_crtc_helper_add(&dc->base, &tegra_crtc_helper_funcs);
2073
2074 /*
2075 * Keep track of the minimum pitch alignment across all display
2076 * controllers.
2077 */
2078 if (dc->soc->pitch_align > tegra->pitch_align)
2079 tegra->pitch_align = dc->soc->pitch_align;
2080
2081 err = tegra_dc_rgb_init(drm, dc);
2082 if (err < 0 && err != -ENODEV) {
2083 dev_err(dc->dev, "failed to initialize RGB output: %d\n", err);
2084 goto cleanup;
2085 }
2086
2087 err = devm_request_irq(dc->dev, dc->irq, tegra_dc_irq, 0,
2088 dev_name(dc->dev), dc);
2089 if (err < 0) {
2090 dev_err(dc->dev, "failed to request IRQ#%u: %d\n", dc->irq,
2091 err);
2092 goto cleanup;
2093 }
2094
2095 /*
2096 * Inherit the DMA parameters (such as maximum segment size) from the
2097 * parent host1x device.
2098 */
2099 client->dev->dma_parms = client->host->dma_parms;
2100
2101 return 0;
2102
2103 cleanup:
2104 if (!IS_ERR_OR_NULL(cursor))
2105 drm_plane_cleanup(cursor);
2106
2107 if (!IS_ERR(primary))
2108 drm_plane_cleanup(primary);
2109
2110 host1x_client_iommu_detach(client);
2111 host1x_syncpt_free(dc->syncpt);
2112
2113 return err;
2114 }
2115
2116 static int tegra_dc_exit(struct host1x_client *client)
2117 {
2118 struct tegra_dc *dc = host1x_client_to_dc(client);
2119 int err;
2120
2121 if (!tegra_dc_has_window_groups(dc))
2122 return 0;
2123
2124 /* avoid a dangling pointer just in case this disappears */
2125 client->dev->dma_parms = NULL;
2126
2127 devm_free_irq(dc->dev, dc->irq, dc);
2128
2129 err = tegra_dc_rgb_exit(dc);
2130 if (err) {
2131 dev_err(dc->dev, "failed to shutdown RGB output: %d\n", err);
2132 return err;
2133 }
2134
2135 host1x_client_iommu_detach(client);
2136 host1x_syncpt_free(dc->syncpt);
2137
2138 return 0;
2139 }
2140
2141 static int tegra_dc_runtime_suspend(struct host1x_client *client)
2142 {
2143 struct tegra_dc *dc = host1x_client_to_dc(client);
2144 struct device *dev = client->dev;
2145 int err;
2146
2147 err = reset_control_assert(dc->rst);
2148 if (err < 0) {
2149 dev_err(dev, "failed to assert reset: %d\n", err);
2150 return err;
2151 }
2152
2153 if (dc->soc->has_powergate)
2154 tegra_powergate_power_off(dc->powergate);
2155
2156 clk_disable_unprepare(dc->clk);
2157 pm_runtime_put_sync(dev);
2158
2159 return 0;
2160 }
2161
2162 static int tegra_dc_runtime_resume(struct host1x_client *client)
2163 {
2164 struct tegra_dc *dc = host1x_client_to_dc(client);
2165 struct device *dev = client->dev;
2166 int err;
2167
2168 err = pm_runtime_get_sync(dev);
2169 if (err < 0) {
2170 dev_err(dev, "failed to get runtime PM: %d\n", err);
2171 return err;
2172 }
2173
2174 if (dc->soc->has_powergate) {
2175 err = tegra_powergate_sequence_power_up(dc->powergate, dc->clk,
2176 dc->rst);
2177 if (err < 0) {
2178 dev_err(dev, "failed to power partition: %d\n", err);
2179 goto put_rpm;
2180 }
2181 } else {
2182 err = clk_prepare_enable(dc->clk);
2183 if (err < 0) {
2184 dev_err(dev, "failed to enable clock: %d\n", err);
2185 goto put_rpm;
2186 }
2187
2188 err = reset_control_deassert(dc->rst);
2189 if (err < 0) {
2190 dev_err(dev, "failed to deassert reset: %d\n", err);
2191 goto disable_clk;
2192 }
2193 }
2194
2195 return 0;
2196
2197 disable_clk:
2198 clk_disable_unprepare(dc->clk);
2199 put_rpm:
2200 pm_runtime_put_sync(dev);
2201 return err;
2202 }
2203
2204 static const struct host1x_client_ops dc_client_ops = {
2205 .init = tegra_dc_init,
2206 .exit = tegra_dc_exit,
2207 .suspend = tegra_dc_runtime_suspend,
2208 .resume = tegra_dc_runtime_resume,
2209 };
2210
2211 static const struct tegra_dc_soc_info tegra20_dc_soc_info = {
2212 .supports_background_color = false,
2213 .supports_interlacing = false,
2214 .supports_cursor = false,
2215 .supports_block_linear = false,
2216 .has_legacy_blending = true,
2217 .pitch_align = 8,
2218 .has_powergate = false,
2219 .coupled_pm = true,
2220 .has_nvdisplay = false,
2221 .num_primary_formats = ARRAY_SIZE(tegra20_primary_formats),
2222 .primary_formats = tegra20_primary_formats,
2223 .num_overlay_formats = ARRAY_SIZE(tegra20_overlay_formats),
2224 .overlay_formats = tegra20_overlay_formats,
2225 .modifiers = tegra20_modifiers,
2226 .has_win_a_without_filters = true,
2227 .has_win_c_without_vert_filter = true,
2228 };
2229
2230 static const struct tegra_dc_soc_info tegra30_dc_soc_info = {
2231 .supports_background_color = false,
2232 .supports_interlacing = false,
2233 .supports_cursor = false,
2234 .supports_block_linear = false,
2235 .has_legacy_blending = true,
2236 .pitch_align = 8,
2237 .has_powergate = false,
2238 .coupled_pm = false,
2239 .has_nvdisplay = false,
2240 .num_primary_formats = ARRAY_SIZE(tegra20_primary_formats),
2241 .primary_formats = tegra20_primary_formats,
2242 .num_overlay_formats = ARRAY_SIZE(tegra20_overlay_formats),
2243 .overlay_formats = tegra20_overlay_formats,
2244 .modifiers = tegra20_modifiers,
2245 .has_win_a_without_filters = false,
2246 .has_win_c_without_vert_filter = false,
2247 };
2248
2249 static const struct tegra_dc_soc_info tegra114_dc_soc_info = {
2250 .supports_background_color = false,
2251 .supports_interlacing = false,
2252 .supports_cursor = false,
2253 .supports_block_linear = false,
2254 .has_legacy_blending = true,
2255 .pitch_align = 64,
2256 .has_powergate = true,
2257 .coupled_pm = false,
2258 .has_nvdisplay = false,
2259 .num_primary_formats = ARRAY_SIZE(tegra114_primary_formats),
2260 .primary_formats = tegra114_primary_formats,
2261 .num_overlay_formats = ARRAY_SIZE(tegra114_overlay_formats),
2262 .overlay_formats = tegra114_overlay_formats,
2263 .modifiers = tegra20_modifiers,
2264 .has_win_a_without_filters = false,
2265 .has_win_c_without_vert_filter = false,
2266 };
2267
2268 static const struct tegra_dc_soc_info tegra124_dc_soc_info = {
2269 .supports_background_color = true,
2270 .supports_interlacing = true,
2271 .supports_cursor = true,
2272 .supports_block_linear = true,
2273 .has_legacy_blending = false,
2274 .pitch_align = 64,
2275 .has_powergate = true,
2276 .coupled_pm = false,
2277 .has_nvdisplay = false,
2278 .num_primary_formats = ARRAY_SIZE(tegra124_primary_formats),
2279 .primary_formats = tegra124_primary_formats,
2280 .num_overlay_formats = ARRAY_SIZE(tegra124_overlay_formats),
2281 .overlay_formats = tegra124_overlay_formats,
2282 .modifiers = tegra124_modifiers,
2283 .has_win_a_without_filters = false,
2284 .has_win_c_without_vert_filter = false,
2285 };
2286
2287 static const struct tegra_dc_soc_info tegra210_dc_soc_info = {
2288 .supports_background_color = true,
2289 .supports_interlacing = true,
2290 .supports_cursor = true,
2291 .supports_block_linear = true,
2292 .has_legacy_blending = false,
2293 .pitch_align = 64,
2294 .has_powergate = true,
2295 .coupled_pm = false,
2296 .has_nvdisplay = false,
2297 .num_primary_formats = ARRAY_SIZE(tegra114_primary_formats),
2298 .primary_formats = tegra114_primary_formats,
2299 .num_overlay_formats = ARRAY_SIZE(tegra114_overlay_formats),
2300 .overlay_formats = tegra114_overlay_formats,
2301 .modifiers = tegra124_modifiers,
2302 .has_win_a_without_filters = false,
2303 .has_win_c_without_vert_filter = false,
2304 };
2305
2306 static const struct tegra_windowgroup_soc tegra186_dc_wgrps[] = {
2307 {
2308 .index = 0,
2309 .dc = 0,
2310 .windows = (const unsigned int[]) { 0 },
2311 .num_windows = 1,
2312 }, {
2313 .index = 1,
2314 .dc = 1,
2315 .windows = (const unsigned int[]) { 1 },
2316 .num_windows = 1,
2317 }, {
2318 .index = 2,
2319 .dc = 1,
2320 .windows = (const unsigned int[]) { 2 },
2321 .num_windows = 1,
2322 }, {
2323 .index = 3,
2324 .dc = 2,
2325 .windows = (const unsigned int[]) { 3 },
2326 .num_windows = 1,
2327 }, {
2328 .index = 4,
2329 .dc = 2,
2330 .windows = (const unsigned int[]) { 4 },
2331 .num_windows = 1,
2332 }, {
2333 .index = 5,
2334 .dc = 2,
2335 .windows = (const unsigned int[]) { 5 },
2336 .num_windows = 1,
2337 },
2338 };
2339
2340 static const struct tegra_dc_soc_info tegra186_dc_soc_info = {
2341 .supports_background_color = true,
2342 .supports_interlacing = true,
2343 .supports_cursor = true,
2344 .supports_block_linear = true,
2345 .has_legacy_blending = false,
2346 .pitch_align = 64,
2347 .has_powergate = false,
2348 .coupled_pm = false,
2349 .has_nvdisplay = true,
2350 .wgrps = tegra186_dc_wgrps,
2351 .num_wgrps = ARRAY_SIZE(tegra186_dc_wgrps),
2352 };
2353
2354 static const struct tegra_windowgroup_soc tegra194_dc_wgrps[] = {
2355 {
2356 .index = 0,
2357 .dc = 0,
2358 .windows = (const unsigned int[]) { 0 },
2359 .num_windows = 1,
2360 }, {
2361 .index = 1,
2362 .dc = 1,
2363 .windows = (const unsigned int[]) { 1 },
2364 .num_windows = 1,
2365 }, {
2366 .index = 2,
2367 .dc = 1,
2368 .windows = (const unsigned int[]) { 2 },
2369 .num_windows = 1,
2370 }, {
2371 .index = 3,
2372 .dc = 2,
2373 .windows = (const unsigned int[]) { 3 },
2374 .num_windows = 1,
2375 }, {
2376 .index = 4,
2377 .dc = 2,
2378 .windows = (const unsigned int[]) { 4 },
2379 .num_windows = 1,
2380 }, {
2381 .index = 5,
2382 .dc = 2,
2383 .windows = (const unsigned int[]) { 5 },
2384 .num_windows = 1,
2385 },
2386 };
2387
2388 static const struct tegra_dc_soc_info tegra194_dc_soc_info = {
2389 .supports_background_color = true,
2390 .supports_interlacing = true,
2391 .supports_cursor = true,
2392 .supports_block_linear = true,
2393 .has_legacy_blending = false,
2394 .pitch_align = 64,
2395 .has_powergate = false,
2396 .coupled_pm = false,
2397 .has_nvdisplay = true,
2398 .wgrps = tegra194_dc_wgrps,
2399 .num_wgrps = ARRAY_SIZE(tegra194_dc_wgrps),
2400 };
2401
2402 static const struct of_device_id tegra_dc_of_match[] = {
2403 {
2404 .compatible = "nvidia,tegra194-dc",
2405 .data = &tegra194_dc_soc_info,
2406 }, {
2407 .compatible = "nvidia,tegra186-dc",
2408 .data = &tegra186_dc_soc_info,
2409 }, {
2410 .compatible = "nvidia,tegra210-dc",
2411 .data = &tegra210_dc_soc_info,
2412 }, {
2413 .compatible = "nvidia,tegra124-dc",
2414 .data = &tegra124_dc_soc_info,
2415 }, {
2416 .compatible = "nvidia,tegra114-dc",
2417 .data = &tegra114_dc_soc_info,
2418 }, {
2419 .compatible = "nvidia,tegra30-dc",
2420 .data = &tegra30_dc_soc_info,
2421 }, {
2422 .compatible = "nvidia,tegra20-dc",
2423 .data = &tegra20_dc_soc_info,
2424 }, {
2425 /* sentinel */
2426 }
2427 };
2428 MODULE_DEVICE_TABLE(of, tegra_dc_of_match);
2429
2430 static int tegra_dc_parse_dt(struct tegra_dc *dc)
2431 {
2432 struct device_node *np;
2433 u32 value = 0;
2434 int err;
2435
2436 err = of_property_read_u32(dc->dev->of_node, "nvidia,head", &value);
2437 if (err < 0) {
2438 dev_err(dc->dev, "missing \"nvidia,head\" property\n");
2439
2440 /*
2441 * If the nvidia,head property isn't present, try to find the
2442 * correct head number by looking up the position of this
2443 * display controller's node within the device tree. Assuming
2444 * that the nodes are ordered properly in the DTS file and
2445 * that the translation into a flattened device tree blob
2446 * preserves that ordering this will actually yield the right
2447 * head number.
2448 *
2449 * If those assumptions don't hold, this will still work for
2450 * cases where only a single display controller is used.
2451 */
2452 for_each_matching_node(np, tegra_dc_of_match) {
2453 if (np == dc->dev->of_node) {
2454 of_node_put(np);
2455 break;
2456 }
2457
2458 value++;
2459 }
2460 }
2461
2462 dc->pipe = value;
2463
2464 return 0;
2465 }
2466
2467 static int tegra_dc_match_by_pipe(struct device *dev, const void *data)
2468 {
2469 struct tegra_dc *dc = dev_get_drvdata(dev);
2470 unsigned int pipe = (unsigned long)(void *)data;
2471
2472 return dc->pipe == pipe;
2473 }
2474
2475 static int tegra_dc_couple(struct tegra_dc *dc)
2476 {
2477 /*
2478 * On Tegra20, DC1 requires DC0 to be taken out of reset in order to
2479 * be enabled, otherwise CPU hangs on writing to CMD_DISPLAY_COMMAND /
2480 * POWER_CONTROL registers during CRTC enabling.
2481 */
2482 if (dc->soc->coupled_pm && dc->pipe == 1) {
2483 u32 flags = DL_FLAG_PM_RUNTIME | DL_FLAG_AUTOREMOVE_CONSUMER;
2484 struct device_link *link;
2485 struct device *partner;
2486
2487 partner = driver_find_device(dc->dev->driver, NULL, NULL,
2488 tegra_dc_match_by_pipe);
2489 if (!partner)
2490 return -EPROBE_DEFER;
2491
2492 link = device_link_add(dc->dev, partner, flags);
2493 if (!link) {
2494 dev_err(dc->dev, "failed to link controllers\n");
2495 return -EINVAL;
2496 }
2497
2498 dev_dbg(dc->dev, "coupled to %s\n", dev_name(partner));
2499 }
2500
2501 return 0;
2502 }
2503
2504 static int tegra_dc_probe(struct platform_device *pdev)
2505 {
2506 struct resource *regs;
2507 struct tegra_dc *dc;
2508 int err;
2509
2510 dc = devm_kzalloc(&pdev->dev, sizeof(*dc), GFP_KERNEL);
2511 if (!dc)
2512 return -ENOMEM;
2513
2514 dc->soc = of_device_get_match_data(&pdev->dev);
2515
2516 INIT_LIST_HEAD(&dc->list);
2517 dc->dev = &pdev->dev;
2518
2519 err = tegra_dc_parse_dt(dc);
2520 if (err < 0)
2521 return err;
2522
2523 err = tegra_dc_couple(dc);
2524 if (err < 0)
2525 return err;
2526
2527 dc->clk = devm_clk_get(&pdev->dev, NULL);
2528 if (IS_ERR(dc->clk)) {
2529 dev_err(&pdev->dev, "failed to get clock\n");
2530 return PTR_ERR(dc->clk);
2531 }
2532
2533 dc->rst = devm_reset_control_get(&pdev->dev, "dc");
2534 if (IS_ERR(dc->rst)) {
2535 dev_err(&pdev->dev, "failed to get reset\n");
2536 return PTR_ERR(dc->rst);
2537 }
2538
2539 /* assert reset and disable clock */
2540 err = clk_prepare_enable(dc->clk);
2541 if (err < 0)
2542 return err;
2543
2544 usleep_range(2000, 4000);
2545
2546 err = reset_control_assert(dc->rst);
2547 if (err < 0)
2548 return err;
2549
2550 usleep_range(2000, 4000);
2551
2552 clk_disable_unprepare(dc->clk);
2553
2554 if (dc->soc->has_powergate) {
2555 if (dc->pipe == 0)
2556 dc->powergate = TEGRA_POWERGATE_DIS;
2557 else
2558 dc->powergate = TEGRA_POWERGATE_DISB;
2559
2560 tegra_powergate_power_off(dc->powergate);
2561 }
2562
2563 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2564 dc->regs = devm_ioremap_resource(&pdev->dev, regs);
2565 if (IS_ERR(dc->regs))
2566 return PTR_ERR(dc->regs);
2567
2568 dc->irq = platform_get_irq(pdev, 0);
2569 if (dc->irq < 0) {
2570 dev_err(&pdev->dev, "failed to get IRQ\n");
2571 return -ENXIO;
2572 }
2573
2574 err = tegra_dc_rgb_probe(dc);
2575 if (err < 0 && err != -ENODEV) {
2576 dev_err(&pdev->dev, "failed to probe RGB output: %d\n", err);
2577 return err;
2578 }
2579
2580 platform_set_drvdata(pdev, dc);
2581 pm_runtime_enable(&pdev->dev);
2582
2583 INIT_LIST_HEAD(&dc->client.list);
2584 dc->client.ops = &dc_client_ops;
2585 dc->client.dev = &pdev->dev;
2586
2587 err = host1x_client_register(&dc->client);
2588 if (err < 0) {
2589 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
2590 err);
2591 return err;
2592 }
2593
2594 return 0;
2595 }
2596
2597 static int tegra_dc_remove(struct platform_device *pdev)
2598 {
2599 struct tegra_dc *dc = platform_get_drvdata(pdev);
2600 int err;
2601
2602 err = host1x_client_unregister(&dc->client);
2603 if (err < 0) {
2604 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
2605 err);
2606 return err;
2607 }
2608
2609 err = tegra_dc_rgb_remove(dc);
2610 if (err < 0) {
2611 dev_err(&pdev->dev, "failed to remove RGB output: %d\n", err);
2612 return err;
2613 }
2614
2615 pm_runtime_disable(&pdev->dev);
2616
2617 return 0;
2618 }
2619
2620 struct platform_driver tegra_dc_driver = {
2621 .driver = {
2622 .name = "tegra-dc",
2623 .of_match_table = tegra_dc_of_match,
2624 },
2625 .probe = tegra_dc_probe,
2626 .remove = tegra_dc_remove,
2627 };
Linux with added FPC-III support