?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
treewide: remove redundant IS_ERR() before error code check
[linux/fpc-iii.git] / drivers / gpu / drm / tegra / dsi.c
blob88b9d64c77bf2ee71528ff65ca857b4e6cc3b652
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2013 NVIDIA Corporation
4 */
5
6 #include <linux/clk.h>
7 #include <linux/debugfs.h>
8 #include <linux/delay.h>
9 #include <linux/host1x.h>
10 #include <linux/module.h>
11 #include <linux/of.h>
12 #include <linux/of_platform.h>
13 #include <linux/platform_device.h>
14 #include <linux/pm_runtime.h>
15 #include <linux/regulator/consumer.h>
16 #include <linux/reset.h>
17
18 #include <video/mipi_display.h>
19
20 #include <drm/drm_atomic_helper.h>
21 #include <drm/drm_debugfs.h>
22 #include <drm/drm_file.h>
23 #include <drm/drm_mipi_dsi.h>
24 #include <drm/drm_panel.h>
25
26 #include "dc.h"
27 #include "drm.h"
28 #include "dsi.h"
29 #include "mipi-phy.h"
30 #include "trace.h"
31
32 struct tegra_dsi_state {
33 struct drm_connector_state base;
34
35 struct mipi_dphy_timing timing;
36 unsigned long period;
37
38 unsigned int vrefresh;
39 unsigned int lanes;
40 unsigned long pclk;
41 unsigned long bclk;
42
43 enum tegra_dsi_format format;
44 unsigned int mul;
45 unsigned int div;
46 };
47
48 static inline struct tegra_dsi_state *
49 to_dsi_state(struct drm_connector_state *state)
50 {
51 return container_of(state, struct tegra_dsi_state, base);
52 }
53
54 struct tegra_dsi {
55 struct host1x_client client;
56 struct tegra_output output;
57 struct device *dev;
58
59 void __iomem *regs;
60
61 struct reset_control *rst;
62 struct clk *clk_parent;
63 struct clk *clk_lp;
64 struct clk *clk;
65
66 struct drm_info_list *debugfs_files;
67
68 unsigned long flags;
69 enum mipi_dsi_pixel_format format;
70 unsigned int lanes;
71
72 struct tegra_mipi_device *mipi;
73 struct mipi_dsi_host host;
74
75 struct regulator *vdd;
76
77 unsigned int video_fifo_depth;
78 unsigned int host_fifo_depth;
79
80 /* for ganged-mode support */
81 struct tegra_dsi *master;
82 struct tegra_dsi *slave;
83 };
84
85 static inline struct tegra_dsi *
86 host1x_client_to_dsi(struct host1x_client *client)
87 {
88 return container_of(client, struct tegra_dsi, client);
89 }
90
91 static inline struct tegra_dsi *host_to_tegra(struct mipi_dsi_host *host)
92 {
93 return container_of(host, struct tegra_dsi, host);
94 }
95
96 static inline struct tegra_dsi *to_dsi(struct tegra_output *output)
97 {
98 return container_of(output, struct tegra_dsi, output);
99 }
100
101 static struct tegra_dsi_state *tegra_dsi_get_state(struct tegra_dsi *dsi)
102 {
103 return to_dsi_state(dsi->output.connector.state);
104 }
105
106 static inline u32 tegra_dsi_readl(struct tegra_dsi *dsi, unsigned int offset)
107 {
108 u32 value = readl(dsi->regs + (offset << 2));
109
110 trace_dsi_readl(dsi->dev, offset, value);
111
112 return value;
113 }
114
115 static inline void tegra_dsi_writel(struct tegra_dsi *dsi, u32 value,
116 unsigned int offset)
117 {
118 trace_dsi_writel(dsi->dev, offset, value);
119 writel(value, dsi->regs + (offset << 2));
120 }
121
122 #define DEBUGFS_REG32(_name) { .name = #_name, .offset = _name }
123
124 static const struct debugfs_reg32 tegra_dsi_regs[] = {
125 DEBUGFS_REG32(DSI_INCR_SYNCPT),
126 DEBUGFS_REG32(DSI_INCR_SYNCPT_CONTROL),
127 DEBUGFS_REG32(DSI_INCR_SYNCPT_ERROR),
128 DEBUGFS_REG32(DSI_CTXSW),
129 DEBUGFS_REG32(DSI_RD_DATA),
130 DEBUGFS_REG32(DSI_WR_DATA),
131 DEBUGFS_REG32(DSI_POWER_CONTROL),
132 DEBUGFS_REG32(DSI_INT_ENABLE),
133 DEBUGFS_REG32(DSI_INT_STATUS),
134 DEBUGFS_REG32(DSI_INT_MASK),
135 DEBUGFS_REG32(DSI_HOST_CONTROL),
136 DEBUGFS_REG32(DSI_CONTROL),
137 DEBUGFS_REG32(DSI_SOL_DELAY),
138 DEBUGFS_REG32(DSI_MAX_THRESHOLD),
139 DEBUGFS_REG32(DSI_TRIGGER),
140 DEBUGFS_REG32(DSI_TX_CRC),
141 DEBUGFS_REG32(DSI_STATUS),
142 DEBUGFS_REG32(DSI_INIT_SEQ_CONTROL),
143 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_0),
144 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_1),
145 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_2),
146 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_3),
147 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_4),
148 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_5),
149 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_6),
150 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_7),
151 DEBUGFS_REG32(DSI_PKT_SEQ_0_LO),
152 DEBUGFS_REG32(DSI_PKT_SEQ_0_HI),
153 DEBUGFS_REG32(DSI_PKT_SEQ_1_LO),
154 DEBUGFS_REG32(DSI_PKT_SEQ_1_HI),
155 DEBUGFS_REG32(DSI_PKT_SEQ_2_LO),
156 DEBUGFS_REG32(DSI_PKT_SEQ_2_HI),
157 DEBUGFS_REG32(DSI_PKT_SEQ_3_LO),
158 DEBUGFS_REG32(DSI_PKT_SEQ_3_HI),
159 DEBUGFS_REG32(DSI_PKT_SEQ_4_LO),
160 DEBUGFS_REG32(DSI_PKT_SEQ_4_HI),
161 DEBUGFS_REG32(DSI_PKT_SEQ_5_LO),
162 DEBUGFS_REG32(DSI_PKT_SEQ_5_HI),
163 DEBUGFS_REG32(DSI_DCS_CMDS),
164 DEBUGFS_REG32(DSI_PKT_LEN_0_1),
165 DEBUGFS_REG32(DSI_PKT_LEN_2_3),
166 DEBUGFS_REG32(DSI_PKT_LEN_4_5),
167 DEBUGFS_REG32(DSI_PKT_LEN_6_7),
168 DEBUGFS_REG32(DSI_PHY_TIMING_0),
169 DEBUGFS_REG32(DSI_PHY_TIMING_1),
170 DEBUGFS_REG32(DSI_PHY_TIMING_2),
171 DEBUGFS_REG32(DSI_BTA_TIMING),
172 DEBUGFS_REG32(DSI_TIMEOUT_0),
173 DEBUGFS_REG32(DSI_TIMEOUT_1),
174 DEBUGFS_REG32(DSI_TO_TALLY),
175 DEBUGFS_REG32(DSI_PAD_CONTROL_0),
176 DEBUGFS_REG32(DSI_PAD_CONTROL_CD),
177 DEBUGFS_REG32(DSI_PAD_CD_STATUS),
178 DEBUGFS_REG32(DSI_VIDEO_MODE_CONTROL),
179 DEBUGFS_REG32(DSI_PAD_CONTROL_1),
180 DEBUGFS_REG32(DSI_PAD_CONTROL_2),
181 DEBUGFS_REG32(DSI_PAD_CONTROL_3),
182 DEBUGFS_REG32(DSI_PAD_CONTROL_4),
183 DEBUGFS_REG32(DSI_GANGED_MODE_CONTROL),
184 DEBUGFS_REG32(DSI_GANGED_MODE_START),
185 DEBUGFS_REG32(DSI_GANGED_MODE_SIZE),
186 DEBUGFS_REG32(DSI_RAW_DATA_BYTE_COUNT),
187 DEBUGFS_REG32(DSI_ULTRA_LOW_POWER_CONTROL),
188 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_8),
189 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_9),
190 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_10),
191 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_11),
192 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_12),
193 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_13),
194 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_14),
195 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_15),
196 };
197
198 static int tegra_dsi_show_regs(struct seq_file *s, void *data)
199 {
200 struct drm_info_node *node = s->private;
201 struct tegra_dsi *dsi = node->info_ent->data;
202 struct drm_crtc *crtc = dsi->output.encoder.crtc;
203 struct drm_device *drm = node->minor->dev;
204 unsigned int i;
205 int err = 0;
206
207 drm_modeset_lock_all(drm);
208
209 if (!crtc || !crtc->state->active) {
210 err = -EBUSY;
211 goto unlock;
212 }
213
214 for (i = 0; i < ARRAY_SIZE(tegra_dsi_regs); i++) {
215 unsigned int offset = tegra_dsi_regs[i].offset;
216
217 seq_printf(s, "%-32s %#05x %08x\n", tegra_dsi_regs[i].name,
218 offset, tegra_dsi_readl(dsi, offset));
219 }
220
221 unlock:
222 drm_modeset_unlock_all(drm);
223 return err;
224 }
225
226 static struct drm_info_list debugfs_files[] = {
227 { "regs", tegra_dsi_show_regs, 0, NULL },
228 };
229
230 static int tegra_dsi_late_register(struct drm_connector *connector)
231 {
232 struct tegra_output *output = connector_to_output(connector);
233 unsigned int i, count = ARRAY_SIZE(debugfs_files);
234 struct drm_minor *minor = connector->dev->primary;
235 struct dentry *root = connector->debugfs_entry;
236 struct tegra_dsi *dsi = to_dsi(output);
237 int err;
238
239 dsi->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
240 GFP_KERNEL);
241 if (!dsi->debugfs_files)
242 return -ENOMEM;
243
244 for (i = 0; i < count; i++)
245 dsi->debugfs_files[i].data = dsi;
246
247 err = drm_debugfs_create_files(dsi->debugfs_files, count, root, minor);
248 if (err < 0)
249 goto free;
250
251 return 0;
252
253 free:
254 kfree(dsi->debugfs_files);
255 dsi->debugfs_files = NULL;
256
257 return err;
258 }
259
260 static void tegra_dsi_early_unregister(struct drm_connector *connector)
261 {
262 struct tegra_output *output = connector_to_output(connector);
263 unsigned int count = ARRAY_SIZE(debugfs_files);
264 struct tegra_dsi *dsi = to_dsi(output);
265
266 drm_debugfs_remove_files(dsi->debugfs_files, count,
267 connector->dev->primary);
268 kfree(dsi->debugfs_files);
269 dsi->debugfs_files = NULL;
270 }
271
272 #define PKT_ID0(id) ((((id) & 0x3f) << 3) | (1 << 9))
273 #define PKT_LEN0(len) (((len) & 0x07) << 0)
274 #define PKT_ID1(id) ((((id) & 0x3f) << 13) | (1 << 19))
275 #define PKT_LEN1(len) (((len) & 0x07) << 10)
276 #define PKT_ID2(id) ((((id) & 0x3f) << 23) | (1 << 29))
277 #define PKT_LEN2(len) (((len) & 0x07) << 20)
278
279 #define PKT_LP (1 << 30)
280 #define NUM_PKT_SEQ 12
281
282 /*
283 * non-burst mode with sync pulses
284 */
285 static const u32 pkt_seq_video_non_burst_sync_pulses[NUM_PKT_SEQ] = {
286 [ 0] = PKT_ID0(MIPI_DSI_V_SYNC_START) | PKT_LEN0(0) |
287 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
288 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) |
289 PKT_LP,
290 [ 1] = 0,
291 [ 2] = PKT_ID0(MIPI_DSI_V_SYNC_END) | PKT_LEN0(0) |
292 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
293 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) |
294 PKT_LP,
295 [ 3] = 0,
296 [ 4] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
297 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
298 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) |
299 PKT_LP,
300 [ 5] = 0,
301 [ 6] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
302 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
303 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0),
304 [ 7] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(2) |
305 PKT_ID1(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN1(3) |
306 PKT_ID2(MIPI_DSI_BLANKING_PACKET) | PKT_LEN2(4),
307 [ 8] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
308 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
309 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) |
310 PKT_LP,
311 [ 9] = 0,
312 [10] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
313 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
314 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0),
315 [11] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(2) |
316 PKT_ID1(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN1(3) |
317 PKT_ID2(MIPI_DSI_BLANKING_PACKET) | PKT_LEN2(4),
318 };
319
320 /*
321 * non-burst mode with sync events
322 */
323 static const u32 pkt_seq_video_non_burst_sync_events[NUM_PKT_SEQ] = {
324 [ 0] = PKT_ID0(MIPI_DSI_V_SYNC_START) | PKT_LEN0(0) |
325 PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) |
326 PKT_LP,
327 [ 1] = 0,
328 [ 2] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
329 PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) |
330 PKT_LP,
331 [ 3] = 0,
332 [ 4] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
333 PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) |
334 PKT_LP,
335 [ 5] = 0,
336 [ 6] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
337 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(2) |
338 PKT_ID2(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN2(3),
339 [ 7] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(4),
340 [ 8] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
341 PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) |
342 PKT_LP,
343 [ 9] = 0,
344 [10] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
345 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(2) |
346 PKT_ID2(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN2(3),
347 [11] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(4),
348 };
349
350 static const u32 pkt_seq_command_mode[NUM_PKT_SEQ] = {
351 [ 0] = 0,
352 [ 1] = 0,
353 [ 2] = 0,
354 [ 3] = 0,
355 [ 4] = 0,
356 [ 5] = 0,
357 [ 6] = PKT_ID0(MIPI_DSI_DCS_LONG_WRITE) | PKT_LEN0(3) | PKT_LP,
358 [ 7] = 0,
359 [ 8] = 0,
360 [ 9] = 0,
361 [10] = PKT_ID0(MIPI_DSI_DCS_LONG_WRITE) | PKT_LEN0(5) | PKT_LP,
362 [11] = 0,
363 };
364
365 static void tegra_dsi_set_phy_timing(struct tegra_dsi *dsi,
366 unsigned long period,
367 const struct mipi_dphy_timing *timing)
368 {
369 u32 value;
370
371 value = DSI_TIMING_FIELD(timing->hsexit, period, 1) << 24 |
372 DSI_TIMING_FIELD(timing->hstrail, period, 0) << 16 |
373 DSI_TIMING_FIELD(timing->hszero, period, 3) << 8 |
374 DSI_TIMING_FIELD(timing->hsprepare, period, 1);
375 tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_0);
376
377 value = DSI_TIMING_FIELD(timing->clktrail, period, 1) << 24 |
378 DSI_TIMING_FIELD(timing->clkpost, period, 1) << 16 |
379 DSI_TIMING_FIELD(timing->clkzero, period, 1) << 8 |
380 DSI_TIMING_FIELD(timing->lpx, period, 1);
381 tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_1);
382
383 value = DSI_TIMING_FIELD(timing->clkprepare, period, 1) << 16 |
384 DSI_TIMING_FIELD(timing->clkpre, period, 1) << 8 |
385 DSI_TIMING_FIELD(0xff * period, period, 0) << 0;
386 tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_2);
387
388 value = DSI_TIMING_FIELD(timing->taget, period, 1) << 16 |
389 DSI_TIMING_FIELD(timing->tasure, period, 1) << 8 |
390 DSI_TIMING_FIELD(timing->tago, period, 1);
391 tegra_dsi_writel(dsi, value, DSI_BTA_TIMING);
392
393 if (dsi->slave)
394 tegra_dsi_set_phy_timing(dsi->slave, period, timing);
395 }
396
397 static int tegra_dsi_get_muldiv(enum mipi_dsi_pixel_format format,
398 unsigned int *mulp, unsigned int *divp)
399 {
400 switch (format) {
401 case MIPI_DSI_FMT_RGB666_PACKED:
402 case MIPI_DSI_FMT_RGB888:
403 *mulp = 3;
404 *divp = 1;
405 break;
406
407 case MIPI_DSI_FMT_RGB565:
408 *mulp = 2;
409 *divp = 1;
410 break;
411
412 case MIPI_DSI_FMT_RGB666:
413 *mulp = 9;
414 *divp = 4;
415 break;
416
417 default:
418 return -EINVAL;
419 }
420
421 return 0;
422 }
423
424 static int tegra_dsi_get_format(enum mipi_dsi_pixel_format format,
425 enum tegra_dsi_format *fmt)
426 {
427 switch (format) {
428 case MIPI_DSI_FMT_RGB888:
429 *fmt = TEGRA_DSI_FORMAT_24P;
430 break;
431
432 case MIPI_DSI_FMT_RGB666:
433 *fmt = TEGRA_DSI_FORMAT_18NP;
434 break;
435
436 case MIPI_DSI_FMT_RGB666_PACKED:
437 *fmt = TEGRA_DSI_FORMAT_18P;
438 break;
439
440 case MIPI_DSI_FMT_RGB565:
441 *fmt = TEGRA_DSI_FORMAT_16P;
442 break;
443
444 default:
445 return -EINVAL;
446 }
447
448 return 0;
449 }
450
451 static void tegra_dsi_ganged_enable(struct tegra_dsi *dsi, unsigned int start,
452 unsigned int size)
453 {
454 u32 value;
455
456 tegra_dsi_writel(dsi, start, DSI_GANGED_MODE_START);
457 tegra_dsi_writel(dsi, size << 16 | size, DSI_GANGED_MODE_SIZE);
458
459 value = DSI_GANGED_MODE_CONTROL_ENABLE;
460 tegra_dsi_writel(dsi, value, DSI_GANGED_MODE_CONTROL);
461 }
462
463 static void tegra_dsi_enable(struct tegra_dsi *dsi)
464 {
465 u32 value;
466
467 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
468 value |= DSI_POWER_CONTROL_ENABLE;
469 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
470
471 if (dsi->slave)
472 tegra_dsi_enable(dsi->slave);
473 }
474
475 static unsigned int tegra_dsi_get_lanes(struct tegra_dsi *dsi)
476 {
477 if (dsi->master)
478 return dsi->master->lanes + dsi->lanes;
479
480 if (dsi->slave)
481 return dsi->lanes + dsi->slave->lanes;
482
483 return dsi->lanes;
484 }
485
486 static void tegra_dsi_configure(struct tegra_dsi *dsi, unsigned int pipe,
487 const struct drm_display_mode *mode)
488 {
489 unsigned int hact, hsw, hbp, hfp, i, mul, div;
490 struct tegra_dsi_state *state;
491 const u32 *pkt_seq;
492 u32 value;
493
494 /* XXX: pass in state into this function? */
495 if (dsi->master)
496 state = tegra_dsi_get_state(dsi->master);
497 else
498 state = tegra_dsi_get_state(dsi);
499
500 mul = state->mul;
501 div = state->div;
502
503 if (dsi->flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) {
504 DRM_DEBUG_KMS("Non-burst video mode with sync pulses\n");
505 pkt_seq = pkt_seq_video_non_burst_sync_pulses;
506 } else if (dsi->flags & MIPI_DSI_MODE_VIDEO) {
507 DRM_DEBUG_KMS("Non-burst video mode with sync events\n");
508 pkt_seq = pkt_seq_video_non_burst_sync_events;
509 } else {
510 DRM_DEBUG_KMS("Command mode\n");
511 pkt_seq = pkt_seq_command_mode;
512 }
513
514 value = DSI_CONTROL_CHANNEL(0) |
515 DSI_CONTROL_FORMAT(state->format) |
516 DSI_CONTROL_LANES(dsi->lanes - 1) |
517 DSI_CONTROL_SOURCE(pipe);
518 tegra_dsi_writel(dsi, value, DSI_CONTROL);
519
520 tegra_dsi_writel(dsi, dsi->video_fifo_depth, DSI_MAX_THRESHOLD);
521
522 value = DSI_HOST_CONTROL_HS;
523 tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);
524
525 value = tegra_dsi_readl(dsi, DSI_CONTROL);
526
527 if (dsi->flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)
528 value |= DSI_CONTROL_HS_CLK_CTRL;
529
530 value &= ~DSI_CONTROL_TX_TRIG(3);
531
532 /* enable DCS commands for command mode */
533 if (dsi->flags & MIPI_DSI_MODE_VIDEO)
534 value &= ~DSI_CONTROL_DCS_ENABLE;
535 else
536 value |= DSI_CONTROL_DCS_ENABLE;
537
538 value |= DSI_CONTROL_VIDEO_ENABLE;
539 value &= ~DSI_CONTROL_HOST_ENABLE;
540 tegra_dsi_writel(dsi, value, DSI_CONTROL);
541
542 for (i = 0; i < NUM_PKT_SEQ; i++)
543 tegra_dsi_writel(dsi, pkt_seq[i], DSI_PKT_SEQ_0_LO + i);
544
545 if (dsi->flags & MIPI_DSI_MODE_VIDEO) {
546 /* horizontal active pixels */
547 hact = mode->hdisplay * mul / div;
548
549 /* horizontal sync width */
550 hsw = (mode->hsync_end - mode->hsync_start) * mul / div;
551
552 /* horizontal back porch */
553 hbp = (mode->htotal - mode->hsync_end) * mul / div;
554
555 if ((dsi->flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) == 0)
556 hbp += hsw;
557
558 /* horizontal front porch */
559 hfp = (mode->hsync_start - mode->hdisplay) * mul / div;
560
561 /* subtract packet overhead */
562 hsw -= 10;
563 hbp -= 14;
564 hfp -= 8;
565
566 tegra_dsi_writel(dsi, hsw << 16 | 0, DSI_PKT_LEN_0_1);
567 tegra_dsi_writel(dsi, hact << 16 | hbp, DSI_PKT_LEN_2_3);
568 tegra_dsi_writel(dsi, hfp, DSI_PKT_LEN_4_5);
569 tegra_dsi_writel(dsi, 0x0f0f << 16, DSI_PKT_LEN_6_7);
570
571 /* set SOL delay (for non-burst mode only) */
572 tegra_dsi_writel(dsi, 8 * mul / div, DSI_SOL_DELAY);
573
574 /* TODO: implement ganged mode */
575 } else {
576 u16 bytes;
577
578 if (dsi->master || dsi->slave) {
579 /*
580 * For ganged mode, assume symmetric left-right mode.
581 */
582 bytes = 1 + (mode->hdisplay / 2) * mul / div;
583 } else {
584 /* 1 byte (DCS command) + pixel data */
585 bytes = 1 + mode->hdisplay * mul / div;
586 }
587
588 tegra_dsi_writel(dsi, 0, DSI_PKT_LEN_0_1);
589 tegra_dsi_writel(dsi, bytes << 16, DSI_PKT_LEN_2_3);
590 tegra_dsi_writel(dsi, bytes << 16, DSI_PKT_LEN_4_5);
591 tegra_dsi_writel(dsi, 0, DSI_PKT_LEN_6_7);
592
593 value = MIPI_DCS_WRITE_MEMORY_START << 8 |
594 MIPI_DCS_WRITE_MEMORY_CONTINUE;
595 tegra_dsi_writel(dsi, value, DSI_DCS_CMDS);
596
597 /* set SOL delay */
598 if (dsi->master || dsi->slave) {
599 unsigned long delay, bclk, bclk_ganged;
600 unsigned int lanes = state->lanes;
601
602 /* SOL to valid, valid to FIFO and FIFO write delay */
603 delay = 4 + 4 + 2;
604 delay = DIV_ROUND_UP(delay * mul, div * lanes);
605 /* FIFO read delay */
606 delay = delay + 6;
607
608 bclk = DIV_ROUND_UP(mode->htotal * mul, div * lanes);
609 bclk_ganged = DIV_ROUND_UP(bclk * lanes / 2, lanes);
610 value = bclk - bclk_ganged + delay + 20;
611 } else {
612 /* TODO: revisit for non-ganged mode */
613 value = 8 * mul / div;
614 }
615
616 tegra_dsi_writel(dsi, value, DSI_SOL_DELAY);
617 }
618
619 if (dsi->slave) {
620 tegra_dsi_configure(dsi->slave, pipe, mode);
621
622 /*
623 * TODO: Support modes other than symmetrical left-right
624 * split.
625 */
626 tegra_dsi_ganged_enable(dsi, 0, mode->hdisplay / 2);
627 tegra_dsi_ganged_enable(dsi->slave, mode->hdisplay / 2,
628 mode->hdisplay / 2);
629 }
630 }
631
632 static int tegra_dsi_wait_idle(struct tegra_dsi *dsi, unsigned long timeout)
633 {
634 u32 value;
635
636 timeout = jiffies + msecs_to_jiffies(timeout);
637
638 while (time_before(jiffies, timeout)) {
639 value = tegra_dsi_readl(dsi, DSI_STATUS);
640 if (value & DSI_STATUS_IDLE)
641 return 0;
642
643 usleep_range(1000, 2000);
644 }
645
646 return -ETIMEDOUT;
647 }
648
649 static void tegra_dsi_video_disable(struct tegra_dsi *dsi)
650 {
651 u32 value;
652
653 value = tegra_dsi_readl(dsi, DSI_CONTROL);
654 value &= ~DSI_CONTROL_VIDEO_ENABLE;
655 tegra_dsi_writel(dsi, value, DSI_CONTROL);
656
657 if (dsi->slave)
658 tegra_dsi_video_disable(dsi->slave);
659 }
660
661 static void tegra_dsi_ganged_disable(struct tegra_dsi *dsi)
662 {
663 tegra_dsi_writel(dsi, 0, DSI_GANGED_MODE_START);
664 tegra_dsi_writel(dsi, 0, DSI_GANGED_MODE_SIZE);
665 tegra_dsi_writel(dsi, 0, DSI_GANGED_MODE_CONTROL);
666 }
667
668 static int tegra_dsi_pad_enable(struct tegra_dsi *dsi)
669 {
670 u32 value;
671
672 value = DSI_PAD_CONTROL_VS1_PULLDN(0) | DSI_PAD_CONTROL_VS1_PDIO(0);
673 tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_0);
674
675 return 0;
676 }
677
678 static int tegra_dsi_pad_calibrate(struct tegra_dsi *dsi)
679 {
680 u32 value;
681
682 /*
683 * XXX Is this still needed? The module reset is deasserted right
684 * before this function is called.
685 */
686 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_0);
687 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_1);
688 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_2);
689 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_3);
690 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_4);
691
692 /* start calibration */
693 tegra_dsi_pad_enable(dsi);
694
695 value = DSI_PAD_SLEW_UP(0x7) | DSI_PAD_SLEW_DN(0x7) |
696 DSI_PAD_LP_UP(0x1) | DSI_PAD_LP_DN(0x1) |
697 DSI_PAD_OUT_CLK(0x0);
698 tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_2);
699
700 value = DSI_PAD_PREEMP_PD_CLK(0x3) | DSI_PAD_PREEMP_PU_CLK(0x3) |
701 DSI_PAD_PREEMP_PD(0x03) | DSI_PAD_PREEMP_PU(0x3);
702 tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_3);
703
704 return tegra_mipi_calibrate(dsi->mipi);
705 }
706
707 static void tegra_dsi_set_timeout(struct tegra_dsi *dsi, unsigned long bclk,
708 unsigned int vrefresh)
709 {
710 unsigned int timeout;
711 u32 value;
712
713 /* one frame high-speed transmission timeout */
714 timeout = (bclk / vrefresh) / 512;
715 value = DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(timeout);
716 tegra_dsi_writel(dsi, value, DSI_TIMEOUT_0);
717
718 /* 2 ms peripheral timeout for panel */
719 timeout = 2 * bclk / 512 * 1000;
720 value = DSI_TIMEOUT_PR(timeout) | DSI_TIMEOUT_TA(0x2000);
721 tegra_dsi_writel(dsi, value, DSI_TIMEOUT_1);
722
723 value = DSI_TALLY_TA(0) | DSI_TALLY_LRX(0) | DSI_TALLY_HTX(0);
724 tegra_dsi_writel(dsi, value, DSI_TO_TALLY);
725
726 if (dsi->slave)
727 tegra_dsi_set_timeout(dsi->slave, bclk, vrefresh);
728 }
729
730 static void tegra_dsi_disable(struct tegra_dsi *dsi)
731 {
732 u32 value;
733
734 if (dsi->slave) {
735 tegra_dsi_ganged_disable(dsi->slave);
736 tegra_dsi_ganged_disable(dsi);
737 }
738
739 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
740 value &= ~DSI_POWER_CONTROL_ENABLE;
741 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
742
743 if (dsi->slave)
744 tegra_dsi_disable(dsi->slave);
745
746 usleep_range(5000, 10000);
747 }
748
749 static void tegra_dsi_soft_reset(struct tegra_dsi *dsi)
750 {
751 u32 value;
752
753 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
754 value &= ~DSI_POWER_CONTROL_ENABLE;
755 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
756
757 usleep_range(300, 1000);
758
759 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
760 value |= DSI_POWER_CONTROL_ENABLE;
761 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
762
763 usleep_range(300, 1000);
764
765 value = tegra_dsi_readl(dsi, DSI_TRIGGER);
766 if (value)
767 tegra_dsi_writel(dsi, 0, DSI_TRIGGER);
768
769 if (dsi->slave)
770 tegra_dsi_soft_reset(dsi->slave);
771 }
772
773 static void tegra_dsi_connector_reset(struct drm_connector *connector)
774 {
775 struct tegra_dsi_state *state = kzalloc(sizeof(*state), GFP_KERNEL);
776
777 if (!state)
778 return;
779
780 if (connector->state) {
781 __drm_atomic_helper_connector_destroy_state(connector->state);
782 kfree(connector->state);
783 }
784
785 __drm_atomic_helper_connector_reset(connector, &state->base);
786 }
787
788 static struct drm_connector_state *
789 tegra_dsi_connector_duplicate_state(struct drm_connector *connector)
790 {
791 struct tegra_dsi_state *state = to_dsi_state(connector->state);
792 struct tegra_dsi_state *copy;
793
794 copy = kmemdup(state, sizeof(*state), GFP_KERNEL);
795 if (!copy)
796 return NULL;
797
798 __drm_atomic_helper_connector_duplicate_state(connector,
799 &copy->base);
800
801 return &copy->base;
802 }
803
804 static const struct drm_connector_funcs tegra_dsi_connector_funcs = {
805 .reset = tegra_dsi_connector_reset,
806 .detect = tegra_output_connector_detect,
807 .fill_modes = drm_helper_probe_single_connector_modes,
808 .destroy = tegra_output_connector_destroy,
809 .atomic_duplicate_state = tegra_dsi_connector_duplicate_state,
810 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
811 .late_register = tegra_dsi_late_register,
812 .early_unregister = tegra_dsi_early_unregister,
813 };
814
815 static enum drm_mode_status
816 tegra_dsi_connector_mode_valid(struct drm_connector *connector,
817 struct drm_display_mode *mode)
818 {
819 return MODE_OK;
820 }
821
822 static const struct drm_connector_helper_funcs tegra_dsi_connector_helper_funcs = {
823 .get_modes = tegra_output_connector_get_modes,
824 .mode_valid = tegra_dsi_connector_mode_valid,
825 };
826
827 static const struct drm_encoder_funcs tegra_dsi_encoder_funcs = {
828 .destroy = tegra_output_encoder_destroy,
829 };
830
831 static void tegra_dsi_unprepare(struct tegra_dsi *dsi)
832 {
833 int err;
834
835 if (dsi->slave)
836 tegra_dsi_unprepare(dsi->slave);
837
838 err = tegra_mipi_disable(dsi->mipi);
839 if (err < 0)
840 dev_err(dsi->dev, "failed to disable MIPI calibration: %d\n",
841 err);
842
843 err = host1x_client_suspend(&dsi->client);
844 if (err < 0)
845 dev_err(dsi->dev, "failed to suspend: %d\n", err);
846 }
847
848 static void tegra_dsi_encoder_disable(struct drm_encoder *encoder)
849 {
850 struct tegra_output *output = encoder_to_output(encoder);
851 struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
852 struct tegra_dsi *dsi = to_dsi(output);
853 u32 value;
854 int err;
855
856 if (output->panel)
857 drm_panel_disable(output->panel);
858
859 tegra_dsi_video_disable(dsi);
860
861 /*
862 * The following accesses registers of the display controller, so make
863 * sure it's only executed when the output is attached to one.
864 */
865 if (dc) {
866 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
867 value &= ~DSI_ENABLE;
868 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
869
870 tegra_dc_commit(dc);
871 }
872
873 err = tegra_dsi_wait_idle(dsi, 100);
874 if (err < 0)
875 dev_dbg(dsi->dev, "failed to idle DSI: %d\n", err);
876
877 tegra_dsi_soft_reset(dsi);
878
879 if (output->panel)
880 drm_panel_unprepare(output->panel);
881
882 tegra_dsi_disable(dsi);
883
884 tegra_dsi_unprepare(dsi);
885 }
886
887 static int tegra_dsi_prepare(struct tegra_dsi *dsi)
888 {
889 int err;
890
891 err = host1x_client_resume(&dsi->client);
892 if (err < 0) {
893 dev_err(dsi->dev, "failed to resume: %d\n", err);
894 return err;
895 }
896
897 err = tegra_mipi_enable(dsi->mipi);
898 if (err < 0)
899 dev_err(dsi->dev, "failed to enable MIPI calibration: %d\n",
900 err);
901
902 err = tegra_dsi_pad_calibrate(dsi);
903 if (err < 0)
904 dev_err(dsi->dev, "MIPI calibration failed: %d\n", err);
905
906 if (dsi->slave)
907 tegra_dsi_prepare(dsi->slave);
908
909 return 0;
910 }
911
912 static void tegra_dsi_encoder_enable(struct drm_encoder *encoder)
913 {
914 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
915 struct tegra_output *output = encoder_to_output(encoder);
916 struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
917 struct tegra_dsi *dsi = to_dsi(output);
918 struct tegra_dsi_state *state;
919 u32 value;
920 int err;
921
922 err = tegra_dsi_prepare(dsi);
923 if (err < 0) {
924 dev_err(dsi->dev, "failed to prepare: %d\n", err);
925 return;
926 }
927
928 state = tegra_dsi_get_state(dsi);
929
930 tegra_dsi_set_timeout(dsi, state->bclk, state->vrefresh);
931
932 /*
933 * The D-PHY timing fields are expressed in byte-clock cycles, so
934 * multiply the period by 8.
935 */
936 tegra_dsi_set_phy_timing(dsi, state->period * 8, &state->timing);
937
938 if (output->panel)
939 drm_panel_prepare(output->panel);
940
941 tegra_dsi_configure(dsi, dc->pipe, mode);
942
943 /* enable display controller */
944 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
945 value |= DSI_ENABLE;
946 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
947
948 tegra_dc_commit(dc);
949
950 /* enable DSI controller */
951 tegra_dsi_enable(dsi);
952
953 if (output->panel)
954 drm_panel_enable(output->panel);
955 }
956
957 static int
958 tegra_dsi_encoder_atomic_check(struct drm_encoder *encoder,
959 struct drm_crtc_state *crtc_state,
960 struct drm_connector_state *conn_state)
961 {
962 struct tegra_output *output = encoder_to_output(encoder);
963 struct tegra_dsi_state *state = to_dsi_state(conn_state);
964 struct tegra_dc *dc = to_tegra_dc(conn_state->crtc);
965 struct tegra_dsi *dsi = to_dsi(output);
966 unsigned int scdiv;
967 unsigned long plld;
968 int err;
969
970 state->pclk = crtc_state->mode.clock * 1000;
971
972 err = tegra_dsi_get_muldiv(dsi->format, &state->mul, &state->div);
973 if (err < 0)
974 return err;
975
976 state->lanes = tegra_dsi_get_lanes(dsi);
977
978 err = tegra_dsi_get_format(dsi->format, &state->format);
979 if (err < 0)
980 return err;
981
982 state->vrefresh = drm_mode_vrefresh(&crtc_state->mode);
983
984 /* compute byte clock */
985 state->bclk = (state->pclk * state->mul) / (state->div * state->lanes);
986
987 DRM_DEBUG_KMS("mul: %u, div: %u, lanes: %u\n", state->mul, state->div,
988 state->lanes);
989 DRM_DEBUG_KMS("format: %u, vrefresh: %u\n", state->format,
990 state->vrefresh);
991 DRM_DEBUG_KMS("bclk: %lu\n", state->bclk);
992
993 /*
994 * Compute bit clock and round up to the next MHz.
995 */
996 plld = DIV_ROUND_UP(state->bclk * 8, USEC_PER_SEC) * USEC_PER_SEC;
997 state->period = DIV_ROUND_CLOSEST(NSEC_PER_SEC, plld);
998
999 err = mipi_dphy_timing_get_default(&state->timing, state->period);
1000 if (err < 0)
1001 return err;
1002
1003 err = mipi_dphy_timing_validate(&state->timing, state->period);
1004 if (err < 0) {
1005 dev_err(dsi->dev, "failed to validate D-PHY timing: %d\n", err);
1006 return err;
1007 }
1008
1009 /*
1010 * We divide the frequency by two here, but we make up for that by
1011 * setting the shift clock divider (further below) to half of the
1012 * correct value.
1013 */
1014 plld /= 2;
1015
1016 /*
1017 * Derive pixel clock from bit clock using the shift clock divider.
1018 * Note that this is only half of what we would expect, but we need
1019 * that to make up for the fact that we divided the bit clock by a
1020 * factor of two above.
1021 *
1022 * It's not clear exactly why this is necessary, but the display is
1023 * not working properly otherwise. Perhaps the PLLs cannot generate
1024 * frequencies sufficiently high.
1025 */
1026 scdiv = ((8 * state->mul) / (state->div * state->lanes)) - 2;
1027
1028 err = tegra_dc_state_setup_clock(dc, crtc_state, dsi->clk_parent,
1029 plld, scdiv);
1030 if (err < 0) {
1031 dev_err(output->dev, "failed to setup CRTC state: %d\n", err);
1032 return err;
1033 }
1034
1035 return err;
1036 }
1037
1038 static const struct drm_encoder_helper_funcs tegra_dsi_encoder_helper_funcs = {
1039 .disable = tegra_dsi_encoder_disable,
1040 .enable = tegra_dsi_encoder_enable,
1041 .atomic_check = tegra_dsi_encoder_atomic_check,
1042 };
1043
1044 static int tegra_dsi_init(struct host1x_client *client)
1045 {
1046 struct drm_device *drm = dev_get_drvdata(client->host);
1047 struct tegra_dsi *dsi = host1x_client_to_dsi(client);
1048 int err;
1049
1050 /* Gangsters must not register their own outputs. */
1051 if (!dsi->master) {
1052 dsi->output.dev = client->dev;
1053
1054 drm_connector_init(drm, &dsi->output.connector,
1055 &tegra_dsi_connector_funcs,
1056 DRM_MODE_CONNECTOR_DSI);
1057 drm_connector_helper_add(&dsi->output.connector,
1058 &tegra_dsi_connector_helper_funcs);
1059 dsi->output.connector.dpms = DRM_MODE_DPMS_OFF;
1060
1061 drm_encoder_init(drm, &dsi->output.encoder,
1062 &tegra_dsi_encoder_funcs,
1063 DRM_MODE_ENCODER_DSI, NULL);
1064 drm_encoder_helper_add(&dsi->output.encoder,
1065 &tegra_dsi_encoder_helper_funcs);
1066
1067 drm_connector_attach_encoder(&dsi->output.connector,
1068 &dsi->output.encoder);
1069 drm_connector_register(&dsi->output.connector);
1070
1071 err = tegra_output_init(drm, &dsi->output);
1072 if (err < 0)
1073 dev_err(dsi->dev, "failed to initialize output: %d\n",
1074 err);
1075
1076 dsi->output.encoder.possible_crtcs = 0x3;
1077 }
1078
1079 return 0;
1080 }
1081
1082 static int tegra_dsi_exit(struct host1x_client *client)
1083 {
1084 struct tegra_dsi *dsi = host1x_client_to_dsi(client);
1085
1086 tegra_output_exit(&dsi->output);
1087
1088 return 0;
1089 }
1090
1091 static int tegra_dsi_runtime_suspend(struct host1x_client *client)
1092 {
1093 struct tegra_dsi *dsi = host1x_client_to_dsi(client);
1094 struct device *dev = client->dev;
1095 int err;
1096
1097 if (dsi->rst) {
1098 err = reset_control_assert(dsi->rst);
1099 if (err < 0) {
1100 dev_err(dev, "failed to assert reset: %d\n", err);
1101 return err;
1102 }
1103 }
1104
1105 usleep_range(1000, 2000);
1106
1107 clk_disable_unprepare(dsi->clk_lp);
1108 clk_disable_unprepare(dsi->clk);
1109
1110 regulator_disable(dsi->vdd);
1111 pm_runtime_put_sync(dev);
1112
1113 return 0;
1114 }
1115
1116 static int tegra_dsi_runtime_resume(struct host1x_client *client)
1117 {
1118 struct tegra_dsi *dsi = host1x_client_to_dsi(client);
1119 struct device *dev = client->dev;
1120 int err;
1121
1122 err = pm_runtime_get_sync(dev);
1123 if (err < 0) {
1124 dev_err(dev, "failed to get runtime PM: %d\n", err);
1125 return err;
1126 }
1127
1128 err = regulator_enable(dsi->vdd);
1129 if (err < 0) {
1130 dev_err(dev, "failed to enable VDD supply: %d\n", err);
1131 goto put_rpm;
1132 }
1133
1134 err = clk_prepare_enable(dsi->clk);
1135 if (err < 0) {
1136 dev_err(dev, "cannot enable DSI clock: %d\n", err);
1137 goto disable_vdd;
1138 }
1139
1140 err = clk_prepare_enable(dsi->clk_lp);
1141 if (err < 0) {
1142 dev_err(dev, "cannot enable low-power clock: %d\n", err);
1143 goto disable_clk;
1144 }
1145
1146 usleep_range(1000, 2000);
1147
1148 if (dsi->rst) {
1149 err = reset_control_deassert(dsi->rst);
1150 if (err < 0) {
1151 dev_err(dev, "cannot assert reset: %d\n", err);
1152 goto disable_clk_lp;
1153 }
1154 }
1155
1156 return 0;
1157
1158 disable_clk_lp:
1159 clk_disable_unprepare(dsi->clk_lp);
1160 disable_clk:
1161 clk_disable_unprepare(dsi->clk);
1162 disable_vdd:
1163 regulator_disable(dsi->vdd);
1164 put_rpm:
1165 pm_runtime_put_sync(dev);
1166 return err;
1167 }
1168
1169 static const struct host1x_client_ops dsi_client_ops = {
1170 .init = tegra_dsi_init,
1171 .exit = tegra_dsi_exit,
1172 .suspend = tegra_dsi_runtime_suspend,
1173 .resume = tegra_dsi_runtime_resume,
1174 };
1175
1176 static int tegra_dsi_setup_clocks(struct tegra_dsi *dsi)
1177 {
1178 struct clk *parent;
1179 int err;
1180
1181 parent = clk_get_parent(dsi->clk);
1182 if (!parent)
1183 return -EINVAL;
1184
1185 err = clk_set_parent(parent, dsi->clk_parent);
1186 if (err < 0)
1187 return err;
1188
1189 return 0;
1190 }
1191
1192 static const char * const error_report[16] = {
1193 "SoT Error",
1194 "SoT Sync Error",
1195 "EoT Sync Error",
1196 "Escape Mode Entry Command Error",
1197 "Low-Power Transmit Sync Error",
1198 "Peripheral Timeout Error",
1199 "False Control Error",
1200 "Contention Detected",
1201 "ECC Error, single-bit",
1202 "ECC Error, multi-bit",
1203 "Checksum Error",
1204 "DSI Data Type Not Recognized",
1205 "DSI VC ID Invalid",
1206 "Invalid Transmission Length",
1207 "Reserved",
1208 "DSI Protocol Violation",
1209 };
1210
1211 static ssize_t tegra_dsi_read_response(struct tegra_dsi *dsi,
1212 const struct mipi_dsi_msg *msg,
1213 size_t count)
1214 {
1215 u8 *rx = msg->rx_buf;
1216 unsigned int i, j, k;
1217 size_t size = 0;
1218 u16 errors;
1219 u32 value;
1220
1221 /* read and parse packet header */
1222 value = tegra_dsi_readl(dsi, DSI_RD_DATA);
1223
1224 switch (value & 0x3f) {
1225 case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT:
1226 errors = (value >> 8) & 0xffff;
1227 dev_dbg(dsi->dev, "Acknowledge and error report: %04x\n",
1228 errors);
1229 for (i = 0; i < ARRAY_SIZE(error_report); i++)
1230 if (errors & BIT(i))
1231 dev_dbg(dsi->dev, " %2u: %s\n", i,
1232 error_report[i]);
1233 break;
1234
1235 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE:
1236 rx[0] = (value >> 8) & 0xff;
1237 size = 1;
1238 break;
1239
1240 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE:
1241 rx[0] = (value >> 8) & 0xff;
1242 rx[1] = (value >> 16) & 0xff;
1243 size = 2;
1244 break;
1245
1246 case MIPI_DSI_RX_DCS_LONG_READ_RESPONSE:
1247 size = ((value >> 8) & 0xff00) | ((value >> 8) & 0xff);
1248 break;
1249
1250 case MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE:
1251 size = ((value >> 8) & 0xff00) | ((value >> 8) & 0xff);
1252 break;
1253
1254 default:
1255 dev_err(dsi->dev, "unhandled response type: %02x\n",
1256 value & 0x3f);
1257 return -EPROTO;
1258 }
1259
1260 size = min(size, msg->rx_len);
1261
1262 if (msg->rx_buf && size > 0) {
1263 for (i = 0, j = 0; i < count - 1; i++, j += 4) {
1264 u8 *rx = msg->rx_buf + j;
1265
1266 value = tegra_dsi_readl(dsi, DSI_RD_DATA);
1267
1268 for (k = 0; k < 4 && (j + k) < msg->rx_len; k++)
1269 rx[j + k] = (value >> (k << 3)) & 0xff;
1270 }
1271 }
1272
1273 return size;
1274 }
1275
1276 static int tegra_dsi_transmit(struct tegra_dsi *dsi, unsigned long timeout)
1277 {
1278 tegra_dsi_writel(dsi, DSI_TRIGGER_HOST, DSI_TRIGGER);
1279
1280 timeout = jiffies + msecs_to_jiffies(timeout);
1281
1282 while (time_before(jiffies, timeout)) {
1283 u32 value = tegra_dsi_readl(dsi, DSI_TRIGGER);
1284 if ((value & DSI_TRIGGER_HOST) == 0)
1285 return 0;
1286
1287 usleep_range(1000, 2000);
1288 }
1289
1290 DRM_DEBUG_KMS("timeout waiting for transmission to complete\n");
1291 return -ETIMEDOUT;
1292 }
1293
1294 static int tegra_dsi_wait_for_response(struct tegra_dsi *dsi,
1295 unsigned long timeout)
1296 {
1297 timeout = jiffies + msecs_to_jiffies(250);
1298
1299 while (time_before(jiffies, timeout)) {
1300 u32 value = tegra_dsi_readl(dsi, DSI_STATUS);
1301 u8 count = value & 0x1f;
1302
1303 if (count > 0)
1304 return count;
1305
1306 usleep_range(1000, 2000);
1307 }
1308
1309 DRM_DEBUG_KMS("peripheral returned no data\n");
1310 return -ETIMEDOUT;
1311 }
1312
1313 static void tegra_dsi_writesl(struct tegra_dsi *dsi, unsigned long offset,
1314 const void *buffer, size_t size)
1315 {
1316 const u8 *buf = buffer;
1317 size_t i, j;
1318 u32 value;
1319
1320 for (j = 0; j < size; j += 4) {
1321 value = 0;
1322
1323 for (i = 0; i < 4 && j + i < size; i++)
1324 value |= buf[j + i] << (i << 3);
1325
1326 tegra_dsi_writel(dsi, value, DSI_WR_DATA);
1327 }
1328 }
1329
1330 static ssize_t tegra_dsi_host_transfer(struct mipi_dsi_host *host,
1331 const struct mipi_dsi_msg *msg)
1332 {
1333 struct tegra_dsi *dsi = host_to_tegra(host);
1334 struct mipi_dsi_packet packet;
1335 const u8 *header;
1336 size_t count;
1337 ssize_t err;
1338 u32 value;
1339
1340 err = mipi_dsi_create_packet(&packet, msg);
1341 if (err < 0)
1342 return err;
1343
1344 header = packet.header;
1345
1346 /* maximum FIFO depth is 1920 words */
1347 if (packet.size > dsi->video_fifo_depth * 4)
1348 return -ENOSPC;
1349
1350 /* reset underflow/overflow flags */
1351 value = tegra_dsi_readl(dsi, DSI_STATUS);
1352 if (value & (DSI_STATUS_UNDERFLOW | DSI_STATUS_OVERFLOW)) {
1353 value = DSI_HOST_CONTROL_FIFO_RESET;
1354 tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);
1355 usleep_range(10, 20);
1356 }
1357
1358 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
1359 value |= DSI_POWER_CONTROL_ENABLE;
1360 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
1361
1362 usleep_range(5000, 10000);
1363
1364 value = DSI_HOST_CONTROL_CRC_RESET | DSI_HOST_CONTROL_TX_TRIG_HOST |
1365 DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC;
1366
1367 if ((msg->flags & MIPI_DSI_MSG_USE_LPM) == 0)
1368 value |= DSI_HOST_CONTROL_HS;
1369
1370 /*
1371 * The host FIFO has a maximum of 64 words, so larger transmissions
1372 * need to use the video FIFO.
1373 */
1374 if (packet.size > dsi->host_fifo_depth * 4)
1375 value |= DSI_HOST_CONTROL_FIFO_SEL;
1376
1377 tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);
1378
1379 /*
1380 * For reads and messages with explicitly requested ACK, generate a
1381 * BTA sequence after the transmission of the packet.
1382 */
1383 if ((msg->flags & MIPI_DSI_MSG_REQ_ACK) ||
1384 (msg->rx_buf && msg->rx_len > 0)) {
1385 value = tegra_dsi_readl(dsi, DSI_HOST_CONTROL);
1386 value |= DSI_HOST_CONTROL_PKT_BTA;
1387 tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);
1388 }
1389
1390 value = DSI_CONTROL_LANES(0) | DSI_CONTROL_HOST_ENABLE;
1391 tegra_dsi_writel(dsi, value, DSI_CONTROL);
1392
1393 /* write packet header, ECC is generated by hardware */
1394 value = header[2] << 16 | header[1] << 8 | header[0];
1395 tegra_dsi_writel(dsi, value, DSI_WR_DATA);
1396
1397 /* write payload (if any) */
1398 if (packet.payload_length > 0)
1399 tegra_dsi_writesl(dsi, DSI_WR_DATA, packet.payload,
1400 packet.payload_length);
1401
1402 err = tegra_dsi_transmit(dsi, 250);
1403 if (err < 0)
1404 return err;
1405
1406 if ((msg->flags & MIPI_DSI_MSG_REQ_ACK) ||
1407 (msg->rx_buf && msg->rx_len > 0)) {
1408 err = tegra_dsi_wait_for_response(dsi, 250);
1409 if (err < 0)
1410 return err;
1411
1412 count = err;
1413
1414 value = tegra_dsi_readl(dsi, DSI_RD_DATA);
1415 switch (value) {
1416 case 0x84:
1417 /*
1418 dev_dbg(dsi->dev, "ACK\n");
1419 */
1420 break;
1421
1422 case 0x87:
1423 /*
1424 dev_dbg(dsi->dev, "ESCAPE\n");
1425 */
1426 break;
1427
1428 default:
1429 dev_err(dsi->dev, "unknown status: %08x\n", value);
1430 break;
1431 }
1432
1433 if (count > 1) {
1434 err = tegra_dsi_read_response(dsi, msg, count);
1435 if (err < 0)
1436 dev_err(dsi->dev,
1437 "failed to parse response: %zd\n",
1438 err);
1439 else {
1440 /*
1441 * For read commands, return the number of
1442 * bytes returned by the peripheral.
1443 */
1444 count = err;
1445 }
1446 }
1447 } else {
1448 /*
1449 * For write commands, we have transmitted the 4-byte header
1450 * plus the variable-length payload.
1451 */
1452 count = 4 + packet.payload_length;
1453 }
1454
1455 return count;
1456 }
1457
1458 static int tegra_dsi_ganged_setup(struct tegra_dsi *dsi)
1459 {
1460 struct clk *parent;
1461 int err;
1462
1463 /* make sure both DSI controllers share the same PLL */
1464 parent = clk_get_parent(dsi->slave->clk);
1465 if (!parent)
1466 return -EINVAL;
1467
1468 err = clk_set_parent(parent, dsi->clk_parent);
1469 if (err < 0)
1470 return err;
1471
1472 return 0;
1473 }
1474
1475 static int tegra_dsi_host_attach(struct mipi_dsi_host *host,
1476 struct mipi_dsi_device *device)
1477 {
1478 struct tegra_dsi *dsi = host_to_tegra(host);
1479
1480 dsi->flags = device->mode_flags;
1481 dsi->format = device->format;
1482 dsi->lanes = device->lanes;
1483
1484 if (dsi->slave) {
1485 int err;
1486
1487 dev_dbg(dsi->dev, "attaching dual-channel device %s\n",
1488 dev_name(&device->dev));
1489
1490 err = tegra_dsi_ganged_setup(dsi);
1491 if (err < 0) {
1492 dev_err(dsi->dev, "failed to set up ganged mode: %d\n",
1493 err);
1494 return err;
1495 }
1496 }
1497
1498 /*
1499 * Slaves don't have a panel associated with them, so they provide
1500 * merely the second channel.
1501 */
1502 if (!dsi->master) {
1503 struct tegra_output *output = &dsi->output;
1504
1505 output->panel = of_drm_find_panel(device->dev.of_node);
1506 if (IS_ERR(output->panel))
1507 output->panel = NULL;
1508
1509 if (output->panel && output->connector.dev) {
1510 drm_panel_attach(output->panel, &output->connector);
1511 drm_helper_hpd_irq_event(output->connector.dev);
1512 }
1513 }
1514
1515 return 0;
1516 }
1517
1518 static int tegra_dsi_host_detach(struct mipi_dsi_host *host,
1519 struct mipi_dsi_device *device)
1520 {
1521 struct tegra_dsi *dsi = host_to_tegra(host);
1522 struct tegra_output *output = &dsi->output;
1523
1524 if (output->panel && &device->dev == output->panel->dev) {
1525 output->panel = NULL;
1526
1527 if (output->connector.dev)
1528 drm_helper_hpd_irq_event(output->connector.dev);
1529 }
1530
1531 return 0;
1532 }
1533
1534 static const struct mipi_dsi_host_ops tegra_dsi_host_ops = {
1535 .attach = tegra_dsi_host_attach,
1536 .detach = tegra_dsi_host_detach,
1537 .transfer = tegra_dsi_host_transfer,
1538 };
1539
1540 static int tegra_dsi_ganged_probe(struct tegra_dsi *dsi)
1541 {
1542 struct device_node *np;
1543
1544 np = of_parse_phandle(dsi->dev->of_node, "nvidia,ganged-mode", 0);
1545 if (np) {
1546 struct platform_device *gangster = of_find_device_by_node(np);
1547
1548 dsi->slave = platform_get_drvdata(gangster);
1549 of_node_put(np);
1550
1551 if (!dsi->slave)
1552 return -EPROBE_DEFER;
1553
1554 dsi->slave->master = dsi;
1555 }
1556
1557 return 0;
1558 }
1559
1560 static int tegra_dsi_probe(struct platform_device *pdev)
1561 {
1562 struct tegra_dsi *dsi;
1563 struct resource *regs;
1564 int err;
1565
1566 dsi = devm_kzalloc(&pdev->dev, sizeof(*dsi), GFP_KERNEL);
1567 if (!dsi)
1568 return -ENOMEM;
1569
1570 dsi->output.dev = dsi->dev = &pdev->dev;
1571 dsi->video_fifo_depth = 1920;
1572 dsi->host_fifo_depth = 64;
1573
1574 err = tegra_dsi_ganged_probe(dsi);
1575 if (err < 0)
1576 return err;
1577
1578 err = tegra_output_probe(&dsi->output);
1579 if (err < 0)
1580 return err;
1581
1582 dsi->output.connector.polled = DRM_CONNECTOR_POLL_HPD;
1583
1584 /*
1585 * Assume these values by default. When a DSI peripheral driver
1586 * attaches to the DSI host, the parameters will be taken from
1587 * the attached device.
1588 */
1589 dsi->flags = MIPI_DSI_MODE_VIDEO;
1590 dsi->format = MIPI_DSI_FMT_RGB888;
1591 dsi->lanes = 4;
1592
1593 if (!pdev->dev.pm_domain) {
1594 dsi->rst = devm_reset_control_get(&pdev->dev, "dsi");
1595 if (IS_ERR(dsi->rst))
1596 return PTR_ERR(dsi->rst);
1597 }
1598
1599 dsi->clk = devm_clk_get(&pdev->dev, NULL);
1600 if (IS_ERR(dsi->clk)) {
1601 dev_err(&pdev->dev, "cannot get DSI clock\n");
1602 return PTR_ERR(dsi->clk);
1603 }
1604
1605 dsi->clk_lp = devm_clk_get(&pdev->dev, "lp");
1606 if (IS_ERR(dsi->clk_lp)) {
1607 dev_err(&pdev->dev, "cannot get low-power clock\n");
1608 return PTR_ERR(dsi->clk_lp);
1609 }
1610
1611 dsi->clk_parent = devm_clk_get(&pdev->dev, "parent");
1612 if (IS_ERR(dsi->clk_parent)) {
1613 dev_err(&pdev->dev, "cannot get parent clock\n");
1614 return PTR_ERR(dsi->clk_parent);
1615 }
1616
1617 dsi->vdd = devm_regulator_get(&pdev->dev, "avdd-dsi-csi");
1618 if (IS_ERR(dsi->vdd)) {
1619 dev_err(&pdev->dev, "cannot get VDD supply\n");
1620 return PTR_ERR(dsi->vdd);
1621 }
1622
1623 err = tegra_dsi_setup_clocks(dsi);
1624 if (err < 0) {
1625 dev_err(&pdev->dev, "cannot setup clocks\n");
1626 return err;
1627 }
1628
1629 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1630 dsi->regs = devm_ioremap_resource(&pdev->dev, regs);
1631 if (IS_ERR(dsi->regs))
1632 return PTR_ERR(dsi->regs);
1633
1634 dsi->mipi = tegra_mipi_request(&pdev->dev);
1635 if (IS_ERR(dsi->mipi))
1636 return PTR_ERR(dsi->mipi);
1637
1638 dsi->host.ops = &tegra_dsi_host_ops;
1639 dsi->host.dev = &pdev->dev;
1640
1641 err = mipi_dsi_host_register(&dsi->host);
1642 if (err < 0) {
1643 dev_err(&pdev->dev, "failed to register DSI host: %d\n", err);
1644 goto mipi_free;
1645 }
1646
1647 platform_set_drvdata(pdev, dsi);
1648 pm_runtime_enable(&pdev->dev);
1649
1650 INIT_LIST_HEAD(&dsi->client.list);
1651 dsi->client.ops = &dsi_client_ops;
1652 dsi->client.dev = &pdev->dev;
1653
1654 err = host1x_client_register(&dsi->client);
1655 if (err < 0) {
1656 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
1657 err);
1658 goto unregister;
1659 }
1660
1661 return 0;
1662
1663 unregister:
1664 mipi_dsi_host_unregister(&dsi->host);
1665 mipi_free:
1666 tegra_mipi_free(dsi->mipi);
1667 return err;
1668 }
1669
1670 static int tegra_dsi_remove(struct platform_device *pdev)
1671 {
1672 struct tegra_dsi *dsi = platform_get_drvdata(pdev);
1673 int err;
1674
1675 pm_runtime_disable(&pdev->dev);
1676
1677 err = host1x_client_unregister(&dsi->client);
1678 if (err < 0) {
1679 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
1680 err);
1681 return err;
1682 }
1683
1684 tegra_output_remove(&dsi->output);
1685
1686 mipi_dsi_host_unregister(&dsi->host);
1687 tegra_mipi_free(dsi->mipi);
1688
1689 return 0;
1690 }
1691
1692 static const struct of_device_id tegra_dsi_of_match[] = {
1693 { .compatible = "nvidia,tegra210-dsi", },
1694 { .compatible = "nvidia,tegra132-dsi", },
1695 { .compatible = "nvidia,tegra124-dsi", },
1696 { .compatible = "nvidia,tegra114-dsi", },
1697 { },
1698 };
1699 MODULE_DEVICE_TABLE(of, tegra_dsi_of_match);
1700
1701 struct platform_driver tegra_dsi_driver = {
1702 .driver = {
1703 .name = "tegra-dsi",
1704 .of_match_table = tegra_dsi_of_match,
1705 },
1706 .probe = tegra_dsi_probe,
1707 .remove = tegra_dsi_remove,
1708 };
Linux with added FPC-III support