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treewide: remove redundant IS_ERR() before error code check
[linux/fpc-iii.git] / drivers / gpu / ipu-v3 / ipu-common.c
blobee2a025e54cfea007c55c304ae90dba22062e373
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Copyright (c) 2010 Sascha Hauer <s.hauer@pengutronix.de>
4 * Copyright (C) 2005-2009 Freescale Semiconductor, Inc.
5 */
6 #include <linux/module.h>
7 #include <linux/export.h>
8 #include <linux/types.h>
9 #include <linux/reset.h>
10 #include <linux/platform_device.h>
11 #include <linux/err.h>
12 #include <linux/spinlock.h>
13 #include <linux/delay.h>
14 #include <linux/interrupt.h>
15 #include <linux/io.h>
16 #include <linux/clk.h>
17 #include <linux/list.h>
18 #include <linux/irq.h>
19 #include <linux/irqchip/chained_irq.h>
20 #include <linux/irqdomain.h>
21 #include <linux/of_device.h>
22 #include <linux/of_graph.h>
23
24 #include <drm/drm_fourcc.h>
25
26 #include <video/imx-ipu-v3.h>
27 #include "ipu-prv.h"
28
29 static inline u32 ipu_cm_read(struct ipu_soc *ipu, unsigned offset)
30 {
31 return readl(ipu->cm_reg + offset);
32 }
33
34 static inline void ipu_cm_write(struct ipu_soc *ipu, u32 value, unsigned offset)
35 {
36 writel(value, ipu->cm_reg + offset);
37 }
38
39 int ipu_get_num(struct ipu_soc *ipu)
40 {
41 return ipu->id;
42 }
43 EXPORT_SYMBOL_GPL(ipu_get_num);
44
45 void ipu_srm_dp_update(struct ipu_soc *ipu, bool sync)
46 {
47 u32 val;
48
49 val = ipu_cm_read(ipu, IPU_SRM_PRI2);
50 val &= ~DP_S_SRM_MODE_MASK;
51 val |= sync ? DP_S_SRM_MODE_NEXT_FRAME :
52 DP_S_SRM_MODE_NOW;
53 ipu_cm_write(ipu, val, IPU_SRM_PRI2);
54 }
55 EXPORT_SYMBOL_GPL(ipu_srm_dp_update);
56
57 enum ipu_color_space ipu_drm_fourcc_to_colorspace(u32 drm_fourcc)
58 {
59 switch (drm_fourcc) {
60 case DRM_FORMAT_ARGB1555:
61 case DRM_FORMAT_ABGR1555:
62 case DRM_FORMAT_RGBA5551:
63 case DRM_FORMAT_BGRA5551:
64 case DRM_FORMAT_RGB565:
65 case DRM_FORMAT_BGR565:
66 case DRM_FORMAT_RGB888:
67 case DRM_FORMAT_BGR888:
68 case DRM_FORMAT_ARGB4444:
69 case DRM_FORMAT_XRGB8888:
70 case DRM_FORMAT_XBGR8888:
71 case DRM_FORMAT_RGBX8888:
72 case DRM_FORMAT_BGRX8888:
73 case DRM_FORMAT_ARGB8888:
74 case DRM_FORMAT_ABGR8888:
75 case DRM_FORMAT_RGBA8888:
76 case DRM_FORMAT_BGRA8888:
77 case DRM_FORMAT_RGB565_A8:
78 case DRM_FORMAT_BGR565_A8:
79 case DRM_FORMAT_RGB888_A8:
80 case DRM_FORMAT_BGR888_A8:
81 case DRM_FORMAT_RGBX8888_A8:
82 case DRM_FORMAT_BGRX8888_A8:
83 return IPUV3_COLORSPACE_RGB;
84 case DRM_FORMAT_YUYV:
85 case DRM_FORMAT_UYVY:
86 case DRM_FORMAT_YUV420:
87 case DRM_FORMAT_YVU420:
88 case DRM_FORMAT_YUV422:
89 case DRM_FORMAT_YVU422:
90 case DRM_FORMAT_YUV444:
91 case DRM_FORMAT_YVU444:
92 case DRM_FORMAT_NV12:
93 case DRM_FORMAT_NV21:
94 case DRM_FORMAT_NV16:
95 case DRM_FORMAT_NV61:
96 return IPUV3_COLORSPACE_YUV;
97 default:
98 return IPUV3_COLORSPACE_UNKNOWN;
99 }
100 }
101 EXPORT_SYMBOL_GPL(ipu_drm_fourcc_to_colorspace);
102
103 enum ipu_color_space ipu_pixelformat_to_colorspace(u32 pixelformat)
104 {
105 switch (pixelformat) {
106 case V4L2_PIX_FMT_YUV420:
107 case V4L2_PIX_FMT_YVU420:
108 case V4L2_PIX_FMT_YUV422P:
109 case V4L2_PIX_FMT_UYVY:
110 case V4L2_PIX_FMT_YUYV:
111 case V4L2_PIX_FMT_NV12:
112 case V4L2_PIX_FMT_NV21:
113 case V4L2_PIX_FMT_NV16:
114 case V4L2_PIX_FMT_NV61:
115 return IPUV3_COLORSPACE_YUV;
116 case V4L2_PIX_FMT_RGB565:
117 case V4L2_PIX_FMT_BGR24:
118 case V4L2_PIX_FMT_RGB24:
119 case V4L2_PIX_FMT_ABGR32:
120 case V4L2_PIX_FMT_XBGR32:
121 case V4L2_PIX_FMT_BGRA32:
122 case V4L2_PIX_FMT_BGRX32:
123 case V4L2_PIX_FMT_RGBA32:
124 case V4L2_PIX_FMT_RGBX32:
125 case V4L2_PIX_FMT_ARGB32:
126 case V4L2_PIX_FMT_XRGB32:
127 return IPUV3_COLORSPACE_RGB;
128 default:
129 return IPUV3_COLORSPACE_UNKNOWN;
130 }
131 }
132 EXPORT_SYMBOL_GPL(ipu_pixelformat_to_colorspace);
133
134 bool ipu_pixelformat_is_planar(u32 pixelformat)
135 {
136 switch (pixelformat) {
137 case V4L2_PIX_FMT_YUV420:
138 case V4L2_PIX_FMT_YVU420:
139 case V4L2_PIX_FMT_YUV422P:
140 case V4L2_PIX_FMT_NV12:
141 case V4L2_PIX_FMT_NV21:
142 case V4L2_PIX_FMT_NV16:
143 case V4L2_PIX_FMT_NV61:
144 return true;
145 }
146
147 return false;
148 }
149 EXPORT_SYMBOL_GPL(ipu_pixelformat_is_planar);
150
151 enum ipu_color_space ipu_mbus_code_to_colorspace(u32 mbus_code)
152 {
153 switch (mbus_code & 0xf000) {
154 case 0x1000:
155 return IPUV3_COLORSPACE_RGB;
156 case 0x2000:
157 return IPUV3_COLORSPACE_YUV;
158 default:
159 return IPUV3_COLORSPACE_UNKNOWN;
160 }
161 }
162 EXPORT_SYMBOL_GPL(ipu_mbus_code_to_colorspace);
163
164 int ipu_stride_to_bytes(u32 pixel_stride, u32 pixelformat)
165 {
166 switch (pixelformat) {
167 case V4L2_PIX_FMT_YUV420:
168 case V4L2_PIX_FMT_YVU420:
169 case V4L2_PIX_FMT_YUV422P:
170 case V4L2_PIX_FMT_NV12:
171 case V4L2_PIX_FMT_NV21:
172 case V4L2_PIX_FMT_NV16:
173 case V4L2_PIX_FMT_NV61:
174 /*
175 * for the planar YUV formats, the stride passed to
176 * cpmem must be the stride in bytes of the Y plane.
177 * And all the planar YUV formats have an 8-bit
178 * Y component.
179 */
180 return (8 * pixel_stride) >> 3;
181 case V4L2_PIX_FMT_RGB565:
182 case V4L2_PIX_FMT_YUYV:
183 case V4L2_PIX_FMT_UYVY:
184 return (16 * pixel_stride) >> 3;
185 case V4L2_PIX_FMT_BGR24:
186 case V4L2_PIX_FMT_RGB24:
187 return (24 * pixel_stride) >> 3;
188 case V4L2_PIX_FMT_BGR32:
189 case V4L2_PIX_FMT_RGB32:
190 case V4L2_PIX_FMT_XBGR32:
191 case V4L2_PIX_FMT_XRGB32:
192 return (32 * pixel_stride) >> 3;
193 default:
194 break;
195 }
196
197 return -EINVAL;
198 }
199 EXPORT_SYMBOL_GPL(ipu_stride_to_bytes);
200
201 int ipu_degrees_to_rot_mode(enum ipu_rotate_mode *mode, int degrees,
202 bool hflip, bool vflip)
203 {
204 u32 r90, vf, hf;
205
206 switch (degrees) {
207 case 0:
208 vf = hf = r90 = 0;
209 break;
210 case 90:
211 vf = hf = 0;
212 r90 = 1;
213 break;
214 case 180:
215 vf = hf = 1;
216 r90 = 0;
217 break;
218 case 270:
219 vf = hf = r90 = 1;
220 break;
221 default:
222 return -EINVAL;
223 }
224
225 hf ^= (u32)hflip;
226 vf ^= (u32)vflip;
227
228 *mode = (enum ipu_rotate_mode)((r90 << 2) | (hf << 1) | vf);
229 return 0;
230 }
231 EXPORT_SYMBOL_GPL(ipu_degrees_to_rot_mode);
232
233 int ipu_rot_mode_to_degrees(int *degrees, enum ipu_rotate_mode mode,
234 bool hflip, bool vflip)
235 {
236 u32 r90, vf, hf;
237
238 r90 = ((u32)mode >> 2) & 0x1;
239 hf = ((u32)mode >> 1) & 0x1;
240 vf = ((u32)mode >> 0) & 0x1;
241 hf ^= (u32)hflip;
242 vf ^= (u32)vflip;
243
244 switch ((enum ipu_rotate_mode)((r90 << 2) | (hf << 1) | vf)) {
245 case IPU_ROTATE_NONE:
246 *degrees = 0;
247 break;
248 case IPU_ROTATE_90_RIGHT:
249 *degrees = 90;
250 break;
251 case IPU_ROTATE_180:
252 *degrees = 180;
253 break;
254 case IPU_ROTATE_90_LEFT:
255 *degrees = 270;
256 break;
257 default:
258 return -EINVAL;
259 }
260
261 return 0;
262 }
263 EXPORT_SYMBOL_GPL(ipu_rot_mode_to_degrees);
264
265 struct ipuv3_channel *ipu_idmac_get(struct ipu_soc *ipu, unsigned num)
266 {
267 struct ipuv3_channel *channel;
268
269 dev_dbg(ipu->dev, "%s %d\n", __func__, num);
270
271 if (num > 63)
272 return ERR_PTR(-ENODEV);
273
274 mutex_lock(&ipu->channel_lock);
275
276 list_for_each_entry(channel, &ipu->channels, list) {
277 if (channel->num == num) {
278 channel = ERR_PTR(-EBUSY);
279 goto out;
280 }
281 }
282
283 channel = kzalloc(sizeof(*channel), GFP_KERNEL);
284 if (!channel) {
285 channel = ERR_PTR(-ENOMEM);
286 goto out;
287 }
288
289 channel->num = num;
290 channel->ipu = ipu;
291 list_add(&channel->list, &ipu->channels);
292
293 out:
294 mutex_unlock(&ipu->channel_lock);
295
296 return channel;
297 }
298 EXPORT_SYMBOL_GPL(ipu_idmac_get);
299
300 void ipu_idmac_put(struct ipuv3_channel *channel)
301 {
302 struct ipu_soc *ipu = channel->ipu;
303
304 dev_dbg(ipu->dev, "%s %d\n", __func__, channel->num);
305
306 mutex_lock(&ipu->channel_lock);
307
308 list_del(&channel->list);
309 kfree(channel);
310
311 mutex_unlock(&ipu->channel_lock);
312 }
313 EXPORT_SYMBOL_GPL(ipu_idmac_put);
314
315 #define idma_mask(ch) (1 << ((ch) & 0x1f))
316
317 /*
318 * This is an undocumented feature, a write one to a channel bit in
319 * IPU_CHA_CUR_BUF and IPU_CHA_TRIPLE_CUR_BUF will reset the channel's
320 * internal current buffer pointer so that transfers start from buffer
321 * 0 on the next channel enable (that's the theory anyway, the imx6 TRM
322 * only says these are read-only registers). This operation is required
323 * for channel linking to work correctly, for instance video capture
324 * pipelines that carry out image rotations will fail after the first
325 * streaming unless this function is called for each channel before
326 * re-enabling the channels.
327 */
328 static void __ipu_idmac_reset_current_buffer(struct ipuv3_channel *channel)
329 {
330 struct ipu_soc *ipu = channel->ipu;
331 unsigned int chno = channel->num;
332
333 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_CUR_BUF(chno));
334 }
335
336 void ipu_idmac_set_double_buffer(struct ipuv3_channel *channel,
337 bool doublebuffer)
338 {
339 struct ipu_soc *ipu = channel->ipu;
340 unsigned long flags;
341 u32 reg;
342
343 spin_lock_irqsave(&ipu->lock, flags);
344
345 reg = ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(channel->num));
346 if (doublebuffer)
347 reg |= idma_mask(channel->num);
348 else
349 reg &= ~idma_mask(channel->num);
350 ipu_cm_write(ipu, reg, IPU_CHA_DB_MODE_SEL(channel->num));
351
352 __ipu_idmac_reset_current_buffer(channel);
353
354 spin_unlock_irqrestore(&ipu->lock, flags);
355 }
356 EXPORT_SYMBOL_GPL(ipu_idmac_set_double_buffer);
357
358 static const struct {
359 int chnum;
360 u32 reg;
361 int shift;
362 } idmac_lock_en_info[] = {
363 { .chnum = 5, .reg = IDMAC_CH_LOCK_EN_1, .shift = 0, },
364 { .chnum = 11, .reg = IDMAC_CH_LOCK_EN_1, .shift = 2, },
365 { .chnum = 12, .reg = IDMAC_CH_LOCK_EN_1, .shift = 4, },
366 { .chnum = 14, .reg = IDMAC_CH_LOCK_EN_1, .shift = 6, },
367 { .chnum = 15, .reg = IDMAC_CH_LOCK_EN_1, .shift = 8, },
368 { .chnum = 20, .reg = IDMAC_CH_LOCK_EN_1, .shift = 10, },
369 { .chnum = 21, .reg = IDMAC_CH_LOCK_EN_1, .shift = 12, },
370 { .chnum = 22, .reg = IDMAC_CH_LOCK_EN_1, .shift = 14, },
371 { .chnum = 23, .reg = IDMAC_CH_LOCK_EN_1, .shift = 16, },
372 { .chnum = 27, .reg = IDMAC_CH_LOCK_EN_1, .shift = 18, },
373 { .chnum = 28, .reg = IDMAC_CH_LOCK_EN_1, .shift = 20, },
374 { .chnum = 45, .reg = IDMAC_CH_LOCK_EN_2, .shift = 0, },
375 { .chnum = 46, .reg = IDMAC_CH_LOCK_EN_2, .shift = 2, },
376 { .chnum = 47, .reg = IDMAC_CH_LOCK_EN_2, .shift = 4, },
377 { .chnum = 48, .reg = IDMAC_CH_LOCK_EN_2, .shift = 6, },
378 { .chnum = 49, .reg = IDMAC_CH_LOCK_EN_2, .shift = 8, },
379 { .chnum = 50, .reg = IDMAC_CH_LOCK_EN_2, .shift = 10, },
380 };
381
382 int ipu_idmac_lock_enable(struct ipuv3_channel *channel, int num_bursts)
383 {
384 struct ipu_soc *ipu = channel->ipu;
385 unsigned long flags;
386 u32 bursts, regval;
387 int i;
388
389 switch (num_bursts) {
390 case 0:
391 case 1:
392 bursts = 0x00; /* locking disabled */
393 break;
394 case 2:
395 bursts = 0x01;
396 break;
397 case 4:
398 bursts = 0x02;
399 break;
400 case 8:
401 bursts = 0x03;
402 break;
403 default:
404 return -EINVAL;
405 }
406
407 /*
408 * IPUv3EX / i.MX51 has a different register layout, and on IPUv3M /
409 * i.MX53 channel arbitration locking doesn't seem to work properly.
410 * Allow enabling the lock feature on IPUv3H / i.MX6 only.
411 */
412 if (bursts && ipu->ipu_type != IPUV3H)
413 return -EINVAL;
414
415 for (i = 0; i < ARRAY_SIZE(idmac_lock_en_info); i++) {
416 if (channel->num == idmac_lock_en_info[i].chnum)
417 break;
418 }
419 if (i >= ARRAY_SIZE(idmac_lock_en_info))
420 return -EINVAL;
421
422 spin_lock_irqsave(&ipu->lock, flags);
423
424 regval = ipu_idmac_read(ipu, idmac_lock_en_info[i].reg);
425 regval &= ~(0x03 << idmac_lock_en_info[i].shift);
426 regval |= (bursts << idmac_lock_en_info[i].shift);
427 ipu_idmac_write(ipu, regval, idmac_lock_en_info[i].reg);
428
429 spin_unlock_irqrestore(&ipu->lock, flags);
430
431 return 0;
432 }
433 EXPORT_SYMBOL_GPL(ipu_idmac_lock_enable);
434
435 int ipu_module_enable(struct ipu_soc *ipu, u32 mask)
436 {
437 unsigned long lock_flags;
438 u32 val;
439
440 spin_lock_irqsave(&ipu->lock, lock_flags);
441
442 val = ipu_cm_read(ipu, IPU_DISP_GEN);
443
444 if (mask & IPU_CONF_DI0_EN)
445 val |= IPU_DI0_COUNTER_RELEASE;
446 if (mask & IPU_CONF_DI1_EN)
447 val |= IPU_DI1_COUNTER_RELEASE;
448
449 ipu_cm_write(ipu, val, IPU_DISP_GEN);
450
451 val = ipu_cm_read(ipu, IPU_CONF);
452 val |= mask;
453 ipu_cm_write(ipu, val, IPU_CONF);
454
455 spin_unlock_irqrestore(&ipu->lock, lock_flags);
456
457 return 0;
458 }
459 EXPORT_SYMBOL_GPL(ipu_module_enable);
460
461 int ipu_module_disable(struct ipu_soc *ipu, u32 mask)
462 {
463 unsigned long lock_flags;
464 u32 val;
465
466 spin_lock_irqsave(&ipu->lock, lock_flags);
467
468 val = ipu_cm_read(ipu, IPU_CONF);
469 val &= ~mask;
470 ipu_cm_write(ipu, val, IPU_CONF);
471
472 val = ipu_cm_read(ipu, IPU_DISP_GEN);
473
474 if (mask & IPU_CONF_DI0_EN)
475 val &= ~IPU_DI0_COUNTER_RELEASE;
476 if (mask & IPU_CONF_DI1_EN)
477 val &= ~IPU_DI1_COUNTER_RELEASE;
478
479 ipu_cm_write(ipu, val, IPU_DISP_GEN);
480
481 spin_unlock_irqrestore(&ipu->lock, lock_flags);
482
483 return 0;
484 }
485 EXPORT_SYMBOL_GPL(ipu_module_disable);
486
487 int ipu_idmac_get_current_buffer(struct ipuv3_channel *channel)
488 {
489 struct ipu_soc *ipu = channel->ipu;
490 unsigned int chno = channel->num;
491
492 return (ipu_cm_read(ipu, IPU_CHA_CUR_BUF(chno)) & idma_mask(chno)) ? 1 : 0;
493 }
494 EXPORT_SYMBOL_GPL(ipu_idmac_get_current_buffer);
495
496 bool ipu_idmac_buffer_is_ready(struct ipuv3_channel *channel, u32 buf_num)
497 {
498 struct ipu_soc *ipu = channel->ipu;
499 unsigned long flags;
500 u32 reg = 0;
501
502 spin_lock_irqsave(&ipu->lock, flags);
503 switch (buf_num) {
504 case 0:
505 reg = ipu_cm_read(ipu, IPU_CHA_BUF0_RDY(channel->num));
506 break;
507 case 1:
508 reg = ipu_cm_read(ipu, IPU_CHA_BUF1_RDY(channel->num));
509 break;
510 case 2:
511 reg = ipu_cm_read(ipu, IPU_CHA_BUF2_RDY(channel->num));
512 break;
513 }
514 spin_unlock_irqrestore(&ipu->lock, flags);
515
516 return ((reg & idma_mask(channel->num)) != 0);
517 }
518 EXPORT_SYMBOL_GPL(ipu_idmac_buffer_is_ready);
519
520 void ipu_idmac_select_buffer(struct ipuv3_channel *channel, u32 buf_num)
521 {
522 struct ipu_soc *ipu = channel->ipu;
523 unsigned int chno = channel->num;
524 unsigned long flags;
525
526 spin_lock_irqsave(&ipu->lock, flags);
527
528 /* Mark buffer as ready. */
529 if (buf_num == 0)
530 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF0_RDY(chno));
531 else
532 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF1_RDY(chno));
533
534 spin_unlock_irqrestore(&ipu->lock, flags);
535 }
536 EXPORT_SYMBOL_GPL(ipu_idmac_select_buffer);
537
538 void ipu_idmac_clear_buffer(struct ipuv3_channel *channel, u32 buf_num)
539 {
540 struct ipu_soc *ipu = channel->ipu;
541 unsigned int chno = channel->num;
542 unsigned long flags;
543
544 spin_lock_irqsave(&ipu->lock, flags);
545
546 ipu_cm_write(ipu, 0xF0300000, IPU_GPR); /* write one to clear */
547 switch (buf_num) {
548 case 0:
549 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF0_RDY(chno));
550 break;
551 case 1:
552 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF1_RDY(chno));
553 break;
554 case 2:
555 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF2_RDY(chno));
556 break;
557 default:
558 break;
559 }
560 ipu_cm_write(ipu, 0x0, IPU_GPR); /* write one to set */
561
562 spin_unlock_irqrestore(&ipu->lock, flags);
563 }
564 EXPORT_SYMBOL_GPL(ipu_idmac_clear_buffer);
565
566 int ipu_idmac_enable_channel(struct ipuv3_channel *channel)
567 {
568 struct ipu_soc *ipu = channel->ipu;
569 u32 val;
570 unsigned long flags;
571
572 spin_lock_irqsave(&ipu->lock, flags);
573
574 val = ipu_idmac_read(ipu, IDMAC_CHA_EN(channel->num));
575 val |= idma_mask(channel->num);
576 ipu_idmac_write(ipu, val, IDMAC_CHA_EN(channel->num));
577
578 spin_unlock_irqrestore(&ipu->lock, flags);
579
580 return 0;
581 }
582 EXPORT_SYMBOL_GPL(ipu_idmac_enable_channel);
583
584 bool ipu_idmac_channel_busy(struct ipu_soc *ipu, unsigned int chno)
585 {
586 return (ipu_idmac_read(ipu, IDMAC_CHA_BUSY(chno)) & idma_mask(chno));
587 }
588 EXPORT_SYMBOL_GPL(ipu_idmac_channel_busy);
589
590 int ipu_idmac_wait_busy(struct ipuv3_channel *channel, int ms)
591 {
592 struct ipu_soc *ipu = channel->ipu;
593 unsigned long timeout;
594
595 timeout = jiffies + msecs_to_jiffies(ms);
596 while (ipu_idmac_read(ipu, IDMAC_CHA_BUSY(channel->num)) &
597 idma_mask(channel->num)) {
598 if (time_after(jiffies, timeout))
599 return -ETIMEDOUT;
600 cpu_relax();
601 }
602
603 return 0;
604 }
605 EXPORT_SYMBOL_GPL(ipu_idmac_wait_busy);
606
607 int ipu_idmac_disable_channel(struct ipuv3_channel *channel)
608 {
609 struct ipu_soc *ipu = channel->ipu;
610 u32 val;
611 unsigned long flags;
612
613 spin_lock_irqsave(&ipu->lock, flags);
614
615 /* Disable DMA channel(s) */
616 val = ipu_idmac_read(ipu, IDMAC_CHA_EN(channel->num));
617 val &= ~idma_mask(channel->num);
618 ipu_idmac_write(ipu, val, IDMAC_CHA_EN(channel->num));
619
620 __ipu_idmac_reset_current_buffer(channel);
621
622 /* Set channel buffers NOT to be ready */
623 ipu_cm_write(ipu, 0xf0000000, IPU_GPR); /* write one to clear */
624
625 if (ipu_cm_read(ipu, IPU_CHA_BUF0_RDY(channel->num)) &
626 idma_mask(channel->num)) {
627 ipu_cm_write(ipu, idma_mask(channel->num),
628 IPU_CHA_BUF0_RDY(channel->num));
629 }
630
631 if (ipu_cm_read(ipu, IPU_CHA_BUF1_RDY(channel->num)) &
632 idma_mask(channel->num)) {
633 ipu_cm_write(ipu, idma_mask(channel->num),
634 IPU_CHA_BUF1_RDY(channel->num));
635 }
636
637 ipu_cm_write(ipu, 0x0, IPU_GPR); /* write one to set */
638
639 /* Reset the double buffer */
640 val = ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(channel->num));
641 val &= ~idma_mask(channel->num);
642 ipu_cm_write(ipu, val, IPU_CHA_DB_MODE_SEL(channel->num));
643
644 spin_unlock_irqrestore(&ipu->lock, flags);
645
646 return 0;
647 }
648 EXPORT_SYMBOL_GPL(ipu_idmac_disable_channel);
649
650 /*
651 * The imx6 rev. D TRM says that enabling the WM feature will increase
652 * a channel's priority. Refer to Table 36-8 Calculated priority value.
653 * The sub-module that is the sink or source for the channel must enable
654 * watermark signal for this to take effect (SMFC_WM for instance).
655 */
656 void ipu_idmac_enable_watermark(struct ipuv3_channel *channel, bool enable)
657 {
658 struct ipu_soc *ipu = channel->ipu;
659 unsigned long flags;
660 u32 val;
661
662 spin_lock_irqsave(&ipu->lock, flags);
663
664 val = ipu_idmac_read(ipu, IDMAC_WM_EN(channel->num));
665 if (enable)
666 val |= 1 << (channel->num % 32);
667 else
668 val &= ~(1 << (channel->num % 32));
669 ipu_idmac_write(ipu, val, IDMAC_WM_EN(channel->num));
670
671 spin_unlock_irqrestore(&ipu->lock, flags);
672 }
673 EXPORT_SYMBOL_GPL(ipu_idmac_enable_watermark);
674
675 static int ipu_memory_reset(struct ipu_soc *ipu)
676 {
677 unsigned long timeout;
678
679 ipu_cm_write(ipu, 0x807FFFFF, IPU_MEM_RST);
680
681 timeout = jiffies + msecs_to_jiffies(1000);
682 while (ipu_cm_read(ipu, IPU_MEM_RST) & 0x80000000) {
683 if (time_after(jiffies, timeout))
684 return -ETIME;
685 cpu_relax();
686 }
687
688 return 0;
689 }
690
691 /*
692 * Set the source mux for the given CSI. Selects either parallel or
693 * MIPI CSI2 sources.
694 */
695 void ipu_set_csi_src_mux(struct ipu_soc *ipu, int csi_id, bool mipi_csi2)
696 {
697 unsigned long flags;
698 u32 val, mask;
699
700 mask = (csi_id == 1) ? IPU_CONF_CSI1_DATA_SOURCE :
701 IPU_CONF_CSI0_DATA_SOURCE;
702
703 spin_lock_irqsave(&ipu->lock, flags);
704
705 val = ipu_cm_read(ipu, IPU_CONF);
706 if (mipi_csi2)
707 val |= mask;
708 else
709 val &= ~mask;
710 ipu_cm_write(ipu, val, IPU_CONF);
711
712 spin_unlock_irqrestore(&ipu->lock, flags);
713 }
714 EXPORT_SYMBOL_GPL(ipu_set_csi_src_mux);
715
716 /*
717 * Set the source mux for the IC. Selects either CSI[01] or the VDI.
718 */
719 void ipu_set_ic_src_mux(struct ipu_soc *ipu, int csi_id, bool vdi)
720 {
721 unsigned long flags;
722 u32 val;
723
724 spin_lock_irqsave(&ipu->lock, flags);
725
726 val = ipu_cm_read(ipu, IPU_CONF);
727 if (vdi)
728 val |= IPU_CONF_IC_INPUT;
729 else
730 val &= ~IPU_CONF_IC_INPUT;
731
732 if (csi_id == 1)
733 val |= IPU_CONF_CSI_SEL;
734 else
735 val &= ~IPU_CONF_CSI_SEL;
736
737 ipu_cm_write(ipu, val, IPU_CONF);
738
739 spin_unlock_irqrestore(&ipu->lock, flags);
740 }
741 EXPORT_SYMBOL_GPL(ipu_set_ic_src_mux);
742
743
744 /* Frame Synchronization Unit Channel Linking */
745
746 struct fsu_link_reg_info {
747 int chno;
748 u32 reg;
749 u32 mask;
750 u32 val;
751 };
752
753 struct fsu_link_info {
754 struct fsu_link_reg_info src;
755 struct fsu_link_reg_info sink;
756 };
757
758 static const struct fsu_link_info fsu_link_info[] = {
759 {
760 .src = { IPUV3_CHANNEL_IC_PRP_ENC_MEM, IPU_FS_PROC_FLOW2,
761 FS_PRP_ENC_DEST_SEL_MASK, FS_PRP_ENC_DEST_SEL_IRT_ENC },
762 .sink = { IPUV3_CHANNEL_MEM_ROT_ENC, IPU_FS_PROC_FLOW1,
763 FS_PRPENC_ROT_SRC_SEL_MASK, FS_PRPENC_ROT_SRC_SEL_ENC },
764 }, {
765 .src = { IPUV3_CHANNEL_IC_PRP_VF_MEM, IPU_FS_PROC_FLOW2,
766 FS_PRPVF_DEST_SEL_MASK, FS_PRPVF_DEST_SEL_IRT_VF },
767 .sink = { IPUV3_CHANNEL_MEM_ROT_VF, IPU_FS_PROC_FLOW1,
768 FS_PRPVF_ROT_SRC_SEL_MASK, FS_PRPVF_ROT_SRC_SEL_VF },
769 }, {
770 .src = { IPUV3_CHANNEL_IC_PP_MEM, IPU_FS_PROC_FLOW2,
771 FS_PP_DEST_SEL_MASK, FS_PP_DEST_SEL_IRT_PP },
772 .sink = { IPUV3_CHANNEL_MEM_ROT_PP, IPU_FS_PROC_FLOW1,
773 FS_PP_ROT_SRC_SEL_MASK, FS_PP_ROT_SRC_SEL_PP },
774 }, {
775 .src = { IPUV3_CHANNEL_CSI_DIRECT, 0 },
776 .sink = { IPUV3_CHANNEL_CSI_VDI_PREV, IPU_FS_PROC_FLOW1,
777 FS_VDI_SRC_SEL_MASK, FS_VDI_SRC_SEL_CSI_DIRECT },
778 },
779 };
780
781 static const struct fsu_link_info *find_fsu_link_info(int src, int sink)
782 {
783 int i;
784
785 for (i = 0; i < ARRAY_SIZE(fsu_link_info); i++) {
786 if (src == fsu_link_info[i].src.chno &&
787 sink == fsu_link_info[i].sink.chno)
788 return &fsu_link_info[i];
789 }
790
791 return NULL;
792 }
793
794 /*
795 * Links a source channel to a sink channel in the FSU.
796 */
797 int ipu_fsu_link(struct ipu_soc *ipu, int src_ch, int sink_ch)
798 {
799 const struct fsu_link_info *link;
800 u32 src_reg, sink_reg;
801 unsigned long flags;
802
803 link = find_fsu_link_info(src_ch, sink_ch);
804 if (!link)
805 return -EINVAL;
806
807 spin_lock_irqsave(&ipu->lock, flags);
808
809 if (link->src.mask) {
810 src_reg = ipu_cm_read(ipu, link->src.reg);
811 src_reg &= ~link->src.mask;
812 src_reg |= link->src.val;
813 ipu_cm_write(ipu, src_reg, link->src.reg);
814 }
815
816 if (link->sink.mask) {
817 sink_reg = ipu_cm_read(ipu, link->sink.reg);
818 sink_reg &= ~link->sink.mask;
819 sink_reg |= link->sink.val;
820 ipu_cm_write(ipu, sink_reg, link->sink.reg);
821 }
822
823 spin_unlock_irqrestore(&ipu->lock, flags);
824 return 0;
825 }
826 EXPORT_SYMBOL_GPL(ipu_fsu_link);
827
828 /*
829 * Unlinks source and sink channels in the FSU.
830 */
831 int ipu_fsu_unlink(struct ipu_soc *ipu, int src_ch, int sink_ch)
832 {
833 const struct fsu_link_info *link;
834 u32 src_reg, sink_reg;
835 unsigned long flags;
836
837 link = find_fsu_link_info(src_ch, sink_ch);
838 if (!link)
839 return -EINVAL;
840
841 spin_lock_irqsave(&ipu->lock, flags);
842
843 if (link->src.mask) {
844 src_reg = ipu_cm_read(ipu, link->src.reg);
845 src_reg &= ~link->src.mask;
846 ipu_cm_write(ipu, src_reg, link->src.reg);
847 }
848
849 if (link->sink.mask) {
850 sink_reg = ipu_cm_read(ipu, link->sink.reg);
851 sink_reg &= ~link->sink.mask;
852 ipu_cm_write(ipu, sink_reg, link->sink.reg);
853 }
854
855 spin_unlock_irqrestore(&ipu->lock, flags);
856 return 0;
857 }
858 EXPORT_SYMBOL_GPL(ipu_fsu_unlink);
859
860 /* Link IDMAC channels in the FSU */
861 int ipu_idmac_link(struct ipuv3_channel *src, struct ipuv3_channel *sink)
862 {
863 return ipu_fsu_link(src->ipu, src->num, sink->num);
864 }
865 EXPORT_SYMBOL_GPL(ipu_idmac_link);
866
867 /* Unlink IDMAC channels in the FSU */
868 int ipu_idmac_unlink(struct ipuv3_channel *src, struct ipuv3_channel *sink)
869 {
870 return ipu_fsu_unlink(src->ipu, src->num, sink->num);
871 }
872 EXPORT_SYMBOL_GPL(ipu_idmac_unlink);
873
874 struct ipu_devtype {
875 const char *name;
876 unsigned long cm_ofs;
877 unsigned long cpmem_ofs;
878 unsigned long srm_ofs;
879 unsigned long tpm_ofs;
880 unsigned long csi0_ofs;
881 unsigned long csi1_ofs;
882 unsigned long ic_ofs;
883 unsigned long disp0_ofs;
884 unsigned long disp1_ofs;
885 unsigned long dc_tmpl_ofs;
886 unsigned long vdi_ofs;
887 enum ipuv3_type type;
888 };
889
890 static struct ipu_devtype ipu_type_imx51 = {
891 .name = "IPUv3EX",
892 .cm_ofs = 0x1e000000,
893 .cpmem_ofs = 0x1f000000,
894 .srm_ofs = 0x1f040000,
895 .tpm_ofs = 0x1f060000,
896 .csi0_ofs = 0x1e030000,
897 .csi1_ofs = 0x1e038000,
898 .ic_ofs = 0x1e020000,
899 .disp0_ofs = 0x1e040000,
900 .disp1_ofs = 0x1e048000,
901 .dc_tmpl_ofs = 0x1f080000,
902 .vdi_ofs = 0x1e068000,
903 .type = IPUV3EX,
904 };
905
906 static struct ipu_devtype ipu_type_imx53 = {
907 .name = "IPUv3M",
908 .cm_ofs = 0x06000000,
909 .cpmem_ofs = 0x07000000,
910 .srm_ofs = 0x07040000,
911 .tpm_ofs = 0x07060000,
912 .csi0_ofs = 0x06030000,
913 .csi1_ofs = 0x06038000,
914 .ic_ofs = 0x06020000,
915 .disp0_ofs = 0x06040000,
916 .disp1_ofs = 0x06048000,
917 .dc_tmpl_ofs = 0x07080000,
918 .vdi_ofs = 0x06068000,
919 .type = IPUV3M,
920 };
921
922 static struct ipu_devtype ipu_type_imx6q = {
923 .name = "IPUv3H",
924 .cm_ofs = 0x00200000,
925 .cpmem_ofs = 0x00300000,
926 .srm_ofs = 0x00340000,
927 .tpm_ofs = 0x00360000,
928 .csi0_ofs = 0x00230000,
929 .csi1_ofs = 0x00238000,
930 .ic_ofs = 0x00220000,
931 .disp0_ofs = 0x00240000,
932 .disp1_ofs = 0x00248000,
933 .dc_tmpl_ofs = 0x00380000,
934 .vdi_ofs = 0x00268000,
935 .type = IPUV3H,
936 };
937
938 static const struct of_device_id imx_ipu_dt_ids[] = {
939 { .compatible = "fsl,imx51-ipu", .data = &ipu_type_imx51, },
940 { .compatible = "fsl,imx53-ipu", .data = &ipu_type_imx53, },
941 { .compatible = "fsl,imx6q-ipu", .data = &ipu_type_imx6q, },
942 { .compatible = "fsl,imx6qp-ipu", .data = &ipu_type_imx6q, },
943 { /* sentinel */ }
944 };
945 MODULE_DEVICE_TABLE(of, imx_ipu_dt_ids);
946
947 static int ipu_submodules_init(struct ipu_soc *ipu,
948 struct platform_device *pdev, unsigned long ipu_base,
949 struct clk *ipu_clk)
950 {
951 char *unit;
952 int ret;
953 struct device *dev = &pdev->dev;
954 const struct ipu_devtype *devtype = ipu->devtype;
955
956 ret = ipu_cpmem_init(ipu, dev, ipu_base + devtype->cpmem_ofs);
957 if (ret) {
958 unit = "cpmem";
959 goto err_cpmem;
960 }
961
962 ret = ipu_csi_init(ipu, dev, 0, ipu_base + devtype->csi0_ofs,
963 IPU_CONF_CSI0_EN, ipu_clk);
964 if (ret) {
965 unit = "csi0";
966 goto err_csi_0;
967 }
968
969 ret = ipu_csi_init(ipu, dev, 1, ipu_base + devtype->csi1_ofs,
970 IPU_CONF_CSI1_EN, ipu_clk);
971 if (ret) {
972 unit = "csi1";
973 goto err_csi_1;
974 }
975
976 ret = ipu_ic_init(ipu, dev,
977 ipu_base + devtype->ic_ofs,
978 ipu_base + devtype->tpm_ofs);
979 if (ret) {
980 unit = "ic";
981 goto err_ic;
982 }
983
984 ret = ipu_vdi_init(ipu, dev, ipu_base + devtype->vdi_ofs,
985 IPU_CONF_VDI_EN | IPU_CONF_ISP_EN |
986 IPU_CONF_IC_INPUT);
987 if (ret) {
988 unit = "vdi";
989 goto err_vdi;
990 }
991
992 ret = ipu_image_convert_init(ipu, dev);
993 if (ret) {
994 unit = "image_convert";
995 goto err_image_convert;
996 }
997
998 ret = ipu_di_init(ipu, dev, 0, ipu_base + devtype->disp0_ofs,
999 IPU_CONF_DI0_EN, ipu_clk);
1000 if (ret) {
1001 unit = "di0";
1002 goto err_di_0;
1003 }
1004
1005 ret = ipu_di_init(ipu, dev, 1, ipu_base + devtype->disp1_ofs,
1006 IPU_CONF_DI1_EN, ipu_clk);
1007 if (ret) {
1008 unit = "di1";
1009 goto err_di_1;
1010 }
1011
1012 ret = ipu_dc_init(ipu, dev, ipu_base + devtype->cm_ofs +
1013 IPU_CM_DC_REG_OFS, ipu_base + devtype->dc_tmpl_ofs);
1014 if (ret) {
1015 unit = "dc_template";
1016 goto err_dc;
1017 }
1018
1019 ret = ipu_dmfc_init(ipu, dev, ipu_base +
1020 devtype->cm_ofs + IPU_CM_DMFC_REG_OFS, ipu_clk);
1021 if (ret) {
1022 unit = "dmfc";
1023 goto err_dmfc;
1024 }
1025
1026 ret = ipu_dp_init(ipu, dev, ipu_base + devtype->srm_ofs);
1027 if (ret) {
1028 unit = "dp";
1029 goto err_dp;
1030 }
1031
1032 ret = ipu_smfc_init(ipu, dev, ipu_base +
1033 devtype->cm_ofs + IPU_CM_SMFC_REG_OFS);
1034 if (ret) {
1035 unit = "smfc";
1036 goto err_smfc;
1037 }
1038
1039 return 0;
1040
1041 err_smfc:
1042 ipu_dp_exit(ipu);
1043 err_dp:
1044 ipu_dmfc_exit(ipu);
1045 err_dmfc:
1046 ipu_dc_exit(ipu);
1047 err_dc:
1048 ipu_di_exit(ipu, 1);
1049 err_di_1:
1050 ipu_di_exit(ipu, 0);
1051 err_di_0:
1052 ipu_image_convert_exit(ipu);
1053 err_image_convert:
1054 ipu_vdi_exit(ipu);
1055 err_vdi:
1056 ipu_ic_exit(ipu);
1057 err_ic:
1058 ipu_csi_exit(ipu, 1);
1059 err_csi_1:
1060 ipu_csi_exit(ipu, 0);
1061 err_csi_0:
1062 ipu_cpmem_exit(ipu);
1063 err_cpmem:
1064 dev_err(&pdev->dev, "init %s failed with %d\n", unit, ret);
1065 return ret;
1066 }
1067
1068 static void ipu_irq_handle(struct ipu_soc *ipu, const int *regs, int num_regs)
1069 {
1070 unsigned long status;
1071 int i, bit, irq;
1072
1073 for (i = 0; i < num_regs; i++) {
1074
1075 status = ipu_cm_read(ipu, IPU_INT_STAT(regs[i]));
1076 status &= ipu_cm_read(ipu, IPU_INT_CTRL(regs[i]));
1077
1078 for_each_set_bit(bit, &status, 32) {
1079 irq = irq_linear_revmap(ipu->domain,
1080 regs[i] * 32 + bit);
1081 if (irq)
1082 generic_handle_irq(irq);
1083 }
1084 }
1085 }
1086
1087 static void ipu_irq_handler(struct irq_desc *desc)
1088 {
1089 struct ipu_soc *ipu = irq_desc_get_handler_data(desc);
1090 struct irq_chip *chip = irq_desc_get_chip(desc);
1091 static const int int_reg[] = { 0, 1, 2, 3, 10, 11, 12, 13, 14};
1092
1093 chained_irq_enter(chip, desc);
1094
1095 ipu_irq_handle(ipu, int_reg, ARRAY_SIZE(int_reg));
1096
1097 chained_irq_exit(chip, desc);
1098 }
1099
1100 static void ipu_err_irq_handler(struct irq_desc *desc)
1101 {
1102 struct ipu_soc *ipu = irq_desc_get_handler_data(desc);
1103 struct irq_chip *chip = irq_desc_get_chip(desc);
1104 static const int int_reg[] = { 4, 5, 8, 9};
1105
1106 chained_irq_enter(chip, desc);
1107
1108 ipu_irq_handle(ipu, int_reg, ARRAY_SIZE(int_reg));
1109
1110 chained_irq_exit(chip, desc);
1111 }
1112
1113 int ipu_map_irq(struct ipu_soc *ipu, int irq)
1114 {
1115 int virq;
1116
1117 virq = irq_linear_revmap(ipu->domain, irq);
1118 if (!virq)
1119 virq = irq_create_mapping(ipu->domain, irq);
1120
1121 return virq;
1122 }
1123 EXPORT_SYMBOL_GPL(ipu_map_irq);
1124
1125 int ipu_idmac_channel_irq(struct ipu_soc *ipu, struct ipuv3_channel *channel,
1126 enum ipu_channel_irq irq_type)
1127 {
1128 return ipu_map_irq(ipu, irq_type + channel->num);
1129 }
1130 EXPORT_SYMBOL_GPL(ipu_idmac_channel_irq);
1131
1132 static void ipu_submodules_exit(struct ipu_soc *ipu)
1133 {
1134 ipu_smfc_exit(ipu);
1135 ipu_dp_exit(ipu);
1136 ipu_dmfc_exit(ipu);
1137 ipu_dc_exit(ipu);
1138 ipu_di_exit(ipu, 1);
1139 ipu_di_exit(ipu, 0);
1140 ipu_image_convert_exit(ipu);
1141 ipu_vdi_exit(ipu);
1142 ipu_ic_exit(ipu);
1143 ipu_csi_exit(ipu, 1);
1144 ipu_csi_exit(ipu, 0);
1145 ipu_cpmem_exit(ipu);
1146 }
1147
1148 static int platform_remove_devices_fn(struct device *dev, void *unused)
1149 {
1150 struct platform_device *pdev = to_platform_device(dev);
1151
1152 platform_device_unregister(pdev);
1153
1154 return 0;
1155 }
1156
1157 static void platform_device_unregister_children(struct platform_device *pdev)
1158 {
1159 device_for_each_child(&pdev->dev, NULL, platform_remove_devices_fn);
1160 }
1161
1162 struct ipu_platform_reg {
1163 struct ipu_client_platformdata pdata;
1164 const char *name;
1165 };
1166
1167 /* These must be in the order of the corresponding device tree port nodes */
1168 static struct ipu_platform_reg client_reg[] = {
1169 {
1170 .pdata = {
1171 .csi = 0,
1172 .dma[0] = IPUV3_CHANNEL_CSI0,
1173 .dma[1] = -EINVAL,
1174 },
1175 .name = "imx-ipuv3-csi",
1176 }, {
1177 .pdata = {
1178 .csi = 1,
1179 .dma[0] = IPUV3_CHANNEL_CSI1,
1180 .dma[1] = -EINVAL,
1181 },
1182 .name = "imx-ipuv3-csi",
1183 }, {
1184 .pdata = {
1185 .di = 0,
1186 .dc = 5,
1187 .dp = IPU_DP_FLOW_SYNC_BG,
1188 .dma[0] = IPUV3_CHANNEL_MEM_BG_SYNC,
1189 .dma[1] = IPUV3_CHANNEL_MEM_FG_SYNC,
1190 },
1191 .name = "imx-ipuv3-crtc",
1192 }, {
1193 .pdata = {
1194 .di = 1,
1195 .dc = 1,
1196 .dp = -EINVAL,
1197 .dma[0] = IPUV3_CHANNEL_MEM_DC_SYNC,
1198 .dma[1] = -EINVAL,
1199 },
1200 .name = "imx-ipuv3-crtc",
1201 },
1202 };
1203
1204 static DEFINE_MUTEX(ipu_client_id_mutex);
1205 static int ipu_client_id;
1206
1207 static int ipu_add_client_devices(struct ipu_soc *ipu, unsigned long ipu_base)
1208 {
1209 struct device *dev = ipu->dev;
1210 unsigned i;
1211 int id, ret;
1212
1213 mutex_lock(&ipu_client_id_mutex);
1214 id = ipu_client_id;
1215 ipu_client_id += ARRAY_SIZE(client_reg);
1216 mutex_unlock(&ipu_client_id_mutex);
1217
1218 for (i = 0; i < ARRAY_SIZE(client_reg); i++) {
1219 struct ipu_platform_reg *reg = &client_reg[i];
1220 struct platform_device *pdev;
1221 struct device_node *of_node;
1222
1223 /* Associate subdevice with the corresponding port node */
1224 of_node = of_graph_get_port_by_id(dev->of_node, i);
1225 if (!of_node) {
1226 dev_info(dev,
1227 "no port@%d node in %pOF, not using %s%d\n",
1228 i, dev->of_node,
1229 (i / 2) ? "DI" : "CSI", i % 2);
1230 continue;
1231 }
1232
1233 pdev = platform_device_alloc(reg->name, id++);
1234 if (!pdev) {
1235 ret = -ENOMEM;
1236 goto err_register;
1237 }
1238
1239 pdev->dev.parent = dev;
1240
1241 reg->pdata.of_node = of_node;
1242 ret = platform_device_add_data(pdev, &reg->pdata,
1243 sizeof(reg->pdata));
1244 if (!ret)
1245 ret = platform_device_add(pdev);
1246 if (ret) {
1247 platform_device_put(pdev);
1248 goto err_register;
1249 }
1250 }
1251
1252 return 0;
1253
1254 err_register:
1255 platform_device_unregister_children(to_platform_device(dev));
1256
1257 return ret;
1258 }
1259
1260
1261 static int ipu_irq_init(struct ipu_soc *ipu)
1262 {
1263 struct irq_chip_generic *gc;
1264 struct irq_chip_type *ct;
1265 unsigned long unused[IPU_NUM_IRQS / 32] = {
1266 0x400100d0, 0xffe000fd,
1267 0x400100d0, 0xffe000fd,
1268 0x400100d0, 0xffe000fd,
1269 0x4077ffff, 0xffe7e1fd,
1270 0x23fffffe, 0x8880fff0,
1271 0xf98fe7d0, 0xfff81fff,
1272 0x400100d0, 0xffe000fd,
1273 0x00000000,
1274 };
1275 int ret, i;
1276
1277 ipu->domain = irq_domain_add_linear(ipu->dev->of_node, IPU_NUM_IRQS,
1278 &irq_generic_chip_ops, ipu);
1279 if (!ipu->domain) {
1280 dev_err(ipu->dev, "failed to add irq domain\n");
1281 return -ENODEV;
1282 }
1283
1284 ret = irq_alloc_domain_generic_chips(ipu->domain, 32, 1, "IPU",
1285 handle_level_irq, 0, 0, 0);
1286 if (ret < 0) {
1287 dev_err(ipu->dev, "failed to alloc generic irq chips\n");
1288 irq_domain_remove(ipu->domain);
1289 return ret;
1290 }
1291
1292 /* Mask and clear all interrupts */
1293 for (i = 0; i < IPU_NUM_IRQS; i += 32) {
1294 ipu_cm_write(ipu, 0, IPU_INT_CTRL(i / 32));
1295 ipu_cm_write(ipu, ~unused[i / 32], IPU_INT_STAT(i / 32));
1296 }
1297
1298 for (i = 0; i < IPU_NUM_IRQS; i += 32) {
1299 gc = irq_get_domain_generic_chip(ipu->domain, i);
1300 gc->reg_base = ipu->cm_reg;
1301 gc->unused = unused[i / 32];
1302 ct = gc->chip_types;
1303 ct->chip.irq_ack = irq_gc_ack_set_bit;
1304 ct->chip.irq_mask = irq_gc_mask_clr_bit;
1305 ct->chip.irq_unmask = irq_gc_mask_set_bit;
1306 ct->regs.ack = IPU_INT_STAT(i / 32);
1307 ct->regs.mask = IPU_INT_CTRL(i / 32);
1308 }
1309
1310 irq_set_chained_handler_and_data(ipu->irq_sync, ipu_irq_handler, ipu);
1311 irq_set_chained_handler_and_data(ipu->irq_err, ipu_err_irq_handler,
1312 ipu);
1313
1314 return 0;
1315 }
1316
1317 static void ipu_irq_exit(struct ipu_soc *ipu)
1318 {
1319 int i, irq;
1320
1321 irq_set_chained_handler_and_data(ipu->irq_err, NULL, NULL);
1322 irq_set_chained_handler_and_data(ipu->irq_sync, NULL, NULL);
1323
1324 /* TODO: remove irq_domain_generic_chips */
1325
1326 for (i = 0; i < IPU_NUM_IRQS; i++) {
1327 irq = irq_linear_revmap(ipu->domain, i);
1328 if (irq)
1329 irq_dispose_mapping(irq);
1330 }
1331
1332 irq_domain_remove(ipu->domain);
1333 }
1334
1335 void ipu_dump(struct ipu_soc *ipu)
1336 {
1337 int i;
1338
1339 dev_dbg(ipu->dev, "IPU_CONF = \t0x%08X\n",
1340 ipu_cm_read(ipu, IPU_CONF));
1341 dev_dbg(ipu->dev, "IDMAC_CONF = \t0x%08X\n",
1342 ipu_idmac_read(ipu, IDMAC_CONF));
1343 dev_dbg(ipu->dev, "IDMAC_CHA_EN1 = \t0x%08X\n",
1344 ipu_idmac_read(ipu, IDMAC_CHA_EN(0)));
1345 dev_dbg(ipu->dev, "IDMAC_CHA_EN2 = \t0x%08X\n",
1346 ipu_idmac_read(ipu, IDMAC_CHA_EN(32)));
1347 dev_dbg(ipu->dev, "IDMAC_CHA_PRI1 = \t0x%08X\n",
1348 ipu_idmac_read(ipu, IDMAC_CHA_PRI(0)));
1349 dev_dbg(ipu->dev, "IDMAC_CHA_PRI2 = \t0x%08X\n",
1350 ipu_idmac_read(ipu, IDMAC_CHA_PRI(32)));
1351 dev_dbg(ipu->dev, "IDMAC_BAND_EN1 = \t0x%08X\n",
1352 ipu_idmac_read(ipu, IDMAC_BAND_EN(0)));
1353 dev_dbg(ipu->dev, "IDMAC_BAND_EN2 = \t0x%08X\n",
1354 ipu_idmac_read(ipu, IDMAC_BAND_EN(32)));
1355 dev_dbg(ipu->dev, "IPU_CHA_DB_MODE_SEL0 = \t0x%08X\n",
1356 ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(0)));
1357 dev_dbg(ipu->dev, "IPU_CHA_DB_MODE_SEL1 = \t0x%08X\n",
1358 ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(32)));
1359 dev_dbg(ipu->dev, "IPU_FS_PROC_FLOW1 = \t0x%08X\n",
1360 ipu_cm_read(ipu, IPU_FS_PROC_FLOW1));
1361 dev_dbg(ipu->dev, "IPU_FS_PROC_FLOW2 = \t0x%08X\n",
1362 ipu_cm_read(ipu, IPU_FS_PROC_FLOW2));
1363 dev_dbg(ipu->dev, "IPU_FS_PROC_FLOW3 = \t0x%08X\n",
1364 ipu_cm_read(ipu, IPU_FS_PROC_FLOW3));
1365 dev_dbg(ipu->dev, "IPU_FS_DISP_FLOW1 = \t0x%08X\n",
1366 ipu_cm_read(ipu, IPU_FS_DISP_FLOW1));
1367 for (i = 0; i < 15; i++)
1368 dev_dbg(ipu->dev, "IPU_INT_CTRL(%d) = \t%08X\n", i,
1369 ipu_cm_read(ipu, IPU_INT_CTRL(i)));
1370 }
1371 EXPORT_SYMBOL_GPL(ipu_dump);
1372
1373 static int ipu_probe(struct platform_device *pdev)
1374 {
1375 struct device_node *np = pdev->dev.of_node;
1376 struct ipu_soc *ipu;
1377 struct resource *res;
1378 unsigned long ipu_base;
1379 int ret, irq_sync, irq_err;
1380 const struct ipu_devtype *devtype;
1381
1382 devtype = of_device_get_match_data(&pdev->dev);
1383 if (!devtype)
1384 return -EINVAL;
1385
1386 irq_sync = platform_get_irq(pdev, 0);
1387 irq_err = platform_get_irq(pdev, 1);
1388 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1389
1390 dev_dbg(&pdev->dev, "irq_sync: %d irq_err: %d\n",
1391 irq_sync, irq_err);
1392
1393 if (!res || irq_sync < 0 || irq_err < 0)
1394 return -ENODEV;
1395
1396 ipu_base = res->start;
1397
1398 ipu = devm_kzalloc(&pdev->dev, sizeof(*ipu), GFP_KERNEL);
1399 if (!ipu)
1400 return -ENODEV;
1401
1402 ipu->id = of_alias_get_id(np, "ipu");
1403 if (ipu->id < 0)
1404 ipu->id = 0;
1405
1406 if (of_device_is_compatible(np, "fsl,imx6qp-ipu") &&
1407 IS_ENABLED(CONFIG_DRM)) {
1408 ipu->prg_priv = ipu_prg_lookup_by_phandle(&pdev->dev,
1409 "fsl,prg", ipu->id);
1410 if (!ipu->prg_priv)
1411 return -EPROBE_DEFER;
1412 }
1413
1414 ipu->devtype = devtype;
1415 ipu->ipu_type = devtype->type;
1416
1417 spin_lock_init(&ipu->lock);
1418 mutex_init(&ipu->channel_lock);
1419 INIT_LIST_HEAD(&ipu->channels);
1420
1421 dev_dbg(&pdev->dev, "cm_reg: 0x%08lx\n",
1422 ipu_base + devtype->cm_ofs);
1423 dev_dbg(&pdev->dev, "idmac: 0x%08lx\n",
1424 ipu_base + devtype->cm_ofs + IPU_CM_IDMAC_REG_OFS);
1425 dev_dbg(&pdev->dev, "cpmem: 0x%08lx\n",
1426 ipu_base + devtype->cpmem_ofs);
1427 dev_dbg(&pdev->dev, "csi0: 0x%08lx\n",
1428 ipu_base + devtype->csi0_ofs);
1429 dev_dbg(&pdev->dev, "csi1: 0x%08lx\n",
1430 ipu_base + devtype->csi1_ofs);
1431 dev_dbg(&pdev->dev, "ic: 0x%08lx\n",
1432 ipu_base + devtype->ic_ofs);
1433 dev_dbg(&pdev->dev, "disp0: 0x%08lx\n",
1434 ipu_base + devtype->disp0_ofs);
1435 dev_dbg(&pdev->dev, "disp1: 0x%08lx\n",
1436 ipu_base + devtype->disp1_ofs);
1437 dev_dbg(&pdev->dev, "srm: 0x%08lx\n",
1438 ipu_base + devtype->srm_ofs);
1439 dev_dbg(&pdev->dev, "tpm: 0x%08lx\n",
1440 ipu_base + devtype->tpm_ofs);
1441 dev_dbg(&pdev->dev, "dc: 0x%08lx\n",
1442 ipu_base + devtype->cm_ofs + IPU_CM_DC_REG_OFS);
1443 dev_dbg(&pdev->dev, "ic: 0x%08lx\n",
1444 ipu_base + devtype->cm_ofs + IPU_CM_IC_REG_OFS);
1445 dev_dbg(&pdev->dev, "dmfc: 0x%08lx\n",
1446 ipu_base + devtype->cm_ofs + IPU_CM_DMFC_REG_OFS);
1447 dev_dbg(&pdev->dev, "vdi: 0x%08lx\n",
1448 ipu_base + devtype->vdi_ofs);
1449
1450 ipu->cm_reg = devm_ioremap(&pdev->dev,
1451 ipu_base + devtype->cm_ofs, PAGE_SIZE);
1452 ipu->idmac_reg = devm_ioremap(&pdev->dev,
1453 ipu_base + devtype->cm_ofs + IPU_CM_IDMAC_REG_OFS,
1454 PAGE_SIZE);
1455
1456 if (!ipu->cm_reg || !ipu->idmac_reg)
1457 return -ENOMEM;
1458
1459 ipu->clk = devm_clk_get(&pdev->dev, "bus");
1460 if (IS_ERR(ipu->clk)) {
1461 ret = PTR_ERR(ipu->clk);
1462 dev_err(&pdev->dev, "clk_get failed with %d", ret);
1463 return ret;
1464 }
1465
1466 platform_set_drvdata(pdev, ipu);
1467
1468 ret = clk_prepare_enable(ipu->clk);
1469 if (ret) {
1470 dev_err(&pdev->dev, "clk_prepare_enable failed: %d\n", ret);
1471 return ret;
1472 }
1473
1474 ipu->dev = &pdev->dev;
1475 ipu->irq_sync = irq_sync;
1476 ipu->irq_err = irq_err;
1477
1478 ret = device_reset(&pdev->dev);
1479 if (ret) {
1480 dev_err(&pdev->dev, "failed to reset: %d\n", ret);
1481 goto out_failed_reset;
1482 }
1483 ret = ipu_memory_reset(ipu);
1484 if (ret)
1485 goto out_failed_reset;
1486
1487 ret = ipu_irq_init(ipu);
1488 if (ret)
1489 goto out_failed_irq;
1490
1491 /* Set MCU_T to divide MCU access window into 2 */
1492 ipu_cm_write(ipu, 0x00400000L | (IPU_MCU_T_DEFAULT << 18),
1493 IPU_DISP_GEN);
1494
1495 ret = ipu_submodules_init(ipu, pdev, ipu_base, ipu->clk);
1496 if (ret)
1497 goto failed_submodules_init;
1498
1499 ret = ipu_add_client_devices(ipu, ipu_base);
1500 if (ret) {
1501 dev_err(&pdev->dev, "adding client devices failed with %d\n",
1502 ret);
1503 goto failed_add_clients;
1504 }
1505
1506 dev_info(&pdev->dev, "%s probed\n", devtype->name);
1507
1508 return 0;
1509
1510 failed_add_clients:
1511 ipu_submodules_exit(ipu);
1512 failed_submodules_init:
1513 ipu_irq_exit(ipu);
1514 out_failed_irq:
1515 out_failed_reset:
1516 clk_disable_unprepare(ipu->clk);
1517 return ret;
1518 }
1519
1520 static int ipu_remove(struct platform_device *pdev)
1521 {
1522 struct ipu_soc *ipu = platform_get_drvdata(pdev);
1523
1524 platform_device_unregister_children(pdev);
1525 ipu_submodules_exit(ipu);
1526 ipu_irq_exit(ipu);
1527
1528 clk_disable_unprepare(ipu->clk);
1529
1530 return 0;
1531 }
1532
1533 static struct platform_driver imx_ipu_driver = {
1534 .driver = {
1535 .name = "imx-ipuv3",
1536 .of_match_table = imx_ipu_dt_ids,
1537 },
1538 .probe = ipu_probe,
1539 .remove = ipu_remove,
1540 };
1541
1542 static struct platform_driver * const drivers[] = {
1543 #if IS_ENABLED(CONFIG_DRM)
1544 &ipu_pre_drv,
1545 &ipu_prg_drv,
1546 #endif
1547 &imx_ipu_driver,
1548 };
1549
1550 static int __init imx_ipu_init(void)
1551 {
1552 return platform_register_drivers(drivers, ARRAY_SIZE(drivers));
1553 }
1554 module_init(imx_ipu_init);
1555
1556 static void __exit imx_ipu_exit(void)
1557 {
1558 platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
1559 }
1560 module_exit(imx_ipu_exit);
1561
1562 MODULE_ALIAS("platform:imx-ipuv3");
1563 MODULE_DESCRIPTION("i.MX IPU v3 driver");
1564 MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
1565 MODULE_LICENSE("GPL");
Linux with added FPC-III support