1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * APM X-Gene SoC Hardware Monitoring Driver
5 * Copyright (c) 2016, Applied Micro Circuits Corporation
6 * Author: Loc Ho <lho@apm.com>
7 * Hoan Tran <hotran@apm.com>
9 * This driver provides the following features:
10 * - Retrieve CPU total power (uW)
11 * - Retrieve IO total power (uW)
12 * - Retrieve SoC temperature (milli-degree C) and alarm
14 #include <linux/acpi.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/hwmon.h>
17 #include <linux/hwmon-sysfs.h>
19 #include <linux/interrupt.h>
20 #include <linux/kfifo.h>
21 #include <linux/mailbox_controller.h>
22 #include <linux/mailbox_client.h>
23 #include <linux/module.h>
25 #include <linux/platform_device.h>
29 /* SLIMpro message defines */
30 #define MSG_TYPE_DBG 0
31 #define MSG_TYPE_ERR 7
32 #define MSG_TYPE_PWRMGMT 9
34 #define MSG_TYPE(v) (((v) & 0xF0000000) >> 28)
35 #define MSG_TYPE_SET(v) (((v) << 28) & 0xF0000000)
36 #define MSG_SUBTYPE(v) (((v) & 0x0F000000) >> 24)
37 #define MSG_SUBTYPE_SET(v) (((v) << 24) & 0x0F000000)
39 #define DBG_SUBTYPE_SENSOR_READ 4
40 #define SENSOR_RD_MSG 0x04FFE902
41 #define SENSOR_RD_EN_ADDR(a) ((a) & 0x000FFFFF)
42 #define PMD_PWR_REG 0x20
43 #define PMD_PWR_MW_REG 0x26
44 #define SOC_PWR_REG 0x21
45 #define SOC_PWR_MW_REG 0x27
46 #define SOC_TEMP_REG 0x10
48 #define TEMP_NEGATIVE_BIT 8
49 #define SENSOR_INVALID_DATA BIT(15)
51 #define PWRMGMT_SUBTYPE_TPC 1
53 #define TPC_GET_ALARM 3
54 #define TPC_CMD(v) (((v) & 0x00FF0000) >> 16)
55 #define TPC_CMD_SET(v) (((v) << 16) & 0x00FF0000)
56 #define TPC_EN_MSG(hndl, cmd, type) \
57 (MSG_TYPE_SET(MSG_TYPE_PWRMGMT) | \
58 MSG_SUBTYPE_SET(hndl) | TPC_CMD_SET(cmd) | type)
61 #define PCC_SIGNATURE_MASK 0x50424300
62 #define PCCC_GENERATE_DB_INT BIT(15)
63 #define PCCS_CMD_COMPLETE BIT(0)
64 #define PCCS_SCI_DOORBEL BIT(1)
65 #define PCCS_PLATFORM_NOTIFICATION BIT(3)
67 * Arbitrary retries in case the remote processor is slow to respond
70 #define PCC_NUM_RETRIES 500
72 #define ASYNC_MSG_FIFO_SIZE 16
73 #define MBOX_OP_TIMEOUTMS 1000
75 #define WATT_TO_mWATT(x) ((x) * 1000)
76 #define mWATT_TO_uWATT(x) ((x) * 1000)
77 #define CELSIUS_TO_mCELSIUS(x) ((x) * 1000)
79 #define to_xgene_hwmon_dev(cl) \
80 container_of(cl, struct xgene_hwmon_dev, mbox_client)
82 enum xgene_hwmon_version
{
87 struct slimpro_resp_msg
{
93 struct xgene_hwmon_dev
{
95 struct mbox_chan
*mbox_chan
;
96 struct mbox_client mbox_client
;
99 spinlock_t kfifo_lock
;
100 struct mutex rd_mutex
;
101 struct completion rd_complete
;
103 struct slimpro_resp_msg sync_msg
;
105 struct work_struct workq
;
106 struct kfifo_rec_ptr_1 async_msg_fifo
;
108 struct device
*hwmon_dev
;
109 bool temp_critical_alarm
;
111 phys_addr_t comm_base_addr
;
117 * This function tests and clears a bitmask then returns its old value
119 static u16
xgene_word_tst_and_clr(u16
*addr
, u16 mask
)
123 val
= le16_to_cpu(READ_ONCE(*addr
));
126 WRITE_ONCE(*addr
, cpu_to_le16(val
));
131 static int xgene_hwmon_pcc_rd(struct xgene_hwmon_dev
*ctx
, u32
*msg
)
133 struct acpi_pcct_shared_memory
*generic_comm_base
= ctx
->pcc_comm_addr
;
134 u32
*ptr
= (void *)(generic_comm_base
+ 1);
138 mutex_lock(&ctx
->rd_mutex
);
139 init_completion(&ctx
->rd_complete
);
140 ctx
->resp_pending
= true;
142 /* Write signature for subspace */
143 WRITE_ONCE(generic_comm_base
->signature
,
144 cpu_to_le32(PCC_SIGNATURE_MASK
| ctx
->mbox_idx
));
146 /* Write to the shared command region */
147 WRITE_ONCE(generic_comm_base
->command
,
148 cpu_to_le16(MSG_TYPE(msg
[0]) | PCCC_GENERATE_DB_INT
));
150 /* Flip CMD COMPLETE bit */
151 val
= le16_to_cpu(READ_ONCE(generic_comm_base
->status
));
152 val
&= ~PCCS_CMD_COMPLETE
;
153 WRITE_ONCE(generic_comm_base
->status
, cpu_to_le16(val
));
155 /* Copy the message to the PCC comm space */
156 for (i
= 0; i
< sizeof(struct slimpro_resp_msg
) / 4; i
++)
157 WRITE_ONCE(ptr
[i
], cpu_to_le32(msg
[i
]));
159 /* Ring the doorbell */
160 rc
= mbox_send_message(ctx
->mbox_chan
, msg
);
162 dev_err(ctx
->dev
, "Mailbox send error %d\n", rc
);
165 if (!wait_for_completion_timeout(&ctx
->rd_complete
,
166 usecs_to_jiffies(ctx
->usecs_lat
))) {
167 dev_err(ctx
->dev
, "Mailbox operation timed out\n");
172 /* Check for error message */
173 if (MSG_TYPE(ctx
->sync_msg
.msg
) == MSG_TYPE_ERR
) {
178 msg
[0] = ctx
->sync_msg
.msg
;
179 msg
[1] = ctx
->sync_msg
.param1
;
180 msg
[2] = ctx
->sync_msg
.param2
;
183 mbox_chan_txdone(ctx
->mbox_chan
, 0);
184 ctx
->resp_pending
= false;
185 mutex_unlock(&ctx
->rd_mutex
);
189 static int xgene_hwmon_rd(struct xgene_hwmon_dev
*ctx
, u32
*msg
)
193 mutex_lock(&ctx
->rd_mutex
);
194 init_completion(&ctx
->rd_complete
);
195 ctx
->resp_pending
= true;
197 rc
= mbox_send_message(ctx
->mbox_chan
, msg
);
199 dev_err(ctx
->dev
, "Mailbox send error %d\n", rc
);
203 if (!wait_for_completion_timeout(&ctx
->rd_complete
,
204 msecs_to_jiffies(MBOX_OP_TIMEOUTMS
))) {
205 dev_err(ctx
->dev
, "Mailbox operation timed out\n");
210 /* Check for error message */
211 if (MSG_TYPE(ctx
->sync_msg
.msg
) == MSG_TYPE_ERR
) {
216 msg
[0] = ctx
->sync_msg
.msg
;
217 msg
[1] = ctx
->sync_msg
.param1
;
218 msg
[2] = ctx
->sync_msg
.param2
;
221 ctx
->resp_pending
= false;
222 mutex_unlock(&ctx
->rd_mutex
);
226 static int xgene_hwmon_reg_map_rd(struct xgene_hwmon_dev
*ctx
, u32 addr
,
232 msg
[0] = SENSOR_RD_MSG
;
233 msg
[1] = SENSOR_RD_EN_ADDR(addr
);
237 rc
= xgene_hwmon_rd(ctx
, msg
);
239 rc
= xgene_hwmon_pcc_rd(ctx
, msg
);
245 * Check if sensor data is valid.
247 if (msg
[1] & SENSOR_INVALID_DATA
)
255 static int xgene_hwmon_get_notification_msg(struct xgene_hwmon_dev
*ctx
,
261 msg
[0] = TPC_EN_MSG(PWRMGMT_SUBTYPE_TPC
, TPC_GET_ALARM
, 0);
265 rc
= xgene_hwmon_pcc_rd(ctx
, msg
);
276 static int xgene_hwmon_get_cpu_pwr(struct xgene_hwmon_dev
*ctx
, u32
*val
)
281 rc
= xgene_hwmon_reg_map_rd(ctx
, PMD_PWR_REG
, &watt
);
285 rc
= xgene_hwmon_reg_map_rd(ctx
, PMD_PWR_MW_REG
, &mwatt
);
289 *val
= WATT_TO_mWATT(watt
) + mwatt
;
293 static int xgene_hwmon_get_io_pwr(struct xgene_hwmon_dev
*ctx
, u32
*val
)
298 rc
= xgene_hwmon_reg_map_rd(ctx
, SOC_PWR_REG
, &watt
);
302 rc
= xgene_hwmon_reg_map_rd(ctx
, SOC_PWR_MW_REG
, &mwatt
);
306 *val
= WATT_TO_mWATT(watt
) + mwatt
;
310 static int xgene_hwmon_get_temp(struct xgene_hwmon_dev
*ctx
, u32
*val
)
312 return xgene_hwmon_reg_map_rd(ctx
, SOC_TEMP_REG
, val
);
316 * Sensor temperature/power functions
318 static ssize_t
temp1_input_show(struct device
*dev
,
319 struct device_attribute
*attr
,
322 struct xgene_hwmon_dev
*ctx
= dev_get_drvdata(dev
);
326 rc
= xgene_hwmon_get_temp(ctx
, &val
);
330 temp
= sign_extend32(val
, TEMP_NEGATIVE_BIT
);
332 return snprintf(buf
, PAGE_SIZE
, "%d\n", CELSIUS_TO_mCELSIUS(temp
));
335 static ssize_t
temp1_label_show(struct device
*dev
,
336 struct device_attribute
*attr
,
339 return snprintf(buf
, PAGE_SIZE
, "SoC Temperature\n");
342 static ssize_t
temp1_critical_alarm_show(struct device
*dev
,
343 struct device_attribute
*devattr
,
346 struct xgene_hwmon_dev
*ctx
= dev_get_drvdata(dev
);
348 return snprintf(buf
, PAGE_SIZE
, "%d\n", ctx
->temp_critical_alarm
);
351 static ssize_t
power1_label_show(struct device
*dev
,
352 struct device_attribute
*attr
,
355 return snprintf(buf
, PAGE_SIZE
, "CPU power\n");
358 static ssize_t
power2_label_show(struct device
*dev
,
359 struct device_attribute
*attr
,
362 return snprintf(buf
, PAGE_SIZE
, "IO power\n");
365 static ssize_t
power1_input_show(struct device
*dev
,
366 struct device_attribute
*attr
,
369 struct xgene_hwmon_dev
*ctx
= dev_get_drvdata(dev
);
373 rc
= xgene_hwmon_get_cpu_pwr(ctx
, &val
);
377 return snprintf(buf
, PAGE_SIZE
, "%u\n", mWATT_TO_uWATT(val
));
380 static ssize_t
power2_input_show(struct device
*dev
,
381 struct device_attribute
*attr
,
384 struct xgene_hwmon_dev
*ctx
= dev_get_drvdata(dev
);
388 rc
= xgene_hwmon_get_io_pwr(ctx
, &val
);
392 return snprintf(buf
, PAGE_SIZE
, "%u\n", mWATT_TO_uWATT(val
));
395 static DEVICE_ATTR_RO(temp1_label
);
396 static DEVICE_ATTR_RO(temp1_input
);
397 static DEVICE_ATTR_RO(temp1_critical_alarm
);
398 static DEVICE_ATTR_RO(power1_label
);
399 static DEVICE_ATTR_RO(power1_input
);
400 static DEVICE_ATTR_RO(power2_label
);
401 static DEVICE_ATTR_RO(power2_input
);
403 static struct attribute
*xgene_hwmon_attrs
[] = {
404 &dev_attr_temp1_label
.attr
,
405 &dev_attr_temp1_input
.attr
,
406 &dev_attr_temp1_critical_alarm
.attr
,
407 &dev_attr_power1_label
.attr
,
408 &dev_attr_power1_input
.attr
,
409 &dev_attr_power2_label
.attr
,
410 &dev_attr_power2_input
.attr
,
414 ATTRIBUTE_GROUPS(xgene_hwmon
);
416 static int xgene_hwmon_tpc_alarm(struct xgene_hwmon_dev
*ctx
,
417 struct slimpro_resp_msg
*amsg
)
419 ctx
->temp_critical_alarm
= !!amsg
->param2
;
420 sysfs_notify(&ctx
->dev
->kobj
, NULL
, "temp1_critical_alarm");
425 static void xgene_hwmon_process_pwrmsg(struct xgene_hwmon_dev
*ctx
,
426 struct slimpro_resp_msg
*amsg
)
428 if ((MSG_SUBTYPE(amsg
->msg
) == PWRMGMT_SUBTYPE_TPC
) &&
429 (TPC_CMD(amsg
->msg
) == TPC_ALARM
))
430 xgene_hwmon_tpc_alarm(ctx
, amsg
);
434 * This function is called to process async work queue
436 static void xgene_hwmon_evt_work(struct work_struct
*work
)
438 struct slimpro_resp_msg amsg
;
439 struct xgene_hwmon_dev
*ctx
;
442 ctx
= container_of(work
, struct xgene_hwmon_dev
, workq
);
443 while (kfifo_out_spinlocked(&ctx
->async_msg_fifo
, &amsg
,
444 sizeof(struct slimpro_resp_msg
),
447 * If PCC, send a consumer command to Platform to get info
448 * If Slimpro Mailbox, get message from specific FIFO
450 if (!acpi_disabled
) {
451 ret
= xgene_hwmon_get_notification_msg(ctx
,
457 if (MSG_TYPE(amsg
.msg
) == MSG_TYPE_PWRMGMT
)
458 xgene_hwmon_process_pwrmsg(ctx
, &amsg
);
462 static int xgene_hwmon_rx_ready(struct xgene_hwmon_dev
*ctx
, void *msg
)
464 if (IS_ERR_OR_NULL(ctx
->hwmon_dev
) && !ctx
->resp_pending
) {
465 /* Enqueue to the FIFO */
466 kfifo_in_spinlocked(&ctx
->async_msg_fifo
, msg
,
467 sizeof(struct slimpro_resp_msg
),
476 * This function is called when the SLIMpro Mailbox received a message
478 static void xgene_hwmon_rx_cb(struct mbox_client
*cl
, void *msg
)
480 struct xgene_hwmon_dev
*ctx
= to_xgene_hwmon_dev(cl
);
483 * While the driver registers with the mailbox framework, an interrupt
484 * can be pending before the probe function completes its
485 * initialization. If such condition occurs, just queue up the message
486 * as the driver is not ready for servicing the callback.
488 if (xgene_hwmon_rx_ready(ctx
, msg
) < 0)
492 * Response message format:
493 * msg[0] is the return code of the operation
494 * msg[1] is the first parameter word
495 * msg[2] is the second parameter word
497 * As message only supports dword size, just assign it.
500 /* Check for sync query */
501 if (ctx
->resp_pending
&&
502 ((MSG_TYPE(((u32
*)msg
)[0]) == MSG_TYPE_ERR
) ||
503 (MSG_TYPE(((u32
*)msg
)[0]) == MSG_TYPE_DBG
&&
504 MSG_SUBTYPE(((u32
*)msg
)[0]) == DBG_SUBTYPE_SENSOR_READ
) ||
505 (MSG_TYPE(((u32
*)msg
)[0]) == MSG_TYPE_PWRMGMT
&&
506 MSG_SUBTYPE(((u32
*)msg
)[0]) == PWRMGMT_SUBTYPE_TPC
&&
507 TPC_CMD(((u32
*)msg
)[0]) == TPC_ALARM
))) {
508 ctx
->sync_msg
.msg
= ((u32
*)msg
)[0];
509 ctx
->sync_msg
.param1
= ((u32
*)msg
)[1];
510 ctx
->sync_msg
.param2
= ((u32
*)msg
)[2];
512 /* Operation waiting for response */
513 complete(&ctx
->rd_complete
);
518 /* Enqueue to the FIFO */
519 kfifo_in_spinlocked(&ctx
->async_msg_fifo
, msg
,
520 sizeof(struct slimpro_resp_msg
), &ctx
->kfifo_lock
);
521 /* Schedule the bottom handler */
522 schedule_work(&ctx
->workq
);
526 * This function is called when the PCC Mailbox received a message
528 static void xgene_hwmon_pcc_rx_cb(struct mbox_client
*cl
, void *msg
)
530 struct xgene_hwmon_dev
*ctx
= to_xgene_hwmon_dev(cl
);
531 struct acpi_pcct_shared_memory
*generic_comm_base
= ctx
->pcc_comm_addr
;
532 struct slimpro_resp_msg amsg
;
535 * While the driver registers with the mailbox framework, an interrupt
536 * can be pending before the probe function completes its
537 * initialization. If such condition occurs, just queue up the message
538 * as the driver is not ready for servicing the callback.
540 if (xgene_hwmon_rx_ready(ctx
, &amsg
) < 0)
543 msg
= generic_comm_base
+ 1;
544 /* Check if platform sends interrupt */
545 if (!xgene_word_tst_and_clr(&generic_comm_base
->status
,
550 * Response message format:
551 * msg[0] is the return code of the operation
552 * msg[1] is the first parameter word
553 * msg[2] is the second parameter word
555 * As message only supports dword size, just assign it.
558 /* Check for sync query */
559 if (ctx
->resp_pending
&&
560 ((MSG_TYPE(((u32
*)msg
)[0]) == MSG_TYPE_ERR
) ||
561 (MSG_TYPE(((u32
*)msg
)[0]) == MSG_TYPE_DBG
&&
562 MSG_SUBTYPE(((u32
*)msg
)[0]) == DBG_SUBTYPE_SENSOR_READ
) ||
563 (MSG_TYPE(((u32
*)msg
)[0]) == MSG_TYPE_PWRMGMT
&&
564 MSG_SUBTYPE(((u32
*)msg
)[0]) == PWRMGMT_SUBTYPE_TPC
&&
565 TPC_CMD(((u32
*)msg
)[0]) == TPC_ALARM
))) {
566 /* Check if platform completes command */
567 if (xgene_word_tst_and_clr(&generic_comm_base
->status
,
568 PCCS_CMD_COMPLETE
)) {
569 ctx
->sync_msg
.msg
= ((u32
*)msg
)[0];
570 ctx
->sync_msg
.param1
= ((u32
*)msg
)[1];
571 ctx
->sync_msg
.param2
= ((u32
*)msg
)[2];
573 /* Operation waiting for response */
574 complete(&ctx
->rd_complete
);
581 * Platform notifies interrupt to OSPM.
582 * OPSM schedules a consumer command to get this information
583 * in a workqueue. Platform must wait until OSPM has issued
584 * a consumer command that serves this notification.
587 /* Enqueue to the FIFO */
588 kfifo_in_spinlocked(&ctx
->async_msg_fifo
, &amsg
,
589 sizeof(struct slimpro_resp_msg
), &ctx
->kfifo_lock
);
590 /* Schedule the bottom handler */
591 schedule_work(&ctx
->workq
);
594 static void xgene_hwmon_tx_done(struct mbox_client
*cl
, void *msg
, int ret
)
597 dev_dbg(cl
->dev
, "TX did not complete: CMD sent:%x, ret:%d\n",
600 dev_dbg(cl
->dev
, "TX completed. CMD sent:%x, ret:%d\n",
606 static const struct acpi_device_id xgene_hwmon_acpi_match
[] = {
607 {"APMC0D29", XGENE_HWMON_V1
},
608 {"APMC0D8A", XGENE_HWMON_V2
},
611 MODULE_DEVICE_TABLE(acpi
, xgene_hwmon_acpi_match
);
614 static int xgene_hwmon_probe(struct platform_device
*pdev
)
616 struct xgene_hwmon_dev
*ctx
;
617 struct mbox_client
*cl
;
620 ctx
= devm_kzalloc(&pdev
->dev
, sizeof(*ctx
), GFP_KERNEL
);
624 ctx
->dev
= &pdev
->dev
;
625 platform_set_drvdata(pdev
, ctx
);
626 cl
= &ctx
->mbox_client
;
628 spin_lock_init(&ctx
->kfifo_lock
);
629 mutex_init(&ctx
->rd_mutex
);
631 rc
= kfifo_alloc(&ctx
->async_msg_fifo
,
632 sizeof(struct slimpro_resp_msg
) * ASYNC_MSG_FIFO_SIZE
,
637 INIT_WORK(&ctx
->workq
, xgene_hwmon_evt_work
);
639 /* Request mailbox channel */
640 cl
->dev
= &pdev
->dev
;
641 cl
->tx_done
= xgene_hwmon_tx_done
;
642 cl
->tx_block
= false;
643 cl
->tx_tout
= MBOX_OP_TIMEOUTMS
;
644 cl
->knows_txdone
= false;
646 cl
->rx_callback
= xgene_hwmon_rx_cb
;
647 ctx
->mbox_chan
= mbox_request_channel(cl
, 0);
648 if (IS_ERR(ctx
->mbox_chan
)) {
650 "SLIMpro mailbox channel request failed\n");
655 struct acpi_pcct_hw_reduced
*cppc_ss
;
656 const struct acpi_device_id
*acpi_id
;
659 acpi_id
= acpi_match_device(pdev
->dev
.driver
->acpi_match_table
,
664 version
= (int)acpi_id
->driver_data
;
666 if (device_property_read_u32(&pdev
->dev
, "pcc-channel",
668 dev_err(&pdev
->dev
, "no pcc-channel property\n");
673 cl
->rx_callback
= xgene_hwmon_pcc_rx_cb
;
674 ctx
->mbox_chan
= pcc_mbox_request_channel(cl
, ctx
->mbox_idx
);
675 if (IS_ERR(ctx
->mbox_chan
)) {
677 "PPC channel request failed\n");
683 * The PCC mailbox controller driver should
684 * have parsed the PCCT (global table of all
685 * PCC channels) and stored pointers to the
686 * subspace communication region in con_priv.
688 cppc_ss
= ctx
->mbox_chan
->con_priv
;
690 dev_err(&pdev
->dev
, "PPC subspace not found\n");
695 if (!ctx
->mbox_chan
->mbox
->txdone_irq
) {
696 dev_err(&pdev
->dev
, "PCC IRQ not supported\n");
702 * This is the shared communication region
703 * for the OS and Platform to communicate over.
705 ctx
->comm_base_addr
= cppc_ss
->base_address
;
706 if (ctx
->comm_base_addr
) {
707 if (version
== XGENE_HWMON_V2
)
708 ctx
->pcc_comm_addr
= (void __force
*)ioremap(
712 ctx
->pcc_comm_addr
= memremap(
717 dev_err(&pdev
->dev
, "Failed to get PCC comm region\n");
722 if (!ctx
->pcc_comm_addr
) {
724 "Failed to ioremap PCC comm region\n");
730 * cppc_ss->latency is just a Nominal value. In reality
731 * the remote processor could be much slower to reply.
732 * So add an arbitrary amount of wait on top of Nominal.
734 ctx
->usecs_lat
= PCC_NUM_RETRIES
* cppc_ss
->latency
;
737 ctx
->hwmon_dev
= hwmon_device_register_with_groups(ctx
->dev
,
741 if (IS_ERR(ctx
->hwmon_dev
)) {
742 dev_err(&pdev
->dev
, "Failed to register HW monitor device\n");
743 rc
= PTR_ERR(ctx
->hwmon_dev
);
748 * Schedule the bottom handler if there is a pending message.
750 schedule_work(&ctx
->workq
);
752 dev_info(&pdev
->dev
, "APM X-Gene SoC HW monitor driver registered\n");
758 mbox_free_channel(ctx
->mbox_chan
);
760 pcc_mbox_free_channel(ctx
->mbox_chan
);
762 kfifo_free(&ctx
->async_msg_fifo
);
767 static int xgene_hwmon_remove(struct platform_device
*pdev
)
769 struct xgene_hwmon_dev
*ctx
= platform_get_drvdata(pdev
);
771 hwmon_device_unregister(ctx
->hwmon_dev
);
772 kfifo_free(&ctx
->async_msg_fifo
);
774 mbox_free_channel(ctx
->mbox_chan
);
776 pcc_mbox_free_channel(ctx
->mbox_chan
);
781 static const struct of_device_id xgene_hwmon_of_match
[] = {
782 {.compatible
= "apm,xgene-slimpro-hwmon"},
785 MODULE_DEVICE_TABLE(of
, xgene_hwmon_of_match
);
787 static struct platform_driver xgene_hwmon_driver __refdata
= {
788 .probe
= xgene_hwmon_probe
,
789 .remove
= xgene_hwmon_remove
,
791 .name
= "xgene-slimpro-hwmon",
792 .of_match_table
= xgene_hwmon_of_match
,
793 .acpi_match_table
= ACPI_PTR(xgene_hwmon_acpi_match
),
796 module_platform_driver(xgene_hwmon_driver
);
798 MODULE_DESCRIPTION("APM X-Gene SoC hardware monitor");
799 MODULE_LICENSE("GPL");