drivers/i2c/busses/i2c-designware-common.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Synopsys DesignWare I2C adapter driver.
   4  *
   5  * Based on the TI DAVINCI I2C adapter driver.
   6  *
   7  * Copyright (C) 2006 Texas Instruments.
   8  * Copyright (C) 2007 MontaVista Software Inc.
   9  * Copyright (C) 2009 Provigent Ltd.
  10  */
  11 #include <linux/clk.h>
  12 #include <linux/delay.h>
  13 #include <linux/export.h>
  14 #include <linux/errno.h>
  15 #include <linux/err.h>
  16 #include <linux/i2c.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/io.h>
  19 #include <linux/module.h>
  20 #include <linux/pm_runtime.h>
  21 #include <linux/swab.h>
  22
  23 #include "i2c-designware-core.h"
  24
  25 static char *abort_sources[] = {
  26         [ABRT_7B_ADDR_NOACK] =
  27                 "slave address not acknowledged (7bit mode)",
  28         [ABRT_10ADDR1_NOACK] =
  29                 "first address byte not acknowledged (10bit mode)",
  30         [ABRT_10ADDR2_NOACK] =
  31                 "second address byte not acknowledged (10bit mode)",
  32         [ABRT_TXDATA_NOACK] =
  33                 "data not acknowledged",
  34         [ABRT_GCALL_NOACK] =
  35                 "no acknowledgement for a general call",
  36         [ABRT_GCALL_READ] =
  37                 "read after general call",
  38         [ABRT_SBYTE_ACKDET] =
  39                 "start byte acknowledged",
  40         [ABRT_SBYTE_NORSTRT] =
  41                 "trying to send start byte when restart is disabled",
  42         [ABRT_10B_RD_NORSTRT] =
  43                 "trying to read when restart is disabled (10bit mode)",
  44         [ABRT_MASTER_DIS] =
  45                 "trying to use disabled adapter",
  46         [ARB_LOST] =
  47                 "lost arbitration",
  48         [ABRT_SLAVE_FLUSH_TXFIFO] =
  49                 "read command so flush old data in the TX FIFO",
  50         [ABRT_SLAVE_ARBLOST] =
  51                 "slave lost the bus while transmitting data to a remote master",
  52         [ABRT_SLAVE_RD_INTX] =
  53                 "incorrect slave-transmitter mode configuration",
  54 };
  55
  56 u32 dw_readl(struct dw_i2c_dev *dev, int offset)
  57 {
  58         u32 value;
  59
  60         if (dev->flags & ACCESS_16BIT)
  61                 value = readw_relaxed(dev->base + offset) |
  62                         (readw_relaxed(dev->base + offset + 2) << 16);
  63         else
  64                 value = readl_relaxed(dev->base + offset);
  65
  66         if (dev->flags & ACCESS_SWAP)
  67                 return swab32(value);
  68         else
  69                 return value;
  70 }
  71
  72 void dw_writel(struct dw_i2c_dev *dev, u32 b, int offset)
  73 {
  74         if (dev->flags & ACCESS_SWAP)
  75                 b = swab32(b);
  76
  77         if (dev->flags & ACCESS_16BIT) {
  78                 writew_relaxed((u16)b, dev->base + offset);
  79                 writew_relaxed((u16)(b >> 16), dev->base + offset + 2);
  80         } else {
  81                 writel_relaxed(b, dev->base + offset);
  82         }
  83 }
  84
  85 /**
  86  * i2c_dw_set_reg_access() - Set register access flags
  87  * @dev: device private data
  88  *
  89  * Autodetects needed register access mode and sets access flags accordingly.
  90  * This must be called before doing any other register access.
  91  */
  92 int i2c_dw_set_reg_access(struct dw_i2c_dev *dev)
  93 {
  94         u32 reg;
  95         int ret;
  96
  97         ret = i2c_dw_acquire_lock(dev);
  98         if (ret)
  99                 return ret;
 100
 101         reg = dw_readl(dev, DW_IC_COMP_TYPE);
 102         i2c_dw_release_lock(dev);
 103
 104         if (reg == swab32(DW_IC_COMP_TYPE_VALUE)) {
 105                 /* Configure register endianess access */
 106                 dev->flags |= ACCESS_SWAP;
 107         } else if (reg == (DW_IC_COMP_TYPE_VALUE & 0x0000ffff)) {
 108                 /* Configure register access mode 16bit */
 109                 dev->flags |= ACCESS_16BIT;
 110         } else if (reg != DW_IC_COMP_TYPE_VALUE) {
 111                 dev_err(dev->dev,
 112                         "Unknown Synopsys component type: 0x%08x\n", reg);
 113                 return -ENODEV;
 114         }
 115
 116         return 0;
 117 }
 118
 119 u32 i2c_dw_scl_hcnt(u32 ic_clk, u32 tSYMBOL, u32 tf, int cond, int offset)
 120 {
 121         /*
 122          * DesignWare I2C core doesn't seem to have solid strategy to meet
 123          * the tHD;STA timing spec.  Configuring _HCNT based on tHIGH spec
 124          * will result in violation of the tHD;STA spec.
 125          */
 126         if (cond)
 127                 /*
 128                  * Conditional expression:
 129                  *
 130                  *   IC_[FS]S_SCL_HCNT + (1+4+3) >= IC_CLK * tHIGH
 131                  *
 132                  * This is based on the DW manuals, and represents an ideal
 133                  * configuration.  The resulting I2C bus speed will be
 134                  * faster than any of the others.
 135                  *
 136                  * If your hardware is free from tHD;STA issue, try this one.
 137                  */
 138                 return (ic_clk * tSYMBOL + 500000) / 1000000 - 8 + offset;
 139         else
 140                 /*
 141                  * Conditional expression:
 142                  *
 143                  *   IC_[FS]S_SCL_HCNT + 3 >= IC_CLK * (tHD;STA + tf)
 144                  *
 145                  * This is just experimental rule; the tHD;STA period turned
 146                  * out to be proportinal to (_HCNT + 3).  With this setting,
 147                  * we could meet both tHIGH and tHD;STA timing specs.
 148                  *
 149                  * If unsure, you'd better to take this alternative.
 150                  *
 151                  * The reason why we need to take into account "tf" here,
 152                  * is the same as described in i2c_dw_scl_lcnt().
 153                  */
 154                 return (ic_clk * (tSYMBOL + tf) + 500000) / 1000000
 155                         - 3 + offset;
 156 }
 157
 158 u32 i2c_dw_scl_lcnt(u32 ic_clk, u32 tLOW, u32 tf, int offset)
 159 {
 160         /*
 161          * Conditional expression:
 162          *
 163          *   IC_[FS]S_SCL_LCNT + 1 >= IC_CLK * (tLOW + tf)
 164          *
 165          * DW I2C core starts counting the SCL CNTs for the LOW period
 166          * of the SCL clock (tLOW) as soon as it pulls the SCL line.
 167          * In order to meet the tLOW timing spec, we need to take into
 168          * account the fall time of SCL signal (tf).  Default tf value
 169          * should be 0.3 us, for safety.
 170          */
 171         return ((ic_clk * (tLOW + tf) + 500000) / 1000000) - 1 + offset;
 172 }
 173
 174 int i2c_dw_set_sda_hold(struct dw_i2c_dev *dev)
 175 {
 176         u32 reg;
 177         int ret;
 178
 179         ret = i2c_dw_acquire_lock(dev);
 180         if (ret)
 181                 return ret;
 182
 183         /* Configure SDA Hold Time if required */
 184         reg = dw_readl(dev, DW_IC_COMP_VERSION);
 185         if (reg >= DW_IC_SDA_HOLD_MIN_VERS) {
 186                 if (!dev->sda_hold_time) {
 187                         /* Keep previous hold time setting if no one set it */
 188                         dev->sda_hold_time = dw_readl(dev, DW_IC_SDA_HOLD);
 189                 }
 190
 191                 /*
 192                  * Workaround for avoiding TX arbitration lost in case I2C
 193                  * slave pulls SDA down "too quickly" after falling egde of
 194                  * SCL by enabling non-zero SDA RX hold. Specification says it
 195                  * extends incoming SDA low to high transition while SCL is
 196                  * high but it apprears to help also above issue.
 197                  */
 198                 if (!(dev->sda_hold_time & DW_IC_SDA_HOLD_RX_MASK))
 199                         dev->sda_hold_time |= 1 << DW_IC_SDA_HOLD_RX_SHIFT;
 200
 201                 dev_dbg(dev->dev, "SDA Hold Time TX:RX = %d:%d\n",
 202                         dev->sda_hold_time & ~(u32)DW_IC_SDA_HOLD_RX_MASK,
 203                         dev->sda_hold_time >> DW_IC_SDA_HOLD_RX_SHIFT);
 204         } else if (dev->set_sda_hold_time) {
 205                 dev->set_sda_hold_time(dev);
 206         } else if (dev->sda_hold_time) {
 207                 dev_warn(dev->dev,
 208                         "Hardware too old to adjust SDA hold time.\n");
 209                 dev->sda_hold_time = 0;
 210         }
 211
 212         i2c_dw_release_lock(dev);
 213
 214         return 0;
 215 }
 216
 217 void __i2c_dw_disable(struct dw_i2c_dev *dev)
 218 {
 219         int timeout = 100;
 220
 221         do {
 222                 __i2c_dw_disable_nowait(dev);
 223                 /*
 224                  * The enable status register may be unimplemented, but
 225                  * in that case this test reads zero and exits the loop.
 226                  */
 227                 if ((dw_readl(dev, DW_IC_ENABLE_STATUS) & 1) == 0)
 228                         return;
 229
 230                 /*
 231                  * Wait 10 times the signaling period of the highest I2C
 232                  * transfer supported by the driver (for 400KHz this is
 233                  * 25us) as described in the DesignWare I2C databook.
 234                  */
 235                 usleep_range(25, 250);
 236         } while (timeout--);
 237
 238         dev_warn(dev->dev, "timeout in disabling adapter\n");
 239 }
 240
 241 unsigned long i2c_dw_clk_rate(struct dw_i2c_dev *dev)
 242 {
 243         /*
 244          * Clock is not necessary if we got LCNT/HCNT values directly from
 245          * the platform code.
 246          */
 247         if (WARN_ON_ONCE(!dev->get_clk_rate_khz))
 248                 return 0;
 249         return dev->get_clk_rate_khz(dev);
 250 }
 251
 252 int i2c_dw_prepare_clk(struct dw_i2c_dev *dev, bool prepare)
 253 {
 254         int ret;
 255
 256         if (IS_ERR(dev->clk))
 257                 return PTR_ERR(dev->clk);
 258
 259         if (prepare) {
 260                 /* Optional interface clock */
 261                 ret = clk_prepare_enable(dev->pclk);
 262                 if (ret)
 263                         return ret;
 264
 265                 ret = clk_prepare_enable(dev->clk);
 266                 if (ret)
 267                         clk_disable_unprepare(dev->pclk);
 268
 269                 return ret;
 270         }
 271
 272         clk_disable_unprepare(dev->clk);
 273         clk_disable_unprepare(dev->pclk);
 274
 275         return 0;
 276 }
 277 EXPORT_SYMBOL_GPL(i2c_dw_prepare_clk);
 278
 279 int i2c_dw_acquire_lock(struct dw_i2c_dev *dev)
 280 {
 281         int ret;
 282
 283         if (!dev->acquire_lock)
 284                 return 0;
 285
 286         ret = dev->acquire_lock();
 287         if (!ret)
 288                 return 0;
 289
 290         dev_err(dev->dev, "couldn't acquire bus ownership\n");
 291
 292         return ret;
 293 }
 294
 295 void i2c_dw_release_lock(struct dw_i2c_dev *dev)
 296 {
 297         if (dev->release_lock)
 298                 dev->release_lock();
 299 }
 300
 301 /*
 302  * Waiting for bus not busy
 303  */
 304 int i2c_dw_wait_bus_not_busy(struct dw_i2c_dev *dev)
 305 {
 306         int timeout = TIMEOUT;
 307
 308         while (dw_readl(dev, DW_IC_STATUS) & DW_IC_STATUS_ACTIVITY) {
 309                 if (timeout <= 0) {
 310                         dev_warn(dev->dev, "timeout waiting for bus ready\n");
 311                         i2c_recover_bus(&dev->adapter);
 312
 313                         if (dw_readl(dev, DW_IC_STATUS) & DW_IC_STATUS_ACTIVITY)
 314                                 return -ETIMEDOUT;
 315                         return 0;
 316                 }
 317                 timeout--;
 318                 usleep_range(1000, 1100);
 319         }
 320
 321         return 0;
 322 }
 323
 324 int i2c_dw_handle_tx_abort(struct dw_i2c_dev *dev)
 325 {
 326         unsigned long abort_source = dev->abort_source;
 327         int i;
 328
 329         if (abort_source & DW_IC_TX_ABRT_NOACK) {
 330                 for_each_set_bit(i, &abort_source, ARRAY_SIZE(abort_sources))
 331                         dev_dbg(dev->dev,
 332                                 "%s: %s\n", __func__, abort_sources[i]);
 333                 return -EREMOTEIO;
 334         }
 335
 336         for_each_set_bit(i, &abort_source, ARRAY_SIZE(abort_sources))
 337                 dev_err(dev->dev, "%s: %s\n", __func__, abort_sources[i]);
 338
 339         if (abort_source & DW_IC_TX_ARB_LOST)
 340                 return -EAGAIN;
 341         else if (abort_source & DW_IC_TX_ABRT_GCALL_READ)
 342                 return -EINVAL; /* wrong msgs[] data */
 343         else
 344                 return -EIO;
 345 }
 346
 347 u32 i2c_dw_func(struct i2c_adapter *adap)
 348 {
 349         struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
 350
 351         return dev->functionality;
 352 }
 353
 354 void i2c_dw_disable(struct dw_i2c_dev *dev)
 355 {
 356         /* Disable controller */
 357         __i2c_dw_disable(dev);
 358
 359         /* Disable all interupts */
 360         dw_writel(dev, 0, DW_IC_INTR_MASK);
 361         dw_readl(dev, DW_IC_CLR_INTR);
 362 }
 363
 364 void i2c_dw_disable_int(struct dw_i2c_dev *dev)
 365 {
 366         dw_writel(dev, 0, DW_IC_INTR_MASK);
 367 }
 368
 369 u32 i2c_dw_read_comp_param(struct dw_i2c_dev *dev)
 370 {
 371         return dw_readl(dev, DW_IC_COMP_PARAM_1);
 372 }
 373 EXPORT_SYMBOL_GPL(i2c_dw_read_comp_param);
 374
 375 MODULE_DESCRIPTION("Synopsys DesignWare I2C bus adapter core");
 376 MODULE_LICENSE("GPL");