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treewide: remove redundant IS_ERR() before error code check
[linux/fpc-iii.git] / drivers / i2c / busses / i2c-i801.c
blobf5e69fe565321e6c2f9a54791165ede04fad9b54
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl>,
4 Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker
5 <mdsxyz123@yahoo.com>
6 Copyright (C) 2007 - 2014 Jean Delvare <jdelvare@suse.de>
7 Copyright (C) 2010 Intel Corporation,
8 David Woodhouse <dwmw2@infradead.org>
9
10 */
11
12 /*
13 * Supports the following Intel I/O Controller Hubs (ICH):
14 *
15 * I/O Block I2C
16 * region SMBus Block proc. block
17 * Chip name PCI ID size PEC buffer call read
18 * ---------------------------------------------------------------------------
19 * 82801AA (ICH) 0x2413 16 no no no no
20 * 82801AB (ICH0) 0x2423 16 no no no no
21 * 82801BA (ICH2) 0x2443 16 no no no no
22 * 82801CA (ICH3) 0x2483 32 soft no no no
23 * 82801DB (ICH4) 0x24c3 32 hard yes no no
24 * 82801E (ICH5) 0x24d3 32 hard yes yes yes
25 * 6300ESB 0x25a4 32 hard yes yes yes
26 * 82801F (ICH6) 0x266a 32 hard yes yes yes
27 * 6310ESB/6320ESB 0x269b 32 hard yes yes yes
28 * 82801G (ICH7) 0x27da 32 hard yes yes yes
29 * 82801H (ICH8) 0x283e 32 hard yes yes yes
30 * 82801I (ICH9) 0x2930 32 hard yes yes yes
31 * EP80579 (Tolapai) 0x5032 32 hard yes yes yes
32 * ICH10 0x3a30 32 hard yes yes yes
33 * ICH10 0x3a60 32 hard yes yes yes
34 * 5/3400 Series (PCH) 0x3b30 32 hard yes yes yes
35 * 6 Series (PCH) 0x1c22 32 hard yes yes yes
36 * Patsburg (PCH) 0x1d22 32 hard yes yes yes
37 * Patsburg (PCH) IDF 0x1d70 32 hard yes yes yes
38 * Patsburg (PCH) IDF 0x1d71 32 hard yes yes yes
39 * Patsburg (PCH) IDF 0x1d72 32 hard yes yes yes
40 * DH89xxCC (PCH) 0x2330 32 hard yes yes yes
41 * Panther Point (PCH) 0x1e22 32 hard yes yes yes
42 * Lynx Point (PCH) 0x8c22 32 hard yes yes yes
43 * Lynx Point-LP (PCH) 0x9c22 32 hard yes yes yes
44 * Avoton (SOC) 0x1f3c 32 hard yes yes yes
45 * Wellsburg (PCH) 0x8d22 32 hard yes yes yes
46 * Wellsburg (PCH) MS 0x8d7d 32 hard yes yes yes
47 * Wellsburg (PCH) MS 0x8d7e 32 hard yes yes yes
48 * Wellsburg (PCH) MS 0x8d7f 32 hard yes yes yes
49 * Coleto Creek (PCH) 0x23b0 32 hard yes yes yes
50 * Wildcat Point (PCH) 0x8ca2 32 hard yes yes yes
51 * Wildcat Point-LP (PCH) 0x9ca2 32 hard yes yes yes
52 * BayTrail (SOC) 0x0f12 32 hard yes yes yes
53 * Braswell (SOC) 0x2292 32 hard yes yes yes
54 * Sunrise Point-H (PCH) 0xa123 32 hard yes yes yes
55 * Sunrise Point-LP (PCH) 0x9d23 32 hard yes yes yes
56 * DNV (SOC) 0x19df 32 hard yes yes yes
57 * Broxton (SOC) 0x5ad4 32 hard yes yes yes
58 * Lewisburg (PCH) 0xa1a3 32 hard yes yes yes
59 * Lewisburg Supersku (PCH) 0xa223 32 hard yes yes yes
60 * Kaby Lake PCH-H (PCH) 0xa2a3 32 hard yes yes yes
61 * Gemini Lake (SOC) 0x31d4 32 hard yes yes yes
62 * Cannon Lake-H (PCH) 0xa323 32 hard yes yes yes
63 * Cannon Lake-LP (PCH) 0x9da3 32 hard yes yes yes
64 * Cedar Fork (PCH) 0x18df 32 hard yes yes yes
65 * Ice Lake-LP (PCH) 0x34a3 32 hard yes yes yes
66 * Comet Lake (PCH) 0x02a3 32 hard yes yes yes
67 * Comet Lake-H (PCH) 0x06a3 32 hard yes yes yes
68 * Elkhart Lake (PCH) 0x4b23 32 hard yes yes yes
69 * Tiger Lake-LP (PCH) 0xa0a3 32 hard yes yes yes
70 * Jasper Lake (SOC) 0x4da3 32 hard yes yes yes
71 *
72 * Features supported by this driver:
73 * Software PEC no
74 * Hardware PEC yes
75 * Block buffer yes
76 * Block process call transaction yes
77 * I2C block read transaction yes (doesn't use the block buffer)
78 * Slave mode no
79 * SMBus Host Notify yes
80 * Interrupt processing yes
81 *
82 * See the file Documentation/i2c/busses/i2c-i801.rst for details.
83 */
84
85 #include <linux/interrupt.h>
86 #include <linux/module.h>
87 #include <linux/pci.h>
88 #include <linux/kernel.h>
89 #include <linux/stddef.h>
90 #include <linux/delay.h>
91 #include <linux/ioport.h>
92 #include <linux/init.h>
93 #include <linux/i2c.h>
94 #include <linux/i2c-smbus.h>
95 #include <linux/acpi.h>
96 #include <linux/io.h>
97 #include <linux/dmi.h>
98 #include <linux/slab.h>
99 #include <linux/string.h>
100 #include <linux/wait.h>
101 #include <linux/err.h>
102 #include <linux/platform_device.h>
103 #include <linux/platform_data/itco_wdt.h>
104 #include <linux/pm_runtime.h>
105
106 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI
107 #include <linux/gpio/machine.h>
108 #include <linux/platform_data/i2c-mux-gpio.h>
109 #endif
110
111 /* I801 SMBus address offsets */
112 #define SMBHSTSTS(p) (0 + (p)->smba)
113 #define SMBHSTCNT(p) (2 + (p)->smba)
114 #define SMBHSTCMD(p) (3 + (p)->smba)
115 #define SMBHSTADD(p) (4 + (p)->smba)
116 #define SMBHSTDAT0(p) (5 + (p)->smba)
117 #define SMBHSTDAT1(p) (6 + (p)->smba)
118 #define SMBBLKDAT(p) (7 + (p)->smba)
119 #define SMBPEC(p) (8 + (p)->smba) /* ICH3 and later */
120 #define SMBAUXSTS(p) (12 + (p)->smba) /* ICH4 and later */
121 #define SMBAUXCTL(p) (13 + (p)->smba) /* ICH4 and later */
122 #define SMBSLVSTS(p) (16 + (p)->smba) /* ICH3 and later */
123 #define SMBSLVCMD(p) (17 + (p)->smba) /* ICH3 and later */
124 #define SMBNTFDADD(p) (20 + (p)->smba) /* ICH3 and later */
125
126 /* PCI Address Constants */
127 #define SMBBAR 4
128 #define SMBPCICTL 0x004
129 #define SMBPCISTS 0x006
130 #define SMBHSTCFG 0x040
131 #define TCOBASE 0x050
132 #define TCOCTL 0x054
133
134 #define ACPIBASE 0x040
135 #define ACPIBASE_SMI_OFF 0x030
136 #define ACPICTRL 0x044
137 #define ACPICTRL_EN 0x080
138
139 #define SBREG_BAR 0x10
140 #define SBREG_SMBCTRL 0xc6000c
141 #define SBREG_SMBCTRL_DNV 0xcf000c
142
143 /* Host status bits for SMBPCISTS */
144 #define SMBPCISTS_INTS BIT(3)
145
146 /* Control bits for SMBPCICTL */
147 #define SMBPCICTL_INTDIS BIT(10)
148
149 /* Host configuration bits for SMBHSTCFG */
150 #define SMBHSTCFG_HST_EN BIT(0)
151 #define SMBHSTCFG_SMB_SMI_EN BIT(1)
152 #define SMBHSTCFG_I2C_EN BIT(2)
153 #define SMBHSTCFG_SPD_WD BIT(4)
154
155 /* TCO configuration bits for TCOCTL */
156 #define TCOCTL_EN BIT(8)
157
158 /* Auxiliary status register bits, ICH4+ only */
159 #define SMBAUXSTS_CRCE BIT(0)
160 #define SMBAUXSTS_STCO BIT(1)
161
162 /* Auxiliary control register bits, ICH4+ only */
163 #define SMBAUXCTL_CRC BIT(0)
164 #define SMBAUXCTL_E32B BIT(1)
165
166 /* Other settings */
167 #define MAX_RETRIES 400
168
169 /* I801 command constants */
170 #define I801_QUICK 0x00
171 #define I801_BYTE 0x04
172 #define I801_BYTE_DATA 0x08
173 #define I801_WORD_DATA 0x0C
174 #define I801_PROC_CALL 0x10 /* unimplemented */
175 #define I801_BLOCK_DATA 0x14
176 #define I801_I2C_BLOCK_DATA 0x18 /* ICH5 and later */
177 #define I801_BLOCK_PROC_CALL 0x1C
178
179 /* I801 Host Control register bits */
180 #define SMBHSTCNT_INTREN BIT(0)
181 #define SMBHSTCNT_KILL BIT(1)
182 #define SMBHSTCNT_LAST_BYTE BIT(5)
183 #define SMBHSTCNT_START BIT(6)
184 #define SMBHSTCNT_PEC_EN BIT(7) /* ICH3 and later */
185
186 /* I801 Hosts Status register bits */
187 #define SMBHSTSTS_BYTE_DONE BIT(7)
188 #define SMBHSTSTS_INUSE_STS BIT(6)
189 #define SMBHSTSTS_SMBALERT_STS BIT(5)
190 #define SMBHSTSTS_FAILED BIT(4)
191 #define SMBHSTSTS_BUS_ERR BIT(3)
192 #define SMBHSTSTS_DEV_ERR BIT(2)
193 #define SMBHSTSTS_INTR BIT(1)
194 #define SMBHSTSTS_HOST_BUSY BIT(0)
195
196 /* Host Notify Status register bits */
197 #define SMBSLVSTS_HST_NTFY_STS BIT(0)
198
199 /* Host Notify Command register bits */
200 #define SMBSLVCMD_HST_NTFY_INTREN BIT(0)
201
202 #define STATUS_ERROR_FLAGS (SMBHSTSTS_FAILED | SMBHSTSTS_BUS_ERR | \
203 SMBHSTSTS_DEV_ERR)
204
205 #define STATUS_FLAGS (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR | \
206 STATUS_ERROR_FLAGS)
207
208 /* Older devices have their ID defined in <linux/pci_ids.h> */
209 #define PCI_DEVICE_ID_INTEL_COMETLAKE_SMBUS 0x02a3
210 #define PCI_DEVICE_ID_INTEL_COMETLAKE_H_SMBUS 0x06a3
211 #define PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS 0x0f12
212 #define PCI_DEVICE_ID_INTEL_CDF_SMBUS 0x18df
213 #define PCI_DEVICE_ID_INTEL_DNV_SMBUS 0x19df
214 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS 0x1c22
215 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS 0x1d22
216 /* Patsburg also has three 'Integrated Device Function' SMBus controllers */
217 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0 0x1d70
218 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1 0x1d71
219 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2 0x1d72
220 #define PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS 0x1e22
221 #define PCI_DEVICE_ID_INTEL_AVOTON_SMBUS 0x1f3c
222 #define PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS 0x2292
223 #define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS 0x2330
224 #define PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS 0x23b0
225 #define PCI_DEVICE_ID_INTEL_GEMINILAKE_SMBUS 0x31d4
226 #define PCI_DEVICE_ID_INTEL_ICELAKE_LP_SMBUS 0x34a3
227 #define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS 0x3b30
228 #define PCI_DEVICE_ID_INTEL_ELKHART_LAKE_SMBUS 0x4b23
229 #define PCI_DEVICE_ID_INTEL_JASPER_LAKE_SMBUS 0x4da3
230 #define PCI_DEVICE_ID_INTEL_BROXTON_SMBUS 0x5ad4
231 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS 0x8c22
232 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS 0x8ca2
233 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS 0x8d22
234 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0 0x8d7d
235 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1 0x8d7e
236 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2 0x8d7f
237 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS 0x9c22
238 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS 0x9ca2
239 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS 0x9d23
240 #define PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS 0x9da3
241 #define PCI_DEVICE_ID_INTEL_TIGERLAKE_LP_SMBUS 0xa0a3
242 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS 0xa123
243 #define PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS 0xa1a3
244 #define PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS 0xa223
245 #define PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS 0xa2a3
246 #define PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS 0xa323
247
248 struct i801_mux_config {
249 char *gpio_chip;
250 unsigned values[3];
251 int n_values;
252 unsigned classes[3];
253 unsigned gpios[2]; /* Relative to gpio_chip->base */
254 int n_gpios;
255 };
256
257 struct i801_priv {
258 struct i2c_adapter adapter;
259 unsigned long smba;
260 unsigned char original_hstcfg;
261 unsigned char original_slvcmd;
262 struct pci_dev *pci_dev;
263 unsigned int features;
264
265 /* isr processing */
266 wait_queue_head_t waitq;
267 u8 status;
268
269 /* Command state used by isr for byte-by-byte block transactions */
270 u8 cmd;
271 bool is_read;
272 int count;
273 int len;
274 u8 *data;
275
276 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI
277 const struct i801_mux_config *mux_drvdata;
278 struct platform_device *mux_pdev;
279 struct gpiod_lookup_table *lookup;
280 #endif
281 struct platform_device *tco_pdev;
282
283 /*
284 * If set to true the host controller registers are reserved for
285 * ACPI AML use. Protected by acpi_lock.
286 */
287 bool acpi_reserved;
288 struct mutex acpi_lock;
289 };
290
291 #define FEATURE_SMBUS_PEC BIT(0)
292 #define FEATURE_BLOCK_BUFFER BIT(1)
293 #define FEATURE_BLOCK_PROC BIT(2)
294 #define FEATURE_I2C_BLOCK_READ BIT(3)
295 #define FEATURE_IRQ BIT(4)
296 #define FEATURE_HOST_NOTIFY BIT(5)
297 /* Not really a feature, but it's convenient to handle it as such */
298 #define FEATURE_IDF BIT(15)
299 #define FEATURE_TCO_SPT BIT(16)
300 #define FEATURE_TCO_CNL BIT(17)
301
302 static const char *i801_feature_names[] = {
303 "SMBus PEC",
304 "Block buffer",
305 "Block process call",
306 "I2C block read",
307 "Interrupt",
308 "SMBus Host Notify",
309 };
310
311 static unsigned int disable_features;
312 module_param(disable_features, uint, S_IRUGO | S_IWUSR);
313 MODULE_PARM_DESC(disable_features, "Disable selected driver features:\n"
314 "\t\t 0x01 disable SMBus PEC\n"
315 "\t\t 0x02 disable the block buffer\n"
316 "\t\t 0x08 disable the I2C block read functionality\n"
317 "\t\t 0x10 don't use interrupts\n"
318 "\t\t 0x20 disable SMBus Host Notify ");
319
320 /* Make sure the SMBus host is ready to start transmitting.
321 Return 0 if it is, -EBUSY if it is not. */
322 static int i801_check_pre(struct i801_priv *priv)
323 {
324 int status;
325
326 status = inb_p(SMBHSTSTS(priv));
327 if (status & SMBHSTSTS_HOST_BUSY) {
328 dev_err(&priv->pci_dev->dev, "SMBus is busy, can't use it!\n");
329 return -EBUSY;
330 }
331
332 status &= STATUS_FLAGS;
333 if (status) {
334 dev_dbg(&priv->pci_dev->dev, "Clearing status flags (%02x)\n",
335 status);
336 outb_p(status, SMBHSTSTS(priv));
337 status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS;
338 if (status) {
339 dev_err(&priv->pci_dev->dev,
340 "Failed clearing status flags (%02x)\n",
341 status);
342 return -EBUSY;
343 }
344 }
345
346 /*
347 * Clear CRC status if needed.
348 * During normal operation, i801_check_post() takes care
349 * of it after every operation. We do it here only in case
350 * the hardware was already in this state when the driver
351 * started.
352 */
353 if (priv->features & FEATURE_SMBUS_PEC) {
354 status = inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE;
355 if (status) {
356 dev_dbg(&priv->pci_dev->dev,
357 "Clearing aux status flags (%02x)\n", status);
358 outb_p(status, SMBAUXSTS(priv));
359 status = inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE;
360 if (status) {
361 dev_err(&priv->pci_dev->dev,
362 "Failed clearing aux status flags (%02x)\n",
363 status);
364 return -EBUSY;
365 }
366 }
367 }
368
369 return 0;
370 }
371
372 /*
373 * Convert the status register to an error code, and clear it.
374 * Note that status only contains the bits we want to clear, not the
375 * actual register value.
376 */
377 static int i801_check_post(struct i801_priv *priv, int status)
378 {
379 int result = 0;
380
381 /*
382 * If the SMBus is still busy, we give up
383 * Note: This timeout condition only happens when using polling
384 * transactions. For interrupt operation, NAK/timeout is indicated by
385 * DEV_ERR.
386 */
387 if (unlikely(status < 0)) {
388 dev_err(&priv->pci_dev->dev, "Transaction timeout\n");
389 /* try to stop the current command */
390 dev_dbg(&priv->pci_dev->dev, "Terminating the current operation\n");
391 outb_p(inb_p(SMBHSTCNT(priv)) | SMBHSTCNT_KILL,
392 SMBHSTCNT(priv));
393 usleep_range(1000, 2000);
394 outb_p(inb_p(SMBHSTCNT(priv)) & (~SMBHSTCNT_KILL),
395 SMBHSTCNT(priv));
396
397 /* Check if it worked */
398 status = inb_p(SMBHSTSTS(priv));
399 if ((status & SMBHSTSTS_HOST_BUSY) ||
400 !(status & SMBHSTSTS_FAILED))
401 dev_err(&priv->pci_dev->dev,
402 "Failed terminating the transaction\n");
403 outb_p(STATUS_FLAGS, SMBHSTSTS(priv));
404 return -ETIMEDOUT;
405 }
406
407 if (status & SMBHSTSTS_FAILED) {
408 result = -EIO;
409 dev_err(&priv->pci_dev->dev, "Transaction failed\n");
410 }
411 if (status & SMBHSTSTS_DEV_ERR) {
412 /*
413 * This may be a PEC error, check and clear it.
414 *
415 * AUXSTS is handled differently from HSTSTS.
416 * For HSTSTS, i801_isr() or i801_wait_intr()
417 * has already cleared the error bits in hardware,
418 * and we are passed a copy of the original value
419 * in "status".
420 * For AUXSTS, the hardware register is left
421 * for us to handle here.
422 * This is asymmetric, slightly iffy, but safe,
423 * since all this code is serialized and the CRCE
424 * bit is harmless as long as it's cleared before
425 * the next operation.
426 */
427 if ((priv->features & FEATURE_SMBUS_PEC) &&
428 (inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE)) {
429 outb_p(SMBAUXSTS_CRCE, SMBAUXSTS(priv));
430 result = -EBADMSG;
431 dev_dbg(&priv->pci_dev->dev, "PEC error\n");
432 } else {
433 result = -ENXIO;
434 dev_dbg(&priv->pci_dev->dev, "No response\n");
435 }
436 }
437 if (status & SMBHSTSTS_BUS_ERR) {
438 result = -EAGAIN;
439 dev_dbg(&priv->pci_dev->dev, "Lost arbitration\n");
440 }
441
442 /* Clear status flags except BYTE_DONE, to be cleared by caller */
443 outb_p(status, SMBHSTSTS(priv));
444
445 return result;
446 }
447
448 /* Wait for BUSY being cleared and either INTR or an error flag being set */
449 static int i801_wait_intr(struct i801_priv *priv)
450 {
451 int timeout = 0;
452 int status;
453
454 /* We will always wait for a fraction of a second! */
455 do {
456 usleep_range(250, 500);
457 status = inb_p(SMBHSTSTS(priv));
458 } while (((status & SMBHSTSTS_HOST_BUSY) ||
459 !(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR))) &&
460 (timeout++ < MAX_RETRIES));
461
462 if (timeout > MAX_RETRIES) {
463 dev_dbg(&priv->pci_dev->dev, "INTR Timeout!\n");
464 return -ETIMEDOUT;
465 }
466 return status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR);
467 }
468
469 /* Wait for either BYTE_DONE or an error flag being set */
470 static int i801_wait_byte_done(struct i801_priv *priv)
471 {
472 int timeout = 0;
473 int status;
474
475 /* We will always wait for a fraction of a second! */
476 do {
477 usleep_range(250, 500);
478 status = inb_p(SMBHSTSTS(priv));
479 } while (!(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_BYTE_DONE)) &&
480 (timeout++ < MAX_RETRIES));
481
482 if (timeout > MAX_RETRIES) {
483 dev_dbg(&priv->pci_dev->dev, "BYTE_DONE Timeout!\n");
484 return -ETIMEDOUT;
485 }
486 return status & STATUS_ERROR_FLAGS;
487 }
488
489 static int i801_transaction(struct i801_priv *priv, int xact)
490 {
491 int status;
492 int result;
493 const struct i2c_adapter *adap = &priv->adapter;
494
495 result = i801_check_pre(priv);
496 if (result < 0)
497 return result;
498
499 if (priv->features & FEATURE_IRQ) {
500 outb_p(xact | SMBHSTCNT_INTREN | SMBHSTCNT_START,
501 SMBHSTCNT(priv));
502 result = wait_event_timeout(priv->waitq,
503 (status = priv->status),
504 adap->timeout);
505 if (!result) {
506 status = -ETIMEDOUT;
507 dev_warn(&priv->pci_dev->dev,
508 "Timeout waiting for interrupt!\n");
509 }
510 priv->status = 0;
511 return i801_check_post(priv, status);
512 }
513
514 /* the current contents of SMBHSTCNT can be overwritten, since PEC,
515 * SMBSCMD are passed in xact */
516 outb_p(xact | SMBHSTCNT_START, SMBHSTCNT(priv));
517
518 status = i801_wait_intr(priv);
519 return i801_check_post(priv, status);
520 }
521
522 static int i801_block_transaction_by_block(struct i801_priv *priv,
523 union i2c_smbus_data *data,
524 char read_write, int command,
525 int hwpec)
526 {
527 int i, len;
528 int status;
529 int xact = hwpec ? SMBHSTCNT_PEC_EN : 0;
530
531 switch (command) {
532 case I2C_SMBUS_BLOCK_PROC_CALL:
533 xact |= I801_BLOCK_PROC_CALL;
534 break;
535 case I2C_SMBUS_BLOCK_DATA:
536 xact |= I801_BLOCK_DATA;
537 break;
538 default:
539 return -EOPNOTSUPP;
540 }
541
542 inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */
543
544 /* Use 32-byte buffer to process this transaction */
545 if (read_write == I2C_SMBUS_WRITE) {
546 len = data->block[0];
547 outb_p(len, SMBHSTDAT0(priv));
548 for (i = 0; i < len; i++)
549 outb_p(data->block[i+1], SMBBLKDAT(priv));
550 }
551
552 status = i801_transaction(priv, xact);
553 if (status)
554 return status;
555
556 if (read_write == I2C_SMBUS_READ ||
557 command == I2C_SMBUS_BLOCK_PROC_CALL) {
558 len = inb_p(SMBHSTDAT0(priv));
559 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX)
560 return -EPROTO;
561
562 data->block[0] = len;
563 for (i = 0; i < len; i++)
564 data->block[i + 1] = inb_p(SMBBLKDAT(priv));
565 }
566 return 0;
567 }
568
569 static void i801_isr_byte_done(struct i801_priv *priv)
570 {
571 if (priv->is_read) {
572 /* For SMBus block reads, length is received with first byte */
573 if (((priv->cmd & 0x1c) == I801_BLOCK_DATA) &&
574 (priv->count == 0)) {
575 priv->len = inb_p(SMBHSTDAT0(priv));
576 if (priv->len < 1 || priv->len > I2C_SMBUS_BLOCK_MAX) {
577 dev_err(&priv->pci_dev->dev,
578 "Illegal SMBus block read size %d\n",
579 priv->len);
580 /* FIXME: Recover */
581 priv->len = I2C_SMBUS_BLOCK_MAX;
582 } else {
583 dev_dbg(&priv->pci_dev->dev,
584 "SMBus block read size is %d\n",
585 priv->len);
586 }
587 priv->data[-1] = priv->len;
588 }
589
590 /* Read next byte */
591 if (priv->count < priv->len)
592 priv->data[priv->count++] = inb(SMBBLKDAT(priv));
593 else
594 dev_dbg(&priv->pci_dev->dev,
595 "Discarding extra byte on block read\n");
596
597 /* Set LAST_BYTE for last byte of read transaction */
598 if (priv->count == priv->len - 1)
599 outb_p(priv->cmd | SMBHSTCNT_LAST_BYTE,
600 SMBHSTCNT(priv));
601 } else if (priv->count < priv->len - 1) {
602 /* Write next byte, except for IRQ after last byte */
603 outb_p(priv->data[++priv->count], SMBBLKDAT(priv));
604 }
605
606 /* Clear BYTE_DONE to continue with next byte */
607 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv));
608 }
609
610 static irqreturn_t i801_host_notify_isr(struct i801_priv *priv)
611 {
612 unsigned short addr;
613
614 addr = inb_p(SMBNTFDADD(priv)) >> 1;
615
616 /*
617 * With the tested platforms, reading SMBNTFDDAT (22 + (p)->smba)
618 * always returns 0. Our current implementation doesn't provide
619 * data, so we just ignore it.
620 */
621 i2c_handle_smbus_host_notify(&priv->adapter, addr);
622
623 /* clear Host Notify bit and return */
624 outb_p(SMBSLVSTS_HST_NTFY_STS, SMBSLVSTS(priv));
625 return IRQ_HANDLED;
626 }
627
628 /*
629 * There are three kinds of interrupts:
630 *
631 * 1) i801 signals transaction completion with one of these interrupts:
632 * INTR - Success
633 * DEV_ERR - Invalid command, NAK or communication timeout
634 * BUS_ERR - SMI# transaction collision
635 * FAILED - transaction was canceled due to a KILL request
636 * When any of these occur, update ->status and wake up the waitq.
637 * ->status must be cleared before kicking off the next transaction.
638 *
639 * 2) For byte-by-byte (I2C read/write) transactions, one BYTE_DONE interrupt
640 * occurs for each byte of a byte-by-byte to prepare the next byte.
641 *
642 * 3) Host Notify interrupts
643 */
644 static irqreturn_t i801_isr(int irq, void *dev_id)
645 {
646 struct i801_priv *priv = dev_id;
647 u16 pcists;
648 u8 status;
649
650 /* Confirm this is our interrupt */
651 pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists);
652 if (!(pcists & SMBPCISTS_INTS))
653 return IRQ_NONE;
654
655 if (priv->features & FEATURE_HOST_NOTIFY) {
656 status = inb_p(SMBSLVSTS(priv));
657 if (status & SMBSLVSTS_HST_NTFY_STS)
658 return i801_host_notify_isr(priv);
659 }
660
661 status = inb_p(SMBHSTSTS(priv));
662 if (status & SMBHSTSTS_BYTE_DONE)
663 i801_isr_byte_done(priv);
664
665 /*
666 * Clear irq sources and report transaction result.
667 * ->status must be cleared before the next transaction is started.
668 */
669 status &= SMBHSTSTS_INTR | STATUS_ERROR_FLAGS;
670 if (status) {
671 outb_p(status, SMBHSTSTS(priv));
672 priv->status = status;
673 wake_up(&priv->waitq);
674 }
675
676 return IRQ_HANDLED;
677 }
678
679 /*
680 * For "byte-by-byte" block transactions:
681 * I2C write uses cmd=I801_BLOCK_DATA, I2C_EN=1
682 * I2C read uses cmd=I801_I2C_BLOCK_DATA
683 */
684 static int i801_block_transaction_byte_by_byte(struct i801_priv *priv,
685 union i2c_smbus_data *data,
686 char read_write, int command,
687 int hwpec)
688 {
689 int i, len;
690 int smbcmd;
691 int status;
692 int result;
693 const struct i2c_adapter *adap = &priv->adapter;
694
695 if (command == I2C_SMBUS_BLOCK_PROC_CALL)
696 return -EOPNOTSUPP;
697
698 result = i801_check_pre(priv);
699 if (result < 0)
700 return result;
701
702 len = data->block[0];
703
704 if (read_write == I2C_SMBUS_WRITE) {
705 outb_p(len, SMBHSTDAT0(priv));
706 outb_p(data->block[1], SMBBLKDAT(priv));
707 }
708
709 if (command == I2C_SMBUS_I2C_BLOCK_DATA &&
710 read_write == I2C_SMBUS_READ)
711 smbcmd = I801_I2C_BLOCK_DATA;
712 else
713 smbcmd = I801_BLOCK_DATA;
714
715 if (priv->features & FEATURE_IRQ) {
716 priv->is_read = (read_write == I2C_SMBUS_READ);
717 if (len == 1 && priv->is_read)
718 smbcmd |= SMBHSTCNT_LAST_BYTE;
719 priv->cmd = smbcmd | SMBHSTCNT_INTREN;
720 priv->len = len;
721 priv->count = 0;
722 priv->data = &data->block[1];
723
724 outb_p(priv->cmd | SMBHSTCNT_START, SMBHSTCNT(priv));
725 result = wait_event_timeout(priv->waitq,
726 (status = priv->status),
727 adap->timeout);
728 if (!result) {
729 status = -ETIMEDOUT;
730 dev_warn(&priv->pci_dev->dev,
731 "Timeout waiting for interrupt!\n");
732 }
733 priv->status = 0;
734 return i801_check_post(priv, status);
735 }
736
737 for (i = 1; i <= len; i++) {
738 if (i == len && read_write == I2C_SMBUS_READ)
739 smbcmd |= SMBHSTCNT_LAST_BYTE;
740 outb_p(smbcmd, SMBHSTCNT(priv));
741
742 if (i == 1)
743 outb_p(inb(SMBHSTCNT(priv)) | SMBHSTCNT_START,
744 SMBHSTCNT(priv));
745
746 status = i801_wait_byte_done(priv);
747 if (status)
748 goto exit;
749
750 if (i == 1 && read_write == I2C_SMBUS_READ
751 && command != I2C_SMBUS_I2C_BLOCK_DATA) {
752 len = inb_p(SMBHSTDAT0(priv));
753 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) {
754 dev_err(&priv->pci_dev->dev,
755 "Illegal SMBus block read size %d\n",
756 len);
757 /* Recover */
758 while (inb_p(SMBHSTSTS(priv)) &
759 SMBHSTSTS_HOST_BUSY)
760 outb_p(SMBHSTSTS_BYTE_DONE,
761 SMBHSTSTS(priv));
762 outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv));
763 return -EPROTO;
764 }
765 data->block[0] = len;
766 }
767
768 /* Retrieve/store value in SMBBLKDAT */
769 if (read_write == I2C_SMBUS_READ)
770 data->block[i] = inb_p(SMBBLKDAT(priv));
771 if (read_write == I2C_SMBUS_WRITE && i+1 <= len)
772 outb_p(data->block[i+1], SMBBLKDAT(priv));
773
774 /* signals SMBBLKDAT ready */
775 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv));
776 }
777
778 status = i801_wait_intr(priv);
779 exit:
780 return i801_check_post(priv, status);
781 }
782
783 static int i801_set_block_buffer_mode(struct i801_priv *priv)
784 {
785 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv));
786 if ((inb_p(SMBAUXCTL(priv)) & SMBAUXCTL_E32B) == 0)
787 return -EIO;
788 return 0;
789 }
790
791 /* Block transaction function */
792 static int i801_block_transaction(struct i801_priv *priv,
793 union i2c_smbus_data *data, char read_write,
794 int command, int hwpec)
795 {
796 int result = 0;
797 unsigned char hostc;
798
799 if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
800 if (read_write == I2C_SMBUS_WRITE) {
801 /* set I2C_EN bit in configuration register */
802 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc);
803 pci_write_config_byte(priv->pci_dev, SMBHSTCFG,
804 hostc | SMBHSTCFG_I2C_EN);
805 } else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) {
806 dev_err(&priv->pci_dev->dev,
807 "I2C block read is unsupported!\n");
808 return -EOPNOTSUPP;
809 }
810 }
811
812 if (read_write == I2C_SMBUS_WRITE
813 || command == I2C_SMBUS_I2C_BLOCK_DATA) {
814 if (data->block[0] < 1)
815 data->block[0] = 1;
816 if (data->block[0] > I2C_SMBUS_BLOCK_MAX)
817 data->block[0] = I2C_SMBUS_BLOCK_MAX;
818 } else {
819 data->block[0] = 32; /* max for SMBus block reads */
820 }
821
822 /* Experience has shown that the block buffer can only be used for
823 SMBus (not I2C) block transactions, even though the datasheet
824 doesn't mention this limitation. */
825 if ((priv->features & FEATURE_BLOCK_BUFFER)
826 && command != I2C_SMBUS_I2C_BLOCK_DATA
827 && i801_set_block_buffer_mode(priv) == 0)
828 result = i801_block_transaction_by_block(priv, data,
829 read_write,
830 command, hwpec);
831 else
832 result = i801_block_transaction_byte_by_byte(priv, data,
833 read_write,
834 command, hwpec);
835
836 if (command == I2C_SMBUS_I2C_BLOCK_DATA
837 && read_write == I2C_SMBUS_WRITE) {
838 /* restore saved configuration register value */
839 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc);
840 }
841 return result;
842 }
843
844 /* Return negative errno on error. */
845 static s32 i801_access(struct i2c_adapter *adap, u16 addr,
846 unsigned short flags, char read_write, u8 command,
847 int size, union i2c_smbus_data *data)
848 {
849 int hwpec;
850 int block = 0;
851 int ret = 0, xact = 0;
852 struct i801_priv *priv = i2c_get_adapdata(adap);
853
854 mutex_lock(&priv->acpi_lock);
855 if (priv->acpi_reserved) {
856 mutex_unlock(&priv->acpi_lock);
857 return -EBUSY;
858 }
859
860 pm_runtime_get_sync(&priv->pci_dev->dev);
861
862 hwpec = (priv->features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC)
863 && size != I2C_SMBUS_QUICK
864 && size != I2C_SMBUS_I2C_BLOCK_DATA;
865
866 switch (size) {
867 case I2C_SMBUS_QUICK:
868 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
869 SMBHSTADD(priv));
870 xact = I801_QUICK;
871 break;
872 case I2C_SMBUS_BYTE:
873 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
874 SMBHSTADD(priv));
875 if (read_write == I2C_SMBUS_WRITE)
876 outb_p(command, SMBHSTCMD(priv));
877 xact = I801_BYTE;
878 break;
879 case I2C_SMBUS_BYTE_DATA:
880 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
881 SMBHSTADD(priv));
882 outb_p(command, SMBHSTCMD(priv));
883 if (read_write == I2C_SMBUS_WRITE)
884 outb_p(data->byte, SMBHSTDAT0(priv));
885 xact = I801_BYTE_DATA;
886 break;
887 case I2C_SMBUS_WORD_DATA:
888 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
889 SMBHSTADD(priv));
890 outb_p(command, SMBHSTCMD(priv));
891 if (read_write == I2C_SMBUS_WRITE) {
892 outb_p(data->word & 0xff, SMBHSTDAT0(priv));
893 outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv));
894 }
895 xact = I801_WORD_DATA;
896 break;
897 case I2C_SMBUS_BLOCK_DATA:
898 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
899 SMBHSTADD(priv));
900 outb_p(command, SMBHSTCMD(priv));
901 block = 1;
902 break;
903 case I2C_SMBUS_I2C_BLOCK_DATA:
904 /*
905 * NB: page 240 of ICH5 datasheet shows that the R/#W
906 * bit should be cleared here, even when reading.
907 * However if SPD Write Disable is set (Lynx Point and later),
908 * the read will fail if we don't set the R/#W bit.
909 */
910 outb_p(((addr & 0x7f) << 1) |
911 ((priv->original_hstcfg & SMBHSTCFG_SPD_WD) ?
912 (read_write & 0x01) : 0),
913 SMBHSTADD(priv));
914 if (read_write == I2C_SMBUS_READ) {
915 /* NB: page 240 of ICH5 datasheet also shows
916 * that DATA1 is the cmd field when reading */
917 outb_p(command, SMBHSTDAT1(priv));
918 } else
919 outb_p(command, SMBHSTCMD(priv));
920 block = 1;
921 break;
922 case I2C_SMBUS_BLOCK_PROC_CALL:
923 /*
924 * Bit 0 of the slave address register always indicate a write
925 * command.
926 */
927 outb_p((addr & 0x7f) << 1, SMBHSTADD(priv));
928 outb_p(command, SMBHSTCMD(priv));
929 block = 1;
930 break;
931 default:
932 dev_err(&priv->pci_dev->dev, "Unsupported transaction %d\n",
933 size);
934 ret = -EOPNOTSUPP;
935 goto out;
936 }
937
938 if (hwpec) /* enable/disable hardware PEC */
939 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv));
940 else
941 outb_p(inb_p(SMBAUXCTL(priv)) & (~SMBAUXCTL_CRC),
942 SMBAUXCTL(priv));
943
944 if (block)
945 ret = i801_block_transaction(priv, data, read_write, size,
946 hwpec);
947 else
948 ret = i801_transaction(priv, xact);
949
950 /* Some BIOSes don't like it when PEC is enabled at reboot or resume
951 time, so we forcibly disable it after every transaction. Turn off
952 E32B for the same reason. */
953 if (hwpec || block)
954 outb_p(inb_p(SMBAUXCTL(priv)) &
955 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
956
957 if (block)
958 goto out;
959 if (ret)
960 goto out;
961 if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK))
962 goto out;
963
964 switch (xact & 0x7f) {
965 case I801_BYTE: /* Result put in SMBHSTDAT0 */
966 case I801_BYTE_DATA:
967 data->byte = inb_p(SMBHSTDAT0(priv));
968 break;
969 case I801_WORD_DATA:
970 data->word = inb_p(SMBHSTDAT0(priv)) +
971 (inb_p(SMBHSTDAT1(priv)) << 8);
972 break;
973 }
974
975 out:
976 pm_runtime_mark_last_busy(&priv->pci_dev->dev);
977 pm_runtime_put_autosuspend(&priv->pci_dev->dev);
978 mutex_unlock(&priv->acpi_lock);
979 return ret;
980 }
981
982
983 static u32 i801_func(struct i2c_adapter *adapter)
984 {
985 struct i801_priv *priv = i2c_get_adapdata(adapter);
986
987 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
988 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
989 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK |
990 ((priv->features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) |
991 ((priv->features & FEATURE_BLOCK_PROC) ?
992 I2C_FUNC_SMBUS_BLOCK_PROC_CALL : 0) |
993 ((priv->features & FEATURE_I2C_BLOCK_READ) ?
994 I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0) |
995 ((priv->features & FEATURE_HOST_NOTIFY) ?
996 I2C_FUNC_SMBUS_HOST_NOTIFY : 0);
997 }
998
999 static void i801_enable_host_notify(struct i2c_adapter *adapter)
1000 {
1001 struct i801_priv *priv = i2c_get_adapdata(adapter);
1002
1003 if (!(priv->features & FEATURE_HOST_NOTIFY))
1004 return;
1005
1006 if (!(SMBSLVCMD_HST_NTFY_INTREN & priv->original_slvcmd))
1007 outb_p(SMBSLVCMD_HST_NTFY_INTREN | priv->original_slvcmd,
1008 SMBSLVCMD(priv));
1009
1010 /* clear Host Notify bit to allow a new notification */
1011 outb_p(SMBSLVSTS_HST_NTFY_STS, SMBSLVSTS(priv));
1012 }
1013
1014 static void i801_disable_host_notify(struct i801_priv *priv)
1015 {
1016 if (!(priv->features & FEATURE_HOST_NOTIFY))
1017 return;
1018
1019 outb_p(priv->original_slvcmd, SMBSLVCMD(priv));
1020 }
1021
1022 static const struct i2c_algorithm smbus_algorithm = {
1023 .smbus_xfer = i801_access,
1024 .functionality = i801_func,
1025 };
1026
1027 static const struct pci_device_id i801_ids[] = {
1028 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) },
1029 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) },
1030 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) },
1031 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) },
1032 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) },
1033 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) },
1034 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) },
1035 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) },
1036 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) },
1037 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) },
1038 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) },
1039 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_6) },
1040 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EP80579_1) },
1041 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_4) },
1042 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_5) },
1043 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS) },
1044 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS) },
1045 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS) },
1046 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0) },
1047 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1) },
1048 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2) },
1049 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS) },
1050 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS) },
1051 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS) },
1052 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS) },
1053 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_AVOTON_SMBUS) },
1054 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS) },
1055 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0) },
1056 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1) },
1057 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2) },
1058 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS) },
1059 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_GEMINILAKE_SMBUS) },
1060 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS) },
1061 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS) },
1062 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS) },
1063 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS) },
1064 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS) },
1065 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS) },
1066 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CDF_SMBUS) },
1067 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DNV_SMBUS) },
1068 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BROXTON_SMBUS) },
1069 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS) },
1070 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS) },
1071 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS) },
1072 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS) },
1073 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS) },
1074 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICELAKE_LP_SMBUS) },
1075 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COMETLAKE_SMBUS) },
1076 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COMETLAKE_H_SMBUS) },
1077 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ELKHART_LAKE_SMBUS) },
1078 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TIGERLAKE_LP_SMBUS) },
1079 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_JASPER_LAKE_SMBUS) },
1080 { 0, }
1081 };
1082
1083 MODULE_DEVICE_TABLE(pci, i801_ids);
1084
1085 #if defined CONFIG_X86 && defined CONFIG_DMI
1086 static unsigned char apanel_addr;
1087
1088 /* Scan the system ROM for the signature "FJKEYINF" */
1089 static __init const void __iomem *bios_signature(const void __iomem *bios)
1090 {
1091 ssize_t offset;
1092 const unsigned char signature[] = "FJKEYINF";
1093
1094 for (offset = 0; offset < 0x10000; offset += 0x10) {
1095 if (check_signature(bios + offset, signature,
1096 sizeof(signature)-1))
1097 return bios + offset;
1098 }
1099 return NULL;
1100 }
1101
1102 static void __init input_apanel_init(void)
1103 {
1104 void __iomem *bios;
1105 const void __iomem *p;
1106
1107 bios = ioremap(0xF0000, 0x10000); /* Can't fail */
1108 p = bios_signature(bios);
1109 if (p) {
1110 /* just use the first address */
1111 apanel_addr = readb(p + 8 + 3) >> 1;
1112 }
1113 iounmap(bios);
1114 }
1115
1116 struct dmi_onboard_device_info {
1117 const char *name;
1118 u8 type;
1119 unsigned short i2c_addr;
1120 const char *i2c_type;
1121 };
1122
1123 static const struct dmi_onboard_device_info dmi_devices[] = {
1124 { "Syleus", DMI_DEV_TYPE_OTHER, 0x73, "fscsyl" },
1125 { "Hermes", DMI_DEV_TYPE_OTHER, 0x73, "fscher" },
1126 { "Hades", DMI_DEV_TYPE_OTHER, 0x73, "fschds" },
1127 };
1128
1129 static void dmi_check_onboard_device(u8 type, const char *name,
1130 struct i2c_adapter *adap)
1131 {
1132 int i;
1133 struct i2c_board_info info;
1134
1135 for (i = 0; i < ARRAY_SIZE(dmi_devices); i++) {
1136 /* & ~0x80, ignore enabled/disabled bit */
1137 if ((type & ~0x80) != dmi_devices[i].type)
1138 continue;
1139 if (strcasecmp(name, dmi_devices[i].name))
1140 continue;
1141
1142 memset(&info, 0, sizeof(struct i2c_board_info));
1143 info.addr = dmi_devices[i].i2c_addr;
1144 strlcpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE);
1145 i2c_new_device(adap, &info);
1146 break;
1147 }
1148 }
1149
1150 /* We use our own function to check for onboard devices instead of
1151 dmi_find_device() as some buggy BIOS's have the devices we are interested
1152 in marked as disabled */
1153 static void dmi_check_onboard_devices(const struct dmi_header *dm, void *adap)
1154 {
1155 int i, count;
1156
1157 if (dm->type != 10)
1158 return;
1159
1160 count = (dm->length - sizeof(struct dmi_header)) / 2;
1161 for (i = 0; i < count; i++) {
1162 const u8 *d = (char *)(dm + 1) + (i * 2);
1163 const char *name = ((char *) dm) + dm->length;
1164 u8 type = d[0];
1165 u8 s = d[1];
1166
1167 if (!s)
1168 continue;
1169 s--;
1170 while (s > 0 && name[0]) {
1171 name += strlen(name) + 1;
1172 s--;
1173 }
1174 if (name[0] == 0) /* Bogus string reference */
1175 continue;
1176
1177 dmi_check_onboard_device(type, name, adap);
1178 }
1179 }
1180
1181 /* NOTE: Keep this list in sync with drivers/platform/x86/dell-smo8800.c */
1182 static const char *const acpi_smo8800_ids[] = {
1183 "SMO8800",
1184 "SMO8801",
1185 "SMO8810",
1186 "SMO8811",
1187 "SMO8820",
1188 "SMO8821",
1189 "SMO8830",
1190 "SMO8831",
1191 };
1192
1193 static acpi_status check_acpi_smo88xx_device(acpi_handle obj_handle,
1194 u32 nesting_level,
1195 void *context,
1196 void **return_value)
1197 {
1198 struct acpi_device_info *info;
1199 acpi_status status;
1200 char *hid;
1201 int i;
1202
1203 status = acpi_get_object_info(obj_handle, &info);
1204 if (ACPI_FAILURE(status))
1205 return AE_OK;
1206
1207 if (!(info->valid & ACPI_VALID_HID))
1208 goto smo88xx_not_found;
1209
1210 hid = info->hardware_id.string;
1211 if (!hid)
1212 goto smo88xx_not_found;
1213
1214 i = match_string(acpi_smo8800_ids, ARRAY_SIZE(acpi_smo8800_ids), hid);
1215 if (i < 0)
1216 goto smo88xx_not_found;
1217
1218 kfree(info);
1219
1220 *((bool *)return_value) = true;
1221 return AE_CTRL_TERMINATE;
1222
1223 smo88xx_not_found:
1224 kfree(info);
1225 return AE_OK;
1226 }
1227
1228 static bool is_dell_system_with_lis3lv02d(void)
1229 {
1230 bool found;
1231 const char *vendor;
1232
1233 vendor = dmi_get_system_info(DMI_SYS_VENDOR);
1234 if (!vendor || strcmp(vendor, "Dell Inc."))
1235 return false;
1236
1237 /*
1238 * Check that ACPI device SMO88xx is present and is functioning.
1239 * Function acpi_get_devices() already filters all ACPI devices
1240 * which are not present or are not functioning.
1241 * ACPI device SMO88xx represents our ST microelectronics lis3lv02d
1242 * accelerometer but unfortunately ACPI does not provide any other
1243 * information (like I2C address).
1244 */
1245 found = false;
1246 acpi_get_devices(NULL, check_acpi_smo88xx_device, NULL,
1247 (void **)&found);
1248
1249 return found;
1250 }
1251
1252 /*
1253 * Accelerometer's I2C address is not specified in DMI nor ACPI,
1254 * so it is needed to define mapping table based on DMI product names.
1255 */
1256 static const struct {
1257 const char *dmi_product_name;
1258 unsigned short i2c_addr;
1259 } dell_lis3lv02d_devices[] = {
1260 /*
1261 * Dell platform team told us that these Latitude devices have
1262 * ST microelectronics accelerometer at I2C address 0x29.
1263 */
1264 { "Latitude E5250", 0x29 },
1265 { "Latitude E5450", 0x29 },
1266 { "Latitude E5550", 0x29 },
1267 { "Latitude E6440", 0x29 },
1268 { "Latitude E6440 ATG", 0x29 },
1269 { "Latitude E6540", 0x29 },
1270 /*
1271 * Additional individual entries were added after verification.
1272 */
1273 { "Vostro V131", 0x1d },
1274 };
1275
1276 static void register_dell_lis3lv02d_i2c_device(struct i801_priv *priv)
1277 {
1278 struct i2c_board_info info;
1279 const char *dmi_product_name;
1280 int i;
1281
1282 dmi_product_name = dmi_get_system_info(DMI_PRODUCT_NAME);
1283 for (i = 0; i < ARRAY_SIZE(dell_lis3lv02d_devices); ++i) {
1284 if (strcmp(dmi_product_name,
1285 dell_lis3lv02d_devices[i].dmi_product_name) == 0)
1286 break;
1287 }
1288
1289 if (i == ARRAY_SIZE(dell_lis3lv02d_devices)) {
1290 dev_warn(&priv->pci_dev->dev,
1291 "Accelerometer lis3lv02d is present on SMBus but its"
1292 " address is unknown, skipping registration\n");
1293 return;
1294 }
1295
1296 memset(&info, 0, sizeof(struct i2c_board_info));
1297 info.addr = dell_lis3lv02d_devices[i].i2c_addr;
1298 strlcpy(info.type, "lis3lv02d", I2C_NAME_SIZE);
1299 i2c_new_device(&priv->adapter, &info);
1300 }
1301
1302 /* Register optional slaves */
1303 static void i801_probe_optional_slaves(struct i801_priv *priv)
1304 {
1305 /* Only register slaves on main SMBus channel */
1306 if (priv->features & FEATURE_IDF)
1307 return;
1308
1309 if (apanel_addr) {
1310 struct i2c_board_info info;
1311
1312 memset(&info, 0, sizeof(struct i2c_board_info));
1313 info.addr = apanel_addr;
1314 strlcpy(info.type, "fujitsu_apanel", I2C_NAME_SIZE);
1315 i2c_new_device(&priv->adapter, &info);
1316 }
1317
1318 if (dmi_name_in_vendors("FUJITSU"))
1319 dmi_walk(dmi_check_onboard_devices, &priv->adapter);
1320
1321 if (is_dell_system_with_lis3lv02d())
1322 register_dell_lis3lv02d_i2c_device(priv);
1323 }
1324 #else
1325 static void __init input_apanel_init(void) {}
1326 static void i801_probe_optional_slaves(struct i801_priv *priv) {}
1327 #endif /* CONFIG_X86 && CONFIG_DMI */
1328
1329 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI
1330 static struct i801_mux_config i801_mux_config_asus_z8_d12 = {
1331 .gpio_chip = "gpio_ich",
1332 .values = { 0x02, 0x03 },
1333 .n_values = 2,
1334 .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD },
1335 .gpios = { 52, 53 },
1336 .n_gpios = 2,
1337 };
1338
1339 static struct i801_mux_config i801_mux_config_asus_z8_d18 = {
1340 .gpio_chip = "gpio_ich",
1341 .values = { 0x02, 0x03, 0x01 },
1342 .n_values = 3,
1343 .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD, I2C_CLASS_SPD },
1344 .gpios = { 52, 53 },
1345 .n_gpios = 2,
1346 };
1347
1348 static const struct dmi_system_id mux_dmi_table[] = {
1349 {
1350 .matches = {
1351 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1352 DMI_MATCH(DMI_BOARD_NAME, "Z8NA-D6(C)"),
1353 },
1354 .driver_data = &i801_mux_config_asus_z8_d12,
1355 },
1356 {
1357 .matches = {
1358 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1359 DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)E-D12(X)"),
1360 },
1361 .driver_data = &i801_mux_config_asus_z8_d12,
1362 },
1363 {
1364 .matches = {
1365 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1366 DMI_MATCH(DMI_BOARD_NAME, "Z8NH-D12"),
1367 },
1368 .driver_data = &i801_mux_config_asus_z8_d12,
1369 },
1370 {
1371 .matches = {
1372 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1373 DMI_MATCH(DMI_BOARD_NAME, "Z8PH-D12/IFB"),
1374 },
1375 .driver_data = &i801_mux_config_asus_z8_d12,
1376 },
1377 {
1378 .matches = {
1379 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1380 DMI_MATCH(DMI_BOARD_NAME, "Z8NR-D12"),
1381 },
1382 .driver_data = &i801_mux_config_asus_z8_d12,
1383 },
1384 {
1385 .matches = {
1386 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1387 DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)H-D12"),
1388 },
1389 .driver_data = &i801_mux_config_asus_z8_d12,
1390 },
1391 {
1392 .matches = {
1393 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1394 DMI_MATCH(DMI_BOARD_NAME, "Z8PG-D18"),
1395 },
1396 .driver_data = &i801_mux_config_asus_z8_d18,
1397 },
1398 {
1399 .matches = {
1400 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1401 DMI_MATCH(DMI_BOARD_NAME, "Z8PE-D18"),
1402 },
1403 .driver_data = &i801_mux_config_asus_z8_d18,
1404 },
1405 {
1406 .matches = {
1407 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1408 DMI_MATCH(DMI_BOARD_NAME, "Z8PS-D12"),
1409 },
1410 .driver_data = &i801_mux_config_asus_z8_d12,
1411 },
1412 { }
1413 };
1414
1415 /* Setup multiplexing if needed */
1416 static int i801_add_mux(struct i801_priv *priv)
1417 {
1418 struct device *dev = &priv->adapter.dev;
1419 const struct i801_mux_config *mux_config;
1420 struct i2c_mux_gpio_platform_data gpio_data;
1421 struct gpiod_lookup_table *lookup;
1422 int err, i;
1423
1424 if (!priv->mux_drvdata)
1425 return 0;
1426 mux_config = priv->mux_drvdata;
1427
1428 /* Prepare the platform data */
1429 memset(&gpio_data, 0, sizeof(struct i2c_mux_gpio_platform_data));
1430 gpio_data.parent = priv->adapter.nr;
1431 gpio_data.values = mux_config->values;
1432 gpio_data.n_values = mux_config->n_values;
1433 gpio_data.classes = mux_config->classes;
1434 gpio_data.idle = I2C_MUX_GPIO_NO_IDLE;
1435
1436 /* Register GPIO descriptor lookup table */
1437 lookup = devm_kzalloc(dev,
1438 struct_size(lookup, table, mux_config->n_gpios),
1439 GFP_KERNEL);
1440 if (!lookup)
1441 return -ENOMEM;
1442 lookup->dev_id = "i2c-mux-gpio";
1443 for (i = 0; i < mux_config->n_gpios; i++) {
1444 lookup->table[i].chip_label = mux_config->gpio_chip;
1445 lookup->table[i].chip_hwnum = mux_config->gpios[i];
1446 lookup->table[i].con_id = "mux";
1447 }
1448 gpiod_add_lookup_table(lookup);
1449 priv->lookup = lookup;
1450
1451 /*
1452 * Register the mux device, we use PLATFORM_DEVID_NONE here
1453 * because since we are referring to the GPIO chip by name we are
1454 * anyways in deep trouble if there is more than one of these
1455 * devices, and there should likely only be one platform controller
1456 * hub.
1457 */
1458 priv->mux_pdev = platform_device_register_data(dev, "i2c-mux-gpio",
1459 PLATFORM_DEVID_NONE, &gpio_data,
1460 sizeof(struct i2c_mux_gpio_platform_data));
1461 if (IS_ERR(priv->mux_pdev)) {
1462 err = PTR_ERR(priv->mux_pdev);
1463 gpiod_remove_lookup_table(lookup);
1464 priv->mux_pdev = NULL;
1465 dev_err(dev, "Failed to register i2c-mux-gpio device\n");
1466 return err;
1467 }
1468
1469 return 0;
1470 }
1471
1472 static void i801_del_mux(struct i801_priv *priv)
1473 {
1474 if (priv->mux_pdev)
1475 platform_device_unregister(priv->mux_pdev);
1476 if (priv->lookup)
1477 gpiod_remove_lookup_table(priv->lookup);
1478 }
1479
1480 static unsigned int i801_get_adapter_class(struct i801_priv *priv)
1481 {
1482 const struct dmi_system_id *id;
1483 const struct i801_mux_config *mux_config;
1484 unsigned int class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
1485 int i;
1486
1487 id = dmi_first_match(mux_dmi_table);
1488 if (id) {
1489 /* Remove branch classes from trunk */
1490 mux_config = id->driver_data;
1491 for (i = 0; i < mux_config->n_values; i++)
1492 class &= ~mux_config->classes[i];
1493
1494 /* Remember for later */
1495 priv->mux_drvdata = mux_config;
1496 }
1497
1498 return class;
1499 }
1500 #else
1501 static inline int i801_add_mux(struct i801_priv *priv) { return 0; }
1502 static inline void i801_del_mux(struct i801_priv *priv) { }
1503
1504 static inline unsigned int i801_get_adapter_class(struct i801_priv *priv)
1505 {
1506 return I2C_CLASS_HWMON | I2C_CLASS_SPD;
1507 }
1508 #endif
1509
1510 static const struct itco_wdt_platform_data spt_tco_platform_data = {
1511 .name = "Intel PCH",
1512 .version = 4,
1513 };
1514
1515 static DEFINE_SPINLOCK(p2sb_spinlock);
1516
1517 static struct platform_device *
1518 i801_add_tco_spt(struct i801_priv *priv, struct pci_dev *pci_dev,
1519 struct resource *tco_res)
1520 {
1521 struct resource *res;
1522 unsigned int devfn;
1523 u64 base64_addr;
1524 u32 base_addr;
1525 u8 hidden;
1526
1527 /*
1528 * We must access the NO_REBOOT bit over the Primary to Sideband
1529 * bridge (P2SB). The BIOS prevents the P2SB device from being
1530 * enumerated by the PCI subsystem, so we need to unhide/hide it
1531 * to lookup the P2SB BAR.
1532 */
1533 spin_lock(&p2sb_spinlock);
1534
1535 devfn = PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 1);
1536
1537 /* Unhide the P2SB device, if it is hidden */
1538 pci_bus_read_config_byte(pci_dev->bus, devfn, 0xe1, &hidden);
1539 if (hidden)
1540 pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, 0x0);
1541
1542 pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR, &base_addr);
1543 base64_addr = base_addr & 0xfffffff0;
1544
1545 pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR + 0x4, &base_addr);
1546 base64_addr |= (u64)base_addr << 32;
1547
1548 /* Hide the P2SB device, if it was hidden before */
1549 if (hidden)
1550 pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, hidden);
1551 spin_unlock(&p2sb_spinlock);
1552
1553 res = &tco_res[ICH_RES_MEM_OFF];
1554 if (pci_dev->device == PCI_DEVICE_ID_INTEL_DNV_SMBUS)
1555 res->start = (resource_size_t)base64_addr + SBREG_SMBCTRL_DNV;
1556 else
1557 res->start = (resource_size_t)base64_addr + SBREG_SMBCTRL;
1558
1559 res->end = res->start + 3;
1560 res->flags = IORESOURCE_MEM;
1561
1562 return platform_device_register_resndata(&pci_dev->dev, "iTCO_wdt", -1,
1563 tco_res, 3, &spt_tco_platform_data,
1564 sizeof(spt_tco_platform_data));
1565 }
1566
1567 static const struct itco_wdt_platform_data cnl_tco_platform_data = {
1568 .name = "Intel PCH",
1569 .version = 6,
1570 };
1571
1572 static struct platform_device *
1573 i801_add_tco_cnl(struct i801_priv *priv, struct pci_dev *pci_dev,
1574 struct resource *tco_res)
1575 {
1576 return platform_device_register_resndata(&pci_dev->dev, "iTCO_wdt", -1,
1577 tco_res, 2, &cnl_tco_platform_data,
1578 sizeof(cnl_tco_platform_data));
1579 }
1580
1581 static void i801_add_tco(struct i801_priv *priv)
1582 {
1583 u32 base_addr, tco_base, tco_ctl, ctrl_val;
1584 struct pci_dev *pci_dev = priv->pci_dev;
1585 struct resource tco_res[3], *res;
1586 unsigned int devfn;
1587
1588 /* If we have ACPI based watchdog use that instead */
1589 if (acpi_has_watchdog())
1590 return;
1591
1592 if (!(priv->features & (FEATURE_TCO_SPT | FEATURE_TCO_CNL)))
1593 return;
1594
1595 pci_read_config_dword(pci_dev, TCOBASE, &tco_base);
1596 pci_read_config_dword(pci_dev, TCOCTL, &tco_ctl);
1597 if (!(tco_ctl & TCOCTL_EN))
1598 return;
1599
1600 memset(tco_res, 0, sizeof(tco_res));
1601
1602 res = &tco_res[ICH_RES_IO_TCO];
1603 res->start = tco_base & ~1;
1604 res->end = res->start + 32 - 1;
1605 res->flags = IORESOURCE_IO;
1606
1607 /*
1608 * Power Management registers.
1609 */
1610 devfn = PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 2);
1611 pci_bus_read_config_dword(pci_dev->bus, devfn, ACPIBASE, &base_addr);
1612
1613 res = &tco_res[ICH_RES_IO_SMI];
1614 res->start = (base_addr & ~1) + ACPIBASE_SMI_OFF;
1615 res->end = res->start + 3;
1616 res->flags = IORESOURCE_IO;
1617
1618 /*
1619 * Enable the ACPI I/O space.
1620 */
1621 pci_bus_read_config_dword(pci_dev->bus, devfn, ACPICTRL, &ctrl_val);
1622 ctrl_val |= ACPICTRL_EN;
1623 pci_bus_write_config_dword(pci_dev->bus, devfn, ACPICTRL, ctrl_val);
1624
1625 if (priv->features & FEATURE_TCO_CNL)
1626 priv->tco_pdev = i801_add_tco_cnl(priv, pci_dev, tco_res);
1627 else
1628 priv->tco_pdev = i801_add_tco_spt(priv, pci_dev, tco_res);
1629
1630 if (IS_ERR(priv->tco_pdev))
1631 dev_warn(&pci_dev->dev, "failed to create iTCO device\n");
1632 }
1633
1634 #ifdef CONFIG_ACPI
1635 static bool i801_acpi_is_smbus_ioport(const struct i801_priv *priv,
1636 acpi_physical_address address)
1637 {
1638 return address >= priv->smba &&
1639 address <= pci_resource_end(priv->pci_dev, SMBBAR);
1640 }
1641
1642 static acpi_status
1643 i801_acpi_io_handler(u32 function, acpi_physical_address address, u32 bits,
1644 u64 *value, void *handler_context, void *region_context)
1645 {
1646 struct i801_priv *priv = handler_context;
1647 struct pci_dev *pdev = priv->pci_dev;
1648 acpi_status status;
1649
1650 /*
1651 * Once BIOS AML code touches the OpRegion we warn and inhibit any
1652 * further access from the driver itself. This device is now owned
1653 * by the system firmware.
1654 */
1655 mutex_lock(&priv->acpi_lock);
1656
1657 if (!priv->acpi_reserved && i801_acpi_is_smbus_ioport(priv, address)) {
1658 priv->acpi_reserved = true;
1659
1660 dev_warn(&pdev->dev, "BIOS is accessing SMBus registers\n");
1661 dev_warn(&pdev->dev, "Driver SMBus register access inhibited\n");
1662
1663 /*
1664 * BIOS is accessing the host controller so prevent it from
1665 * suspending automatically from now on.
1666 */
1667 pm_runtime_get_sync(&pdev->dev);
1668 }
1669
1670 if ((function & ACPI_IO_MASK) == ACPI_READ)
1671 status = acpi_os_read_port(address, (u32 *)value, bits);
1672 else
1673 status = acpi_os_write_port(address, (u32)*value, bits);
1674
1675 mutex_unlock(&priv->acpi_lock);
1676
1677 return status;
1678 }
1679
1680 static int i801_acpi_probe(struct i801_priv *priv)
1681 {
1682 struct acpi_device *adev;
1683 acpi_status status;
1684
1685 adev = ACPI_COMPANION(&priv->pci_dev->dev);
1686 if (adev) {
1687 status = acpi_install_address_space_handler(adev->handle,
1688 ACPI_ADR_SPACE_SYSTEM_IO, i801_acpi_io_handler,
1689 NULL, priv);
1690 if (ACPI_SUCCESS(status))
1691 return 0;
1692 }
1693
1694 return acpi_check_resource_conflict(&priv->pci_dev->resource[SMBBAR]);
1695 }
1696
1697 static void i801_acpi_remove(struct i801_priv *priv)
1698 {
1699 struct acpi_device *adev;
1700
1701 adev = ACPI_COMPANION(&priv->pci_dev->dev);
1702 if (!adev)
1703 return;
1704
1705 acpi_remove_address_space_handler(adev->handle,
1706 ACPI_ADR_SPACE_SYSTEM_IO, i801_acpi_io_handler);
1707
1708 mutex_lock(&priv->acpi_lock);
1709 if (priv->acpi_reserved)
1710 pm_runtime_put(&priv->pci_dev->dev);
1711 mutex_unlock(&priv->acpi_lock);
1712 }
1713 #else
1714 static inline int i801_acpi_probe(struct i801_priv *priv) { return 0; }
1715 static inline void i801_acpi_remove(struct i801_priv *priv) { }
1716 #endif
1717
1718 static int i801_probe(struct pci_dev *dev, const struct pci_device_id *id)
1719 {
1720 unsigned char temp;
1721 int err, i;
1722 struct i801_priv *priv;
1723
1724 priv = devm_kzalloc(&dev->dev, sizeof(*priv), GFP_KERNEL);
1725 if (!priv)
1726 return -ENOMEM;
1727
1728 i2c_set_adapdata(&priv->adapter, priv);
1729 priv->adapter.owner = THIS_MODULE;
1730 priv->adapter.class = i801_get_adapter_class(priv);
1731 priv->adapter.algo = &smbus_algorithm;
1732 priv->adapter.dev.parent = &dev->dev;
1733 ACPI_COMPANION_SET(&priv->adapter.dev, ACPI_COMPANION(&dev->dev));
1734 priv->adapter.retries = 3;
1735 mutex_init(&priv->acpi_lock);
1736
1737 priv->pci_dev = dev;
1738 switch (dev->device) {
1739 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS:
1740 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS:
1741 case PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS:
1742 case PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS:
1743 case PCI_DEVICE_ID_INTEL_DNV_SMBUS:
1744 case PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS:
1745 priv->features |= FEATURE_BLOCK_PROC;
1746 priv->features |= FEATURE_I2C_BLOCK_READ;
1747 priv->features |= FEATURE_IRQ;
1748 priv->features |= FEATURE_SMBUS_PEC;
1749 priv->features |= FEATURE_BLOCK_BUFFER;
1750 priv->features |= FEATURE_TCO_SPT;
1751 priv->features |= FEATURE_HOST_NOTIFY;
1752 break;
1753
1754 case PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS:
1755 case PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS:
1756 case PCI_DEVICE_ID_INTEL_CDF_SMBUS:
1757 case PCI_DEVICE_ID_INTEL_ICELAKE_LP_SMBUS:
1758 case PCI_DEVICE_ID_INTEL_COMETLAKE_SMBUS:
1759 case PCI_DEVICE_ID_INTEL_COMETLAKE_H_SMBUS:
1760 case PCI_DEVICE_ID_INTEL_ELKHART_LAKE_SMBUS:
1761 case PCI_DEVICE_ID_INTEL_TIGERLAKE_LP_SMBUS:
1762 case PCI_DEVICE_ID_INTEL_JASPER_LAKE_SMBUS:
1763 priv->features |= FEATURE_BLOCK_PROC;
1764 priv->features |= FEATURE_I2C_BLOCK_READ;
1765 priv->features |= FEATURE_IRQ;
1766 priv->features |= FEATURE_SMBUS_PEC;
1767 priv->features |= FEATURE_BLOCK_BUFFER;
1768 priv->features |= FEATURE_TCO_CNL;
1769 priv->features |= FEATURE_HOST_NOTIFY;
1770 break;
1771
1772 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0:
1773 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1:
1774 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2:
1775 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0:
1776 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1:
1777 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2:
1778 priv->features |= FEATURE_IDF;
1779 /* fall through */
1780 default:
1781 priv->features |= FEATURE_BLOCK_PROC;
1782 priv->features |= FEATURE_I2C_BLOCK_READ;
1783 priv->features |= FEATURE_IRQ;
1784 /* fall through */
1785 case PCI_DEVICE_ID_INTEL_82801DB_3:
1786 priv->features |= FEATURE_SMBUS_PEC;
1787 priv->features |= FEATURE_BLOCK_BUFFER;
1788 /* fall through */
1789 case PCI_DEVICE_ID_INTEL_82801CA_3:
1790 priv->features |= FEATURE_HOST_NOTIFY;
1791 /* fall through */
1792 case PCI_DEVICE_ID_INTEL_82801BA_2:
1793 case PCI_DEVICE_ID_INTEL_82801AB_3:
1794 case PCI_DEVICE_ID_INTEL_82801AA_3:
1795 break;
1796 }
1797
1798 /* Disable features on user request */
1799 for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) {
1800 if (priv->features & disable_features & (1 << i))
1801 dev_notice(&dev->dev, "%s disabled by user\n",
1802 i801_feature_names[i]);
1803 }
1804 priv->features &= ~disable_features;
1805
1806 err = pcim_enable_device(dev);
1807 if (err) {
1808 dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n",
1809 err);
1810 return err;
1811 }
1812 pcim_pin_device(dev);
1813
1814 /* Determine the address of the SMBus area */
1815 priv->smba = pci_resource_start(dev, SMBBAR);
1816 if (!priv->smba) {
1817 dev_err(&dev->dev,
1818 "SMBus base address uninitialized, upgrade BIOS\n");
1819 return -ENODEV;
1820 }
1821
1822 if (i801_acpi_probe(priv))
1823 return -ENODEV;
1824
1825 err = pcim_iomap_regions(dev, 1 << SMBBAR,
1826 dev_driver_string(&dev->dev));
1827 if (err) {
1828 dev_err(&dev->dev,
1829 "Failed to request SMBus region 0x%lx-0x%Lx\n",
1830 priv->smba,
1831 (unsigned long long)pci_resource_end(dev, SMBBAR));
1832 i801_acpi_remove(priv);
1833 return err;
1834 }
1835
1836 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &temp);
1837 priv->original_hstcfg = temp;
1838 temp &= ~SMBHSTCFG_I2C_EN; /* SMBus timing */
1839 if (!(temp & SMBHSTCFG_HST_EN)) {
1840 dev_info(&dev->dev, "Enabling SMBus device\n");
1841 temp |= SMBHSTCFG_HST_EN;
1842 }
1843 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, temp);
1844
1845 if (temp & SMBHSTCFG_SMB_SMI_EN) {
1846 dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n");
1847 /* Disable SMBus interrupt feature if SMBus using SMI# */
1848 priv->features &= ~FEATURE_IRQ;
1849 }
1850 if (temp & SMBHSTCFG_SPD_WD)
1851 dev_info(&dev->dev, "SPD Write Disable is set\n");
1852
1853 /* Clear special mode bits */
1854 if (priv->features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER))
1855 outb_p(inb_p(SMBAUXCTL(priv)) &
1856 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
1857
1858 /* Remember original Host Notify setting */
1859 if (priv->features & FEATURE_HOST_NOTIFY)
1860 priv->original_slvcmd = inb_p(SMBSLVCMD(priv));
1861
1862 /* Default timeout in interrupt mode: 200 ms */
1863 priv->adapter.timeout = HZ / 5;
1864
1865 if (dev->irq == IRQ_NOTCONNECTED)
1866 priv->features &= ~FEATURE_IRQ;
1867
1868 if (priv->features & FEATURE_IRQ) {
1869 u16 pcictl, pcists;
1870
1871 /* Complain if an interrupt is already pending */
1872 pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists);
1873 if (pcists & SMBPCISTS_INTS)
1874 dev_warn(&dev->dev, "An interrupt is pending!\n");
1875
1876 /* Check if interrupts have been disabled */
1877 pci_read_config_word(priv->pci_dev, SMBPCICTL, &pcictl);
1878 if (pcictl & SMBPCICTL_INTDIS) {
1879 dev_info(&dev->dev, "Interrupts are disabled\n");
1880 priv->features &= ~FEATURE_IRQ;
1881 }
1882 }
1883
1884 if (priv->features & FEATURE_IRQ) {
1885 init_waitqueue_head(&priv->waitq);
1886
1887 err = devm_request_irq(&dev->dev, dev->irq, i801_isr,
1888 IRQF_SHARED,
1889 dev_driver_string(&dev->dev), priv);
1890 if (err) {
1891 dev_err(&dev->dev, "Failed to allocate irq %d: %d\n",
1892 dev->irq, err);
1893 priv->features &= ~FEATURE_IRQ;
1894 }
1895 }
1896 dev_info(&dev->dev, "SMBus using %s\n",
1897 priv->features & FEATURE_IRQ ? "PCI interrupt" : "polling");
1898
1899 i801_add_tco(priv);
1900
1901 snprintf(priv->adapter.name, sizeof(priv->adapter.name),
1902 "SMBus I801 adapter at %04lx", priv->smba);
1903 err = i2c_add_adapter(&priv->adapter);
1904 if (err) {
1905 i801_acpi_remove(priv);
1906 return err;
1907 }
1908
1909 i801_enable_host_notify(&priv->adapter);
1910
1911 i801_probe_optional_slaves(priv);
1912 /* We ignore errors - multiplexing is optional */
1913 i801_add_mux(priv);
1914
1915 pci_set_drvdata(dev, priv);
1916
1917 pm_runtime_set_autosuspend_delay(&dev->dev, 1000);
1918 pm_runtime_use_autosuspend(&dev->dev);
1919 pm_runtime_put_autosuspend(&dev->dev);
1920 pm_runtime_allow(&dev->dev);
1921
1922 return 0;
1923 }
1924
1925 static void i801_remove(struct pci_dev *dev)
1926 {
1927 struct i801_priv *priv = pci_get_drvdata(dev);
1928
1929 pm_runtime_forbid(&dev->dev);
1930 pm_runtime_get_noresume(&dev->dev);
1931
1932 i801_disable_host_notify(priv);
1933 i801_del_mux(priv);
1934 i2c_del_adapter(&priv->adapter);
1935 i801_acpi_remove(priv);
1936 pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
1937
1938 platform_device_unregister(priv->tco_pdev);
1939
1940 /*
1941 * do not call pci_disable_device(dev) since it can cause hard hangs on
1942 * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010)
1943 */
1944 }
1945
1946 static void i801_shutdown(struct pci_dev *dev)
1947 {
1948 struct i801_priv *priv = pci_get_drvdata(dev);
1949
1950 /* Restore config registers to avoid hard hang on some systems */
1951 i801_disable_host_notify(priv);
1952 pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
1953 }
1954
1955 #ifdef CONFIG_PM_SLEEP
1956 static int i801_suspend(struct device *dev)
1957 {
1958 struct pci_dev *pci_dev = to_pci_dev(dev);
1959 struct i801_priv *priv = pci_get_drvdata(pci_dev);
1960
1961 pci_write_config_byte(pci_dev, SMBHSTCFG, priv->original_hstcfg);
1962 return 0;
1963 }
1964
1965 static int i801_resume(struct device *dev)
1966 {
1967 struct i801_priv *priv = dev_get_drvdata(dev);
1968
1969 i801_enable_host_notify(&priv->adapter);
1970
1971 return 0;
1972 }
1973 #endif
1974
1975 static SIMPLE_DEV_PM_OPS(i801_pm_ops, i801_suspend, i801_resume);
1976
1977 static struct pci_driver i801_driver = {
1978 .name = "i801_smbus",
1979 .id_table = i801_ids,
1980 .probe = i801_probe,
1981 .remove = i801_remove,
1982 .shutdown = i801_shutdown,
1983 .driver = {
1984 .pm = &i801_pm_ops,
1985 },
1986 };
1987
1988 static int __init i2c_i801_init(void)
1989 {
1990 if (dmi_name_in_vendors("FUJITSU"))
1991 input_apanel_init();
1992 return pci_register_driver(&i801_driver);
1993 }
1994
1995 static void __exit i2c_i801_exit(void)
1996 {
1997 pci_unregister_driver(&i801_driver);
1998 }
1999
2000 MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>, Jean Delvare <jdelvare@suse.de>");
2001 MODULE_DESCRIPTION("I801 SMBus driver");
2002 MODULE_LICENSE("GPL");
2003
2004 module_init(i2c_i801_init);
2005 module_exit(i2c_i801_exit);
Linux with added FPC-III support