drivers/i2c/busses/i2c-isch.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3     i2c-isch.c - Linux kernel driver for Intel SCH chipset SMBus
   4     - Based on i2c-piix4.c
   5     Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl> and
   6     Philip Edelbrock <phil@netroedge.com>
   7     - Intel SCH support
   8     Copyright (c) 2007 - 2008 Jacob Jun Pan <jacob.jun.pan@intel.com>
   9
  10 */
  11
  12 /*
  13    Supports:
  14         Intel SCH chipsets (AF82US15W, AF82US15L, AF82UL11L)
  15    Note: we assume there can only be one device, with one SMBus interface.
  16 */
  17
  18 #include <linux/module.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/kernel.h>
  21 #include <linux/delay.h>
  22 #include <linux/stddef.h>
  23 #include <linux/ioport.h>
  24 #include <linux/i2c.h>
  25 #include <linux/io.h>
  26
  27 /* SCH SMBus address offsets */
  28 #define SMBHSTCNT       (0 + sch_smba)
  29 #define SMBHSTSTS       (1 + sch_smba)
  30 #define SMBHSTCLK       (2 + sch_smba)
  31 #define SMBHSTADD       (4 + sch_smba) /* TSA */
  32 #define SMBHSTCMD       (5 + sch_smba)
  33 #define SMBHSTDAT0      (6 + sch_smba)
  34 #define SMBHSTDAT1      (7 + sch_smba)
  35 #define SMBBLKDAT       (0x20 + sch_smba)
  36
  37 /* Other settings */
  38 #define MAX_RETRIES     5000
  39
  40 /* I2C constants */
  41 #define SCH_QUICK               0x00
  42 #define SCH_BYTE                0x01
  43 #define SCH_BYTE_DATA           0x02
  44 #define SCH_WORD_DATA           0x03
  45 #define SCH_BLOCK_DATA          0x05
  46
  47 static unsigned short sch_smba;
  48 static struct i2c_adapter sch_adapter;
  49 static int backbone_speed = 33000; /* backbone speed in kHz */
  50 module_param(backbone_speed, int, S_IRUSR | S_IWUSR);
  51 MODULE_PARM_DESC(backbone_speed, "Backbone speed in kHz, (default = 33000)");
  52
  53 /*
  54  * Start the i2c transaction -- the i2c_access will prepare the transaction
  55  * and this function will execute it.
  56  * return 0 for success and others for failure.
  57  */
  58 static int sch_transaction(void)
  59 {
  60         int temp;
  61         int result = 0;
  62         int retries = 0;
  63
  64         dev_dbg(&sch_adapter.dev, "Transaction (pre): CNT=%02x, CMD=%02x, "
  65                 "ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb(SMBHSTCNT),
  66                 inb(SMBHSTCMD), inb(SMBHSTADD), inb(SMBHSTDAT0),
  67                 inb(SMBHSTDAT1));
  68
  69         /* Make sure the SMBus host is ready to start transmitting */
  70         temp = inb(SMBHSTSTS) & 0x0f;
  71         if (temp) {
  72                 /* Can not be busy since we checked it in sch_access */
  73                 if (temp & 0x01) {
  74                         dev_dbg(&sch_adapter.dev, "Completion (%02x). "
  75                                 "Clear...\n", temp);
  76                 }
  77                 if (temp & 0x06) {
  78                         dev_dbg(&sch_adapter.dev, "SMBus error (%02x). "
  79                                 "Resetting...\n", temp);
  80                 }
  81                 outb(temp, SMBHSTSTS);
  82                 temp = inb(SMBHSTSTS) & 0x0f;
  83                 if (temp) {
  84                         dev_err(&sch_adapter.dev,
  85                                 "SMBus is not ready: (%02x)\n", temp);
  86                         return -EAGAIN;
  87                 }
  88         }
  89
  90         /* start the transaction by setting bit 4 */
  91         outb(inb(SMBHSTCNT) | 0x10, SMBHSTCNT);
  92
  93         do {
  94                 usleep_range(100, 200);
  95                 temp = inb(SMBHSTSTS) & 0x0f;
  96         } while ((temp & 0x08) && (retries++ < MAX_RETRIES));
  97
  98         /* If the SMBus is still busy, we give up */
  99         if (retries > MAX_RETRIES) {
 100                 dev_err(&sch_adapter.dev, "SMBus Timeout!\n");
 101                 result = -ETIMEDOUT;
 102         }
 103         if (temp & 0x04) {
 104                 result = -EIO;
 105                 dev_dbg(&sch_adapter.dev, "Bus collision! SMBus may be "
 106                         "locked until next hard reset. (sorry!)\n");
 107                 /* Clock stops and slave is stuck in mid-transmission */
 108         } else if (temp & 0x02) {
 109                 result = -EIO;
 110                 dev_err(&sch_adapter.dev, "Error: no response!\n");
 111         } else if (temp & 0x01) {
 112                 dev_dbg(&sch_adapter.dev, "Post complete!\n");
 113                 outb(temp, SMBHSTSTS);
 114                 temp = inb(SMBHSTSTS) & 0x07;
 115                 if (temp & 0x06) {
 116                         /* Completion clear failed */
 117                         dev_dbg(&sch_adapter.dev, "Failed reset at end of "
 118                                 "transaction (%02x), Bus error!\n", temp);
 119                 }
 120         } else {
 121                 result = -ENXIO;
 122                 dev_dbg(&sch_adapter.dev, "No such address.\n");
 123         }
 124         dev_dbg(&sch_adapter.dev, "Transaction (post): CNT=%02x, CMD=%02x, "
 125                 "ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb(SMBHSTCNT),
 126                 inb(SMBHSTCMD), inb(SMBHSTADD), inb(SMBHSTDAT0),
 127                 inb(SMBHSTDAT1));
 128         return result;
 129 }
 130
 131 /*
 132  * This is the main access entry for i2c-sch access
 133  * adap is i2c_adapter pointer, addr is the i2c device bus address, read_write
 134  * (0 for read and 1 for write), size is i2c transaction type and data is the
 135  * union of transaction for data to be transferred or data read from bus.
 136  * return 0 for success and others for failure.
 137  */
 138 static s32 sch_access(struct i2c_adapter *adap, u16 addr,
 139                  unsigned short flags, char read_write,
 140                  u8 command, int size, union i2c_smbus_data *data)
 141 {
 142         int i, len, temp, rc;
 143
 144         /* Make sure the SMBus host is not busy */
 145         temp = inb(SMBHSTSTS) & 0x0f;
 146         if (temp & 0x08) {
 147                 dev_dbg(&sch_adapter.dev, "SMBus busy (%02x)\n", temp);
 148                 return -EAGAIN;
 149         }
 150         temp = inw(SMBHSTCLK);
 151         if (!temp) {
 152                 /*
 153                  * We can't determine if we have 33 or 25 MHz clock for
 154                  * SMBus, so expect 33 MHz and calculate a bus clock of
 155                  * 100 kHz. If we actually run at 25 MHz the bus will be
 156                  * run ~75 kHz instead which should do no harm.
 157                  */
 158                 dev_notice(&sch_adapter.dev,
 159                         "Clock divider uninitialized. Setting defaults\n");
 160                 outw(backbone_speed / (4 * 100), SMBHSTCLK);
 161         }
 162
 163         dev_dbg(&sch_adapter.dev, "access size: %d %s\n", size,
 164                 (read_write)?"READ":"WRITE");
 165         switch (size) {
 166         case I2C_SMBUS_QUICK:
 167                 outb((addr << 1) | read_write, SMBHSTADD);
 168                 size = SCH_QUICK;
 169                 break;
 170         case I2C_SMBUS_BYTE:
 171                 outb((addr << 1) | read_write, SMBHSTADD);
 172                 if (read_write == I2C_SMBUS_WRITE)
 173                         outb(command, SMBHSTCMD);
 174                 size = SCH_BYTE;
 175                 break;
 176         case I2C_SMBUS_BYTE_DATA:
 177                 outb((addr << 1) | read_write, SMBHSTADD);
 178                 outb(command, SMBHSTCMD);
 179                 if (read_write == I2C_SMBUS_WRITE)
 180                         outb(data->byte, SMBHSTDAT0);
 181                 size = SCH_BYTE_DATA;
 182                 break;
 183         case I2C_SMBUS_WORD_DATA:
 184                 outb((addr << 1) | read_write, SMBHSTADD);
 185                 outb(command, SMBHSTCMD);
 186                 if (read_write == I2C_SMBUS_WRITE) {
 187                         outb(data->word & 0xff, SMBHSTDAT0);
 188                         outb((data->word & 0xff00) >> 8, SMBHSTDAT1);
 189                 }
 190                 size = SCH_WORD_DATA;
 191                 break;
 192         case I2C_SMBUS_BLOCK_DATA:
 193                 outb((addr << 1) | read_write, SMBHSTADD);
 194                 outb(command, SMBHSTCMD);
 195                 if (read_write == I2C_SMBUS_WRITE) {
 196                         len = data->block[0];
 197                         if (len == 0 || len > I2C_SMBUS_BLOCK_MAX)
 198                                 return -EINVAL;
 199                         outb(len, SMBHSTDAT0);
 200                         for (i = 1; i <= len; i++)
 201                                 outb(data->block[i], SMBBLKDAT+i-1);
 202                 }
 203                 size = SCH_BLOCK_DATA;
 204                 break;
 205         default:
 206                 dev_warn(&adap->dev, "Unsupported transaction %d\n", size);
 207                 return -EOPNOTSUPP;
 208         }
 209         dev_dbg(&sch_adapter.dev, "write size %d to 0x%04x\n", size, SMBHSTCNT);
 210         outb((inb(SMBHSTCNT) & 0xb0) | (size & 0x7), SMBHSTCNT);
 211
 212         rc = sch_transaction();
 213         if (rc) /* Error in transaction */
 214                 return rc;
 215
 216         if ((read_write == I2C_SMBUS_WRITE) || (size == SCH_QUICK))
 217                 return 0;
 218
 219         switch (size) {
 220         case SCH_BYTE:
 221         case SCH_BYTE_DATA:
 222                 data->byte = inb(SMBHSTDAT0);
 223                 break;
 224         case SCH_WORD_DATA:
 225                 data->word = inb(SMBHSTDAT0) + (inb(SMBHSTDAT1) << 8);
 226                 break;
 227         case SCH_BLOCK_DATA:
 228                 data->block[0] = inb(SMBHSTDAT0);
 229                 if (data->block[0] == 0 || data->block[0] > I2C_SMBUS_BLOCK_MAX)
 230                         return -EPROTO;
 231                 for (i = 1; i <= data->block[0]; i++)
 232                         data->block[i] = inb(SMBBLKDAT+i-1);
 233                 break;
 234         }
 235         return 0;
 236 }
 237
 238 static u32 sch_func(struct i2c_adapter *adapter)
 239 {
 240         return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
 241             I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
 242             I2C_FUNC_SMBUS_BLOCK_DATA;
 243 }
 244
 245 static const struct i2c_algorithm smbus_algorithm = {
 246         .smbus_xfer     = sch_access,
 247         .functionality  = sch_func,
 248 };
 249
 250 static struct i2c_adapter sch_adapter = {
 251         .owner          = THIS_MODULE,
 252         .class          = I2C_CLASS_HWMON | I2C_CLASS_SPD,
 253         .algo           = &smbus_algorithm,
 254 };
 255
 256 static int smbus_sch_probe(struct platform_device *dev)
 257 {
 258         struct resource *res;
 259         int retval;
 260
 261         res = platform_get_resource(dev, IORESOURCE_IO, 0);
 262         if (!res)
 263                 return -EBUSY;
 264
 265         if (!devm_request_region(&dev->dev, res->start, resource_size(res),
 266                                  dev->name)) {
 267                 dev_err(&dev->dev, "SMBus region 0x%x already in use!\n",
 268                         sch_smba);
 269                 return -EBUSY;
 270         }
 271
 272         sch_smba = res->start;
 273
 274         dev_dbg(&dev->dev, "SMBA = 0x%X\n", sch_smba);
 275
 276         /* set up the sysfs linkage to our parent device */
 277         sch_adapter.dev.parent = &dev->dev;
 278
 279         snprintf(sch_adapter.name, sizeof(sch_adapter.name),
 280                 "SMBus SCH adapter at %04x", sch_smba);
 281
 282         retval = i2c_add_adapter(&sch_adapter);
 283         if (retval)
 284                 sch_smba = 0;
 285
 286         return retval;
 287 }
 288
 289 static int smbus_sch_remove(struct platform_device *pdev)
 290 {
 291         if (sch_smba) {
 292                 i2c_del_adapter(&sch_adapter);
 293                 sch_smba = 0;
 294         }
 295
 296         return 0;
 297 }
 298
 299 static struct platform_driver smbus_sch_driver = {
 300         .driver = {
 301                 .name = "isch_smbus",
 302         },
 303         .probe          = smbus_sch_probe,
 304         .remove         = smbus_sch_remove,
 305 };
 306
 307 module_platform_driver(smbus_sch_driver);
 308
 309 MODULE_AUTHOR("Jacob Pan <jacob.jun.pan@intel.com>");
 310 MODULE_DESCRIPTION("Intel SCH SMBus driver");
 311 MODULE_LICENSE("GPL");
 312 MODULE_ALIAS("platform:isch_smbus");