drivers/i2c/busses/i2c-nvidia-gpu.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Nvidia GPU I2C controller Driver
   4  *
   5  * Copyright (C) 2018 NVIDIA Corporation. All rights reserved.
   6  * Author: Ajay Gupta <ajayg@nvidia.com>
   7  */
   8 #include <linux/delay.h>
   9 #include <linux/i2c.h>
  10 #include <linux/interrupt.h>
  11 #include <linux/module.h>
  12 #include <linux/pci.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/pm.h>
  15 #include <linux/pm_runtime.h>
  16
  17 #include <asm/unaligned.h>
  18
  19 /* I2C definitions */
  20 #define I2C_MST_CNTL                            0x00
  21 #define I2C_MST_CNTL_GEN_START                  BIT(0)
  22 #define I2C_MST_CNTL_GEN_STOP                   BIT(1)
  23 #define I2C_MST_CNTL_CMD_READ                   (1 << 2)
  24 #define I2C_MST_CNTL_CMD_WRITE                  (2 << 2)
  25 #define I2C_MST_CNTL_BURST_SIZE_SHIFT           6
  26 #define I2C_MST_CNTL_GEN_NACK                   BIT(28)
  27 #define I2C_MST_CNTL_STATUS                     GENMASK(30, 29)
  28 #define I2C_MST_CNTL_STATUS_OKAY                (0 << 29)
  29 #define I2C_MST_CNTL_STATUS_NO_ACK              (1 << 29)
  30 #define I2C_MST_CNTL_STATUS_TIMEOUT             (2 << 29)
  31 #define I2C_MST_CNTL_STATUS_BUS_BUSY            (3 << 29)
  32 #define I2C_MST_CNTL_CYCLE_TRIGGER              BIT(31)
  33
  34 #define I2C_MST_ADDR                            0x04
  35
  36 #define I2C_MST_I2C0_TIMING                             0x08
  37 #define I2C_MST_I2C0_TIMING_SCL_PERIOD_100KHZ           0x10e
  38 #define I2C_MST_I2C0_TIMING_TIMEOUT_CLK_CNT             16
  39 #define I2C_MST_I2C0_TIMING_TIMEOUT_CLK_CNT_MAX         255
  40 #define I2C_MST_I2C0_TIMING_TIMEOUT_CHECK               BIT(24)
  41
  42 #define I2C_MST_DATA                                    0x0c
  43
  44 #define I2C_MST_HYBRID_PADCTL                           0x20
  45 #define I2C_MST_HYBRID_PADCTL_MODE_I2C                  BIT(0)
  46 #define I2C_MST_HYBRID_PADCTL_I2C_SCL_INPUT_RCV         BIT(14)
  47 #define I2C_MST_HYBRID_PADCTL_I2C_SDA_INPUT_RCV         BIT(15)
  48
  49 struct gpu_i2c_dev {
  50         struct device *dev;
  51         void __iomem *regs;
  52         struct i2c_adapter adapter;
  53         struct i2c_board_info *gpu_ccgx_ucsi;
  54         struct i2c_client *ccgx_client;
  55 };
  56
  57 static void gpu_enable_i2c_bus(struct gpu_i2c_dev *i2cd)
  58 {
  59         u32 val;
  60
  61         /* enable I2C */
  62         val = readl(i2cd->regs + I2C_MST_HYBRID_PADCTL);
  63         val |= I2C_MST_HYBRID_PADCTL_MODE_I2C |
  64                 I2C_MST_HYBRID_PADCTL_I2C_SCL_INPUT_RCV |
  65                 I2C_MST_HYBRID_PADCTL_I2C_SDA_INPUT_RCV;
  66         writel(val, i2cd->regs + I2C_MST_HYBRID_PADCTL);
  67
  68         /* enable 100KHZ mode */
  69         val = I2C_MST_I2C0_TIMING_SCL_PERIOD_100KHZ;
  70         val |= (I2C_MST_I2C0_TIMING_TIMEOUT_CLK_CNT_MAX
  71             << I2C_MST_I2C0_TIMING_TIMEOUT_CLK_CNT);
  72         val |= I2C_MST_I2C0_TIMING_TIMEOUT_CHECK;
  73         writel(val, i2cd->regs + I2C_MST_I2C0_TIMING);
  74 }
  75
  76 static int gpu_i2c_check_status(struct gpu_i2c_dev *i2cd)
  77 {
  78         unsigned long target = jiffies + msecs_to_jiffies(1000);
  79         u32 val;
  80
  81         do {
  82                 val = readl(i2cd->regs + I2C_MST_CNTL);
  83                 if (!(val & I2C_MST_CNTL_CYCLE_TRIGGER))
  84                         break;
  85                 if ((val & I2C_MST_CNTL_STATUS) !=
  86                                 I2C_MST_CNTL_STATUS_BUS_BUSY)
  87                         break;
  88                 usleep_range(500, 600);
  89         } while (time_is_after_jiffies(target));
  90
  91         if (time_is_before_jiffies(target)) {
  92                 dev_err(i2cd->dev, "i2c timeout error %x\n", val);
  93                 return -ETIMEDOUT;
  94         }
  95
  96         val = readl(i2cd->regs + I2C_MST_CNTL);
  97         switch (val & I2C_MST_CNTL_STATUS) {
  98         case I2C_MST_CNTL_STATUS_OKAY:
  99                 return 0;
 100         case I2C_MST_CNTL_STATUS_NO_ACK:
 101                 return -ENXIO;
 102         case I2C_MST_CNTL_STATUS_TIMEOUT:
 103                 return -ETIMEDOUT;
 104         default:
 105                 return 0;
 106         }
 107 }
 108
 109 static int gpu_i2c_read(struct gpu_i2c_dev *i2cd, u8 *data, u16 len)
 110 {
 111         int status;
 112         u32 val;
 113
 114         val = I2C_MST_CNTL_GEN_START | I2C_MST_CNTL_CMD_READ |
 115                 (len << I2C_MST_CNTL_BURST_SIZE_SHIFT) |
 116                 I2C_MST_CNTL_CYCLE_TRIGGER | I2C_MST_CNTL_GEN_NACK;
 117         writel(val, i2cd->regs + I2C_MST_CNTL);
 118
 119         status = gpu_i2c_check_status(i2cd);
 120         if (status < 0)
 121                 return status;
 122
 123         val = readl(i2cd->regs + I2C_MST_DATA);
 124         switch (len) {
 125         case 1:
 126                 data[0] = val;
 127                 break;
 128         case 2:
 129                 put_unaligned_be16(val, data);
 130                 break;
 131         case 3:
 132                 put_unaligned_be16(val >> 8, data);
 133                 data[2] = val;
 134                 break;
 135         case 4:
 136                 put_unaligned_be32(val, data);
 137                 break;
 138         default:
 139                 break;
 140         }
 141         return status;
 142 }
 143
 144 static int gpu_i2c_start(struct gpu_i2c_dev *i2cd)
 145 {
 146         writel(I2C_MST_CNTL_GEN_START, i2cd->regs + I2C_MST_CNTL);
 147         return gpu_i2c_check_status(i2cd);
 148 }
 149
 150 static int gpu_i2c_stop(struct gpu_i2c_dev *i2cd)
 151 {
 152         writel(I2C_MST_CNTL_GEN_STOP, i2cd->regs + I2C_MST_CNTL);
 153         return gpu_i2c_check_status(i2cd);
 154 }
 155
 156 static int gpu_i2c_write(struct gpu_i2c_dev *i2cd, u8 data)
 157 {
 158         u32 val;
 159
 160         writel(data, i2cd->regs + I2C_MST_DATA);
 161
 162         val = I2C_MST_CNTL_CMD_WRITE | (1 << I2C_MST_CNTL_BURST_SIZE_SHIFT);
 163         writel(val, i2cd->regs + I2C_MST_CNTL);
 164
 165         return gpu_i2c_check_status(i2cd);
 166 }
 167
 168 static int gpu_i2c_master_xfer(struct i2c_adapter *adap,
 169                                struct i2c_msg *msgs, int num)
 170 {
 171         struct gpu_i2c_dev *i2cd = i2c_get_adapdata(adap);
 172         int status, status2;
 173         bool send_stop = true;
 174         int i, j;
 175
 176         /*
 177          * The controller supports maximum 4 byte read due to known
 178          * limitation of sending STOP after every read.
 179          */
 180         pm_runtime_get_sync(i2cd->dev);
 181         for (i = 0; i < num; i++) {
 182                 if (msgs[i].flags & I2C_M_RD) {
 183                         /* program client address before starting read */
 184                         writel(msgs[i].addr, i2cd->regs + I2C_MST_ADDR);
 185                         /* gpu_i2c_read has implicit start */
 186                         status = gpu_i2c_read(i2cd, msgs[i].buf, msgs[i].len);
 187                         if (status < 0)
 188                                 goto exit;
 189                 } else {
 190                         u8 addr = i2c_8bit_addr_from_msg(msgs + i);
 191
 192                         status = gpu_i2c_start(i2cd);
 193                         if (status < 0) {
 194                                 if (i == 0)
 195                                         send_stop = false;
 196                                 goto exit;
 197                         }
 198
 199                         status = gpu_i2c_write(i2cd, addr);
 200                         if (status < 0)
 201                                 goto exit;
 202
 203                         for (j = 0; j < msgs[i].len; j++) {
 204                                 status = gpu_i2c_write(i2cd, msgs[i].buf[j]);
 205                                 if (status < 0)
 206                                         goto exit;
 207                         }
 208                 }
 209         }
 210         send_stop = false;
 211         status = gpu_i2c_stop(i2cd);
 212         if (status < 0)
 213                 goto exit;
 214
 215         status = i;
 216 exit:
 217         if (send_stop) {
 218                 status2 = gpu_i2c_stop(i2cd);
 219                 if (status2 < 0)
 220                         dev_err(i2cd->dev, "i2c stop failed %d\n", status2);
 221         }
 222         pm_runtime_mark_last_busy(i2cd->dev);
 223         pm_runtime_put_autosuspend(i2cd->dev);
 224         return status;
 225 }
 226
 227 static const struct i2c_adapter_quirks gpu_i2c_quirks = {
 228         .max_read_len = 4,
 229         .max_comb_2nd_msg_len = 4,
 230         .flags = I2C_AQ_COMB_WRITE_THEN_READ,
 231 };
 232
 233 static u32 gpu_i2c_functionality(struct i2c_adapter *adap)
 234 {
 235         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
 236 }
 237
 238 static const struct i2c_algorithm gpu_i2c_algorithm = {
 239         .master_xfer    = gpu_i2c_master_xfer,
 240         .functionality  = gpu_i2c_functionality,
 241 };
 242
 243 /*
 244  * This driver is for Nvidia GPU cards with USB Type-C interface.
 245  * We want to identify the cards using vendor ID and class code only
 246  * to avoid dependency of adding product id for any new card which
 247  * requires this driver.
 248  * Currently there is no class code defined for UCSI device over PCI
 249  * so using UNKNOWN class for now and it will be updated when UCSI
 250  * over PCI gets a class code.
 251  * There is no other NVIDIA cards with UNKNOWN class code. Even if the
 252  * driver gets loaded for an undesired card then eventually i2c_read()
 253  * (initiated from UCSI i2c_client) will timeout or UCSI commands will
 254  * timeout.
 255  */
 256 #define PCI_CLASS_SERIAL_UNKNOWN        0x0c80
 257 static const struct pci_device_id gpu_i2c_ids[] = {
 258         { PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
 259                 PCI_CLASS_SERIAL_UNKNOWN << 8, 0xffffff00},
 260         { }
 261 };
 262 MODULE_DEVICE_TABLE(pci, gpu_i2c_ids);
 263
 264 static const struct property_entry ccgx_props[] = {
 265         /* Use FW built for NVIDIA (nv) only */
 266         PROPERTY_ENTRY_U16("ccgx,firmware-build", ('n' << 8) | 'v'),
 267         { }
 268 };
 269
 270 static int gpu_populate_client(struct gpu_i2c_dev *i2cd, int irq)
 271 {
 272         i2cd->gpu_ccgx_ucsi = devm_kzalloc(i2cd->dev,
 273                                            sizeof(*i2cd->gpu_ccgx_ucsi),
 274                                            GFP_KERNEL);
 275         if (!i2cd->gpu_ccgx_ucsi)
 276                 return -ENOMEM;
 277
 278         strlcpy(i2cd->gpu_ccgx_ucsi->type, "ccgx-ucsi",
 279                 sizeof(i2cd->gpu_ccgx_ucsi->type));
 280         i2cd->gpu_ccgx_ucsi->addr = 0x8;
 281         i2cd->gpu_ccgx_ucsi->irq = irq;
 282         i2cd->gpu_ccgx_ucsi->properties = ccgx_props;
 283         i2cd->ccgx_client = i2c_new_device(&i2cd->adapter, i2cd->gpu_ccgx_ucsi);
 284         if (!i2cd->ccgx_client)
 285                 return -ENODEV;
 286
 287         return 0;
 288 }
 289
 290 static int gpu_i2c_probe(struct pci_dev *pdev, const struct pci_device_id *id)
 291 {
 292         struct gpu_i2c_dev *i2cd;
 293         int status;
 294
 295         i2cd = devm_kzalloc(&pdev->dev, sizeof(*i2cd), GFP_KERNEL);
 296         if (!i2cd)
 297                 return -ENOMEM;
 298
 299         i2cd->dev = &pdev->dev;
 300         dev_set_drvdata(&pdev->dev, i2cd);
 301
 302         status = pcim_enable_device(pdev);
 303         if (status < 0) {
 304                 dev_err(&pdev->dev, "pcim_enable_device failed %d\n", status);
 305                 return status;
 306         }
 307
 308         pci_set_master(pdev);
 309
 310         i2cd->regs = pcim_iomap(pdev, 0, 0);
 311         if (!i2cd->regs) {
 312                 dev_err(&pdev->dev, "pcim_iomap failed\n");
 313                 return -ENOMEM;
 314         }
 315
 316         status = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI);
 317         if (status < 0) {
 318                 dev_err(&pdev->dev, "pci_alloc_irq_vectors err %d\n", status);
 319                 return status;
 320         }
 321
 322         gpu_enable_i2c_bus(i2cd);
 323
 324         i2c_set_adapdata(&i2cd->adapter, i2cd);
 325         i2cd->adapter.owner = THIS_MODULE;
 326         strlcpy(i2cd->adapter.name, "NVIDIA GPU I2C adapter",
 327                 sizeof(i2cd->adapter.name));
 328         i2cd->adapter.algo = &gpu_i2c_algorithm;
 329         i2cd->adapter.quirks = &gpu_i2c_quirks;
 330         i2cd->adapter.dev.parent = &pdev->dev;
 331         status = i2c_add_adapter(&i2cd->adapter);
 332         if (status < 0)
 333                 goto free_irq_vectors;
 334
 335         status = gpu_populate_client(i2cd, pdev->irq);
 336         if (status < 0) {
 337                 dev_err(&pdev->dev, "gpu_populate_client failed %d\n", status);
 338                 goto del_adapter;
 339         }
 340
 341         pm_runtime_set_autosuspend_delay(&pdev->dev, 3000);
 342         pm_runtime_use_autosuspend(&pdev->dev);
 343         pm_runtime_put_autosuspend(&pdev->dev);
 344         pm_runtime_allow(&pdev->dev);
 345
 346         return 0;
 347
 348 del_adapter:
 349         i2c_del_adapter(&i2cd->adapter);
 350 free_irq_vectors:
 351         pci_free_irq_vectors(pdev);
 352         return status;
 353 }
 354
 355 static void gpu_i2c_remove(struct pci_dev *pdev)
 356 {
 357         struct gpu_i2c_dev *i2cd = dev_get_drvdata(&pdev->dev);
 358
 359         pm_runtime_get_noresume(i2cd->dev);
 360         i2c_del_adapter(&i2cd->adapter);
 361         pci_free_irq_vectors(pdev);
 362 }
 363
 364 /*
 365  * We need gpu_i2c_suspend() even if it is stub, for runtime pm to work
 366  * correctly. Without it, lspci shows runtime pm status as "D0" for the card.
 367  * Documentation/power/pci.rst also insists for driver to provide this.
 368  */
 369 static __maybe_unused int gpu_i2c_suspend(struct device *dev)
 370 {
 371         return 0;
 372 }
 373
 374 static __maybe_unused int gpu_i2c_resume(struct device *dev)
 375 {
 376         struct gpu_i2c_dev *i2cd = dev_get_drvdata(dev);
 377
 378         gpu_enable_i2c_bus(i2cd);
 379         /*
 380          * Runtime resume ccgx client so that it can see for any
 381          * connector change event. Old ccg firmware has known
 382          * issue of not triggering interrupt when a device is
 383          * connected to runtime resume the controller.
 384          */
 385         pm_request_resume(&i2cd->ccgx_client->dev);
 386         return 0;
 387 }
 388
 389 static UNIVERSAL_DEV_PM_OPS(gpu_i2c_driver_pm, gpu_i2c_suspend, gpu_i2c_resume,
 390                             NULL);
 391
 392 static struct pci_driver gpu_i2c_driver = {
 393         .name           = "nvidia-gpu",
 394         .id_table       = gpu_i2c_ids,
 395         .probe          = gpu_i2c_probe,
 396         .remove         = gpu_i2c_remove,
 397         .driver         = {
 398                 .pm     = &gpu_i2c_driver_pm,
 399         },
 400 };
 401
 402 module_pci_driver(gpu_i2c_driver);
 403
 404 MODULE_AUTHOR("Ajay Gupta <ajayg@nvidia.com>");
 405 MODULE_DESCRIPTION("Nvidia GPU I2C controller Driver");
 406 MODULE_LICENSE("GPL v2");