drivers/infiniband/hw/bnxt_re/qplib_res.h

   1 /*
   2  * Broadcom NetXtreme-E RoCE driver.
   3  *
   4  * Copyright (c) 2016 - 2017, Broadcom. All rights reserved.  The term
   5  * Broadcom refers to Broadcom Limited and/or its subsidiaries.
   6  *
   7  * This software is available to you under a choice of one of two
   8  * licenses.  You may choose to be licensed under the terms of the GNU
   9  * General Public License (GPL) Version 2, available from the file
  10  * COPYING in the main directory of this source tree, or the
  11  * BSD license below:
  12  *
  13  * Redistribution and use in source and binary forms, with or without
  14  * modification, are permitted provided that the following conditions
  15  * are met:
  16  *
  17  * 1. Redistributions of source code must retain the above copyright
  18  *    notice, this list of conditions and the following disclaimer.
  19  * 2. Redistributions in binary form must reproduce the above copyright
  20  *    notice, this list of conditions and the following disclaimer in
  21  *    the documentation and/or other materials provided with the
  22  *    distribution.
  23  *
  24  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS''
  25  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  26  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  27  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS
  28  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  29  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  30  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
  31  * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  32  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
  33  * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
  34  * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  35  *
  36  * Description: QPLib resource manager (header)
  37  */
  38
  39 #ifndef __BNXT_QPLIB_RES_H__
  40 #define __BNXT_QPLIB_RES_H__
  41
  42 extern const struct bnxt_qplib_gid bnxt_qplib_gid_zero;
  43
  44 #define PTR_CNT_PER_PG          (PAGE_SIZE / sizeof(void *))
  45 #define PTR_MAX_IDX_PER_PG      (PTR_CNT_PER_PG - 1)
  46 #define PTR_PG(x)               (((x) & ~PTR_MAX_IDX_PER_PG) / PTR_CNT_PER_PG)
  47 #define PTR_IDX(x)              ((x) & PTR_MAX_IDX_PER_PG)
  48
  49 #define HWQ_CMP(idx, hwq)       ((idx) & ((hwq)->max_elements - 1))
  50
  51 #define HWQ_FREE_SLOTS(hwq)     (hwq->max_elements - \
  52                                 ((HWQ_CMP(hwq->prod, hwq)\
  53                                 - HWQ_CMP(hwq->cons, hwq))\
  54                                 & (hwq->max_elements - 1)))
  55 enum bnxt_qplib_hwq_type {
  56         HWQ_TYPE_CTX,
  57         HWQ_TYPE_QUEUE,
  58         HWQ_TYPE_L2_CMPL
  59 };
  60
  61 #define MAX_PBL_LVL_0_PGS               1
  62 #define MAX_PBL_LVL_1_PGS               512
  63 #define MAX_PBL_LVL_1_PGS_SHIFT         9
  64 #define MAX_PBL_LVL_1_PGS_FOR_LVL_2     256
  65 #define MAX_PBL_LVL_2_PGS               (256 * 512)
  66
  67 enum bnxt_qplib_pbl_lvl {
  68         PBL_LVL_0,
  69         PBL_LVL_1,
  70         PBL_LVL_2,
  71         PBL_LVL_MAX
  72 };
  73
  74 #define ROCE_PG_SIZE_4K         (4 * 1024)
  75 #define ROCE_PG_SIZE_8K         (8 * 1024)
  76 #define ROCE_PG_SIZE_64K        (64 * 1024)
  77 #define ROCE_PG_SIZE_2M         (2 * 1024 * 1024)
  78 #define ROCE_PG_SIZE_8M         (8 * 1024 * 1024)
  79 #define ROCE_PG_SIZE_1G         (1024 * 1024 * 1024)
  80
  81 struct bnxt_qplib_pbl {
  82         u32                             pg_count;
  83         u32                             pg_size;
  84         void                            **pg_arr;
  85         dma_addr_t                      *pg_map_arr;
  86 };
  87
  88 struct bnxt_qplib_hwq {
  89         struct pci_dev                  *pdev;
  90         /* lock to protect qplib_hwq */
  91         spinlock_t                      lock;
  92         struct bnxt_qplib_pbl           pbl[PBL_LVL_MAX];
  93         enum bnxt_qplib_pbl_lvl         level;          /* 0, 1, or 2 */
  94         /* ptr for easy access to the PBL entries */
  95         void                            **pbl_ptr;
  96         /* ptr for easy access to the dma_addr */
  97         dma_addr_t                      *pbl_dma_ptr;
  98         u32                             max_elements;
  99         u16                             element_size;   /* Size of each entry */
 100
 101         u32                             prod;           /* raw */
 102         u32                             cons;           /* raw */
 103         u8                              cp_bit;
 104         u8                              is_user;
 105 };
 106
 107 /* Tables */
 108 struct bnxt_qplib_pd_tbl {
 109         unsigned long                   *tbl;
 110         u32                             max;
 111 };
 112
 113 struct bnxt_qplib_sgid_tbl {
 114         struct bnxt_qplib_gid_info      *tbl;
 115         u16                             *hw_id;
 116         u16                             max;
 117         u16                             active;
 118         void                            *ctx;
 119         u8                              *vlan;
 120 };
 121
 122 struct bnxt_qplib_pkey_tbl {
 123         u16                             *tbl;
 124         u16                             max;
 125         u16                             active;
 126 };
 127
 128 struct bnxt_qplib_dpi {
 129         u32                             dpi;
 130         void __iomem                    *dbr;
 131         u64                             umdbr;
 132 };
 133
 134 struct bnxt_qplib_dpi_tbl {
 135         void                            **app_tbl;
 136         unsigned long                   *tbl;
 137         u16                             max;
 138         void __iomem                    *dbr_bar_reg_iomem;
 139         u64                             unmapped_dbr;
 140 };
 141
 142 struct bnxt_qplib_stats {
 143         dma_addr_t                      dma_map;
 144         void                            *dma;
 145         u32                             size;
 146         u32                             fw_id;
 147 };
 148
 149 struct bnxt_qplib_vf_res {
 150         u32 max_qp_per_vf;
 151         u32 max_mrw_per_vf;
 152         u32 max_srq_per_vf;
 153         u32 max_cq_per_vf;
 154         u32 max_gid_per_vf;
 155 };
 156
 157 #define BNXT_QPLIB_MAX_QP_CTX_ENTRY_SIZE        448
 158 #define BNXT_QPLIB_MAX_SRQ_CTX_ENTRY_SIZE       64
 159 #define BNXT_QPLIB_MAX_CQ_CTX_ENTRY_SIZE        64
 160 #define BNXT_QPLIB_MAX_MRW_CTX_ENTRY_SIZE       128
 161
 162 struct bnxt_qplib_ctx {
 163         u32                             qpc_count;
 164         struct bnxt_qplib_hwq           qpc_tbl;
 165         u32                             mrw_count;
 166         struct bnxt_qplib_hwq           mrw_tbl;
 167         u32                             srqc_count;
 168         struct bnxt_qplib_hwq           srqc_tbl;
 169         u32                             cq_count;
 170         struct bnxt_qplib_hwq           cq_tbl;
 171         struct bnxt_qplib_hwq           tim_tbl;
 172 #define MAX_TQM_ALLOC_REQ               48
 173 #define MAX_TQM_ALLOC_BLK_SIZE          8
 174         u8                              tqm_count[MAX_TQM_ALLOC_REQ];
 175         struct bnxt_qplib_hwq           tqm_pde;
 176         u32                             tqm_pde_level;
 177         struct bnxt_qplib_hwq           tqm_tbl[MAX_TQM_ALLOC_REQ];
 178         struct bnxt_qplib_stats         stats;
 179         struct bnxt_qplib_vf_res        vf_res;
 180         u64                             hwrm_intf_ver;
 181 };
 182
 183 struct bnxt_qplib_chip_ctx {
 184         u16     chip_num;
 185         u8      chip_rev;
 186         u8      chip_metal;
 187 };
 188
 189 #define CHIP_NUM_57508          0x1750
 190 #define CHIP_NUM_57504          0x1751
 191 #define CHIP_NUM_57502          0x1752
 192
 193 struct bnxt_qplib_res {
 194         struct pci_dev                  *pdev;
 195         struct bnxt_qplib_chip_ctx      *cctx;
 196         struct net_device               *netdev;
 197
 198         struct bnxt_qplib_rcfw          *rcfw;
 199         struct bnxt_qplib_pd_tbl        pd_tbl;
 200         struct bnxt_qplib_sgid_tbl      sgid_tbl;
 201         struct bnxt_qplib_pkey_tbl      pkey_tbl;
 202         struct bnxt_qplib_dpi_tbl       dpi_tbl;
 203         bool                            prio;
 204 };
 205
 206 static inline bool bnxt_qplib_is_chip_gen_p5(struct bnxt_qplib_chip_ctx *cctx)
 207 {
 208         return (cctx->chip_num == CHIP_NUM_57508 ||
 209                 cctx->chip_num == CHIP_NUM_57504 ||
 210                 cctx->chip_num == CHIP_NUM_57502);
 211 }
 212
 213 static inline u8 bnxt_qplib_get_hwq_type(struct bnxt_qplib_res *res)
 214 {
 215         return bnxt_qplib_is_chip_gen_p5(res->cctx) ?
 216                                         HWQ_TYPE_QUEUE : HWQ_TYPE_L2_CMPL;
 217 }
 218
 219 static inline u8 bnxt_qplib_get_ring_type(struct bnxt_qplib_chip_ctx *cctx)
 220 {
 221         return bnxt_qplib_is_chip_gen_p5(cctx) ?
 222                RING_ALLOC_REQ_RING_TYPE_NQ :
 223                RING_ALLOC_REQ_RING_TYPE_ROCE_CMPL;
 224 }
 225
 226 struct bnxt_qplib_sg_info {
 227         struct scatterlist              *sglist;
 228         u32                             nmap;
 229         u32                             npages;
 230 };
 231
 232 #define to_bnxt_qplib(ptr, type, member)        \
 233         container_of(ptr, type, member)
 234
 235 struct bnxt_qplib_pd;
 236 struct bnxt_qplib_dev_attr;
 237
 238 void bnxt_qplib_free_hwq(struct pci_dev *pdev, struct bnxt_qplib_hwq *hwq);
 239 int bnxt_qplib_alloc_init_hwq(struct pci_dev *pdev, struct bnxt_qplib_hwq *hwq,
 240                               struct bnxt_qplib_sg_info *sg_info, u32 *elements,
 241                               u32 elements_per_page, u32 aux, u32 pg_size,
 242                               enum bnxt_qplib_hwq_type hwq_type);
 243 void bnxt_qplib_get_guid(u8 *dev_addr, u8 *guid);
 244 int bnxt_qplib_alloc_pd(struct bnxt_qplib_pd_tbl *pd_tbl,
 245                         struct bnxt_qplib_pd *pd);
 246 int bnxt_qplib_dealloc_pd(struct bnxt_qplib_res *res,
 247                           struct bnxt_qplib_pd_tbl *pd_tbl,
 248                           struct bnxt_qplib_pd *pd);
 249 int bnxt_qplib_alloc_dpi(struct bnxt_qplib_dpi_tbl *dpit,
 250                          struct bnxt_qplib_dpi     *dpi,
 251                          void                      *app);
 252 int bnxt_qplib_dealloc_dpi(struct bnxt_qplib_res *res,
 253                            struct bnxt_qplib_dpi_tbl *dpi_tbl,
 254                            struct bnxt_qplib_dpi *dpi);
 255 void bnxt_qplib_cleanup_res(struct bnxt_qplib_res *res);
 256 int bnxt_qplib_init_res(struct bnxt_qplib_res *res);
 257 void bnxt_qplib_free_res(struct bnxt_qplib_res *res);
 258 int bnxt_qplib_alloc_res(struct bnxt_qplib_res *res, struct pci_dev *pdev,
 259                          struct net_device *netdev,
 260                          struct bnxt_qplib_dev_attr *dev_attr);
 261 void bnxt_qplib_free_ctx(struct pci_dev *pdev,
 262                          struct bnxt_qplib_ctx *ctx);
 263 int bnxt_qplib_alloc_ctx(struct pci_dev *pdev,
 264                          struct bnxt_qplib_ctx *ctx,
 265                          bool virt_fn, bool is_p5);
 266 #endif /* __BNXT_QPLIB_RES_H__ */