drivers/infiniband/hw/hfi1/platform.h

   1 /*
   2  * Copyright(c) 2015, 2016 Intel Corporation.
   3  *
   4  * This file is provided under a dual BSD/GPLv2 license.  When using or
   5  * redistributing this file, you may do so under either license.
   6  *
   7  * GPL LICENSE SUMMARY
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of version 2 of the GNU General Public License as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  16  * General Public License for more details.
  17  *
  18  * BSD LICENSE
  19  *
  20  * Redistribution and use in source and binary forms, with or without
  21  * modification, are permitted provided that the following conditions
  22  * are met:
  23  *
  24  *  - Redistributions of source code must retain the above copyright
  25  *    notice, this list of conditions and the following disclaimer.
  26  *  - Redistributions in binary form must reproduce the above copyright
  27  *    notice, this list of conditions and the following disclaimer in
  28  *    the documentation and/or other materials provided with the
  29  *    distribution.
  30  *  - Neither the name of Intel Corporation nor the names of its
  31  *    contributors may be used to endorse or promote products derived
  32  *    from this software without specific prior written permission.
  33  *
  34  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  35  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  36  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  37  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  38  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  39  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  40  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  41  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  42  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  43  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  44  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  45  *
  46  */
  47 #ifndef __PLATFORM_H
  48 #define __PLATFORM_H
  49
  50 #define METADATA_TABLE_FIELD_START_SHIFT                0
  51 #define METADATA_TABLE_FIELD_START_LEN_BITS             15
  52 #define METADATA_TABLE_FIELD_LEN_SHIFT                  16
  53 #define METADATA_TABLE_FIELD_LEN_LEN_BITS               16
  54
  55 /* Header structure */
  56 #define PLATFORM_CONFIG_HEADER_RECORD_IDX_SHIFT                 0
  57 #define PLATFORM_CONFIG_HEADER_RECORD_IDX_LEN_BITS              6
  58 #define PLATFORM_CONFIG_HEADER_TABLE_LENGTH_SHIFT               16
  59 #define PLATFORM_CONFIG_HEADER_TABLE_LENGTH_LEN_BITS            12
  60 #define PLATFORM_CONFIG_HEADER_TABLE_TYPE_SHIFT                 28
  61 #define PLATFORM_CONFIG_HEADER_TABLE_TYPE_LEN_BITS              4
  62
  63 enum platform_config_table_type_encoding {
  64         PLATFORM_CONFIG_TABLE_RESERVED,
  65         PLATFORM_CONFIG_SYSTEM_TABLE,
  66         PLATFORM_CONFIG_PORT_TABLE,
  67         PLATFORM_CONFIG_RX_PRESET_TABLE,
  68         PLATFORM_CONFIG_TX_PRESET_TABLE,
  69         PLATFORM_CONFIG_QSFP_ATTEN_TABLE,
  70         PLATFORM_CONFIG_VARIABLE_SETTINGS_TABLE,
  71         PLATFORM_CONFIG_TABLE_MAX
  72 };
  73
  74 enum platform_config_system_table_fields {
  75         SYSTEM_TABLE_RESERVED,
  76         SYSTEM_TABLE_NODE_STRING,
  77         SYSTEM_TABLE_SYSTEM_IMAGE_GUID,
  78         SYSTEM_TABLE_NODE_GUID,
  79         SYSTEM_TABLE_REVISION,
  80         SYSTEM_TABLE_VENDOR_OUI,
  81         SYSTEM_TABLE_META_VERSION,
  82         SYSTEM_TABLE_DEVICE_ID,
  83         SYSTEM_TABLE_PARTITION_ENFORCEMENT_CAP,
  84         SYSTEM_TABLE_QSFP_POWER_CLASS_MAX,
  85         SYSTEM_TABLE_QSFP_ATTENUATION_DEFAULT_12G,
  86         SYSTEM_TABLE_QSFP_ATTENUATION_DEFAULT_25G,
  87         SYSTEM_TABLE_VARIABLE_TABLE_ENTRIES_PER_PORT,
  88         SYSTEM_TABLE_MAX
  89 };
  90
  91 enum platform_config_port_table_fields {
  92         PORT_TABLE_RESERVED,
  93         PORT_TABLE_PORT_TYPE,
  94         PORT_TABLE_LOCAL_ATTEN_12G,
  95         PORT_TABLE_LOCAL_ATTEN_25G,
  96         PORT_TABLE_LINK_SPEED_SUPPORTED,
  97         PORT_TABLE_LINK_WIDTH_SUPPORTED,
  98         PORT_TABLE_AUTO_LANE_SHEDDING_ENABLED,
  99         PORT_TABLE_EXTERNAL_LOOPBACK_ALLOWED,
 100         PORT_TABLE_VL_CAP,
 101         PORT_TABLE_MTU_CAP,
 102         PORT_TABLE_TX_LANE_ENABLE_MASK,
 103         PORT_TABLE_LOCAL_MAX_TIMEOUT,
 104         PORT_TABLE_REMOTE_ATTEN_12G,
 105         PORT_TABLE_REMOTE_ATTEN_25G,
 106         PORT_TABLE_TX_PRESET_IDX_ACTIVE_NO_EQ,
 107         PORT_TABLE_TX_PRESET_IDX_ACTIVE_EQ,
 108         PORT_TABLE_RX_PRESET_IDX,
 109         PORT_TABLE_CABLE_REACH_CLASS,
 110         PORT_TABLE_MAX
 111 };
 112
 113 enum platform_config_rx_preset_table_fields {
 114         RX_PRESET_TABLE_RESERVED,
 115         RX_PRESET_TABLE_QSFP_RX_CDR_APPLY,
 116         RX_PRESET_TABLE_QSFP_RX_EMP_APPLY,
 117         RX_PRESET_TABLE_QSFP_RX_AMP_APPLY,
 118         RX_PRESET_TABLE_QSFP_RX_CDR,
 119         RX_PRESET_TABLE_QSFP_RX_EMP,
 120         RX_PRESET_TABLE_QSFP_RX_AMP,
 121         RX_PRESET_TABLE_MAX
 122 };
 123
 124 enum platform_config_tx_preset_table_fields {
 125         TX_PRESET_TABLE_RESERVED,
 126         TX_PRESET_TABLE_PRECUR,
 127         TX_PRESET_TABLE_ATTN,
 128         TX_PRESET_TABLE_POSTCUR,
 129         TX_PRESET_TABLE_QSFP_TX_CDR_APPLY,
 130         TX_PRESET_TABLE_QSFP_TX_EQ_APPLY,
 131         TX_PRESET_TABLE_QSFP_TX_CDR,
 132         TX_PRESET_TABLE_QSFP_TX_EQ,
 133         TX_PRESET_TABLE_MAX
 134 };
 135
 136 enum platform_config_qsfp_attn_table_fields {
 137         QSFP_ATTEN_TABLE_RESERVED,
 138         QSFP_ATTEN_TABLE_TX_PRESET_IDX,
 139         QSFP_ATTEN_TABLE_RX_PRESET_IDX,
 140         QSFP_ATTEN_TABLE_MAX
 141 };
 142
 143 enum platform_config_variable_settings_table_fields {
 144         VARIABLE_SETTINGS_TABLE_RESERVED,
 145         VARIABLE_SETTINGS_TABLE_TX_PRESET_IDX,
 146         VARIABLE_SETTINGS_TABLE_RX_PRESET_IDX,
 147         VARIABLE_SETTINGS_TABLE_MAX
 148 };
 149
 150 struct platform_config {
 151         size_t size;
 152         const u8 *data;
 153 };
 154
 155 struct platform_config_data {
 156         u32 *table;
 157         u32 *table_metadata;
 158         u32 num_table;
 159 };
 160
 161 /*
 162  * This struct acts as a quick reference into the platform_data binary image
 163  * and is populated by parse_platform_config(...) depending on the specific
 164  * META_VERSION
 165  */
 166 struct platform_config_cache {
 167         u8  cache_valid;
 168         struct platform_config_data config_tables[PLATFORM_CONFIG_TABLE_MAX];
 169 };
 170
 171 /* This section defines default values and encodings for the
 172  * fields defined for each table above
 173  */
 174
 175 /*
 176  * =====================================================
 177  *  System table encodings
 178  * =====================================================
 179  */
 180 #define PLATFORM_CONFIG_MAGIC_NUM               0x3d4f5041
 181 #define PLATFORM_CONFIG_MAGIC_NUMBER_LEN        4
 182
 183 /*
 184  * These power classes are the same as defined in SFF 8636 spec rev 2.4
 185  * describing byte 129 in table 6-16, except enumerated in a different order
 186  */
 187 enum platform_config_qsfp_power_class_encoding {
 188         QSFP_POWER_CLASS_1 = 1,
 189         QSFP_POWER_CLASS_2,
 190         QSFP_POWER_CLASS_3,
 191         QSFP_POWER_CLASS_4,
 192         QSFP_POWER_CLASS_5,
 193         QSFP_POWER_CLASS_6,
 194         QSFP_POWER_CLASS_7
 195 };
 196
 197 /*
 198  * ====================================================
 199  *  Port table encodings
 200  * ====================================================
 201  */
 202 enum platform_config_port_type_encoding {
 203         PORT_TYPE_UNKNOWN,
 204         PORT_TYPE_DISCONNECTED,
 205         PORT_TYPE_FIXED,
 206         PORT_TYPE_VARIABLE,
 207         PORT_TYPE_QSFP,
 208         PORT_TYPE_MAX
 209 };
 210
 211 enum platform_config_link_speed_supported_encoding {
 212         LINK_SPEED_SUPP_12G = 1,
 213         LINK_SPEED_SUPP_25G,
 214         LINK_SPEED_SUPP_12G_25G,
 215         LINK_SPEED_SUPP_MAX
 216 };
 217
 218 /*
 219  * This is a subset (not strict) of the link downgrades
 220  * supported. The link downgrades supported are expected
 221  * to be supplied to the driver by another entity such as
 222  * the fabric manager
 223  */
 224 enum platform_config_link_width_supported_encoding {
 225         LINK_WIDTH_SUPP_1X = 1,
 226         LINK_WIDTH_SUPP_2X,
 227         LINK_WIDTH_SUPP_2X_1X,
 228         LINK_WIDTH_SUPP_3X,
 229         LINK_WIDTH_SUPP_3X_1X,
 230         LINK_WIDTH_SUPP_3X_2X,
 231         LINK_WIDTH_SUPP_3X_2X_1X,
 232         LINK_WIDTH_SUPP_4X,
 233         LINK_WIDTH_SUPP_4X_1X,
 234         LINK_WIDTH_SUPP_4X_2X,
 235         LINK_WIDTH_SUPP_4X_2X_1X,
 236         LINK_WIDTH_SUPP_4X_3X,
 237         LINK_WIDTH_SUPP_4X_3X_1X,
 238         LINK_WIDTH_SUPP_4X_3X_2X,
 239         LINK_WIDTH_SUPP_4X_3X_2X_1X,
 240         LINK_WIDTH_SUPP_MAX
 241 };
 242
 243 enum platform_config_virtual_lane_capability_encoding {
 244         VL_CAP_VL0 = 1,
 245         VL_CAP_VL0_1,
 246         VL_CAP_VL0_2,
 247         VL_CAP_VL0_3,
 248         VL_CAP_VL0_4,
 249         VL_CAP_VL0_5,
 250         VL_CAP_VL0_6,
 251         VL_CAP_VL0_7,
 252         VL_CAP_VL0_8,
 253         VL_CAP_VL0_9,
 254         VL_CAP_VL0_10,
 255         VL_CAP_VL0_11,
 256         VL_CAP_VL0_12,
 257         VL_CAP_VL0_13,
 258         VL_CAP_VL0_14,
 259         VL_CAP_MAX
 260 };
 261
 262 /* Max MTU */
 263 enum platform_config_mtu_capability_encoding {
 264         MTU_CAP_256   = 1,
 265         MTU_CAP_512   = 2,
 266         MTU_CAP_1024  = 3,
 267         MTU_CAP_2048  = 4,
 268         MTU_CAP_4096  = 5,
 269         MTU_CAP_8192  = 6,
 270         MTU_CAP_10240 = 7
 271 };
 272
 273 enum platform_config_local_max_timeout_encoding {
 274         LOCAL_MAX_TIMEOUT_10_MS = 1,
 275         LOCAL_MAX_TIMEOUT_100_MS,
 276         LOCAL_MAX_TIMEOUT_1_S,
 277         LOCAL_MAX_TIMEOUT_10_S,
 278         LOCAL_MAX_TIMEOUT_100_S,
 279         LOCAL_MAX_TIMEOUT_1000_S
 280 };
 281
 282 enum link_tuning_encoding {
 283         OPA_PASSIVE_TUNING,
 284         OPA_ACTIVE_TUNING,
 285         OPA_UNKNOWN_TUNING
 286 };
 287
 288 /*
 289  * Shifts and masks for the link SI tuning values stuffed into the ASIC scratch
 290  * registers for integrated platforms
 291  */
 292 #define PORT0_PORT_TYPE_SHIFT           0
 293 #define PORT0_LOCAL_ATTEN_SHIFT         4
 294 #define PORT0_REMOTE_ATTEN_SHIFT        10
 295 #define PORT0_DEFAULT_ATTEN_SHIFT       32
 296
 297 #define PORT1_PORT_TYPE_SHIFT           16
 298 #define PORT1_LOCAL_ATTEN_SHIFT         20
 299 #define PORT1_REMOTE_ATTEN_SHIFT        26
 300 #define PORT1_DEFAULT_ATTEN_SHIFT       40
 301
 302 #define PORT0_PORT_TYPE_MASK            0xFUL
 303 #define PORT0_LOCAL_ATTEN_MASK          0x3FUL
 304 #define PORT0_REMOTE_ATTEN_MASK         0x3FUL
 305 #define PORT0_DEFAULT_ATTEN_MASK        0xFFUL
 306
 307 #define PORT1_PORT_TYPE_MASK            0xFUL
 308 #define PORT1_LOCAL_ATTEN_MASK          0x3FUL
 309 #define PORT1_REMOTE_ATTEN_MASK         0x3FUL
 310 #define PORT1_DEFAULT_ATTEN_MASK        0xFFUL
 311
 312 #define PORT0_PORT_TYPE_SMASK           (PORT0_PORT_TYPE_MASK << \
 313                                          PORT0_PORT_TYPE_SHIFT)
 314 #define PORT0_LOCAL_ATTEN_SMASK         (PORT0_LOCAL_ATTEN_MASK << \
 315                                          PORT0_LOCAL_ATTEN_SHIFT)
 316 #define PORT0_REMOTE_ATTEN_SMASK        (PORT0_REMOTE_ATTEN_MASK << \
 317                                          PORT0_REMOTE_ATTEN_SHIFT)
 318 #define PORT0_DEFAULT_ATTEN_SMASK       (PORT0_DEFAULT_ATTEN_MASK << \
 319                                          PORT0_DEFAULT_ATTEN_SHIFT)
 320
 321 #define PORT1_PORT_TYPE_SMASK           (PORT1_PORT_TYPE_MASK << \
 322                                          PORT1_PORT_TYPE_SHIFT)
 323 #define PORT1_LOCAL_ATTEN_SMASK         (PORT1_LOCAL_ATTEN_MASK << \
 324                                          PORT1_LOCAL_ATTEN_SHIFT)
 325 #define PORT1_REMOTE_ATTEN_SMASK        (PORT1_REMOTE_ATTEN_MASK << \
 326                                          PORT1_REMOTE_ATTEN_SHIFT)
 327 #define PORT1_DEFAULT_ATTEN_SMASK       (PORT1_DEFAULT_ATTEN_MASK << \
 328                                          PORT1_DEFAULT_ATTEN_SHIFT)
 329
 330 #define QSFP_MAX_POWER_SHIFT            0
 331 #define TX_NO_EQ_SHIFT                  4
 332 #define TX_EQ_SHIFT                     25
 333 #define RX_SHIFT                        46
 334
 335 #define QSFP_MAX_POWER_MASK             0xFUL
 336 #define TX_NO_EQ_MASK                   0x1FFFFFUL
 337 #define TX_EQ_MASK                      0x1FFFFFUL
 338 #define RX_MASK                         0xFFFFUL
 339
 340 #define QSFP_MAX_POWER_SMASK            (QSFP_MAX_POWER_MASK << \
 341                                          QSFP_MAX_POWER_SHIFT)
 342 #define TX_NO_EQ_SMASK                  (TX_NO_EQ_MASK << TX_NO_EQ_SHIFT)
 343 #define TX_EQ_SMASK                     (TX_EQ_MASK << TX_EQ_SHIFT)
 344 #define RX_SMASK                        (RX_MASK << RX_SHIFT)
 345
 346 #define TX_PRECUR_SHIFT                 0
 347 #define TX_ATTN_SHIFT                   4
 348 #define QSFP_TX_CDR_APPLY_SHIFT         9
 349 #define QSFP_TX_EQ_APPLY_SHIFT          10
 350 #define QSFP_TX_CDR_SHIFT               11
 351 #define QSFP_TX_EQ_SHIFT                12
 352 #define TX_POSTCUR_SHIFT                16
 353
 354 #define TX_PRECUR_MASK                  0xFUL
 355 #define TX_ATTN_MASK                    0x1FUL
 356 #define QSFP_TX_CDR_APPLY_MASK          0x1UL
 357 #define QSFP_TX_EQ_APPLY_MASK           0x1UL
 358 #define QSFP_TX_CDR_MASK                0x1UL
 359 #define QSFP_TX_EQ_MASK                 0xFUL
 360 #define TX_POSTCUR_MASK                 0x1FUL
 361
 362 #define TX_PRECUR_SMASK                 (TX_PRECUR_MASK << TX_PRECUR_SHIFT)
 363 #define TX_ATTN_SMASK                   (TX_ATTN_MASK << TX_ATTN_SHIFT)
 364 #define QSFP_TX_CDR_APPLY_SMASK         (QSFP_TX_CDR_APPLY_MASK << \
 365                                          QSFP_TX_CDR_APPLY_SHIFT)
 366 #define QSFP_TX_EQ_APPLY_SMASK          (QSFP_TX_EQ_APPLY_MASK << \
 367                                          QSFP_TX_EQ_APPLY_SHIFT)
 368 #define QSFP_TX_CDR_SMASK               (QSFP_TX_CDR_MASK << QSFP_TX_CDR_SHIFT)
 369 #define QSFP_TX_EQ_SMASK                (QSFP_TX_EQ_MASK << QSFP_TX_EQ_SHIFT)
 370 #define TX_POSTCUR_SMASK                (TX_POSTCUR_MASK << TX_POSTCUR_SHIFT)
 371
 372 #define QSFP_RX_CDR_APPLY_SHIFT         0
 373 #define QSFP_RX_EMP_APPLY_SHIFT         1
 374 #define QSFP_RX_AMP_APPLY_SHIFT         2
 375 #define QSFP_RX_CDR_SHIFT               3
 376 #define QSFP_RX_EMP_SHIFT               4
 377 #define QSFP_RX_AMP_SHIFT               8
 378
 379 #define QSFP_RX_CDR_APPLY_MASK          0x1UL
 380 #define QSFP_RX_EMP_APPLY_MASK          0x1UL
 381 #define QSFP_RX_AMP_APPLY_MASK          0x1UL
 382 #define QSFP_RX_CDR_MASK                0x1UL
 383 #define QSFP_RX_EMP_MASK                0xFUL
 384 #define QSFP_RX_AMP_MASK                0x3UL
 385
 386 #define QSFP_RX_CDR_APPLY_SMASK         (QSFP_RX_CDR_APPLY_MASK << \
 387                                          QSFP_RX_CDR_APPLY_SHIFT)
 388 #define QSFP_RX_EMP_APPLY_SMASK         (QSFP_RX_EMP_APPLY_MASK << \
 389                                          QSFP_RX_EMP_APPLY_SHIFT)
 390 #define QSFP_RX_AMP_APPLY_SMASK         (QSFP_RX_AMP_APPLY_MASK << \
 391                                          QSFP_RX_AMP_APPLY_SHIFT)
 392 #define QSFP_RX_CDR_SMASK               (QSFP_RX_CDR_MASK << QSFP_RX_CDR_SHIFT)
 393 #define QSFP_RX_EMP_SMASK               (QSFP_RX_EMP_MASK << QSFP_RX_EMP_SHIFT)
 394 #define QSFP_RX_AMP_SMASK               (QSFP_RX_AMP_MASK << QSFP_RX_AMP_SHIFT)
 395
 396 #define BITMAP_VERSION                  1
 397 #define BITMAP_VERSION_SHIFT            44
 398 #define BITMAP_VERSION_MASK             0xFUL
 399 #define BITMAP_VERSION_SMASK            (BITMAP_VERSION_MASK << \
 400                                          BITMAP_VERSION_SHIFT)
 401 #define CHECKSUM_SHIFT                  48
 402 #define CHECKSUM_MASK                   0xFFFFUL
 403 #define CHECKSUM_SMASK                  (CHECKSUM_MASK << CHECKSUM_SHIFT)
 404
 405 /* platform.c */
 406 void get_platform_config(struct hfi1_devdata *dd);
 407 void free_platform_config(struct hfi1_devdata *dd);
 408 void get_port_type(struct hfi1_pportdata *ppd);
 409 int set_qsfp_tx(struct hfi1_pportdata *ppd, int on);
 410 void tune_serdes(struct hfi1_pportdata *ppd);
 411
 412 #endif                  /*__PLATFORM_H*/