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treewide: remove redundant IS_ERR() before error code check
[linux/fpc-iii.git] / drivers / infiniband / hw / hns / hns_roce_hw_v1.c
blobc6e66586e533fef0a5aada35eabb9c7434235cf9
1 /*
2 * Copyright (c) 2016 Hisilicon Limited.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #include <linux/platform_device.h>
34 #include <linux/acpi.h>
35 #include <linux/etherdevice.h>
36 #include <linux/interrupt.h>
37 #include <linux/of.h>
38 #include <linux/of_platform.h>
39 #include <rdma/ib_umem.h>
40 #include "hns_roce_common.h"
41 #include "hns_roce_device.h"
42 #include "hns_roce_cmd.h"
43 #include "hns_roce_hem.h"
44 #include "hns_roce_hw_v1.h"
45
46 static void set_data_seg(struct hns_roce_wqe_data_seg *dseg, struct ib_sge *sg)
47 {
48 dseg->lkey = cpu_to_le32(sg->lkey);
49 dseg->addr = cpu_to_le64(sg->addr);
50 dseg->len = cpu_to_le32(sg->length);
51 }
52
53 static void set_raddr_seg(struct hns_roce_wqe_raddr_seg *rseg, u64 remote_addr,
54 u32 rkey)
55 {
56 rseg->raddr = cpu_to_le64(remote_addr);
57 rseg->rkey = cpu_to_le32(rkey);
58 rseg->len = 0;
59 }
60
61 static int hns_roce_v1_post_send(struct ib_qp *ibqp,
62 const struct ib_send_wr *wr,
63 const struct ib_send_wr **bad_wr)
64 {
65 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
66 struct hns_roce_ah *ah = to_hr_ah(ud_wr(wr)->ah);
67 struct hns_roce_ud_send_wqe *ud_sq_wqe = NULL;
68 struct hns_roce_wqe_ctrl_seg *ctrl = NULL;
69 struct hns_roce_wqe_data_seg *dseg = NULL;
70 struct hns_roce_qp *qp = to_hr_qp(ibqp);
71 struct device *dev = &hr_dev->pdev->dev;
72 struct hns_roce_sq_db sq_db;
73 int ps_opcode = 0, i = 0;
74 unsigned long flags = 0;
75 void *wqe = NULL;
76 __le32 doorbell[2];
77 u32 wqe_idx = 0;
78 int nreq = 0;
79 int ret = 0;
80 u8 *smac;
81 int loopback;
82
83 if (unlikely(ibqp->qp_type != IB_QPT_GSI &&
84 ibqp->qp_type != IB_QPT_RC)) {
85 dev_err(dev, "un-supported QP type\n");
86 *bad_wr = NULL;
87 return -EOPNOTSUPP;
88 }
89
90 spin_lock_irqsave(&qp->sq.lock, flags);
91
92 for (nreq = 0; wr; ++nreq, wr = wr->next) {
93 if (hns_roce_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
94 ret = -ENOMEM;
95 *bad_wr = wr;
96 goto out;
97 }
98
99 wqe_idx = (qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1);
100
101 if (unlikely(wr->num_sge > qp->sq.max_gs)) {
102 dev_err(dev, "num_sge=%d > qp->sq.max_gs=%d\n",
103 wr->num_sge, qp->sq.max_gs);
104 ret = -EINVAL;
105 *bad_wr = wr;
106 goto out;
107 }
108
109 wqe = get_send_wqe(qp, wqe_idx);
110 qp->sq.wrid[wqe_idx] = wr->wr_id;
111
112 /* Corresponding to the RC and RD type wqe process separately */
113 if (ibqp->qp_type == IB_QPT_GSI) {
114 ud_sq_wqe = wqe;
115 roce_set_field(ud_sq_wqe->dmac_h,
116 UD_SEND_WQE_U32_4_DMAC_0_M,
117 UD_SEND_WQE_U32_4_DMAC_0_S,
118 ah->av.mac[0]);
119 roce_set_field(ud_sq_wqe->dmac_h,
120 UD_SEND_WQE_U32_4_DMAC_1_M,
121 UD_SEND_WQE_U32_4_DMAC_1_S,
122 ah->av.mac[1]);
123 roce_set_field(ud_sq_wqe->dmac_h,
124 UD_SEND_WQE_U32_4_DMAC_2_M,
125 UD_SEND_WQE_U32_4_DMAC_2_S,
126 ah->av.mac[2]);
127 roce_set_field(ud_sq_wqe->dmac_h,
128 UD_SEND_WQE_U32_4_DMAC_3_M,
129 UD_SEND_WQE_U32_4_DMAC_3_S,
130 ah->av.mac[3]);
131
132 roce_set_field(ud_sq_wqe->u32_8,
133 UD_SEND_WQE_U32_8_DMAC_4_M,
134 UD_SEND_WQE_U32_8_DMAC_4_S,
135 ah->av.mac[4]);
136 roce_set_field(ud_sq_wqe->u32_8,
137 UD_SEND_WQE_U32_8_DMAC_5_M,
138 UD_SEND_WQE_U32_8_DMAC_5_S,
139 ah->av.mac[5]);
140
141 smac = (u8 *)hr_dev->dev_addr[qp->port];
142 loopback = ether_addr_equal_unaligned(ah->av.mac,
143 smac) ? 1 : 0;
144 roce_set_bit(ud_sq_wqe->u32_8,
145 UD_SEND_WQE_U32_8_LOOPBACK_INDICATOR_S,
146 loopback);
147
148 roce_set_field(ud_sq_wqe->u32_8,
149 UD_SEND_WQE_U32_8_OPERATION_TYPE_M,
150 UD_SEND_WQE_U32_8_OPERATION_TYPE_S,
151 HNS_ROCE_WQE_OPCODE_SEND);
152 roce_set_field(ud_sq_wqe->u32_8,
153 UD_SEND_WQE_U32_8_NUMBER_OF_DATA_SEG_M,
154 UD_SEND_WQE_U32_8_NUMBER_OF_DATA_SEG_S,
155 2);
156 roce_set_bit(ud_sq_wqe->u32_8,
157 UD_SEND_WQE_U32_8_SEND_GL_ROUTING_HDR_FLAG_S,
158 1);
159
160 ud_sq_wqe->u32_8 |= (wr->send_flags & IB_SEND_SIGNALED ?
161 cpu_to_le32(HNS_ROCE_WQE_CQ_NOTIFY) : 0) |
162 (wr->send_flags & IB_SEND_SOLICITED ?
163 cpu_to_le32(HNS_ROCE_WQE_SE) : 0) |
164 ((wr->opcode == IB_WR_SEND_WITH_IMM) ?
165 cpu_to_le32(HNS_ROCE_WQE_IMM) : 0);
166
167 roce_set_field(ud_sq_wqe->u32_16,
168 UD_SEND_WQE_U32_16_DEST_QP_M,
169 UD_SEND_WQE_U32_16_DEST_QP_S,
170 ud_wr(wr)->remote_qpn);
171 roce_set_field(ud_sq_wqe->u32_16,
172 UD_SEND_WQE_U32_16_MAX_STATIC_RATE_M,
173 UD_SEND_WQE_U32_16_MAX_STATIC_RATE_S,
174 ah->av.stat_rate);
175
176 roce_set_field(ud_sq_wqe->u32_36,
177 UD_SEND_WQE_U32_36_FLOW_LABEL_M,
178 UD_SEND_WQE_U32_36_FLOW_LABEL_S,
179 ah->av.flowlabel);
180 roce_set_field(ud_sq_wqe->u32_36,
181 UD_SEND_WQE_U32_36_PRIORITY_M,
182 UD_SEND_WQE_U32_36_PRIORITY_S,
183 ah->av.sl);
184 roce_set_field(ud_sq_wqe->u32_36,
185 UD_SEND_WQE_U32_36_SGID_INDEX_M,
186 UD_SEND_WQE_U32_36_SGID_INDEX_S,
187 hns_get_gid_index(hr_dev, qp->phy_port,
188 ah->av.gid_index));
189
190 roce_set_field(ud_sq_wqe->u32_40,
191 UD_SEND_WQE_U32_40_HOP_LIMIT_M,
192 UD_SEND_WQE_U32_40_HOP_LIMIT_S,
193 ah->av.hop_limit);
194 roce_set_field(ud_sq_wqe->u32_40,
195 UD_SEND_WQE_U32_40_TRAFFIC_CLASS_M,
196 UD_SEND_WQE_U32_40_TRAFFIC_CLASS_S,
197 ah->av.tclass);
198
199 memcpy(&ud_sq_wqe->dgid[0], &ah->av.dgid[0], GID_LEN);
200
201 ud_sq_wqe->va0_l =
202 cpu_to_le32((u32)wr->sg_list[0].addr);
203 ud_sq_wqe->va0_h =
204 cpu_to_le32((wr->sg_list[0].addr) >> 32);
205 ud_sq_wqe->l_key0 =
206 cpu_to_le32(wr->sg_list[0].lkey);
207
208 ud_sq_wqe->va1_l =
209 cpu_to_le32((u32)wr->sg_list[1].addr);
210 ud_sq_wqe->va1_h =
211 cpu_to_le32((wr->sg_list[1].addr) >> 32);
212 ud_sq_wqe->l_key1 =
213 cpu_to_le32(wr->sg_list[1].lkey);
214 } else if (ibqp->qp_type == IB_QPT_RC) {
215 u32 tmp_len = 0;
216
217 ctrl = wqe;
218 memset(ctrl, 0, sizeof(struct hns_roce_wqe_ctrl_seg));
219 for (i = 0; i < wr->num_sge; i++)
220 tmp_len += wr->sg_list[i].length;
221
222 ctrl->msg_length =
223 cpu_to_le32(le32_to_cpu(ctrl->msg_length) + tmp_len);
224
225 ctrl->sgl_pa_h = 0;
226 ctrl->flag = 0;
227
228 switch (wr->opcode) {
229 case IB_WR_SEND_WITH_IMM:
230 case IB_WR_RDMA_WRITE_WITH_IMM:
231 ctrl->imm_data = wr->ex.imm_data;
232 break;
233 case IB_WR_SEND_WITH_INV:
234 ctrl->inv_key =
235 cpu_to_le32(wr->ex.invalidate_rkey);
236 break;
237 default:
238 ctrl->imm_data = 0;
239 break;
240 }
241
242 /*Ctrl field, ctrl set type: sig, solic, imm, fence */
243 /* SO wait for conforming application scenarios */
244 ctrl->flag |= (wr->send_flags & IB_SEND_SIGNALED ?
245 cpu_to_le32(HNS_ROCE_WQE_CQ_NOTIFY) : 0) |
246 (wr->send_flags & IB_SEND_SOLICITED ?
247 cpu_to_le32(HNS_ROCE_WQE_SE) : 0) |
248 ((wr->opcode == IB_WR_SEND_WITH_IMM ||
249 wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM) ?
250 cpu_to_le32(HNS_ROCE_WQE_IMM) : 0) |
251 (wr->send_flags & IB_SEND_FENCE ?
252 (cpu_to_le32(HNS_ROCE_WQE_FENCE)) : 0);
253
254 wqe += sizeof(struct hns_roce_wqe_ctrl_seg);
255
256 switch (wr->opcode) {
257 case IB_WR_RDMA_READ:
258 ps_opcode = HNS_ROCE_WQE_OPCODE_RDMA_READ;
259 set_raddr_seg(wqe, rdma_wr(wr)->remote_addr,
260 rdma_wr(wr)->rkey);
261 break;
262 case IB_WR_RDMA_WRITE:
263 case IB_WR_RDMA_WRITE_WITH_IMM:
264 ps_opcode = HNS_ROCE_WQE_OPCODE_RDMA_WRITE;
265 set_raddr_seg(wqe, rdma_wr(wr)->remote_addr,
266 rdma_wr(wr)->rkey);
267 break;
268 case IB_WR_SEND:
269 case IB_WR_SEND_WITH_INV:
270 case IB_WR_SEND_WITH_IMM:
271 ps_opcode = HNS_ROCE_WQE_OPCODE_SEND;
272 break;
273 case IB_WR_LOCAL_INV:
274 break;
275 case IB_WR_ATOMIC_CMP_AND_SWP:
276 case IB_WR_ATOMIC_FETCH_AND_ADD:
277 case IB_WR_LSO:
278 default:
279 ps_opcode = HNS_ROCE_WQE_OPCODE_MASK;
280 break;
281 }
282 ctrl->flag |= cpu_to_le32(ps_opcode);
283 wqe += sizeof(struct hns_roce_wqe_raddr_seg);
284
285 dseg = wqe;
286 if (wr->send_flags & IB_SEND_INLINE && wr->num_sge) {
287 if (le32_to_cpu(ctrl->msg_length) >
288 hr_dev->caps.max_sq_inline) {
289 ret = -EINVAL;
290 *bad_wr = wr;
291 dev_err(dev, "inline len(1-%d)=%d, illegal",
292 ctrl->msg_length,
293 hr_dev->caps.max_sq_inline);
294 goto out;
295 }
296 for (i = 0; i < wr->num_sge; i++) {
297 memcpy(wqe, ((void *) (uintptr_t)
298 wr->sg_list[i].addr),
299 wr->sg_list[i].length);
300 wqe += wr->sg_list[i].length;
301 }
302 ctrl->flag |= cpu_to_le32(HNS_ROCE_WQE_INLINE);
303 } else {
304 /*sqe num is two */
305 for (i = 0; i < wr->num_sge; i++)
306 set_data_seg(dseg + i, wr->sg_list + i);
307
308 ctrl->flag |= cpu_to_le32(wr->num_sge <<
309 HNS_ROCE_WQE_SGE_NUM_BIT);
310 }
311 }
312 }
313
314 out:
315 /* Set DB return */
316 if (likely(nreq)) {
317 qp->sq.head += nreq;
318 /* Memory barrier */
319 wmb();
320
321 sq_db.u32_4 = 0;
322 sq_db.u32_8 = 0;
323 roce_set_field(sq_db.u32_4, SQ_DOORBELL_U32_4_SQ_HEAD_M,
324 SQ_DOORBELL_U32_4_SQ_HEAD_S,
325 (qp->sq.head & ((qp->sq.wqe_cnt << 1) - 1)));
326 roce_set_field(sq_db.u32_4, SQ_DOORBELL_U32_4_SL_M,
327 SQ_DOORBELL_U32_4_SL_S, qp->sl);
328 roce_set_field(sq_db.u32_4, SQ_DOORBELL_U32_4_PORT_M,
329 SQ_DOORBELL_U32_4_PORT_S, qp->phy_port);
330 roce_set_field(sq_db.u32_8, SQ_DOORBELL_U32_8_QPN_M,
331 SQ_DOORBELL_U32_8_QPN_S, qp->doorbell_qpn);
332 roce_set_bit(sq_db.u32_8, SQ_DOORBELL_HW_SYNC_S, 1);
333
334 doorbell[0] = sq_db.u32_4;
335 doorbell[1] = sq_db.u32_8;
336
337 hns_roce_write64_k(doorbell, qp->sq.db_reg_l);
338 }
339
340 spin_unlock_irqrestore(&qp->sq.lock, flags);
341
342 return ret;
343 }
344
345 static int hns_roce_v1_post_recv(struct ib_qp *ibqp,
346 const struct ib_recv_wr *wr,
347 const struct ib_recv_wr **bad_wr)
348 {
349 struct hns_roce_rq_wqe_ctrl *ctrl = NULL;
350 struct hns_roce_wqe_data_seg *scat = NULL;
351 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
352 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
353 struct device *dev = &hr_dev->pdev->dev;
354 struct hns_roce_rq_db rq_db;
355 __le32 doorbell[2] = {0};
356 unsigned long flags = 0;
357 unsigned int wqe_idx;
358 int ret = 0;
359 int nreq = 0;
360 int i = 0;
361 u32 reg_val;
362
363 spin_lock_irqsave(&hr_qp->rq.lock, flags);
364
365 for (nreq = 0; wr; ++nreq, wr = wr->next) {
366 if (hns_roce_wq_overflow(&hr_qp->rq, nreq,
367 hr_qp->ibqp.recv_cq)) {
368 ret = -ENOMEM;
369 *bad_wr = wr;
370 goto out;
371 }
372
373 wqe_idx = (hr_qp->rq.head + nreq) & (hr_qp->rq.wqe_cnt - 1);
374
375 if (unlikely(wr->num_sge > hr_qp->rq.max_gs)) {
376 dev_err(dev, "rq:num_sge=%d > qp->sq.max_gs=%d\n",
377 wr->num_sge, hr_qp->rq.max_gs);
378 ret = -EINVAL;
379 *bad_wr = wr;
380 goto out;
381 }
382
383 ctrl = get_recv_wqe(hr_qp, wqe_idx);
384
385 roce_set_field(ctrl->rwqe_byte_12,
386 RQ_WQE_CTRL_RWQE_BYTE_12_RWQE_SGE_NUM_M,
387 RQ_WQE_CTRL_RWQE_BYTE_12_RWQE_SGE_NUM_S,
388 wr->num_sge);
389
390 scat = (struct hns_roce_wqe_data_seg *)(ctrl + 1);
391
392 for (i = 0; i < wr->num_sge; i++)
393 set_data_seg(scat + i, wr->sg_list + i);
394
395 hr_qp->rq.wrid[wqe_idx] = wr->wr_id;
396 }
397
398 out:
399 if (likely(nreq)) {
400 hr_qp->rq.head += nreq;
401 /* Memory barrier */
402 wmb();
403
404 if (ibqp->qp_type == IB_QPT_GSI) {
405 __le32 tmp;
406
407 /* SW update GSI rq header */
408 reg_val = roce_read(to_hr_dev(ibqp->device),
409 ROCEE_QP1C_CFG3_0_REG +
410 QP1C_CFGN_OFFSET * hr_qp->phy_port);
411 tmp = cpu_to_le32(reg_val);
412 roce_set_field(tmp,
413 ROCEE_QP1C_CFG3_0_ROCEE_QP1C_RQ_HEAD_M,
414 ROCEE_QP1C_CFG3_0_ROCEE_QP1C_RQ_HEAD_S,
415 hr_qp->rq.head);
416 reg_val = le32_to_cpu(tmp);
417 roce_write(to_hr_dev(ibqp->device),
418 ROCEE_QP1C_CFG3_0_REG +
419 QP1C_CFGN_OFFSET * hr_qp->phy_port, reg_val);
420 } else {
421 rq_db.u32_4 = 0;
422 rq_db.u32_8 = 0;
423
424 roce_set_field(rq_db.u32_4, RQ_DOORBELL_U32_4_RQ_HEAD_M,
425 RQ_DOORBELL_U32_4_RQ_HEAD_S,
426 hr_qp->rq.head);
427 roce_set_field(rq_db.u32_8, RQ_DOORBELL_U32_8_QPN_M,
428 RQ_DOORBELL_U32_8_QPN_S, hr_qp->qpn);
429 roce_set_field(rq_db.u32_8, RQ_DOORBELL_U32_8_CMD_M,
430 RQ_DOORBELL_U32_8_CMD_S, 1);
431 roce_set_bit(rq_db.u32_8, RQ_DOORBELL_U32_8_HW_SYNC_S,
432 1);
433
434 doorbell[0] = rq_db.u32_4;
435 doorbell[1] = rq_db.u32_8;
436
437 hns_roce_write64_k(doorbell, hr_qp->rq.db_reg_l);
438 }
439 }
440 spin_unlock_irqrestore(&hr_qp->rq.lock, flags);
441
442 return ret;
443 }
444
445 static void hns_roce_set_db_event_mode(struct hns_roce_dev *hr_dev,
446 int sdb_mode, int odb_mode)
447 {
448 __le32 tmp;
449 u32 val;
450
451 val = roce_read(hr_dev, ROCEE_GLB_CFG_REG);
452 tmp = cpu_to_le32(val);
453 roce_set_bit(tmp, ROCEE_GLB_CFG_ROCEE_DB_SQ_MODE_S, sdb_mode);
454 roce_set_bit(tmp, ROCEE_GLB_CFG_ROCEE_DB_OTH_MODE_S, odb_mode);
455 val = le32_to_cpu(tmp);
456 roce_write(hr_dev, ROCEE_GLB_CFG_REG, val);
457 }
458
459 static void hns_roce_set_db_ext_mode(struct hns_roce_dev *hr_dev, u32 sdb_mode,
460 u32 odb_mode)
461 {
462 __le32 tmp;
463 u32 val;
464
465 /* Configure SDB/ODB extend mode */
466 val = roce_read(hr_dev, ROCEE_GLB_CFG_REG);
467 tmp = cpu_to_le32(val);
468 roce_set_bit(tmp, ROCEE_GLB_CFG_SQ_EXT_DB_MODE_S, sdb_mode);
469 roce_set_bit(tmp, ROCEE_GLB_CFG_OTH_EXT_DB_MODE_S, odb_mode);
470 val = le32_to_cpu(tmp);
471 roce_write(hr_dev, ROCEE_GLB_CFG_REG, val);
472 }
473
474 static void hns_roce_set_sdb(struct hns_roce_dev *hr_dev, u32 sdb_alept,
475 u32 sdb_alful)
476 {
477 __le32 tmp;
478 u32 val;
479
480 /* Configure SDB */
481 val = roce_read(hr_dev, ROCEE_DB_SQ_WL_REG);
482 tmp = cpu_to_le32(val);
483 roce_set_field(tmp, ROCEE_DB_SQ_WL_ROCEE_DB_SQ_WL_M,
484 ROCEE_DB_SQ_WL_ROCEE_DB_SQ_WL_S, sdb_alful);
485 roce_set_field(tmp, ROCEE_DB_SQ_WL_ROCEE_DB_SQ_WL_EMPTY_M,
486 ROCEE_DB_SQ_WL_ROCEE_DB_SQ_WL_EMPTY_S, sdb_alept);
487 val = le32_to_cpu(tmp);
488 roce_write(hr_dev, ROCEE_DB_SQ_WL_REG, val);
489 }
490
491 static void hns_roce_set_odb(struct hns_roce_dev *hr_dev, u32 odb_alept,
492 u32 odb_alful)
493 {
494 __le32 tmp;
495 u32 val;
496
497 /* Configure ODB */
498 val = roce_read(hr_dev, ROCEE_DB_OTHERS_WL_REG);
499 tmp = cpu_to_le32(val);
500 roce_set_field(tmp, ROCEE_DB_OTHERS_WL_ROCEE_DB_OTH_WL_M,
501 ROCEE_DB_OTHERS_WL_ROCEE_DB_OTH_WL_S, odb_alful);
502 roce_set_field(tmp, ROCEE_DB_OTHERS_WL_ROCEE_DB_OTH_WL_EMPTY_M,
503 ROCEE_DB_OTHERS_WL_ROCEE_DB_OTH_WL_EMPTY_S, odb_alept);
504 val = le32_to_cpu(tmp);
505 roce_write(hr_dev, ROCEE_DB_OTHERS_WL_REG, val);
506 }
507
508 static void hns_roce_set_sdb_ext(struct hns_roce_dev *hr_dev, u32 ext_sdb_alept,
509 u32 ext_sdb_alful)
510 {
511 struct device *dev = &hr_dev->pdev->dev;
512 struct hns_roce_v1_priv *priv;
513 struct hns_roce_db_table *db;
514 dma_addr_t sdb_dma_addr;
515 __le32 tmp;
516 u32 val;
517
518 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
519 db = &priv->db_table;
520
521 /* Configure extend SDB threshold */
522 roce_write(hr_dev, ROCEE_EXT_DB_SQ_WL_EMPTY_REG, ext_sdb_alept);
523 roce_write(hr_dev, ROCEE_EXT_DB_SQ_WL_REG, ext_sdb_alful);
524
525 /* Configure extend SDB base addr */
526 sdb_dma_addr = db->ext_db->sdb_buf_list->map;
527 roce_write(hr_dev, ROCEE_EXT_DB_SQ_REG, (u32)(sdb_dma_addr >> 12));
528
529 /* Configure extend SDB depth */
530 val = roce_read(hr_dev, ROCEE_EXT_DB_SQ_H_REG);
531 tmp = cpu_to_le32(val);
532 roce_set_field(tmp, ROCEE_EXT_DB_SQ_H_EXT_DB_SQ_SHIFT_M,
533 ROCEE_EXT_DB_SQ_H_EXT_DB_SQ_SHIFT_S,
534 db->ext_db->esdb_dep);
535 /*
536 * 44 = 32 + 12, When evaluating addr to hardware, shift 12 because of
537 * using 4K page, and shift more 32 because of
538 * caculating the high 32 bit value evaluated to hardware.
539 */
540 roce_set_field(tmp, ROCEE_EXT_DB_SQ_H_EXT_DB_SQ_BA_H_M,
541 ROCEE_EXT_DB_SQ_H_EXT_DB_SQ_BA_H_S, sdb_dma_addr >> 44);
542 val = le32_to_cpu(tmp);
543 roce_write(hr_dev, ROCEE_EXT_DB_SQ_H_REG, val);
544
545 dev_dbg(dev, "ext SDB depth: 0x%x\n", db->ext_db->esdb_dep);
546 dev_dbg(dev, "ext SDB threshold: epmty: 0x%x, ful: 0x%x\n",
547 ext_sdb_alept, ext_sdb_alful);
548 }
549
550 static void hns_roce_set_odb_ext(struct hns_roce_dev *hr_dev, u32 ext_odb_alept,
551 u32 ext_odb_alful)
552 {
553 struct device *dev = &hr_dev->pdev->dev;
554 struct hns_roce_v1_priv *priv;
555 struct hns_roce_db_table *db;
556 dma_addr_t odb_dma_addr;
557 __le32 tmp;
558 u32 val;
559
560 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
561 db = &priv->db_table;
562
563 /* Configure extend ODB threshold */
564 roce_write(hr_dev, ROCEE_EXT_DB_OTHERS_WL_EMPTY_REG, ext_odb_alept);
565 roce_write(hr_dev, ROCEE_EXT_DB_OTHERS_WL_REG, ext_odb_alful);
566
567 /* Configure extend ODB base addr */
568 odb_dma_addr = db->ext_db->odb_buf_list->map;
569 roce_write(hr_dev, ROCEE_EXT_DB_OTH_REG, (u32)(odb_dma_addr >> 12));
570
571 /* Configure extend ODB depth */
572 val = roce_read(hr_dev, ROCEE_EXT_DB_OTH_H_REG);
573 tmp = cpu_to_le32(val);
574 roce_set_field(tmp, ROCEE_EXT_DB_OTH_H_EXT_DB_OTH_SHIFT_M,
575 ROCEE_EXT_DB_OTH_H_EXT_DB_OTH_SHIFT_S,
576 db->ext_db->eodb_dep);
577 roce_set_field(tmp, ROCEE_EXT_DB_SQ_H_EXT_DB_OTH_BA_H_M,
578 ROCEE_EXT_DB_SQ_H_EXT_DB_OTH_BA_H_S,
579 db->ext_db->eodb_dep);
580 val = le32_to_cpu(tmp);
581 roce_write(hr_dev, ROCEE_EXT_DB_OTH_H_REG, val);
582
583 dev_dbg(dev, "ext ODB depth: 0x%x\n", db->ext_db->eodb_dep);
584 dev_dbg(dev, "ext ODB threshold: empty: 0x%x, ful: 0x%x\n",
585 ext_odb_alept, ext_odb_alful);
586 }
587
588 static int hns_roce_db_ext_init(struct hns_roce_dev *hr_dev, u32 sdb_ext_mod,
589 u32 odb_ext_mod)
590 {
591 struct device *dev = &hr_dev->pdev->dev;
592 struct hns_roce_v1_priv *priv;
593 struct hns_roce_db_table *db;
594 dma_addr_t sdb_dma_addr;
595 dma_addr_t odb_dma_addr;
596 int ret = 0;
597
598 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
599 db = &priv->db_table;
600
601 db->ext_db = kmalloc(sizeof(*db->ext_db), GFP_KERNEL);
602 if (!db->ext_db)
603 return -ENOMEM;
604
605 if (sdb_ext_mod) {
606 db->ext_db->sdb_buf_list = kmalloc(
607 sizeof(*db->ext_db->sdb_buf_list), GFP_KERNEL);
608 if (!db->ext_db->sdb_buf_list) {
609 ret = -ENOMEM;
610 goto ext_sdb_buf_fail_out;
611 }
612
613 db->ext_db->sdb_buf_list->buf = dma_alloc_coherent(dev,
614 HNS_ROCE_V1_EXT_SDB_SIZE,
615 &sdb_dma_addr, GFP_KERNEL);
616 if (!db->ext_db->sdb_buf_list->buf) {
617 ret = -ENOMEM;
618 goto alloc_sq_db_buf_fail;
619 }
620 db->ext_db->sdb_buf_list->map = sdb_dma_addr;
621
622 db->ext_db->esdb_dep = ilog2(HNS_ROCE_V1_EXT_SDB_DEPTH);
623 hns_roce_set_sdb_ext(hr_dev, HNS_ROCE_V1_EXT_SDB_ALEPT,
624 HNS_ROCE_V1_EXT_SDB_ALFUL);
625 } else
626 hns_roce_set_sdb(hr_dev, HNS_ROCE_V1_SDB_ALEPT,
627 HNS_ROCE_V1_SDB_ALFUL);
628
629 if (odb_ext_mod) {
630 db->ext_db->odb_buf_list = kmalloc(
631 sizeof(*db->ext_db->odb_buf_list), GFP_KERNEL);
632 if (!db->ext_db->odb_buf_list) {
633 ret = -ENOMEM;
634 goto ext_odb_buf_fail_out;
635 }
636
637 db->ext_db->odb_buf_list->buf = dma_alloc_coherent(dev,
638 HNS_ROCE_V1_EXT_ODB_SIZE,
639 &odb_dma_addr, GFP_KERNEL);
640 if (!db->ext_db->odb_buf_list->buf) {
641 ret = -ENOMEM;
642 goto alloc_otr_db_buf_fail;
643 }
644 db->ext_db->odb_buf_list->map = odb_dma_addr;
645
646 db->ext_db->eodb_dep = ilog2(HNS_ROCE_V1_EXT_ODB_DEPTH);
647 hns_roce_set_odb_ext(hr_dev, HNS_ROCE_V1_EXT_ODB_ALEPT,
648 HNS_ROCE_V1_EXT_ODB_ALFUL);
649 } else
650 hns_roce_set_odb(hr_dev, HNS_ROCE_V1_ODB_ALEPT,
651 HNS_ROCE_V1_ODB_ALFUL);
652
653 hns_roce_set_db_ext_mode(hr_dev, sdb_ext_mod, odb_ext_mod);
654
655 return 0;
656
657 alloc_otr_db_buf_fail:
658 kfree(db->ext_db->odb_buf_list);
659
660 ext_odb_buf_fail_out:
661 if (sdb_ext_mod) {
662 dma_free_coherent(dev, HNS_ROCE_V1_EXT_SDB_SIZE,
663 db->ext_db->sdb_buf_list->buf,
664 db->ext_db->sdb_buf_list->map);
665 }
666
667 alloc_sq_db_buf_fail:
668 if (sdb_ext_mod)
669 kfree(db->ext_db->sdb_buf_list);
670
671 ext_sdb_buf_fail_out:
672 kfree(db->ext_db);
673 return ret;
674 }
675
676 static struct hns_roce_qp *hns_roce_v1_create_lp_qp(struct hns_roce_dev *hr_dev,
677 struct ib_pd *pd)
678 {
679 struct device *dev = &hr_dev->pdev->dev;
680 struct ib_qp_init_attr init_attr;
681 struct ib_qp *qp;
682
683 memset(&init_attr, 0, sizeof(struct ib_qp_init_attr));
684 init_attr.qp_type = IB_QPT_RC;
685 init_attr.sq_sig_type = IB_SIGNAL_ALL_WR;
686 init_attr.cap.max_recv_wr = HNS_ROCE_MIN_WQE_NUM;
687 init_attr.cap.max_send_wr = HNS_ROCE_MIN_WQE_NUM;
688
689 qp = hns_roce_create_qp(pd, &init_attr, NULL);
690 if (IS_ERR(qp)) {
691 dev_err(dev, "Create loop qp for mr free failed!");
692 return NULL;
693 }
694
695 return to_hr_qp(qp);
696 }
697
698 static int hns_roce_v1_rsv_lp_qp(struct hns_roce_dev *hr_dev)
699 {
700 struct hns_roce_caps *caps = &hr_dev->caps;
701 struct device *dev = &hr_dev->pdev->dev;
702 struct ib_cq_init_attr cq_init_attr;
703 struct hns_roce_free_mr *free_mr;
704 struct ib_qp_attr attr = { 0 };
705 struct hns_roce_v1_priv *priv;
706 struct hns_roce_qp *hr_qp;
707 struct ib_device *ibdev;
708 struct ib_cq *cq;
709 struct ib_pd *pd;
710 union ib_gid dgid;
711 __be64 subnet_prefix;
712 int attr_mask = 0;
713 int ret;
714 int i, j;
715 u8 queue_en[HNS_ROCE_V1_RESV_QP] = { 0 };
716 u8 phy_port;
717 u8 port = 0;
718 u8 sl;
719
720 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
721 free_mr = &priv->free_mr;
722
723 /* Reserved cq for loop qp */
724 cq_init_attr.cqe = HNS_ROCE_MIN_WQE_NUM * 2;
725 cq_init_attr.comp_vector = 0;
726
727 ibdev = &hr_dev->ib_dev;
728 cq = rdma_zalloc_drv_obj(ibdev, ib_cq);
729 if (!cq)
730 return -ENOMEM;
731
732 ret = hns_roce_create_cq(cq, &cq_init_attr, NULL);
733 if (ret) {
734 dev_err(dev, "Create cq for reserved loop qp failed!");
735 goto alloc_cq_failed;
736 }
737 free_mr->mr_free_cq = to_hr_cq(cq);
738 free_mr->mr_free_cq->ib_cq.device = &hr_dev->ib_dev;
739 free_mr->mr_free_cq->ib_cq.uobject = NULL;
740 free_mr->mr_free_cq->ib_cq.comp_handler = NULL;
741 free_mr->mr_free_cq->ib_cq.event_handler = NULL;
742 free_mr->mr_free_cq->ib_cq.cq_context = NULL;
743 atomic_set(&free_mr->mr_free_cq->ib_cq.usecnt, 0);
744
745 pd = rdma_zalloc_drv_obj(ibdev, ib_pd);
746 if (!pd) {
747 ret = -ENOMEM;
748 goto alloc_mem_failed;
749 }
750
751 pd->device = ibdev;
752 ret = hns_roce_alloc_pd(pd, NULL);
753 if (ret)
754 goto alloc_pd_failed;
755
756 free_mr->mr_free_pd = to_hr_pd(pd);
757 free_mr->mr_free_pd->ibpd.device = &hr_dev->ib_dev;
758 free_mr->mr_free_pd->ibpd.uobject = NULL;
759 free_mr->mr_free_pd->ibpd.__internal_mr = NULL;
760 atomic_set(&free_mr->mr_free_pd->ibpd.usecnt, 0);
761
762 attr.qp_access_flags = IB_ACCESS_REMOTE_WRITE;
763 attr.pkey_index = 0;
764 attr.min_rnr_timer = 0;
765 /* Disable read ability */
766 attr.max_dest_rd_atomic = 0;
767 attr.max_rd_atomic = 0;
768 /* Use arbitrary values as rq_psn and sq_psn */
769 attr.rq_psn = 0x0808;
770 attr.sq_psn = 0x0808;
771 attr.retry_cnt = 7;
772 attr.rnr_retry = 7;
773 attr.timeout = 0x12;
774 attr.path_mtu = IB_MTU_256;
775 attr.ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE;
776 rdma_ah_set_grh(&attr.ah_attr, NULL, 0, 0, 1, 0);
777 rdma_ah_set_static_rate(&attr.ah_attr, 3);
778
779 subnet_prefix = cpu_to_be64(0xfe80000000000000LL);
780 for (i = 0; i < HNS_ROCE_V1_RESV_QP; i++) {
781 phy_port = (i >= HNS_ROCE_MAX_PORTS) ? (i - 2) :
782 (i % HNS_ROCE_MAX_PORTS);
783 sl = i / HNS_ROCE_MAX_PORTS;
784
785 for (j = 0; j < caps->num_ports; j++) {
786 if (hr_dev->iboe.phy_port[j] == phy_port) {
787 queue_en[i] = 1;
788 port = j;
789 break;
790 }
791 }
792
793 if (!queue_en[i])
794 continue;
795
796 free_mr->mr_free_qp[i] = hns_roce_v1_create_lp_qp(hr_dev, pd);
797 if (!free_mr->mr_free_qp[i]) {
798 dev_err(dev, "Create loop qp failed!\n");
799 ret = -ENOMEM;
800 goto create_lp_qp_failed;
801 }
802 hr_qp = free_mr->mr_free_qp[i];
803
804 hr_qp->port = port;
805 hr_qp->phy_port = phy_port;
806 hr_qp->ibqp.qp_type = IB_QPT_RC;
807 hr_qp->ibqp.device = &hr_dev->ib_dev;
808 hr_qp->ibqp.uobject = NULL;
809 atomic_set(&hr_qp->ibqp.usecnt, 0);
810 hr_qp->ibqp.pd = pd;
811 hr_qp->ibqp.recv_cq = cq;
812 hr_qp->ibqp.send_cq = cq;
813
814 rdma_ah_set_port_num(&attr.ah_attr, port + 1);
815 rdma_ah_set_sl(&attr.ah_attr, sl);
816 attr.port_num = port + 1;
817
818 attr.dest_qp_num = hr_qp->qpn;
819 memcpy(rdma_ah_retrieve_dmac(&attr.ah_attr),
820 hr_dev->dev_addr[port],
821 ETH_ALEN);
822
823 memcpy(&dgid.raw, &subnet_prefix, sizeof(u64));
824 memcpy(&dgid.raw[8], hr_dev->dev_addr[port], 3);
825 memcpy(&dgid.raw[13], hr_dev->dev_addr[port] + 3, 3);
826 dgid.raw[11] = 0xff;
827 dgid.raw[12] = 0xfe;
828 dgid.raw[8] ^= 2;
829 rdma_ah_set_dgid_raw(&attr.ah_attr, dgid.raw);
830
831 ret = hr_dev->hw->modify_qp(&hr_qp->ibqp, &attr, attr_mask,
832 IB_QPS_RESET, IB_QPS_INIT);
833 if (ret) {
834 dev_err(dev, "modify qp failed(%d)!\n", ret);
835 goto create_lp_qp_failed;
836 }
837
838 ret = hr_dev->hw->modify_qp(&hr_qp->ibqp, &attr, IB_QP_DEST_QPN,
839 IB_QPS_INIT, IB_QPS_RTR);
840 if (ret) {
841 dev_err(dev, "modify qp failed(%d)!\n", ret);
842 goto create_lp_qp_failed;
843 }
844
845 ret = hr_dev->hw->modify_qp(&hr_qp->ibqp, &attr, attr_mask,
846 IB_QPS_RTR, IB_QPS_RTS);
847 if (ret) {
848 dev_err(dev, "modify qp failed(%d)!\n", ret);
849 goto create_lp_qp_failed;
850 }
851 }
852
853 return 0;
854
855 create_lp_qp_failed:
856 for (i -= 1; i >= 0; i--) {
857 hr_qp = free_mr->mr_free_qp[i];
858 if (hns_roce_v1_destroy_qp(&hr_qp->ibqp, NULL))
859 dev_err(dev, "Destroy qp %d for mr free failed!\n", i);
860 }
861
862 hns_roce_dealloc_pd(pd, NULL);
863
864 alloc_pd_failed:
865 kfree(pd);
866
867 alloc_mem_failed:
868 hns_roce_destroy_cq(cq, NULL);
869 alloc_cq_failed:
870 kfree(cq);
871 return ret;
872 }
873
874 static void hns_roce_v1_release_lp_qp(struct hns_roce_dev *hr_dev)
875 {
876 struct device *dev = &hr_dev->pdev->dev;
877 struct hns_roce_free_mr *free_mr;
878 struct hns_roce_v1_priv *priv;
879 struct hns_roce_qp *hr_qp;
880 int ret;
881 int i;
882
883 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
884 free_mr = &priv->free_mr;
885
886 for (i = 0; i < HNS_ROCE_V1_RESV_QP; i++) {
887 hr_qp = free_mr->mr_free_qp[i];
888 if (!hr_qp)
889 continue;
890
891 ret = hns_roce_v1_destroy_qp(&hr_qp->ibqp, NULL);
892 if (ret)
893 dev_err(dev, "Destroy qp %d for mr free failed(%d)!\n",
894 i, ret);
895 }
896
897 hns_roce_destroy_cq(&free_mr->mr_free_cq->ib_cq, NULL);
898 kfree(&free_mr->mr_free_cq->ib_cq);
899 hns_roce_dealloc_pd(&free_mr->mr_free_pd->ibpd, NULL);
900 kfree(&free_mr->mr_free_pd->ibpd);
901 }
902
903 static int hns_roce_db_init(struct hns_roce_dev *hr_dev)
904 {
905 struct device *dev = &hr_dev->pdev->dev;
906 struct hns_roce_v1_priv *priv;
907 struct hns_roce_db_table *db;
908 u32 sdb_ext_mod;
909 u32 odb_ext_mod;
910 u32 sdb_evt_mod;
911 u32 odb_evt_mod;
912 int ret = 0;
913
914 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
915 db = &priv->db_table;
916
917 memset(db, 0, sizeof(*db));
918
919 /* Default DB mode */
920 sdb_ext_mod = HNS_ROCE_SDB_EXTEND_MODE;
921 odb_ext_mod = HNS_ROCE_ODB_EXTEND_MODE;
922 sdb_evt_mod = HNS_ROCE_SDB_NORMAL_MODE;
923 odb_evt_mod = HNS_ROCE_ODB_POLL_MODE;
924
925 db->sdb_ext_mod = sdb_ext_mod;
926 db->odb_ext_mod = odb_ext_mod;
927
928 /* Init extend DB */
929 ret = hns_roce_db_ext_init(hr_dev, sdb_ext_mod, odb_ext_mod);
930 if (ret) {
931 dev_err(dev, "Failed in extend DB configuration.\n");
932 return ret;
933 }
934
935 hns_roce_set_db_event_mode(hr_dev, sdb_evt_mod, odb_evt_mod);
936
937 return 0;
938 }
939
940 static void hns_roce_v1_recreate_lp_qp_work_fn(struct work_struct *work)
941 {
942 struct hns_roce_recreate_lp_qp_work *lp_qp_work;
943 struct hns_roce_dev *hr_dev;
944
945 lp_qp_work = container_of(work, struct hns_roce_recreate_lp_qp_work,
946 work);
947 hr_dev = to_hr_dev(lp_qp_work->ib_dev);
948
949 hns_roce_v1_release_lp_qp(hr_dev);
950
951 if (hns_roce_v1_rsv_lp_qp(hr_dev))
952 dev_err(&hr_dev->pdev->dev, "create reserver qp failed\n");
953
954 if (lp_qp_work->comp_flag)
955 complete(lp_qp_work->comp);
956
957 kfree(lp_qp_work);
958 }
959
960 static int hns_roce_v1_recreate_lp_qp(struct hns_roce_dev *hr_dev)
961 {
962 struct device *dev = &hr_dev->pdev->dev;
963 struct hns_roce_recreate_lp_qp_work *lp_qp_work;
964 struct hns_roce_free_mr *free_mr;
965 struct hns_roce_v1_priv *priv;
966 struct completion comp;
967 long end = HNS_ROCE_V1_RECREATE_LP_QP_TIMEOUT_MSECS;
968
969 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
970 free_mr = &priv->free_mr;
971
972 lp_qp_work = kzalloc(sizeof(struct hns_roce_recreate_lp_qp_work),
973 GFP_KERNEL);
974 if (!lp_qp_work)
975 return -ENOMEM;
976
977 INIT_WORK(&(lp_qp_work->work), hns_roce_v1_recreate_lp_qp_work_fn);
978
979 lp_qp_work->ib_dev = &(hr_dev->ib_dev);
980 lp_qp_work->comp = &comp;
981 lp_qp_work->comp_flag = 1;
982
983 init_completion(lp_qp_work->comp);
984
985 queue_work(free_mr->free_mr_wq, &(lp_qp_work->work));
986
987 while (end > 0) {
988 if (try_wait_for_completion(&comp))
989 return 0;
990 msleep(HNS_ROCE_V1_RECREATE_LP_QP_WAIT_VALUE);
991 end -= HNS_ROCE_V1_RECREATE_LP_QP_WAIT_VALUE;
992 }
993
994 lp_qp_work->comp_flag = 0;
995 if (try_wait_for_completion(&comp))
996 return 0;
997
998 dev_warn(dev, "recreate lp qp failed 20s timeout and return failed!\n");
999 return -ETIMEDOUT;
1000 }
1001
1002 static int hns_roce_v1_send_lp_wqe(struct hns_roce_qp *hr_qp)
1003 {
1004 struct hns_roce_dev *hr_dev = to_hr_dev(hr_qp->ibqp.device);
1005 struct device *dev = &hr_dev->pdev->dev;
1006 struct ib_send_wr send_wr;
1007 const struct ib_send_wr *bad_wr;
1008 int ret;
1009
1010 memset(&send_wr, 0, sizeof(send_wr));
1011 send_wr.next = NULL;
1012 send_wr.num_sge = 0;
1013 send_wr.send_flags = 0;
1014 send_wr.sg_list = NULL;
1015 send_wr.wr_id = (unsigned long long)&send_wr;
1016 send_wr.opcode = IB_WR_RDMA_WRITE;
1017
1018 ret = hns_roce_v1_post_send(&hr_qp->ibqp, &send_wr, &bad_wr);
1019 if (ret) {
1020 dev_err(dev, "Post write wqe for mr free failed(%d)!", ret);
1021 return ret;
1022 }
1023
1024 return 0;
1025 }
1026
1027 static void hns_roce_v1_mr_free_work_fn(struct work_struct *work)
1028 {
1029 struct hns_roce_mr_free_work *mr_work;
1030 struct ib_wc wc[HNS_ROCE_V1_RESV_QP];
1031 struct hns_roce_free_mr *free_mr;
1032 struct hns_roce_cq *mr_free_cq;
1033 struct hns_roce_v1_priv *priv;
1034 struct hns_roce_dev *hr_dev;
1035 struct hns_roce_mr *hr_mr;
1036 struct hns_roce_qp *hr_qp;
1037 struct device *dev;
1038 unsigned long end =
1039 msecs_to_jiffies(HNS_ROCE_V1_FREE_MR_TIMEOUT_MSECS) + jiffies;
1040 int i;
1041 int ret;
1042 int ne = 0;
1043
1044 mr_work = container_of(work, struct hns_roce_mr_free_work, work);
1045 hr_mr = (struct hns_roce_mr *)mr_work->mr;
1046 hr_dev = to_hr_dev(mr_work->ib_dev);
1047 dev = &hr_dev->pdev->dev;
1048
1049 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
1050 free_mr = &priv->free_mr;
1051 mr_free_cq = free_mr->mr_free_cq;
1052
1053 for (i = 0; i < HNS_ROCE_V1_RESV_QP; i++) {
1054 hr_qp = free_mr->mr_free_qp[i];
1055 if (!hr_qp)
1056 continue;
1057 ne++;
1058
1059 ret = hns_roce_v1_send_lp_wqe(hr_qp);
1060 if (ret) {
1061 dev_err(dev,
1062 "Send wqe (qp:0x%lx) for mr free failed(%d)!\n",
1063 hr_qp->qpn, ret);
1064 goto free_work;
1065 }
1066 }
1067
1068 if (!ne) {
1069 dev_err(dev, "Reserved loop qp is absent!\n");
1070 goto free_work;
1071 }
1072
1073 do {
1074 ret = hns_roce_v1_poll_cq(&mr_free_cq->ib_cq, ne, wc);
1075 if (ret < 0 && hr_qp) {
1076 dev_err(dev,
1077 "(qp:0x%lx) starts, Poll cqe failed(%d) for mr 0x%x free! Remain %d cqe\n",
1078 hr_qp->qpn, ret, hr_mr->key, ne);
1079 goto free_work;
1080 }
1081 ne -= ret;
1082 usleep_range(HNS_ROCE_V1_FREE_MR_WAIT_VALUE * 1000,
1083 (1 + HNS_ROCE_V1_FREE_MR_WAIT_VALUE) * 1000);
1084 } while (ne && time_before_eq(jiffies, end));
1085
1086 if (ne != 0)
1087 dev_err(dev,
1088 "Poll cqe for mr 0x%x free timeout! Remain %d cqe\n",
1089 hr_mr->key, ne);
1090
1091 free_work:
1092 if (mr_work->comp_flag)
1093 complete(mr_work->comp);
1094 kfree(mr_work);
1095 }
1096
1097 static int hns_roce_v1_dereg_mr(struct hns_roce_dev *hr_dev,
1098 struct hns_roce_mr *mr, struct ib_udata *udata)
1099 {
1100 struct device *dev = &hr_dev->pdev->dev;
1101 struct hns_roce_mr_free_work *mr_work;
1102 struct hns_roce_free_mr *free_mr;
1103 struct hns_roce_v1_priv *priv;
1104 struct completion comp;
1105 long end = HNS_ROCE_V1_FREE_MR_TIMEOUT_MSECS;
1106 unsigned long start = jiffies;
1107 int npages;
1108 int ret = 0;
1109
1110 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
1111 free_mr = &priv->free_mr;
1112
1113 if (mr->enabled) {
1114 if (hns_roce_hw_destroy_mpt(hr_dev, NULL,
1115 key_to_hw_index(mr->key) &
1116 (hr_dev->caps.num_mtpts - 1)))
1117 dev_warn(dev, "DESTROY_MPT failed!\n");
1118 }
1119
1120 mr_work = kzalloc(sizeof(*mr_work), GFP_KERNEL);
1121 if (!mr_work) {
1122 ret = -ENOMEM;
1123 goto free_mr;
1124 }
1125
1126 INIT_WORK(&(mr_work->work), hns_roce_v1_mr_free_work_fn);
1127
1128 mr_work->ib_dev = &(hr_dev->ib_dev);
1129 mr_work->comp = &comp;
1130 mr_work->comp_flag = 1;
1131 mr_work->mr = (void *)mr;
1132 init_completion(mr_work->comp);
1133
1134 queue_work(free_mr->free_mr_wq, &(mr_work->work));
1135
1136 while (end > 0) {
1137 if (try_wait_for_completion(&comp))
1138 goto free_mr;
1139 msleep(HNS_ROCE_V1_FREE_MR_WAIT_VALUE);
1140 end -= HNS_ROCE_V1_FREE_MR_WAIT_VALUE;
1141 }
1142
1143 mr_work->comp_flag = 0;
1144 if (try_wait_for_completion(&comp))
1145 goto free_mr;
1146
1147 dev_warn(dev, "Free mr work 0x%x over 50s and failed!\n", mr->key);
1148 ret = -ETIMEDOUT;
1149
1150 free_mr:
1151 dev_dbg(dev, "Free mr 0x%x use 0x%x us.\n",
1152 mr->key, jiffies_to_usecs(jiffies) - jiffies_to_usecs(start));
1153
1154 if (mr->size != ~0ULL) {
1155 npages = ib_umem_page_count(mr->umem);
1156 dma_free_coherent(dev, npages * 8, mr->pbl_buf,
1157 mr->pbl_dma_addr);
1158 }
1159
1160 hns_roce_bitmap_free(&hr_dev->mr_table.mtpt_bitmap,
1161 key_to_hw_index(mr->key), 0);
1162
1163 ib_umem_release(mr->umem);
1164
1165 kfree(mr);
1166
1167 return ret;
1168 }
1169
1170 static void hns_roce_db_free(struct hns_roce_dev *hr_dev)
1171 {
1172 struct device *dev = &hr_dev->pdev->dev;
1173 struct hns_roce_v1_priv *priv;
1174 struct hns_roce_db_table *db;
1175
1176 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
1177 db = &priv->db_table;
1178
1179 if (db->sdb_ext_mod) {
1180 dma_free_coherent(dev, HNS_ROCE_V1_EXT_SDB_SIZE,
1181 db->ext_db->sdb_buf_list->buf,
1182 db->ext_db->sdb_buf_list->map);
1183 kfree(db->ext_db->sdb_buf_list);
1184 }
1185
1186 if (db->odb_ext_mod) {
1187 dma_free_coherent(dev, HNS_ROCE_V1_EXT_ODB_SIZE,
1188 db->ext_db->odb_buf_list->buf,
1189 db->ext_db->odb_buf_list->map);
1190 kfree(db->ext_db->odb_buf_list);
1191 }
1192
1193 kfree(db->ext_db);
1194 }
1195
1196 static int hns_roce_raq_init(struct hns_roce_dev *hr_dev)
1197 {
1198 int ret;
1199 u32 val;
1200 __le32 tmp;
1201 int raq_shift = 0;
1202 dma_addr_t addr;
1203 struct hns_roce_v1_priv *priv;
1204 struct hns_roce_raq_table *raq;
1205 struct device *dev = &hr_dev->pdev->dev;
1206
1207 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
1208 raq = &priv->raq_table;
1209
1210 raq->e_raq_buf = kzalloc(sizeof(*(raq->e_raq_buf)), GFP_KERNEL);
1211 if (!raq->e_raq_buf)
1212 return -ENOMEM;
1213
1214 raq->e_raq_buf->buf = dma_alloc_coherent(dev, HNS_ROCE_V1_RAQ_SIZE,
1215 &addr, GFP_KERNEL);
1216 if (!raq->e_raq_buf->buf) {
1217 ret = -ENOMEM;
1218 goto err_dma_alloc_raq;
1219 }
1220 raq->e_raq_buf->map = addr;
1221
1222 /* Configure raq extended address. 48bit 4K align*/
1223 roce_write(hr_dev, ROCEE_EXT_RAQ_REG, raq->e_raq_buf->map >> 12);
1224
1225 /* Configure raq_shift */
1226 raq_shift = ilog2(HNS_ROCE_V1_RAQ_SIZE / HNS_ROCE_V1_RAQ_ENTRY);
1227 val = roce_read(hr_dev, ROCEE_EXT_RAQ_H_REG);
1228 tmp = cpu_to_le32(val);
1229 roce_set_field(tmp, ROCEE_EXT_RAQ_H_EXT_RAQ_SHIFT_M,
1230 ROCEE_EXT_RAQ_H_EXT_RAQ_SHIFT_S, raq_shift);
1231 /*
1232 * 44 = 32 + 12, When evaluating addr to hardware, shift 12 because of
1233 * using 4K page, and shift more 32 because of
1234 * caculating the high 32 bit value evaluated to hardware.
1235 */
1236 roce_set_field(tmp, ROCEE_EXT_RAQ_H_EXT_RAQ_BA_H_M,
1237 ROCEE_EXT_RAQ_H_EXT_RAQ_BA_H_S,
1238 raq->e_raq_buf->map >> 44);
1239 val = le32_to_cpu(tmp);
1240 roce_write(hr_dev, ROCEE_EXT_RAQ_H_REG, val);
1241 dev_dbg(dev, "Configure raq_shift 0x%x.\n", val);
1242
1243 /* Configure raq threshold */
1244 val = roce_read(hr_dev, ROCEE_RAQ_WL_REG);
1245 tmp = cpu_to_le32(val);
1246 roce_set_field(tmp, ROCEE_RAQ_WL_ROCEE_RAQ_WL_M,
1247 ROCEE_RAQ_WL_ROCEE_RAQ_WL_S,
1248 HNS_ROCE_V1_EXT_RAQ_WF);
1249 val = le32_to_cpu(tmp);
1250 roce_write(hr_dev, ROCEE_RAQ_WL_REG, val);
1251 dev_dbg(dev, "Configure raq_wl 0x%x.\n", val);
1252
1253 /* Enable extend raq */
1254 val = roce_read(hr_dev, ROCEE_WRMS_POL_TIME_INTERVAL_REG);
1255 tmp = cpu_to_le32(val);
1256 roce_set_field(tmp,
1257 ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_POL_TIME_INTERVAL_M,
1258 ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_POL_TIME_INTERVAL_S,
1259 POL_TIME_INTERVAL_VAL);
1260 roce_set_bit(tmp, ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_EXT_RAQ_MODE, 1);
1261 roce_set_field(tmp,
1262 ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_RAQ_TIMEOUT_CHK_CFG_M,
1263 ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_RAQ_TIMEOUT_CHK_CFG_S,
1264 2);
1265 roce_set_bit(tmp,
1266 ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_RAQ_TIMEOUT_CHK_EN_S, 1);
1267 val = le32_to_cpu(tmp);
1268 roce_write(hr_dev, ROCEE_WRMS_POL_TIME_INTERVAL_REG, val);
1269 dev_dbg(dev, "Configure WrmsPolTimeInterval 0x%x.\n", val);
1270
1271 /* Enable raq drop */
1272 val = roce_read(hr_dev, ROCEE_GLB_CFG_REG);
1273 tmp = cpu_to_le32(val);
1274 roce_set_bit(tmp, ROCEE_GLB_CFG_TRP_RAQ_DROP_EN_S, 1);
1275 val = le32_to_cpu(tmp);
1276 roce_write(hr_dev, ROCEE_GLB_CFG_REG, val);
1277 dev_dbg(dev, "Configure GlbCfg = 0x%x.\n", val);
1278
1279 return 0;
1280
1281 err_dma_alloc_raq:
1282 kfree(raq->e_raq_buf);
1283 return ret;
1284 }
1285
1286 static void hns_roce_raq_free(struct hns_roce_dev *hr_dev)
1287 {
1288 struct device *dev = &hr_dev->pdev->dev;
1289 struct hns_roce_v1_priv *priv;
1290 struct hns_roce_raq_table *raq;
1291
1292 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
1293 raq = &priv->raq_table;
1294
1295 dma_free_coherent(dev, HNS_ROCE_V1_RAQ_SIZE, raq->e_raq_buf->buf,
1296 raq->e_raq_buf->map);
1297 kfree(raq->e_raq_buf);
1298 }
1299
1300 static void hns_roce_port_enable(struct hns_roce_dev *hr_dev, int enable_flag)
1301 {
1302 __le32 tmp;
1303 u32 val;
1304
1305 if (enable_flag) {
1306 val = roce_read(hr_dev, ROCEE_GLB_CFG_REG);
1307 /* Open all ports */
1308 tmp = cpu_to_le32(val);
1309 roce_set_field(tmp, ROCEE_GLB_CFG_ROCEE_PORT_ST_M,
1310 ROCEE_GLB_CFG_ROCEE_PORT_ST_S,
1311 ALL_PORT_VAL_OPEN);
1312 val = le32_to_cpu(tmp);
1313 roce_write(hr_dev, ROCEE_GLB_CFG_REG, val);
1314 } else {
1315 val = roce_read(hr_dev, ROCEE_GLB_CFG_REG);
1316 /* Close all ports */
1317 tmp = cpu_to_le32(val);
1318 roce_set_field(tmp, ROCEE_GLB_CFG_ROCEE_PORT_ST_M,
1319 ROCEE_GLB_CFG_ROCEE_PORT_ST_S, 0x0);
1320 val = le32_to_cpu(tmp);
1321 roce_write(hr_dev, ROCEE_GLB_CFG_REG, val);
1322 }
1323 }
1324
1325 static int hns_roce_bt_init(struct hns_roce_dev *hr_dev)
1326 {
1327 struct device *dev = &hr_dev->pdev->dev;
1328 struct hns_roce_v1_priv *priv;
1329 int ret;
1330
1331 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
1332
1333 priv->bt_table.qpc_buf.buf = dma_alloc_coherent(dev,
1334 HNS_ROCE_BT_RSV_BUF_SIZE, &priv->bt_table.qpc_buf.map,
1335 GFP_KERNEL);
1336 if (!priv->bt_table.qpc_buf.buf)
1337 return -ENOMEM;
1338
1339 priv->bt_table.mtpt_buf.buf = dma_alloc_coherent(dev,
1340 HNS_ROCE_BT_RSV_BUF_SIZE, &priv->bt_table.mtpt_buf.map,
1341 GFP_KERNEL);
1342 if (!priv->bt_table.mtpt_buf.buf) {
1343 ret = -ENOMEM;
1344 goto err_failed_alloc_mtpt_buf;
1345 }
1346
1347 priv->bt_table.cqc_buf.buf = dma_alloc_coherent(dev,
1348 HNS_ROCE_BT_RSV_BUF_SIZE, &priv->bt_table.cqc_buf.map,
1349 GFP_KERNEL);
1350 if (!priv->bt_table.cqc_buf.buf) {
1351 ret = -ENOMEM;
1352 goto err_failed_alloc_cqc_buf;
1353 }
1354
1355 return 0;
1356
1357 err_failed_alloc_cqc_buf:
1358 dma_free_coherent(dev, HNS_ROCE_BT_RSV_BUF_SIZE,
1359 priv->bt_table.mtpt_buf.buf, priv->bt_table.mtpt_buf.map);
1360
1361 err_failed_alloc_mtpt_buf:
1362 dma_free_coherent(dev, HNS_ROCE_BT_RSV_BUF_SIZE,
1363 priv->bt_table.qpc_buf.buf, priv->bt_table.qpc_buf.map);
1364
1365 return ret;
1366 }
1367
1368 static void hns_roce_bt_free(struct hns_roce_dev *hr_dev)
1369 {
1370 struct device *dev = &hr_dev->pdev->dev;
1371 struct hns_roce_v1_priv *priv;
1372
1373 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
1374
1375 dma_free_coherent(dev, HNS_ROCE_BT_RSV_BUF_SIZE,
1376 priv->bt_table.cqc_buf.buf, priv->bt_table.cqc_buf.map);
1377
1378 dma_free_coherent(dev, HNS_ROCE_BT_RSV_BUF_SIZE,
1379 priv->bt_table.mtpt_buf.buf, priv->bt_table.mtpt_buf.map);
1380
1381 dma_free_coherent(dev, HNS_ROCE_BT_RSV_BUF_SIZE,
1382 priv->bt_table.qpc_buf.buf, priv->bt_table.qpc_buf.map);
1383 }
1384
1385 static int hns_roce_tptr_init(struct hns_roce_dev *hr_dev)
1386 {
1387 struct device *dev = &hr_dev->pdev->dev;
1388 struct hns_roce_buf_list *tptr_buf;
1389 struct hns_roce_v1_priv *priv;
1390
1391 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
1392 tptr_buf = &priv->tptr_table.tptr_buf;
1393
1394 /*
1395 * This buffer will be used for CQ's tptr(tail pointer), also
1396 * named ci(customer index). Every CQ will use 2 bytes to save
1397 * cqe ci in hip06. Hardware will read this area to get new ci
1398 * when the queue is almost full.
1399 */
1400 tptr_buf->buf = dma_alloc_coherent(dev, HNS_ROCE_V1_TPTR_BUF_SIZE,
1401 &tptr_buf->map, GFP_KERNEL);
1402 if (!tptr_buf->buf)
1403 return -ENOMEM;
1404
1405 hr_dev->tptr_dma_addr = tptr_buf->map;
1406 hr_dev->tptr_size = HNS_ROCE_V1_TPTR_BUF_SIZE;
1407
1408 return 0;
1409 }
1410
1411 static void hns_roce_tptr_free(struct hns_roce_dev *hr_dev)
1412 {
1413 struct device *dev = &hr_dev->pdev->dev;
1414 struct hns_roce_buf_list *tptr_buf;
1415 struct hns_roce_v1_priv *priv;
1416
1417 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
1418 tptr_buf = &priv->tptr_table.tptr_buf;
1419
1420 dma_free_coherent(dev, HNS_ROCE_V1_TPTR_BUF_SIZE,
1421 tptr_buf->buf, tptr_buf->map);
1422 }
1423
1424 static int hns_roce_free_mr_init(struct hns_roce_dev *hr_dev)
1425 {
1426 struct device *dev = &hr_dev->pdev->dev;
1427 struct hns_roce_free_mr *free_mr;
1428 struct hns_roce_v1_priv *priv;
1429 int ret = 0;
1430
1431 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
1432 free_mr = &priv->free_mr;
1433
1434 free_mr->free_mr_wq = create_singlethread_workqueue("hns_roce_free_mr");
1435 if (!free_mr->free_mr_wq) {
1436 dev_err(dev, "Create free mr workqueue failed!\n");
1437 return -ENOMEM;
1438 }
1439
1440 ret = hns_roce_v1_rsv_lp_qp(hr_dev);
1441 if (ret) {
1442 dev_err(dev, "Reserved loop qp failed(%d)!\n", ret);
1443 flush_workqueue(free_mr->free_mr_wq);
1444 destroy_workqueue(free_mr->free_mr_wq);
1445 }
1446
1447 return ret;
1448 }
1449
1450 static void hns_roce_free_mr_free(struct hns_roce_dev *hr_dev)
1451 {
1452 struct hns_roce_free_mr *free_mr;
1453 struct hns_roce_v1_priv *priv;
1454
1455 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
1456 free_mr = &priv->free_mr;
1457
1458 flush_workqueue(free_mr->free_mr_wq);
1459 destroy_workqueue(free_mr->free_mr_wq);
1460
1461 hns_roce_v1_release_lp_qp(hr_dev);
1462 }
1463
1464 /**
1465 * hns_roce_v1_reset - reset RoCE
1466 * @hr_dev: RoCE device struct pointer
1467 * @enable: true -- drop reset, false -- reset
1468 * return 0 - success , negative --fail
1469 */
1470 static int hns_roce_v1_reset(struct hns_roce_dev *hr_dev, bool dereset)
1471 {
1472 struct device_node *dsaf_node;
1473 struct device *dev = &hr_dev->pdev->dev;
1474 struct device_node *np = dev->of_node;
1475 struct fwnode_handle *fwnode;
1476 int ret;
1477
1478 /* check if this is DT/ACPI case */
1479 if (dev_of_node(dev)) {
1480 dsaf_node = of_parse_phandle(np, "dsaf-handle", 0);
1481 if (!dsaf_node) {
1482 dev_err(dev, "could not find dsaf-handle\n");
1483 return -EINVAL;
1484 }
1485 fwnode = &dsaf_node->fwnode;
1486 } else if (is_acpi_device_node(dev->fwnode)) {
1487 struct fwnode_reference_args args;
1488
1489 ret = acpi_node_get_property_reference(dev->fwnode,
1490 "dsaf-handle", 0, &args);
1491 if (ret) {
1492 dev_err(dev, "could not find dsaf-handle\n");
1493 return ret;
1494 }
1495 fwnode = args.fwnode;
1496 } else {
1497 dev_err(dev, "cannot read data from DT or ACPI\n");
1498 return -ENXIO;
1499 }
1500
1501 ret = hns_dsaf_roce_reset(fwnode, false);
1502 if (ret)
1503 return ret;
1504
1505 if (dereset) {
1506 msleep(SLEEP_TIME_INTERVAL);
1507 ret = hns_dsaf_roce_reset(fwnode, true);
1508 }
1509
1510 return ret;
1511 }
1512
1513 static int hns_roce_v1_profile(struct hns_roce_dev *hr_dev)
1514 {
1515 int i = 0;
1516 struct hns_roce_caps *caps = &hr_dev->caps;
1517
1518 hr_dev->vendor_id = roce_read(hr_dev, ROCEE_VENDOR_ID_REG);
1519 hr_dev->vendor_part_id = roce_read(hr_dev, ROCEE_VENDOR_PART_ID_REG);
1520 hr_dev->sys_image_guid = roce_read(hr_dev, ROCEE_SYS_IMAGE_GUID_L_REG) |
1521 ((u64)roce_read(hr_dev,
1522 ROCEE_SYS_IMAGE_GUID_H_REG) << 32);
1523 hr_dev->hw_rev = HNS_ROCE_HW_VER1;
1524
1525 caps->num_qps = HNS_ROCE_V1_MAX_QP_NUM;
1526 caps->max_wqes = HNS_ROCE_V1_MAX_WQE_NUM;
1527 caps->min_wqes = HNS_ROCE_MIN_WQE_NUM;
1528 caps->num_cqs = HNS_ROCE_V1_MAX_CQ_NUM;
1529 caps->min_cqes = HNS_ROCE_MIN_CQE_NUM;
1530 caps->max_cqes = HNS_ROCE_V1_MAX_CQE_NUM;
1531 caps->max_sq_sg = HNS_ROCE_V1_SG_NUM;
1532 caps->max_rq_sg = HNS_ROCE_V1_SG_NUM;
1533 caps->max_sq_inline = HNS_ROCE_V1_INLINE_SIZE;
1534 caps->num_uars = HNS_ROCE_V1_UAR_NUM;
1535 caps->phy_num_uars = HNS_ROCE_V1_PHY_UAR_NUM;
1536 caps->num_aeq_vectors = HNS_ROCE_V1_AEQE_VEC_NUM;
1537 caps->num_comp_vectors = HNS_ROCE_V1_COMP_VEC_NUM;
1538 caps->num_other_vectors = HNS_ROCE_V1_ABNORMAL_VEC_NUM;
1539 caps->num_mtpts = HNS_ROCE_V1_MAX_MTPT_NUM;
1540 caps->num_mtt_segs = HNS_ROCE_V1_MAX_MTT_SEGS;
1541 caps->num_pds = HNS_ROCE_V1_MAX_PD_NUM;
1542 caps->max_qp_init_rdma = HNS_ROCE_V1_MAX_QP_INIT_RDMA;
1543 caps->max_qp_dest_rdma = HNS_ROCE_V1_MAX_QP_DEST_RDMA;
1544 caps->max_sq_desc_sz = HNS_ROCE_V1_MAX_SQ_DESC_SZ;
1545 caps->max_rq_desc_sz = HNS_ROCE_V1_MAX_RQ_DESC_SZ;
1546 caps->qpc_entry_sz = HNS_ROCE_V1_QPC_ENTRY_SIZE;
1547 caps->irrl_entry_sz = HNS_ROCE_V1_IRRL_ENTRY_SIZE;
1548 caps->cqc_entry_sz = HNS_ROCE_V1_CQC_ENTRY_SIZE;
1549 caps->mtpt_entry_sz = HNS_ROCE_V1_MTPT_ENTRY_SIZE;
1550 caps->mtt_entry_sz = HNS_ROCE_V1_MTT_ENTRY_SIZE;
1551 caps->cq_entry_sz = HNS_ROCE_V1_CQE_ENTRY_SIZE;
1552 caps->page_size_cap = HNS_ROCE_V1_PAGE_SIZE_SUPPORT;
1553 caps->reserved_lkey = 0;
1554 caps->reserved_pds = 0;
1555 caps->reserved_mrws = 1;
1556 caps->reserved_uars = 0;
1557 caps->reserved_cqs = 0;
1558 caps->reserved_qps = 12; /* 2 SQP per port, six ports total 12 */
1559 caps->chunk_sz = HNS_ROCE_V1_TABLE_CHUNK_SIZE;
1560
1561 for (i = 0; i < caps->num_ports; i++)
1562 caps->pkey_table_len[i] = 1;
1563
1564 for (i = 0; i < caps->num_ports; i++) {
1565 /* Six ports shared 16 GID in v1 engine */
1566 if (i >= (HNS_ROCE_V1_GID_NUM % caps->num_ports))
1567 caps->gid_table_len[i] = HNS_ROCE_V1_GID_NUM /
1568 caps->num_ports;
1569 else
1570 caps->gid_table_len[i] = HNS_ROCE_V1_GID_NUM /
1571 caps->num_ports + 1;
1572 }
1573
1574 caps->ceqe_depth = HNS_ROCE_V1_COMP_EQE_NUM;
1575 caps->aeqe_depth = HNS_ROCE_V1_ASYNC_EQE_NUM;
1576 caps->local_ca_ack_delay = roce_read(hr_dev, ROCEE_ACK_DELAY_REG);
1577 caps->max_mtu = IB_MTU_2048;
1578
1579 return 0;
1580 }
1581
1582 static int hns_roce_v1_init(struct hns_roce_dev *hr_dev)
1583 {
1584 int ret;
1585 u32 val;
1586 __le32 tmp;
1587 struct device *dev = &hr_dev->pdev->dev;
1588
1589 /* DMAE user config */
1590 val = roce_read(hr_dev, ROCEE_DMAE_USER_CFG1_REG);
1591 tmp = cpu_to_le32(val);
1592 roce_set_field(tmp, ROCEE_DMAE_USER_CFG1_ROCEE_CACHE_TB_CFG_M,
1593 ROCEE_DMAE_USER_CFG1_ROCEE_CACHE_TB_CFG_S, 0xf);
1594 roce_set_field(tmp, ROCEE_DMAE_USER_CFG1_ROCEE_STREAM_ID_TB_CFG_M,
1595 ROCEE_DMAE_USER_CFG1_ROCEE_STREAM_ID_TB_CFG_S,
1596 1 << PAGES_SHIFT_16);
1597 val = le32_to_cpu(tmp);
1598 roce_write(hr_dev, ROCEE_DMAE_USER_CFG1_REG, val);
1599
1600 val = roce_read(hr_dev, ROCEE_DMAE_USER_CFG2_REG);
1601 tmp = cpu_to_le32(val);
1602 roce_set_field(tmp, ROCEE_DMAE_USER_CFG2_ROCEE_CACHE_PKT_CFG_M,
1603 ROCEE_DMAE_USER_CFG2_ROCEE_CACHE_PKT_CFG_S, 0xf);
1604 roce_set_field(tmp, ROCEE_DMAE_USER_CFG2_ROCEE_STREAM_ID_PKT_CFG_M,
1605 ROCEE_DMAE_USER_CFG2_ROCEE_STREAM_ID_PKT_CFG_S,
1606 1 << PAGES_SHIFT_16);
1607
1608 ret = hns_roce_db_init(hr_dev);
1609 if (ret) {
1610 dev_err(dev, "doorbell init failed!\n");
1611 return ret;
1612 }
1613
1614 ret = hns_roce_raq_init(hr_dev);
1615 if (ret) {
1616 dev_err(dev, "raq init failed!\n");
1617 goto error_failed_raq_init;
1618 }
1619
1620 ret = hns_roce_bt_init(hr_dev);
1621 if (ret) {
1622 dev_err(dev, "bt init failed!\n");
1623 goto error_failed_bt_init;
1624 }
1625
1626 ret = hns_roce_tptr_init(hr_dev);
1627 if (ret) {
1628 dev_err(dev, "tptr init failed!\n");
1629 goto error_failed_tptr_init;
1630 }
1631
1632 ret = hns_roce_free_mr_init(hr_dev);
1633 if (ret) {
1634 dev_err(dev, "free mr init failed!\n");
1635 goto error_failed_free_mr_init;
1636 }
1637
1638 hns_roce_port_enable(hr_dev, HNS_ROCE_PORT_UP);
1639
1640 return 0;
1641
1642 error_failed_free_mr_init:
1643 hns_roce_tptr_free(hr_dev);
1644
1645 error_failed_tptr_init:
1646 hns_roce_bt_free(hr_dev);
1647
1648 error_failed_bt_init:
1649 hns_roce_raq_free(hr_dev);
1650
1651 error_failed_raq_init:
1652 hns_roce_db_free(hr_dev);
1653 return ret;
1654 }
1655
1656 static void hns_roce_v1_exit(struct hns_roce_dev *hr_dev)
1657 {
1658 hns_roce_port_enable(hr_dev, HNS_ROCE_PORT_DOWN);
1659 hns_roce_free_mr_free(hr_dev);
1660 hns_roce_tptr_free(hr_dev);
1661 hns_roce_bt_free(hr_dev);
1662 hns_roce_raq_free(hr_dev);
1663 hns_roce_db_free(hr_dev);
1664 }
1665
1666 static int hns_roce_v1_cmd_pending(struct hns_roce_dev *hr_dev)
1667 {
1668 u32 status = readl(hr_dev->reg_base + ROCEE_MB6_REG);
1669
1670 return (!!(status & (1 << HCR_GO_BIT)));
1671 }
1672
1673 static int hns_roce_v1_post_mbox(struct hns_roce_dev *hr_dev, u64 in_param,
1674 u64 out_param, u32 in_modifier, u8 op_modifier,
1675 u16 op, u16 token, int event)
1676 {
1677 u32 __iomem *hcr = (u32 __iomem *)(hr_dev->reg_base + ROCEE_MB1_REG);
1678 unsigned long end;
1679 u32 val = 0;
1680 __le32 tmp;
1681
1682 end = msecs_to_jiffies(GO_BIT_TIMEOUT_MSECS) + jiffies;
1683 while (hns_roce_v1_cmd_pending(hr_dev)) {
1684 if (time_after(jiffies, end)) {
1685 dev_err(hr_dev->dev, "jiffies=%d end=%d\n",
1686 (int)jiffies, (int)end);
1687 return -EAGAIN;
1688 }
1689 cond_resched();
1690 }
1691
1692 tmp = cpu_to_le32(val);
1693 roce_set_field(tmp, ROCEE_MB6_ROCEE_MB_CMD_M, ROCEE_MB6_ROCEE_MB_CMD_S,
1694 op);
1695 roce_set_field(tmp, ROCEE_MB6_ROCEE_MB_CMD_MDF_M,
1696 ROCEE_MB6_ROCEE_MB_CMD_MDF_S, op_modifier);
1697 roce_set_bit(tmp, ROCEE_MB6_ROCEE_MB_EVENT_S, event);
1698 roce_set_bit(tmp, ROCEE_MB6_ROCEE_MB_HW_RUN_S, 1);
1699 roce_set_field(tmp, ROCEE_MB6_ROCEE_MB_TOKEN_M,
1700 ROCEE_MB6_ROCEE_MB_TOKEN_S, token);
1701
1702 val = le32_to_cpu(tmp);
1703 writeq(in_param, hcr + 0);
1704 writeq(out_param, hcr + 2);
1705 writel(in_modifier, hcr + 4);
1706 /* Memory barrier */
1707 wmb();
1708
1709 writel(val, hcr + 5);
1710
1711 return 0;
1712 }
1713
1714 static int hns_roce_v1_chk_mbox(struct hns_roce_dev *hr_dev,
1715 unsigned long timeout)
1716 {
1717 u8 __iomem *hcr = hr_dev->reg_base + ROCEE_MB1_REG;
1718 unsigned long end = 0;
1719 u32 status = 0;
1720
1721 end = msecs_to_jiffies(timeout) + jiffies;
1722 while (hns_roce_v1_cmd_pending(hr_dev) && time_before(jiffies, end))
1723 cond_resched();
1724
1725 if (hns_roce_v1_cmd_pending(hr_dev)) {
1726 dev_err(hr_dev->dev, "[cmd_poll]hw run cmd TIMEDOUT!\n");
1727 return -ETIMEDOUT;
1728 }
1729
1730 status = le32_to_cpu((__force __le32)
1731 __raw_readl(hcr + HCR_STATUS_OFFSET));
1732 if ((status & STATUS_MASK) != 0x1) {
1733 dev_err(hr_dev->dev, "mailbox status 0x%x!\n", status);
1734 return -EBUSY;
1735 }
1736
1737 return 0;
1738 }
1739
1740 static int hns_roce_v1_set_gid(struct hns_roce_dev *hr_dev, u8 port,
1741 int gid_index, const union ib_gid *gid,
1742 const struct ib_gid_attr *attr)
1743 {
1744 unsigned long flags;
1745 u32 *p = NULL;
1746 u8 gid_idx = 0;
1747
1748 gid_idx = hns_get_gid_index(hr_dev, port, gid_index);
1749
1750 spin_lock_irqsave(&hr_dev->iboe.lock, flags);
1751
1752 p = (u32 *)&gid->raw[0];
1753 roce_raw_write(*p, hr_dev->reg_base + ROCEE_PORT_GID_L_0_REG +
1754 (HNS_ROCE_V1_GID_NUM * gid_idx));
1755
1756 p = (u32 *)&gid->raw[4];
1757 roce_raw_write(*p, hr_dev->reg_base + ROCEE_PORT_GID_ML_0_REG +
1758 (HNS_ROCE_V1_GID_NUM * gid_idx));
1759
1760 p = (u32 *)&gid->raw[8];
1761 roce_raw_write(*p, hr_dev->reg_base + ROCEE_PORT_GID_MH_0_REG +
1762 (HNS_ROCE_V1_GID_NUM * gid_idx));
1763
1764 p = (u32 *)&gid->raw[0xc];
1765 roce_raw_write(*p, hr_dev->reg_base + ROCEE_PORT_GID_H_0_REG +
1766 (HNS_ROCE_V1_GID_NUM * gid_idx));
1767
1768 spin_unlock_irqrestore(&hr_dev->iboe.lock, flags);
1769
1770 return 0;
1771 }
1772
1773 static int hns_roce_v1_set_mac(struct hns_roce_dev *hr_dev, u8 phy_port,
1774 u8 *addr)
1775 {
1776 u32 reg_smac_l;
1777 u16 reg_smac_h;
1778 __le32 tmp;
1779 u16 *p_h;
1780 u32 *p;
1781 u32 val;
1782
1783 /*
1784 * When mac changed, loopback may fail
1785 * because of smac not equal to dmac.
1786 * We Need to release and create reserved qp again.
1787 */
1788 if (hr_dev->hw->dereg_mr) {
1789 int ret;
1790
1791 ret = hns_roce_v1_recreate_lp_qp(hr_dev);
1792 if (ret && ret != -ETIMEDOUT)
1793 return ret;
1794 }
1795
1796 p = (u32 *)(&addr[0]);
1797 reg_smac_l = *p;
1798 roce_raw_write(reg_smac_l, hr_dev->reg_base + ROCEE_SMAC_L_0_REG +
1799 PHY_PORT_OFFSET * phy_port);
1800
1801 val = roce_read(hr_dev,
1802 ROCEE_SMAC_H_0_REG + phy_port * PHY_PORT_OFFSET);
1803 tmp = cpu_to_le32(val);
1804 p_h = (u16 *)(&addr[4]);
1805 reg_smac_h = *p_h;
1806 roce_set_field(tmp, ROCEE_SMAC_H_ROCEE_SMAC_H_M,
1807 ROCEE_SMAC_H_ROCEE_SMAC_H_S, reg_smac_h);
1808 val = le32_to_cpu(tmp);
1809 roce_write(hr_dev, ROCEE_SMAC_H_0_REG + phy_port * PHY_PORT_OFFSET,
1810 val);
1811
1812 return 0;
1813 }
1814
1815 static void hns_roce_v1_set_mtu(struct hns_roce_dev *hr_dev, u8 phy_port,
1816 enum ib_mtu mtu)
1817 {
1818 __le32 tmp;
1819 u32 val;
1820
1821 val = roce_read(hr_dev,
1822 ROCEE_SMAC_H_0_REG + phy_port * PHY_PORT_OFFSET);
1823 tmp = cpu_to_le32(val);
1824 roce_set_field(tmp, ROCEE_SMAC_H_ROCEE_PORT_MTU_M,
1825 ROCEE_SMAC_H_ROCEE_PORT_MTU_S, mtu);
1826 val = le32_to_cpu(tmp);
1827 roce_write(hr_dev, ROCEE_SMAC_H_0_REG + phy_port * PHY_PORT_OFFSET,
1828 val);
1829 }
1830
1831 static int hns_roce_v1_write_mtpt(void *mb_buf, struct hns_roce_mr *mr,
1832 unsigned long mtpt_idx)
1833 {
1834 struct hns_roce_v1_mpt_entry *mpt_entry;
1835 struct sg_dma_page_iter sg_iter;
1836 u64 *pages;
1837 int i;
1838
1839 /* MPT filled into mailbox buf */
1840 mpt_entry = (struct hns_roce_v1_mpt_entry *)mb_buf;
1841 memset(mpt_entry, 0, sizeof(*mpt_entry));
1842
1843 roce_set_field(mpt_entry->mpt_byte_4, MPT_BYTE_4_KEY_STATE_M,
1844 MPT_BYTE_4_KEY_STATE_S, KEY_VALID);
1845 roce_set_field(mpt_entry->mpt_byte_4, MPT_BYTE_4_KEY_M,
1846 MPT_BYTE_4_KEY_S, mr->key);
1847 roce_set_field(mpt_entry->mpt_byte_4, MPT_BYTE_4_PAGE_SIZE_M,
1848 MPT_BYTE_4_PAGE_SIZE_S, MR_SIZE_4K);
1849 roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_MW_TYPE_S, 0);
1850 roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_MW_BIND_ENABLE_S,
1851 (mr->access & IB_ACCESS_MW_BIND ? 1 : 0));
1852 roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_OWN_S, 0);
1853 roce_set_field(mpt_entry->mpt_byte_4, MPT_BYTE_4_MEMORY_LOCATION_TYPE_M,
1854 MPT_BYTE_4_MEMORY_LOCATION_TYPE_S, mr->type);
1855 roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_REMOTE_ATOMIC_S, 0);
1856 roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_LOCAL_WRITE_S,
1857 (mr->access & IB_ACCESS_LOCAL_WRITE ? 1 : 0));
1858 roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_REMOTE_WRITE_S,
1859 (mr->access & IB_ACCESS_REMOTE_WRITE ? 1 : 0));
1860 roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_REMOTE_READ_S,
1861 (mr->access & IB_ACCESS_REMOTE_READ ? 1 : 0));
1862 roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_REMOTE_INVAL_ENABLE_S,
1863 0);
1864 roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_ADDRESS_TYPE_S, 0);
1865
1866 roce_set_field(mpt_entry->mpt_byte_12, MPT_BYTE_12_PBL_ADDR_H_M,
1867 MPT_BYTE_12_PBL_ADDR_H_S, 0);
1868 roce_set_field(mpt_entry->mpt_byte_12, MPT_BYTE_12_MW_BIND_COUNTER_M,
1869 MPT_BYTE_12_MW_BIND_COUNTER_S, 0);
1870
1871 mpt_entry->virt_addr_l = cpu_to_le32((u32)mr->iova);
1872 mpt_entry->virt_addr_h = cpu_to_le32((u32)(mr->iova >> 32));
1873 mpt_entry->length = cpu_to_le32((u32)mr->size);
1874
1875 roce_set_field(mpt_entry->mpt_byte_28, MPT_BYTE_28_PD_M,
1876 MPT_BYTE_28_PD_S, mr->pd);
1877 roce_set_field(mpt_entry->mpt_byte_28, MPT_BYTE_28_L_KEY_IDX_L_M,
1878 MPT_BYTE_28_L_KEY_IDX_L_S, mtpt_idx);
1879 roce_set_field(mpt_entry->mpt_byte_64, MPT_BYTE_64_L_KEY_IDX_H_M,
1880 MPT_BYTE_64_L_KEY_IDX_H_S, mtpt_idx >> MTPT_IDX_SHIFT);
1881
1882 /* DMA memory register */
1883 if (mr->type == MR_TYPE_DMA)
1884 return 0;
1885
1886 pages = (u64 *) __get_free_page(GFP_KERNEL);
1887 if (!pages)
1888 return -ENOMEM;
1889
1890 i = 0;
1891 for_each_sg_dma_page(mr->umem->sg_head.sgl, &sg_iter, mr->umem->nmap, 0) {
1892 pages[i] = ((u64)sg_page_iter_dma_address(&sg_iter)) >> 12;
1893
1894 /* Directly record to MTPT table firstly 7 entry */
1895 if (i >= HNS_ROCE_MAX_INNER_MTPT_NUM)
1896 break;
1897 i++;
1898 }
1899
1900 /* Register user mr */
1901 for (i = 0; i < HNS_ROCE_MAX_INNER_MTPT_NUM; i++) {
1902 switch (i) {
1903 case 0:
1904 mpt_entry->pa0_l = cpu_to_le32((u32)(pages[i]));
1905 roce_set_field(mpt_entry->mpt_byte_36,
1906 MPT_BYTE_36_PA0_H_M,
1907 MPT_BYTE_36_PA0_H_S,
1908 (u32)(pages[i] >> PAGES_SHIFT_32));
1909 break;
1910 case 1:
1911 roce_set_field(mpt_entry->mpt_byte_36,
1912 MPT_BYTE_36_PA1_L_M,
1913 MPT_BYTE_36_PA1_L_S, (u32)(pages[i]));
1914 roce_set_field(mpt_entry->mpt_byte_40,
1915 MPT_BYTE_40_PA1_H_M,
1916 MPT_BYTE_40_PA1_H_S,
1917 (u32)(pages[i] >> PAGES_SHIFT_24));
1918 break;
1919 case 2:
1920 roce_set_field(mpt_entry->mpt_byte_40,
1921 MPT_BYTE_40_PA2_L_M,
1922 MPT_BYTE_40_PA2_L_S, (u32)(pages[i]));
1923 roce_set_field(mpt_entry->mpt_byte_44,
1924 MPT_BYTE_44_PA2_H_M,
1925 MPT_BYTE_44_PA2_H_S,
1926 (u32)(pages[i] >> PAGES_SHIFT_16));
1927 break;
1928 case 3:
1929 roce_set_field(mpt_entry->mpt_byte_44,
1930 MPT_BYTE_44_PA3_L_M,
1931 MPT_BYTE_44_PA3_L_S, (u32)(pages[i]));
1932 roce_set_field(mpt_entry->mpt_byte_48,
1933 MPT_BYTE_48_PA3_H_M,
1934 MPT_BYTE_48_PA3_H_S,
1935 (u32)(pages[i] >> PAGES_SHIFT_8));
1936 break;
1937 case 4:
1938 mpt_entry->pa4_l = cpu_to_le32((u32)(pages[i]));
1939 roce_set_field(mpt_entry->mpt_byte_56,
1940 MPT_BYTE_56_PA4_H_M,
1941 MPT_BYTE_56_PA4_H_S,
1942 (u32)(pages[i] >> PAGES_SHIFT_32));
1943 break;
1944 case 5:
1945 roce_set_field(mpt_entry->mpt_byte_56,
1946 MPT_BYTE_56_PA5_L_M,
1947 MPT_BYTE_56_PA5_L_S, (u32)(pages[i]));
1948 roce_set_field(mpt_entry->mpt_byte_60,
1949 MPT_BYTE_60_PA5_H_M,
1950 MPT_BYTE_60_PA5_H_S,
1951 (u32)(pages[i] >> PAGES_SHIFT_24));
1952 break;
1953 case 6:
1954 roce_set_field(mpt_entry->mpt_byte_60,
1955 MPT_BYTE_60_PA6_L_M,
1956 MPT_BYTE_60_PA6_L_S, (u32)(pages[i]));
1957 roce_set_field(mpt_entry->mpt_byte_64,
1958 MPT_BYTE_64_PA6_H_M,
1959 MPT_BYTE_64_PA6_H_S,
1960 (u32)(pages[i] >> PAGES_SHIFT_16));
1961 break;
1962 default:
1963 break;
1964 }
1965 }
1966
1967 free_page((unsigned long) pages);
1968
1969 mpt_entry->pbl_addr_l = cpu_to_le32((u32)(mr->pbl_dma_addr));
1970
1971 roce_set_field(mpt_entry->mpt_byte_12, MPT_BYTE_12_PBL_ADDR_H_M,
1972 MPT_BYTE_12_PBL_ADDR_H_S,
1973 ((u32)(mr->pbl_dma_addr >> 32)));
1974
1975 return 0;
1976 }
1977
1978 static void *get_cqe(struct hns_roce_cq *hr_cq, int n)
1979 {
1980 return hns_roce_buf_offset(&hr_cq->buf, n * HNS_ROCE_V1_CQE_ENTRY_SIZE);
1981 }
1982
1983 static void *get_sw_cqe(struct hns_roce_cq *hr_cq, int n)
1984 {
1985 struct hns_roce_cqe *hr_cqe = get_cqe(hr_cq, n & hr_cq->ib_cq.cqe);
1986
1987 /* Get cqe when Owner bit is Conversely with the MSB of cons_idx */
1988 return (roce_get_bit(hr_cqe->cqe_byte_4, CQE_BYTE_4_OWNER_S) ^
1989 !!(n & hr_cq->cq_depth)) ? hr_cqe : NULL;
1990 }
1991
1992 static struct hns_roce_cqe *next_cqe_sw(struct hns_roce_cq *hr_cq)
1993 {
1994 return get_sw_cqe(hr_cq, hr_cq->cons_index);
1995 }
1996
1997 static void hns_roce_v1_cq_set_ci(struct hns_roce_cq *hr_cq, u32 cons_index)
1998 {
1999 __le32 doorbell[2];
2000
2001 doorbell[0] = cpu_to_le32(cons_index & ((hr_cq->cq_depth << 1) - 1));
2002 doorbell[1] = 0;
2003 roce_set_bit(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_HW_SYNS_S, 1);
2004 roce_set_field(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_M,
2005 ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_S, 3);
2006 roce_set_field(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_MDF_M,
2007 ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_MDF_S, 0);
2008 roce_set_field(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_INP_H_M,
2009 ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_INP_H_S, hr_cq->cqn);
2010
2011 hns_roce_write64_k(doorbell, hr_cq->cq_db_l);
2012 }
2013
2014 static void __hns_roce_v1_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn,
2015 struct hns_roce_srq *srq)
2016 {
2017 struct hns_roce_cqe *cqe, *dest;
2018 u32 prod_index;
2019 int nfreed = 0;
2020 u8 owner_bit;
2021
2022 for (prod_index = hr_cq->cons_index; get_sw_cqe(hr_cq, prod_index);
2023 ++prod_index) {
2024 if (prod_index == hr_cq->cons_index + hr_cq->ib_cq.cqe)
2025 break;
2026 }
2027
2028 /*
2029 * Now backwards through the CQ, removing CQ entries
2030 * that match our QP by overwriting them with next entries.
2031 */
2032 while ((int) --prod_index - (int) hr_cq->cons_index >= 0) {
2033 cqe = get_cqe(hr_cq, prod_index & hr_cq->ib_cq.cqe);
2034 if ((roce_get_field(cqe->cqe_byte_16, CQE_BYTE_16_LOCAL_QPN_M,
2035 CQE_BYTE_16_LOCAL_QPN_S) &
2036 HNS_ROCE_CQE_QPN_MASK) == qpn) {
2037 /* In v1 engine, not support SRQ */
2038 ++nfreed;
2039 } else if (nfreed) {
2040 dest = get_cqe(hr_cq, (prod_index + nfreed) &
2041 hr_cq->ib_cq.cqe);
2042 owner_bit = roce_get_bit(dest->cqe_byte_4,
2043 CQE_BYTE_4_OWNER_S);
2044 memcpy(dest, cqe, sizeof(*cqe));
2045 roce_set_bit(dest->cqe_byte_4, CQE_BYTE_4_OWNER_S,
2046 owner_bit);
2047 }
2048 }
2049
2050 if (nfreed) {
2051 hr_cq->cons_index += nfreed;
2052 /*
2053 * Make sure update of buffer contents is done before
2054 * updating consumer index.
2055 */
2056 wmb();
2057
2058 hns_roce_v1_cq_set_ci(hr_cq, hr_cq->cons_index);
2059 }
2060 }
2061
2062 static void hns_roce_v1_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn,
2063 struct hns_roce_srq *srq)
2064 {
2065 spin_lock_irq(&hr_cq->lock);
2066 __hns_roce_v1_cq_clean(hr_cq, qpn, srq);
2067 spin_unlock_irq(&hr_cq->lock);
2068 }
2069
2070 static void hns_roce_v1_write_cqc(struct hns_roce_dev *hr_dev,
2071 struct hns_roce_cq *hr_cq, void *mb_buf,
2072 u64 *mtts, dma_addr_t dma_handle)
2073 {
2074 struct hns_roce_cq_context *cq_context = NULL;
2075 struct hns_roce_buf_list *tptr_buf;
2076 struct hns_roce_v1_priv *priv;
2077 dma_addr_t tptr_dma_addr;
2078 int offset;
2079
2080 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
2081 tptr_buf = &priv->tptr_table.tptr_buf;
2082
2083 cq_context = mb_buf;
2084 memset(cq_context, 0, sizeof(*cq_context));
2085
2086 /* Get the tptr for this CQ. */
2087 offset = hr_cq->cqn * HNS_ROCE_V1_TPTR_ENTRY_SIZE;
2088 tptr_dma_addr = tptr_buf->map + offset;
2089 hr_cq->tptr_addr = (u16 *)(tptr_buf->buf + offset);
2090
2091 /* Register cq_context members */
2092 roce_set_field(cq_context->cqc_byte_4,
2093 CQ_CONTEXT_CQC_BYTE_4_CQC_STATE_M,
2094 CQ_CONTEXT_CQC_BYTE_4_CQC_STATE_S, CQ_STATE_VALID);
2095 roce_set_field(cq_context->cqc_byte_4, CQ_CONTEXT_CQC_BYTE_4_CQN_M,
2096 CQ_CONTEXT_CQC_BYTE_4_CQN_S, hr_cq->cqn);
2097
2098 cq_context->cq_bt_l = cpu_to_le32((u32)dma_handle);
2099
2100 roce_set_field(cq_context->cqc_byte_12,
2101 CQ_CONTEXT_CQC_BYTE_12_CQ_BT_H_M,
2102 CQ_CONTEXT_CQC_BYTE_12_CQ_BT_H_S,
2103 ((u64)dma_handle >> 32));
2104 roce_set_field(cq_context->cqc_byte_12,
2105 CQ_CONTEXT_CQC_BYTE_12_CQ_CQE_SHIFT_M,
2106 CQ_CONTEXT_CQC_BYTE_12_CQ_CQE_SHIFT_S,
2107 ilog2(hr_cq->cq_depth));
2108 roce_set_field(cq_context->cqc_byte_12, CQ_CONTEXT_CQC_BYTE_12_CEQN_M,
2109 CQ_CONTEXT_CQC_BYTE_12_CEQN_S, hr_cq->vector);
2110
2111 cq_context->cur_cqe_ba0_l = cpu_to_le32((u32)(mtts[0]));
2112
2113 roce_set_field(cq_context->cqc_byte_20,
2114 CQ_CONTEXT_CQC_BYTE_20_CUR_CQE_BA0_H_M,
2115 CQ_CONTEXT_CQC_BYTE_20_CUR_CQE_BA0_H_S, (mtts[0]) >> 32);
2116 /* Dedicated hardware, directly set 0 */
2117 roce_set_field(cq_context->cqc_byte_20,
2118 CQ_CONTEXT_CQC_BYTE_20_CQ_CUR_INDEX_M,
2119 CQ_CONTEXT_CQC_BYTE_20_CQ_CUR_INDEX_S, 0);
2120 /**
2121 * 44 = 32 + 12, When evaluating addr to hardware, shift 12 because of
2122 * using 4K page, and shift more 32 because of
2123 * caculating the high 32 bit value evaluated to hardware.
2124 */
2125 roce_set_field(cq_context->cqc_byte_20,
2126 CQ_CONTEXT_CQC_BYTE_20_CQE_TPTR_ADDR_H_M,
2127 CQ_CONTEXT_CQC_BYTE_20_CQE_TPTR_ADDR_H_S,
2128 tptr_dma_addr >> 44);
2129
2130 cq_context->cqe_tptr_addr_l = cpu_to_le32((u32)(tptr_dma_addr >> 12));
2131
2132 roce_set_field(cq_context->cqc_byte_32,
2133 CQ_CONTEXT_CQC_BYTE_32_CUR_CQE_BA1_H_M,
2134 CQ_CONTEXT_CQC_BYTE_32_CUR_CQE_BA1_H_S, 0);
2135 roce_set_bit(cq_context->cqc_byte_32,
2136 CQ_CONTEXT_CQC_BYTE_32_SE_FLAG_S, 0);
2137 roce_set_bit(cq_context->cqc_byte_32,
2138 CQ_CONTEXT_CQC_BYTE_32_CE_FLAG_S, 0);
2139 roce_set_bit(cq_context->cqc_byte_32,
2140 CQ_CONTEXT_CQC_BYTE_32_NOTIFICATION_FLAG_S, 0);
2141 roce_set_bit(cq_context->cqc_byte_32,
2142 CQ_CQNTEXT_CQC_BYTE_32_TYPE_OF_COMPLETION_NOTIFICATION_S,
2143 0);
2144 /* The initial value of cq's ci is 0 */
2145 roce_set_field(cq_context->cqc_byte_32,
2146 CQ_CONTEXT_CQC_BYTE_32_CQ_CONS_IDX_M,
2147 CQ_CONTEXT_CQC_BYTE_32_CQ_CONS_IDX_S, 0);
2148 }
2149
2150 static int hns_roce_v1_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period)
2151 {
2152 return -EOPNOTSUPP;
2153 }
2154
2155 static int hns_roce_v1_req_notify_cq(struct ib_cq *ibcq,
2156 enum ib_cq_notify_flags flags)
2157 {
2158 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq);
2159 u32 notification_flag;
2160 __le32 doorbell[2] = {};
2161
2162 notification_flag = (flags & IB_CQ_SOLICITED_MASK) ==
2163 IB_CQ_SOLICITED ? CQ_DB_REQ_NOT : CQ_DB_REQ_NOT_SOL;
2164 /*
2165 * flags = 0; Notification Flag = 1, next
2166 * flags = 1; Notification Flag = 0, solocited
2167 */
2168 doorbell[0] =
2169 cpu_to_le32(hr_cq->cons_index & ((hr_cq->cq_depth << 1) - 1));
2170 roce_set_bit(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_HW_SYNS_S, 1);
2171 roce_set_field(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_M,
2172 ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_S, 3);
2173 roce_set_field(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_MDF_M,
2174 ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_MDF_S, 1);
2175 roce_set_field(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_INP_H_M,
2176 ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_INP_H_S,
2177 hr_cq->cqn | notification_flag);
2178
2179 hns_roce_write64_k(doorbell, hr_cq->cq_db_l);
2180
2181 return 0;
2182 }
2183
2184 static int hns_roce_v1_poll_one(struct hns_roce_cq *hr_cq,
2185 struct hns_roce_qp **cur_qp, struct ib_wc *wc)
2186 {
2187 int qpn;
2188 int is_send;
2189 u16 wqe_ctr;
2190 u32 status;
2191 u32 opcode;
2192 struct hns_roce_cqe *cqe;
2193 struct hns_roce_qp *hr_qp;
2194 struct hns_roce_wq *wq;
2195 struct hns_roce_wqe_ctrl_seg *sq_wqe;
2196 struct hns_roce_dev *hr_dev = to_hr_dev(hr_cq->ib_cq.device);
2197 struct device *dev = &hr_dev->pdev->dev;
2198
2199 /* Find cqe according consumer index */
2200 cqe = next_cqe_sw(hr_cq);
2201 if (!cqe)
2202 return -EAGAIN;
2203
2204 ++hr_cq->cons_index;
2205 /* Memory barrier */
2206 rmb();
2207 /* 0->SQ, 1->RQ */
2208 is_send = !(roce_get_bit(cqe->cqe_byte_4, CQE_BYTE_4_SQ_RQ_FLAG_S));
2209
2210 /* Local_qpn in UD cqe is always 1, so it needs to compute new qpn */
2211 if (roce_get_field(cqe->cqe_byte_16, CQE_BYTE_16_LOCAL_QPN_M,
2212 CQE_BYTE_16_LOCAL_QPN_S) <= 1) {
2213 qpn = roce_get_field(cqe->cqe_byte_20, CQE_BYTE_20_PORT_NUM_M,
2214 CQE_BYTE_20_PORT_NUM_S) +
2215 roce_get_field(cqe->cqe_byte_16, CQE_BYTE_16_LOCAL_QPN_M,
2216 CQE_BYTE_16_LOCAL_QPN_S) *
2217 HNS_ROCE_MAX_PORTS;
2218 } else {
2219 qpn = roce_get_field(cqe->cqe_byte_16, CQE_BYTE_16_LOCAL_QPN_M,
2220 CQE_BYTE_16_LOCAL_QPN_S);
2221 }
2222
2223 if (!*cur_qp || (qpn & HNS_ROCE_CQE_QPN_MASK) != (*cur_qp)->qpn) {
2224 hr_qp = __hns_roce_qp_lookup(hr_dev, qpn);
2225 if (unlikely(!hr_qp)) {
2226 dev_err(dev, "CQ %06lx with entry for unknown QPN %06x\n",
2227 hr_cq->cqn, (qpn & HNS_ROCE_CQE_QPN_MASK));
2228 return -EINVAL;
2229 }
2230
2231 *cur_qp = hr_qp;
2232 }
2233
2234 wc->qp = &(*cur_qp)->ibqp;
2235 wc->vendor_err = 0;
2236
2237 status = roce_get_field(cqe->cqe_byte_4,
2238 CQE_BYTE_4_STATUS_OF_THE_OPERATION_M,
2239 CQE_BYTE_4_STATUS_OF_THE_OPERATION_S) &
2240 HNS_ROCE_CQE_STATUS_MASK;
2241 switch (status) {
2242 case HNS_ROCE_CQE_SUCCESS:
2243 wc->status = IB_WC_SUCCESS;
2244 break;
2245 case HNS_ROCE_CQE_SYNDROME_LOCAL_LENGTH_ERR:
2246 wc->status = IB_WC_LOC_LEN_ERR;
2247 break;
2248 case HNS_ROCE_CQE_SYNDROME_LOCAL_QP_OP_ERR:
2249 wc->status = IB_WC_LOC_QP_OP_ERR;
2250 break;
2251 case HNS_ROCE_CQE_SYNDROME_LOCAL_PROT_ERR:
2252 wc->status = IB_WC_LOC_PROT_ERR;
2253 break;
2254 case HNS_ROCE_CQE_SYNDROME_WR_FLUSH_ERR:
2255 wc->status = IB_WC_WR_FLUSH_ERR;
2256 break;
2257 case HNS_ROCE_CQE_SYNDROME_MEM_MANAGE_OPERATE_ERR:
2258 wc->status = IB_WC_MW_BIND_ERR;
2259 break;
2260 case HNS_ROCE_CQE_SYNDROME_BAD_RESP_ERR:
2261 wc->status = IB_WC_BAD_RESP_ERR;
2262 break;
2263 case HNS_ROCE_CQE_SYNDROME_LOCAL_ACCESS_ERR:
2264 wc->status = IB_WC_LOC_ACCESS_ERR;
2265 break;
2266 case HNS_ROCE_CQE_SYNDROME_REMOTE_INVAL_REQ_ERR:
2267 wc->status = IB_WC_REM_INV_REQ_ERR;
2268 break;
2269 case HNS_ROCE_CQE_SYNDROME_REMOTE_ACCESS_ERR:
2270 wc->status = IB_WC_REM_ACCESS_ERR;
2271 break;
2272 case HNS_ROCE_CQE_SYNDROME_REMOTE_OP_ERR:
2273 wc->status = IB_WC_REM_OP_ERR;
2274 break;
2275 case HNS_ROCE_CQE_SYNDROME_TRANSPORT_RETRY_EXC_ERR:
2276 wc->status = IB_WC_RETRY_EXC_ERR;
2277 break;
2278 case HNS_ROCE_CQE_SYNDROME_RNR_RETRY_EXC_ERR:
2279 wc->status = IB_WC_RNR_RETRY_EXC_ERR;
2280 break;
2281 default:
2282 wc->status = IB_WC_GENERAL_ERR;
2283 break;
2284 }
2285
2286 /* CQE status error, directly return */
2287 if (wc->status != IB_WC_SUCCESS)
2288 return 0;
2289
2290 if (is_send) {
2291 /* SQ conrespond to CQE */
2292 sq_wqe = get_send_wqe(*cur_qp, roce_get_field(cqe->cqe_byte_4,
2293 CQE_BYTE_4_WQE_INDEX_M,
2294 CQE_BYTE_4_WQE_INDEX_S)&
2295 ((*cur_qp)->sq.wqe_cnt-1));
2296 switch (le32_to_cpu(sq_wqe->flag) & HNS_ROCE_WQE_OPCODE_MASK) {
2297 case HNS_ROCE_WQE_OPCODE_SEND:
2298 wc->opcode = IB_WC_SEND;
2299 break;
2300 case HNS_ROCE_WQE_OPCODE_RDMA_READ:
2301 wc->opcode = IB_WC_RDMA_READ;
2302 wc->byte_len = le32_to_cpu(cqe->byte_cnt);
2303 break;
2304 case HNS_ROCE_WQE_OPCODE_RDMA_WRITE:
2305 wc->opcode = IB_WC_RDMA_WRITE;
2306 break;
2307 case HNS_ROCE_WQE_OPCODE_LOCAL_INV:
2308 wc->opcode = IB_WC_LOCAL_INV;
2309 break;
2310 case HNS_ROCE_WQE_OPCODE_UD_SEND:
2311 wc->opcode = IB_WC_SEND;
2312 break;
2313 default:
2314 wc->status = IB_WC_GENERAL_ERR;
2315 break;
2316 }
2317 wc->wc_flags = (le32_to_cpu(sq_wqe->flag) & HNS_ROCE_WQE_IMM ?
2318 IB_WC_WITH_IMM : 0);
2319
2320 wq = &(*cur_qp)->sq;
2321 if ((*cur_qp)->sq_signal_bits) {
2322 /*
2323 * If sg_signal_bit is 1,
2324 * firstly tail pointer updated to wqe
2325 * which current cqe correspond to
2326 */
2327 wqe_ctr = (u16)roce_get_field(cqe->cqe_byte_4,
2328 CQE_BYTE_4_WQE_INDEX_M,
2329 CQE_BYTE_4_WQE_INDEX_S);
2330 wq->tail += (wqe_ctr - (u16)wq->tail) &
2331 (wq->wqe_cnt - 1);
2332 }
2333 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
2334 ++wq->tail;
2335 } else {
2336 /* RQ conrespond to CQE */
2337 wc->byte_len = le32_to_cpu(cqe->byte_cnt);
2338 opcode = roce_get_field(cqe->cqe_byte_4,
2339 CQE_BYTE_4_OPERATION_TYPE_M,
2340 CQE_BYTE_4_OPERATION_TYPE_S) &
2341 HNS_ROCE_CQE_OPCODE_MASK;
2342 switch (opcode) {
2343 case HNS_ROCE_OPCODE_RDMA_WITH_IMM_RECEIVE:
2344 wc->opcode = IB_WC_RECV_RDMA_WITH_IMM;
2345 wc->wc_flags = IB_WC_WITH_IMM;
2346 wc->ex.imm_data =
2347 cpu_to_be32(le32_to_cpu(cqe->immediate_data));
2348 break;
2349 case HNS_ROCE_OPCODE_SEND_DATA_RECEIVE:
2350 if (roce_get_bit(cqe->cqe_byte_4,
2351 CQE_BYTE_4_IMM_INDICATOR_S)) {
2352 wc->opcode = IB_WC_RECV;
2353 wc->wc_flags = IB_WC_WITH_IMM;
2354 wc->ex.imm_data = cpu_to_be32(
2355 le32_to_cpu(cqe->immediate_data));
2356 } else {
2357 wc->opcode = IB_WC_RECV;
2358 wc->wc_flags = 0;
2359 }
2360 break;
2361 default:
2362 wc->status = IB_WC_GENERAL_ERR;
2363 break;
2364 }
2365
2366 /* Update tail pointer, record wr_id */
2367 wq = &(*cur_qp)->rq;
2368 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
2369 ++wq->tail;
2370 wc->sl = (u8)roce_get_field(cqe->cqe_byte_20, CQE_BYTE_20_SL_M,
2371 CQE_BYTE_20_SL_S);
2372 wc->src_qp = (u8)roce_get_field(cqe->cqe_byte_20,
2373 CQE_BYTE_20_REMOTE_QPN_M,
2374 CQE_BYTE_20_REMOTE_QPN_S);
2375 wc->wc_flags |= (roce_get_bit(cqe->cqe_byte_20,
2376 CQE_BYTE_20_GRH_PRESENT_S) ?
2377 IB_WC_GRH : 0);
2378 wc->pkey_index = (u16)roce_get_field(cqe->cqe_byte_28,
2379 CQE_BYTE_28_P_KEY_IDX_M,
2380 CQE_BYTE_28_P_KEY_IDX_S);
2381 }
2382
2383 return 0;
2384 }
2385
2386 int hns_roce_v1_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc)
2387 {
2388 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq);
2389 struct hns_roce_qp *cur_qp = NULL;
2390 unsigned long flags;
2391 int npolled;
2392 int ret = 0;
2393
2394 spin_lock_irqsave(&hr_cq->lock, flags);
2395
2396 for (npolled = 0; npolled < num_entries; ++npolled) {
2397 ret = hns_roce_v1_poll_one(hr_cq, &cur_qp, wc + npolled);
2398 if (ret)
2399 break;
2400 }
2401
2402 if (npolled) {
2403 *hr_cq->tptr_addr = hr_cq->cons_index &
2404 ((hr_cq->cq_depth << 1) - 1);
2405
2406 /* Memroy barrier */
2407 wmb();
2408 hns_roce_v1_cq_set_ci(hr_cq, hr_cq->cons_index);
2409 }
2410
2411 spin_unlock_irqrestore(&hr_cq->lock, flags);
2412
2413 if (ret == 0 || ret == -EAGAIN)
2414 return npolled;
2415 else
2416 return ret;
2417 }
2418
2419 static int hns_roce_v1_clear_hem(struct hns_roce_dev *hr_dev,
2420 struct hns_roce_hem_table *table, int obj,
2421 int step_idx)
2422 {
2423 struct device *dev = &hr_dev->pdev->dev;
2424 struct hns_roce_v1_priv *priv;
2425 unsigned long flags = 0;
2426 long end = HW_SYNC_TIMEOUT_MSECS;
2427 __le32 bt_cmd_val[2] = {0};
2428 void __iomem *bt_cmd;
2429 u64 bt_ba = 0;
2430
2431 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
2432
2433 switch (table->type) {
2434 case HEM_TYPE_QPC:
2435 bt_ba = priv->bt_table.qpc_buf.map >> 12;
2436 break;
2437 case HEM_TYPE_MTPT:
2438 bt_ba = priv->bt_table.mtpt_buf.map >> 12;
2439 break;
2440 case HEM_TYPE_CQC:
2441 bt_ba = priv->bt_table.cqc_buf.map >> 12;
2442 break;
2443 case HEM_TYPE_SRQC:
2444 dev_dbg(dev, "HEM_TYPE_SRQC not support.\n");
2445 return -EINVAL;
2446 default:
2447 return 0;
2448 }
2449 roce_set_field(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_M,
2450 ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_S, table->type);
2451 roce_set_field(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_IN_MDF_M,
2452 ROCEE_BT_CMD_H_ROCEE_BT_CMD_IN_MDF_S, obj);
2453 roce_set_bit(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_S, 0);
2454 roce_set_bit(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_HW_SYNS_S, 1);
2455
2456 spin_lock_irqsave(&hr_dev->bt_cmd_lock, flags);
2457
2458 bt_cmd = hr_dev->reg_base + ROCEE_BT_CMD_H_REG;
2459
2460 while (1) {
2461 if (readl(bt_cmd) >> BT_CMD_SYNC_SHIFT) {
2462 if (!end) {
2463 dev_err(dev, "Write bt_cmd err,hw_sync is not zero.\n");
2464 spin_unlock_irqrestore(&hr_dev->bt_cmd_lock,
2465 flags);
2466 return -EBUSY;
2467 }
2468 } else {
2469 break;
2470 }
2471 mdelay(HW_SYNC_SLEEP_TIME_INTERVAL);
2472 end -= HW_SYNC_SLEEP_TIME_INTERVAL;
2473 }
2474
2475 bt_cmd_val[0] = cpu_to_le32(bt_ba);
2476 roce_set_field(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_BA_H_M,
2477 ROCEE_BT_CMD_H_ROCEE_BT_CMD_BA_H_S, bt_ba >> 32);
2478 hns_roce_write64_k(bt_cmd_val, hr_dev->reg_base + ROCEE_BT_CMD_L_REG);
2479
2480 spin_unlock_irqrestore(&hr_dev->bt_cmd_lock, flags);
2481
2482 return 0;
2483 }
2484
2485 static int hns_roce_v1_qp_modify(struct hns_roce_dev *hr_dev,
2486 struct hns_roce_mtt *mtt,
2487 enum hns_roce_qp_state cur_state,
2488 enum hns_roce_qp_state new_state,
2489 struct hns_roce_qp_context *context,
2490 struct hns_roce_qp *hr_qp)
2491 {
2492 static const u16
2493 op[HNS_ROCE_QP_NUM_STATE][HNS_ROCE_QP_NUM_STATE] = {
2494 [HNS_ROCE_QP_STATE_RST] = {
2495 [HNS_ROCE_QP_STATE_RST] = HNS_ROCE_CMD_2RST_QP,
2496 [HNS_ROCE_QP_STATE_ERR] = HNS_ROCE_CMD_2ERR_QP,
2497 [HNS_ROCE_QP_STATE_INIT] = HNS_ROCE_CMD_RST2INIT_QP,
2498 },
2499 [HNS_ROCE_QP_STATE_INIT] = {
2500 [HNS_ROCE_QP_STATE_RST] = HNS_ROCE_CMD_2RST_QP,
2501 [HNS_ROCE_QP_STATE_ERR] = HNS_ROCE_CMD_2ERR_QP,
2502 /* Note: In v1 engine, HW doesn't support RST2INIT.
2503 * We use RST2INIT cmd instead of INIT2INIT.
2504 */
2505 [HNS_ROCE_QP_STATE_INIT] = HNS_ROCE_CMD_RST2INIT_QP,
2506 [HNS_ROCE_QP_STATE_RTR] = HNS_ROCE_CMD_INIT2RTR_QP,
2507 },
2508 [HNS_ROCE_QP_STATE_RTR] = {
2509 [HNS_ROCE_QP_STATE_RST] = HNS_ROCE_CMD_2RST_QP,
2510 [HNS_ROCE_QP_STATE_ERR] = HNS_ROCE_CMD_2ERR_QP,
2511 [HNS_ROCE_QP_STATE_RTS] = HNS_ROCE_CMD_RTR2RTS_QP,
2512 },
2513 [HNS_ROCE_QP_STATE_RTS] = {
2514 [HNS_ROCE_QP_STATE_RST] = HNS_ROCE_CMD_2RST_QP,
2515 [HNS_ROCE_QP_STATE_ERR] = HNS_ROCE_CMD_2ERR_QP,
2516 [HNS_ROCE_QP_STATE_RTS] = HNS_ROCE_CMD_RTS2RTS_QP,
2517 [HNS_ROCE_QP_STATE_SQD] = HNS_ROCE_CMD_RTS2SQD_QP,
2518 },
2519 [HNS_ROCE_QP_STATE_SQD] = {
2520 [HNS_ROCE_QP_STATE_RST] = HNS_ROCE_CMD_2RST_QP,
2521 [HNS_ROCE_QP_STATE_ERR] = HNS_ROCE_CMD_2ERR_QP,
2522 [HNS_ROCE_QP_STATE_RTS] = HNS_ROCE_CMD_SQD2RTS_QP,
2523 [HNS_ROCE_QP_STATE_SQD] = HNS_ROCE_CMD_SQD2SQD_QP,
2524 },
2525 [HNS_ROCE_QP_STATE_ERR] = {
2526 [HNS_ROCE_QP_STATE_RST] = HNS_ROCE_CMD_2RST_QP,
2527 [HNS_ROCE_QP_STATE_ERR] = HNS_ROCE_CMD_2ERR_QP,
2528 }
2529 };
2530
2531 struct hns_roce_cmd_mailbox *mailbox;
2532 struct device *dev = &hr_dev->pdev->dev;
2533 int ret = 0;
2534
2535 if (cur_state >= HNS_ROCE_QP_NUM_STATE ||
2536 new_state >= HNS_ROCE_QP_NUM_STATE ||
2537 !op[cur_state][new_state]) {
2538 dev_err(dev, "[modify_qp]not support state %d to %d\n",
2539 cur_state, new_state);
2540 return -EINVAL;
2541 }
2542
2543 if (op[cur_state][new_state] == HNS_ROCE_CMD_2RST_QP)
2544 return hns_roce_cmd_mbox(hr_dev, 0, 0, hr_qp->qpn, 2,
2545 HNS_ROCE_CMD_2RST_QP,
2546 HNS_ROCE_CMD_TIMEOUT_MSECS);
2547
2548 if (op[cur_state][new_state] == HNS_ROCE_CMD_2ERR_QP)
2549 return hns_roce_cmd_mbox(hr_dev, 0, 0, hr_qp->qpn, 2,
2550 HNS_ROCE_CMD_2ERR_QP,
2551 HNS_ROCE_CMD_TIMEOUT_MSECS);
2552
2553 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
2554 if (IS_ERR(mailbox))
2555 return PTR_ERR(mailbox);
2556
2557 memcpy(mailbox->buf, context, sizeof(*context));
2558
2559 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, hr_qp->qpn, 0,
2560 op[cur_state][new_state],
2561 HNS_ROCE_CMD_TIMEOUT_MSECS);
2562
2563 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
2564 return ret;
2565 }
2566
2567 static int hns_roce_v1_m_sqp(struct ib_qp *ibqp, const struct ib_qp_attr *attr,
2568 int attr_mask, enum ib_qp_state cur_state,
2569 enum ib_qp_state new_state)
2570 {
2571 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
2572 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
2573 struct hns_roce_sqp_context *context;
2574 struct device *dev = &hr_dev->pdev->dev;
2575 dma_addr_t dma_handle = 0;
2576 u32 __iomem *addr;
2577 int rq_pa_start;
2578 __le32 tmp;
2579 u32 reg_val;
2580 u64 *mtts;
2581
2582 context = kzalloc(sizeof(*context), GFP_KERNEL);
2583 if (!context)
2584 return -ENOMEM;
2585
2586 /* Search QP buf's MTTs */
2587 mtts = hns_roce_table_find(hr_dev, &hr_dev->mr_table.mtt_table,
2588 hr_qp->mtt.first_seg, &dma_handle);
2589 if (!mtts) {
2590 dev_err(dev, "qp buf pa find failed\n");
2591 goto out;
2592 }
2593
2594 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
2595 roce_set_field(context->qp1c_bytes_4,
2596 QP1C_BYTES_4_SQ_WQE_SHIFT_M,
2597 QP1C_BYTES_4_SQ_WQE_SHIFT_S,
2598 ilog2((unsigned int)hr_qp->sq.wqe_cnt));
2599 roce_set_field(context->qp1c_bytes_4,
2600 QP1C_BYTES_4_RQ_WQE_SHIFT_M,
2601 QP1C_BYTES_4_RQ_WQE_SHIFT_S,
2602 ilog2((unsigned int)hr_qp->rq.wqe_cnt));
2603 roce_set_field(context->qp1c_bytes_4, QP1C_BYTES_4_PD_M,
2604 QP1C_BYTES_4_PD_S, to_hr_pd(ibqp->pd)->pdn);
2605
2606 context->sq_rq_bt_l = cpu_to_le32((u32)(dma_handle));
2607 roce_set_field(context->qp1c_bytes_12,
2608 QP1C_BYTES_12_SQ_RQ_BT_H_M,
2609 QP1C_BYTES_12_SQ_RQ_BT_H_S,
2610 ((u32)(dma_handle >> 32)));
2611
2612 roce_set_field(context->qp1c_bytes_16, QP1C_BYTES_16_RQ_HEAD_M,
2613 QP1C_BYTES_16_RQ_HEAD_S, hr_qp->rq.head);
2614 roce_set_field(context->qp1c_bytes_16, QP1C_BYTES_16_PORT_NUM_M,
2615 QP1C_BYTES_16_PORT_NUM_S, hr_qp->phy_port);
2616 roce_set_bit(context->qp1c_bytes_16,
2617 QP1C_BYTES_16_SIGNALING_TYPE_S,
2618 hr_qp->sq_signal_bits);
2619 roce_set_bit(context->qp1c_bytes_16, QP1C_BYTES_16_RQ_BA_FLG_S,
2620 1);
2621 roce_set_bit(context->qp1c_bytes_16, QP1C_BYTES_16_SQ_BA_FLG_S,
2622 1);
2623 roce_set_bit(context->qp1c_bytes_16, QP1C_BYTES_16_QP1_ERR_S,
2624 0);
2625
2626 roce_set_field(context->qp1c_bytes_20, QP1C_BYTES_20_SQ_HEAD_M,
2627 QP1C_BYTES_20_SQ_HEAD_S, hr_qp->sq.head);
2628 roce_set_field(context->qp1c_bytes_20, QP1C_BYTES_20_PKEY_IDX_M,
2629 QP1C_BYTES_20_PKEY_IDX_S, attr->pkey_index);
2630
2631 rq_pa_start = (u32)hr_qp->rq.offset / PAGE_SIZE;
2632 context->cur_rq_wqe_ba_l =
2633 cpu_to_le32((u32)(mtts[rq_pa_start]));
2634
2635 roce_set_field(context->qp1c_bytes_28,
2636 QP1C_BYTES_28_CUR_RQ_WQE_BA_H_M,
2637 QP1C_BYTES_28_CUR_RQ_WQE_BA_H_S,
2638 (mtts[rq_pa_start]) >> 32);
2639 roce_set_field(context->qp1c_bytes_28,
2640 QP1C_BYTES_28_RQ_CUR_IDX_M,
2641 QP1C_BYTES_28_RQ_CUR_IDX_S, 0);
2642
2643 roce_set_field(context->qp1c_bytes_32,
2644 QP1C_BYTES_32_RX_CQ_NUM_M,
2645 QP1C_BYTES_32_RX_CQ_NUM_S,
2646 to_hr_cq(ibqp->recv_cq)->cqn);
2647 roce_set_field(context->qp1c_bytes_32,
2648 QP1C_BYTES_32_TX_CQ_NUM_M,
2649 QP1C_BYTES_32_TX_CQ_NUM_S,
2650 to_hr_cq(ibqp->send_cq)->cqn);
2651
2652 context->cur_sq_wqe_ba_l = cpu_to_le32((u32)mtts[0]);
2653
2654 roce_set_field(context->qp1c_bytes_40,
2655 QP1C_BYTES_40_CUR_SQ_WQE_BA_H_M,
2656 QP1C_BYTES_40_CUR_SQ_WQE_BA_H_S,
2657 (mtts[0]) >> 32);
2658 roce_set_field(context->qp1c_bytes_40,
2659 QP1C_BYTES_40_SQ_CUR_IDX_M,
2660 QP1C_BYTES_40_SQ_CUR_IDX_S, 0);
2661
2662 /* Copy context to QP1C register */
2663 addr = (u32 __iomem *)(hr_dev->reg_base +
2664 ROCEE_QP1C_CFG0_0_REG +
2665 hr_qp->phy_port * sizeof(*context));
2666
2667 writel(le32_to_cpu(context->qp1c_bytes_4), addr);
2668 writel(le32_to_cpu(context->sq_rq_bt_l), addr + 1);
2669 writel(le32_to_cpu(context->qp1c_bytes_12), addr + 2);
2670 writel(le32_to_cpu(context->qp1c_bytes_16), addr + 3);
2671 writel(le32_to_cpu(context->qp1c_bytes_20), addr + 4);
2672 writel(le32_to_cpu(context->cur_rq_wqe_ba_l), addr + 5);
2673 writel(le32_to_cpu(context->qp1c_bytes_28), addr + 6);
2674 writel(le32_to_cpu(context->qp1c_bytes_32), addr + 7);
2675 writel(le32_to_cpu(context->cur_sq_wqe_ba_l), addr + 8);
2676 writel(le32_to_cpu(context->qp1c_bytes_40), addr + 9);
2677 }
2678
2679 /* Modify QP1C status */
2680 reg_val = roce_read(hr_dev, ROCEE_QP1C_CFG0_0_REG +
2681 hr_qp->phy_port * sizeof(*context));
2682 tmp = cpu_to_le32(reg_val);
2683 roce_set_field(tmp, ROCEE_QP1C_CFG0_0_ROCEE_QP1C_QP_ST_M,
2684 ROCEE_QP1C_CFG0_0_ROCEE_QP1C_QP_ST_S, new_state);
2685 reg_val = le32_to_cpu(tmp);
2686 roce_write(hr_dev, ROCEE_QP1C_CFG0_0_REG +
2687 hr_qp->phy_port * sizeof(*context), reg_val);
2688
2689 hr_qp->state = new_state;
2690 if (new_state == IB_QPS_RESET) {
2691 hns_roce_v1_cq_clean(to_hr_cq(ibqp->recv_cq), hr_qp->qpn,
2692 ibqp->srq ? to_hr_srq(ibqp->srq) : NULL);
2693 if (ibqp->send_cq != ibqp->recv_cq)
2694 hns_roce_v1_cq_clean(to_hr_cq(ibqp->send_cq),
2695 hr_qp->qpn, NULL);
2696
2697 hr_qp->rq.head = 0;
2698 hr_qp->rq.tail = 0;
2699 hr_qp->sq.head = 0;
2700 hr_qp->sq.tail = 0;
2701 }
2702
2703 kfree(context);
2704 return 0;
2705
2706 out:
2707 kfree(context);
2708 return -EINVAL;
2709 }
2710
2711 static int hns_roce_v1_m_qp(struct ib_qp *ibqp, const struct ib_qp_attr *attr,
2712 int attr_mask, enum ib_qp_state cur_state,
2713 enum ib_qp_state new_state)
2714 {
2715 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
2716 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
2717 struct device *dev = &hr_dev->pdev->dev;
2718 struct hns_roce_qp_context *context;
2719 const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr);
2720 dma_addr_t dma_handle_2 = 0;
2721 dma_addr_t dma_handle = 0;
2722 __le32 doorbell[2] = {0};
2723 int rq_pa_start = 0;
2724 u64 *mtts_2 = NULL;
2725 int ret = -EINVAL;
2726 u64 *mtts = NULL;
2727 int port;
2728 u8 port_num;
2729 u8 *dmac;
2730 u8 *smac;
2731
2732 context = kzalloc(sizeof(*context), GFP_KERNEL);
2733 if (!context)
2734 return -ENOMEM;
2735
2736 /* Search qp buf's mtts */
2737 mtts = hns_roce_table_find(hr_dev, &hr_dev->mr_table.mtt_table,
2738 hr_qp->mtt.first_seg, &dma_handle);
2739 if (mtts == NULL) {
2740 dev_err(dev, "qp buf pa find failed\n");
2741 goto out;
2742 }
2743
2744 /* Search IRRL's mtts */
2745 mtts_2 = hns_roce_table_find(hr_dev, &hr_dev->qp_table.irrl_table,
2746 hr_qp->qpn, &dma_handle_2);
2747 if (mtts_2 == NULL) {
2748 dev_err(dev, "qp irrl_table find failed\n");
2749 goto out;
2750 }
2751
2752 /*
2753 * Reset to init
2754 * Mandatory param:
2755 * IB_QP_STATE | IB_QP_PKEY_INDEX | IB_QP_PORT | IB_QP_ACCESS_FLAGS
2756 * Optional param: NA
2757 */
2758 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
2759 roce_set_field(context->qpc_bytes_4,
2760 QP_CONTEXT_QPC_BYTES_4_TRANSPORT_SERVICE_TYPE_M,
2761 QP_CONTEXT_QPC_BYTES_4_TRANSPORT_SERVICE_TYPE_S,
2762 to_hr_qp_type(hr_qp->ibqp.qp_type));
2763
2764 roce_set_bit(context->qpc_bytes_4,
2765 QP_CONTEXT_QPC_BYTE_4_ENABLE_FPMR_S, 0);
2766 roce_set_bit(context->qpc_bytes_4,
2767 QP_CONTEXT_QPC_BYTE_4_RDMA_READ_ENABLE_S,
2768 !!(attr->qp_access_flags & IB_ACCESS_REMOTE_READ));
2769 roce_set_bit(context->qpc_bytes_4,
2770 QP_CONTEXT_QPC_BYTE_4_RDMA_WRITE_ENABLE_S,
2771 !!(attr->qp_access_flags & IB_ACCESS_REMOTE_WRITE)
2772 );
2773 roce_set_bit(context->qpc_bytes_4,
2774 QP_CONTEXT_QPC_BYTE_4_ATOMIC_OPERATION_ENABLE_S,
2775 !!(attr->qp_access_flags & IB_ACCESS_REMOTE_ATOMIC)
2776 );
2777 roce_set_bit(context->qpc_bytes_4,
2778 QP_CONTEXT_QPC_BYTE_4_RDMAR_USE_S, 1);
2779 roce_set_field(context->qpc_bytes_4,
2780 QP_CONTEXT_QPC_BYTES_4_SQ_WQE_SHIFT_M,
2781 QP_CONTEXT_QPC_BYTES_4_SQ_WQE_SHIFT_S,
2782 ilog2((unsigned int)hr_qp->sq.wqe_cnt));
2783 roce_set_field(context->qpc_bytes_4,
2784 QP_CONTEXT_QPC_BYTES_4_RQ_WQE_SHIFT_M,
2785 QP_CONTEXT_QPC_BYTES_4_RQ_WQE_SHIFT_S,
2786 ilog2((unsigned int)hr_qp->rq.wqe_cnt));
2787 roce_set_field(context->qpc_bytes_4,
2788 QP_CONTEXT_QPC_BYTES_4_PD_M,
2789 QP_CONTEXT_QPC_BYTES_4_PD_S,
2790 to_hr_pd(ibqp->pd)->pdn);
2791 hr_qp->access_flags = attr->qp_access_flags;
2792 roce_set_field(context->qpc_bytes_8,
2793 QP_CONTEXT_QPC_BYTES_8_TX_COMPLETION_M,
2794 QP_CONTEXT_QPC_BYTES_8_TX_COMPLETION_S,
2795 to_hr_cq(ibqp->send_cq)->cqn);
2796 roce_set_field(context->qpc_bytes_8,
2797 QP_CONTEXT_QPC_BYTES_8_RX_COMPLETION_M,
2798 QP_CONTEXT_QPC_BYTES_8_RX_COMPLETION_S,
2799 to_hr_cq(ibqp->recv_cq)->cqn);
2800
2801 if (ibqp->srq)
2802 roce_set_field(context->qpc_bytes_12,
2803 QP_CONTEXT_QPC_BYTES_12_SRQ_NUMBER_M,
2804 QP_CONTEXT_QPC_BYTES_12_SRQ_NUMBER_S,
2805 to_hr_srq(ibqp->srq)->srqn);
2806
2807 roce_set_field(context->qpc_bytes_12,
2808 QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_M,
2809 QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_S,
2810 attr->pkey_index);
2811 hr_qp->pkey_index = attr->pkey_index;
2812 roce_set_field(context->qpc_bytes_16,
2813 QP_CONTEXT_QPC_BYTES_16_QP_NUM_M,
2814 QP_CONTEXT_QPC_BYTES_16_QP_NUM_S, hr_qp->qpn);
2815
2816 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) {
2817 roce_set_field(context->qpc_bytes_4,
2818 QP_CONTEXT_QPC_BYTES_4_TRANSPORT_SERVICE_TYPE_M,
2819 QP_CONTEXT_QPC_BYTES_4_TRANSPORT_SERVICE_TYPE_S,
2820 to_hr_qp_type(hr_qp->ibqp.qp_type));
2821 roce_set_bit(context->qpc_bytes_4,
2822 QP_CONTEXT_QPC_BYTE_4_ENABLE_FPMR_S, 0);
2823 if (attr_mask & IB_QP_ACCESS_FLAGS) {
2824 roce_set_bit(context->qpc_bytes_4,
2825 QP_CONTEXT_QPC_BYTE_4_RDMA_READ_ENABLE_S,
2826 !!(attr->qp_access_flags &
2827 IB_ACCESS_REMOTE_READ));
2828 roce_set_bit(context->qpc_bytes_4,
2829 QP_CONTEXT_QPC_BYTE_4_RDMA_WRITE_ENABLE_S,
2830 !!(attr->qp_access_flags &
2831 IB_ACCESS_REMOTE_WRITE));
2832 } else {
2833 roce_set_bit(context->qpc_bytes_4,
2834 QP_CONTEXT_QPC_BYTE_4_RDMA_READ_ENABLE_S,
2835 !!(hr_qp->access_flags &
2836 IB_ACCESS_REMOTE_READ));
2837 roce_set_bit(context->qpc_bytes_4,
2838 QP_CONTEXT_QPC_BYTE_4_RDMA_WRITE_ENABLE_S,
2839 !!(hr_qp->access_flags &
2840 IB_ACCESS_REMOTE_WRITE));
2841 }
2842
2843 roce_set_bit(context->qpc_bytes_4,
2844 QP_CONTEXT_QPC_BYTE_4_RDMAR_USE_S, 1);
2845 roce_set_field(context->qpc_bytes_4,
2846 QP_CONTEXT_QPC_BYTES_4_SQ_WQE_SHIFT_M,
2847 QP_CONTEXT_QPC_BYTES_4_SQ_WQE_SHIFT_S,
2848 ilog2((unsigned int)hr_qp->sq.wqe_cnt));
2849 roce_set_field(context->qpc_bytes_4,
2850 QP_CONTEXT_QPC_BYTES_4_RQ_WQE_SHIFT_M,
2851 QP_CONTEXT_QPC_BYTES_4_RQ_WQE_SHIFT_S,
2852 ilog2((unsigned int)hr_qp->rq.wqe_cnt));
2853 roce_set_field(context->qpc_bytes_4,
2854 QP_CONTEXT_QPC_BYTES_4_PD_M,
2855 QP_CONTEXT_QPC_BYTES_4_PD_S,
2856 to_hr_pd(ibqp->pd)->pdn);
2857
2858 roce_set_field(context->qpc_bytes_8,
2859 QP_CONTEXT_QPC_BYTES_8_TX_COMPLETION_M,
2860 QP_CONTEXT_QPC_BYTES_8_TX_COMPLETION_S,
2861 to_hr_cq(ibqp->send_cq)->cqn);
2862 roce_set_field(context->qpc_bytes_8,
2863 QP_CONTEXT_QPC_BYTES_8_RX_COMPLETION_M,
2864 QP_CONTEXT_QPC_BYTES_8_RX_COMPLETION_S,
2865 to_hr_cq(ibqp->recv_cq)->cqn);
2866
2867 if (ibqp->srq)
2868 roce_set_field(context->qpc_bytes_12,
2869 QP_CONTEXT_QPC_BYTES_12_SRQ_NUMBER_M,
2870 QP_CONTEXT_QPC_BYTES_12_SRQ_NUMBER_S,
2871 to_hr_srq(ibqp->srq)->srqn);
2872 if (attr_mask & IB_QP_PKEY_INDEX)
2873 roce_set_field(context->qpc_bytes_12,
2874 QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_M,
2875 QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_S,
2876 attr->pkey_index);
2877 else
2878 roce_set_field(context->qpc_bytes_12,
2879 QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_M,
2880 QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_S,
2881 hr_qp->pkey_index);
2882
2883 roce_set_field(context->qpc_bytes_16,
2884 QP_CONTEXT_QPC_BYTES_16_QP_NUM_M,
2885 QP_CONTEXT_QPC_BYTES_16_QP_NUM_S, hr_qp->qpn);
2886 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
2887 if ((attr_mask & IB_QP_ALT_PATH) ||
2888 (attr_mask & IB_QP_ACCESS_FLAGS) ||
2889 (attr_mask & IB_QP_PKEY_INDEX) ||
2890 (attr_mask & IB_QP_QKEY)) {
2891 dev_err(dev, "INIT2RTR attr_mask error\n");
2892 goto out;
2893 }
2894
2895 dmac = (u8 *)attr->ah_attr.roce.dmac;
2896
2897 context->sq_rq_bt_l = cpu_to_le32((u32)(dma_handle));
2898 roce_set_field(context->qpc_bytes_24,
2899 QP_CONTEXT_QPC_BYTES_24_SQ_RQ_BT_H_M,
2900 QP_CONTEXT_QPC_BYTES_24_SQ_RQ_BT_H_S,
2901 ((u32)(dma_handle >> 32)));
2902 roce_set_bit(context->qpc_bytes_24,
2903 QP_CONTEXT_QPC_BYTE_24_REMOTE_ENABLE_E2E_CREDITS_S,
2904 1);
2905 roce_set_field(context->qpc_bytes_24,
2906 QP_CONTEXT_QPC_BYTES_24_MINIMUM_RNR_NAK_TIMER_M,
2907 QP_CONTEXT_QPC_BYTES_24_MINIMUM_RNR_NAK_TIMER_S,
2908 attr->min_rnr_timer);
2909 context->irrl_ba_l = cpu_to_le32((u32)(dma_handle_2));
2910 roce_set_field(context->qpc_bytes_32,
2911 QP_CONTEXT_QPC_BYTES_32_IRRL_BA_H_M,
2912 QP_CONTEXT_QPC_BYTES_32_IRRL_BA_H_S,
2913 ((u32)(dma_handle_2 >> 32)) &
2914 QP_CONTEXT_QPC_BYTES_32_IRRL_BA_H_M);
2915 roce_set_field(context->qpc_bytes_32,
2916 QP_CONTEXT_QPC_BYTES_32_MIG_STATE_M,
2917 QP_CONTEXT_QPC_BYTES_32_MIG_STATE_S, 0);
2918 roce_set_bit(context->qpc_bytes_32,
2919 QP_CONTEXT_QPC_BYTE_32_LOCAL_ENABLE_E2E_CREDITS_S,
2920 1);
2921 roce_set_bit(context->qpc_bytes_32,
2922 QP_CONTEXT_QPC_BYTE_32_SIGNALING_TYPE_S,
2923 hr_qp->sq_signal_bits);
2924
2925 port = (attr_mask & IB_QP_PORT) ? (attr->port_num - 1) :
2926 hr_qp->port;
2927 smac = (u8 *)hr_dev->dev_addr[port];
2928 /* when dmac equals smac or loop_idc is 1, it should loopback */
2929 if (ether_addr_equal_unaligned(dmac, smac) ||
2930 hr_dev->loop_idc == 0x1)
2931 roce_set_bit(context->qpc_bytes_32,
2932 QP_CONTEXT_QPC_BYTE_32_LOOPBACK_INDICATOR_S, 1);
2933
2934 roce_set_bit(context->qpc_bytes_32,
2935 QP_CONTEXT_QPC_BYTE_32_GLOBAL_HEADER_S,
2936 rdma_ah_get_ah_flags(&attr->ah_attr));
2937 roce_set_field(context->qpc_bytes_32,
2938 QP_CONTEXT_QPC_BYTES_32_RESPONDER_RESOURCES_M,
2939 QP_CONTEXT_QPC_BYTES_32_RESPONDER_RESOURCES_S,
2940 ilog2((unsigned int)attr->max_dest_rd_atomic));
2941
2942 if (attr_mask & IB_QP_DEST_QPN)
2943 roce_set_field(context->qpc_bytes_36,
2944 QP_CONTEXT_QPC_BYTES_36_DEST_QP_M,
2945 QP_CONTEXT_QPC_BYTES_36_DEST_QP_S,
2946 attr->dest_qp_num);
2947
2948 /* Configure GID index */
2949 port_num = rdma_ah_get_port_num(&attr->ah_attr);
2950 roce_set_field(context->qpc_bytes_36,
2951 QP_CONTEXT_QPC_BYTES_36_SGID_INDEX_M,
2952 QP_CONTEXT_QPC_BYTES_36_SGID_INDEX_S,
2953 hns_get_gid_index(hr_dev,
2954 port_num - 1,
2955 grh->sgid_index));
2956
2957 memcpy(&(context->dmac_l), dmac, 4);
2958
2959 roce_set_field(context->qpc_bytes_44,
2960 QP_CONTEXT_QPC_BYTES_44_DMAC_H_M,
2961 QP_CONTEXT_QPC_BYTES_44_DMAC_H_S,
2962 *((u16 *)(&dmac[4])));
2963 roce_set_field(context->qpc_bytes_44,
2964 QP_CONTEXT_QPC_BYTES_44_MAXIMUM_STATIC_RATE_M,
2965 QP_CONTEXT_QPC_BYTES_44_MAXIMUM_STATIC_RATE_S,
2966 rdma_ah_get_static_rate(&attr->ah_attr));
2967 roce_set_field(context->qpc_bytes_44,
2968 QP_CONTEXT_QPC_BYTES_44_HOPLMT_M,
2969 QP_CONTEXT_QPC_BYTES_44_HOPLMT_S,
2970 grh->hop_limit);
2971
2972 roce_set_field(context->qpc_bytes_48,
2973 QP_CONTEXT_QPC_BYTES_48_FLOWLABEL_M,
2974 QP_CONTEXT_QPC_BYTES_48_FLOWLABEL_S,
2975 grh->flow_label);
2976 roce_set_field(context->qpc_bytes_48,
2977 QP_CONTEXT_QPC_BYTES_48_TCLASS_M,
2978 QP_CONTEXT_QPC_BYTES_48_TCLASS_S,
2979 grh->traffic_class);
2980 roce_set_field(context->qpc_bytes_48,
2981 QP_CONTEXT_QPC_BYTES_48_MTU_M,
2982 QP_CONTEXT_QPC_BYTES_48_MTU_S, attr->path_mtu);
2983
2984 memcpy(context->dgid, grh->dgid.raw,
2985 sizeof(grh->dgid.raw));
2986
2987 dev_dbg(dev, "dmac:%x :%lx\n", context->dmac_l,
2988 roce_get_field(context->qpc_bytes_44,
2989 QP_CONTEXT_QPC_BYTES_44_DMAC_H_M,
2990 QP_CONTEXT_QPC_BYTES_44_DMAC_H_S));
2991
2992 roce_set_field(context->qpc_bytes_68,
2993 QP_CONTEXT_QPC_BYTES_68_RQ_HEAD_M,
2994 QP_CONTEXT_QPC_BYTES_68_RQ_HEAD_S,
2995 hr_qp->rq.head);
2996 roce_set_field(context->qpc_bytes_68,
2997 QP_CONTEXT_QPC_BYTES_68_RQ_CUR_INDEX_M,
2998 QP_CONTEXT_QPC_BYTES_68_RQ_CUR_INDEX_S, 0);
2999
3000 rq_pa_start = (u32)hr_qp->rq.offset / PAGE_SIZE;
3001 context->cur_rq_wqe_ba_l =
3002 cpu_to_le32((u32)(mtts[rq_pa_start]));
3003
3004 roce_set_field(context->qpc_bytes_76,
3005 QP_CONTEXT_QPC_BYTES_76_CUR_RQ_WQE_BA_H_M,
3006 QP_CONTEXT_QPC_BYTES_76_CUR_RQ_WQE_BA_H_S,
3007 mtts[rq_pa_start] >> 32);
3008 roce_set_field(context->qpc_bytes_76,
3009 QP_CONTEXT_QPC_BYTES_76_RX_REQ_MSN_M,
3010 QP_CONTEXT_QPC_BYTES_76_RX_REQ_MSN_S, 0);
3011
3012 context->rx_rnr_time = 0;
3013
3014 roce_set_field(context->qpc_bytes_84,
3015 QP_CONTEXT_QPC_BYTES_84_LAST_ACK_PSN_M,
3016 QP_CONTEXT_QPC_BYTES_84_LAST_ACK_PSN_S,
3017 attr->rq_psn - 1);
3018 roce_set_field(context->qpc_bytes_84,
3019 QP_CONTEXT_QPC_BYTES_84_TRRL_HEAD_M,
3020 QP_CONTEXT_QPC_BYTES_84_TRRL_HEAD_S, 0);
3021
3022 roce_set_field(context->qpc_bytes_88,
3023 QP_CONTEXT_QPC_BYTES_88_RX_REQ_EPSN_M,
3024 QP_CONTEXT_QPC_BYTES_88_RX_REQ_EPSN_S,
3025 attr->rq_psn);
3026 roce_set_bit(context->qpc_bytes_88,
3027 QP_CONTEXT_QPC_BYTES_88_RX_REQ_PSN_ERR_FLAG_S, 0);
3028 roce_set_bit(context->qpc_bytes_88,
3029 QP_CONTEXT_QPC_BYTES_88_RX_LAST_OPCODE_FLG_S, 0);
3030 roce_set_field(context->qpc_bytes_88,
3031 QP_CONTEXT_QPC_BYTES_88_RQ_REQ_LAST_OPERATION_TYPE_M,
3032 QP_CONTEXT_QPC_BYTES_88_RQ_REQ_LAST_OPERATION_TYPE_S,
3033 0);
3034 roce_set_field(context->qpc_bytes_88,
3035 QP_CONTEXT_QPC_BYTES_88_RQ_REQ_RDMA_WR_FLAG_M,
3036 QP_CONTEXT_QPC_BYTES_88_RQ_REQ_RDMA_WR_FLAG_S,
3037 0);
3038
3039 context->dma_length = 0;
3040 context->r_key = 0;
3041 context->va_l = 0;
3042 context->va_h = 0;
3043
3044 roce_set_field(context->qpc_bytes_108,
3045 QP_CONTEXT_QPC_BYTES_108_TRRL_SDB_PSN_M,
3046 QP_CONTEXT_QPC_BYTES_108_TRRL_SDB_PSN_S, 0);
3047 roce_set_bit(context->qpc_bytes_108,
3048 QP_CONTEXT_QPC_BYTES_108_TRRL_SDB_PSN_FLG_S, 0);
3049 roce_set_bit(context->qpc_bytes_108,
3050 QP_CONTEXT_QPC_BYTES_108_TRRL_TDB_PSN_FLG_S, 0);
3051
3052 roce_set_field(context->qpc_bytes_112,
3053 QP_CONTEXT_QPC_BYTES_112_TRRL_TDB_PSN_M,
3054 QP_CONTEXT_QPC_BYTES_112_TRRL_TDB_PSN_S, 0);
3055 roce_set_field(context->qpc_bytes_112,
3056 QP_CONTEXT_QPC_BYTES_112_TRRL_TAIL_M,
3057 QP_CONTEXT_QPC_BYTES_112_TRRL_TAIL_S, 0);
3058
3059 /* For chip resp ack */
3060 roce_set_field(context->qpc_bytes_156,
3061 QP_CONTEXT_QPC_BYTES_156_PORT_NUM_M,
3062 QP_CONTEXT_QPC_BYTES_156_PORT_NUM_S,
3063 hr_qp->phy_port);
3064 roce_set_field(context->qpc_bytes_156,
3065 QP_CONTEXT_QPC_BYTES_156_SL_M,
3066 QP_CONTEXT_QPC_BYTES_156_SL_S,
3067 rdma_ah_get_sl(&attr->ah_attr));
3068 hr_qp->sl = rdma_ah_get_sl(&attr->ah_attr);
3069 } else if (cur_state == IB_QPS_RTR &&
3070 new_state == IB_QPS_RTS) {
3071 /* If exist optional param, return error */
3072 if ((attr_mask & IB_QP_ALT_PATH) ||
3073 (attr_mask & IB_QP_ACCESS_FLAGS) ||
3074 (attr_mask & IB_QP_QKEY) ||
3075 (attr_mask & IB_QP_PATH_MIG_STATE) ||
3076 (attr_mask & IB_QP_CUR_STATE) ||
3077 (attr_mask & IB_QP_MIN_RNR_TIMER)) {
3078 dev_err(dev, "RTR2RTS attr_mask error\n");
3079 goto out;
3080 }
3081
3082 context->rx_cur_sq_wqe_ba_l = cpu_to_le32((u32)(mtts[0]));
3083
3084 roce_set_field(context->qpc_bytes_120,
3085 QP_CONTEXT_QPC_BYTES_120_RX_CUR_SQ_WQE_BA_H_M,
3086 QP_CONTEXT_QPC_BYTES_120_RX_CUR_SQ_WQE_BA_H_S,
3087 (mtts[0]) >> 32);
3088
3089 roce_set_field(context->qpc_bytes_124,
3090 QP_CONTEXT_QPC_BYTES_124_RX_ACK_MSN_M,
3091 QP_CONTEXT_QPC_BYTES_124_RX_ACK_MSN_S, 0);
3092 roce_set_field(context->qpc_bytes_124,
3093 QP_CONTEXT_QPC_BYTES_124_IRRL_MSG_IDX_M,
3094 QP_CONTEXT_QPC_BYTES_124_IRRL_MSG_IDX_S, 0);
3095
3096 roce_set_field(context->qpc_bytes_128,
3097 QP_CONTEXT_QPC_BYTES_128_RX_ACK_EPSN_M,
3098 QP_CONTEXT_QPC_BYTES_128_RX_ACK_EPSN_S,
3099 attr->sq_psn);
3100 roce_set_bit(context->qpc_bytes_128,
3101 QP_CONTEXT_QPC_BYTES_128_RX_ACK_PSN_ERR_FLG_S, 0);
3102 roce_set_field(context->qpc_bytes_128,
3103 QP_CONTEXT_QPC_BYTES_128_ACK_LAST_OPERATION_TYPE_M,
3104 QP_CONTEXT_QPC_BYTES_128_ACK_LAST_OPERATION_TYPE_S,
3105 0);
3106 roce_set_bit(context->qpc_bytes_128,
3107 QP_CONTEXT_QPC_BYTES_128_IRRL_PSN_VLD_FLG_S, 0);
3108
3109 roce_set_field(context->qpc_bytes_132,
3110 QP_CONTEXT_QPC_BYTES_132_IRRL_PSN_M,
3111 QP_CONTEXT_QPC_BYTES_132_IRRL_PSN_S, 0);
3112 roce_set_field(context->qpc_bytes_132,
3113 QP_CONTEXT_QPC_BYTES_132_IRRL_TAIL_M,
3114 QP_CONTEXT_QPC_BYTES_132_IRRL_TAIL_S, 0);
3115
3116 roce_set_field(context->qpc_bytes_136,
3117 QP_CONTEXT_QPC_BYTES_136_RETRY_MSG_PSN_M,
3118 QP_CONTEXT_QPC_BYTES_136_RETRY_MSG_PSN_S,
3119 attr->sq_psn);
3120 roce_set_field(context->qpc_bytes_136,
3121 QP_CONTEXT_QPC_BYTES_136_RETRY_MSG_FPKT_PSN_L_M,
3122 QP_CONTEXT_QPC_BYTES_136_RETRY_MSG_FPKT_PSN_L_S,
3123 attr->sq_psn);
3124
3125 roce_set_field(context->qpc_bytes_140,
3126 QP_CONTEXT_QPC_BYTES_140_RETRY_MSG_FPKT_PSN_H_M,
3127 QP_CONTEXT_QPC_BYTES_140_RETRY_MSG_FPKT_PSN_H_S,
3128 (attr->sq_psn >> SQ_PSN_SHIFT));
3129 roce_set_field(context->qpc_bytes_140,
3130 QP_CONTEXT_QPC_BYTES_140_RETRY_MSG_MSN_M,
3131 QP_CONTEXT_QPC_BYTES_140_RETRY_MSG_MSN_S, 0);
3132 roce_set_bit(context->qpc_bytes_140,
3133 QP_CONTEXT_QPC_BYTES_140_RNR_RETRY_FLG_S, 0);
3134
3135 roce_set_field(context->qpc_bytes_148,
3136 QP_CONTEXT_QPC_BYTES_148_CHECK_FLAG_M,
3137 QP_CONTEXT_QPC_BYTES_148_CHECK_FLAG_S, 0);
3138 roce_set_field(context->qpc_bytes_148,
3139 QP_CONTEXT_QPC_BYTES_148_RETRY_COUNT_M,
3140 QP_CONTEXT_QPC_BYTES_148_RETRY_COUNT_S,
3141 attr->retry_cnt);
3142 roce_set_field(context->qpc_bytes_148,
3143 QP_CONTEXT_QPC_BYTES_148_RNR_RETRY_COUNT_M,
3144 QP_CONTEXT_QPC_BYTES_148_RNR_RETRY_COUNT_S,
3145 attr->rnr_retry);
3146 roce_set_field(context->qpc_bytes_148,
3147 QP_CONTEXT_QPC_BYTES_148_LSN_M,
3148 QP_CONTEXT_QPC_BYTES_148_LSN_S, 0x100);
3149
3150 context->rnr_retry = 0;
3151
3152 roce_set_field(context->qpc_bytes_156,
3153 QP_CONTEXT_QPC_BYTES_156_RETRY_COUNT_INIT_M,
3154 QP_CONTEXT_QPC_BYTES_156_RETRY_COUNT_INIT_S,
3155 attr->retry_cnt);
3156 if (attr->timeout < 0x12) {
3157 dev_info(dev, "ack timeout value(0x%x) must bigger than 0x12.\n",
3158 attr->timeout);
3159 roce_set_field(context->qpc_bytes_156,
3160 QP_CONTEXT_QPC_BYTES_156_ACK_TIMEOUT_M,
3161 QP_CONTEXT_QPC_BYTES_156_ACK_TIMEOUT_S,
3162 0x12);
3163 } else {
3164 roce_set_field(context->qpc_bytes_156,
3165 QP_CONTEXT_QPC_BYTES_156_ACK_TIMEOUT_M,
3166 QP_CONTEXT_QPC_BYTES_156_ACK_TIMEOUT_S,
3167 attr->timeout);
3168 }
3169 roce_set_field(context->qpc_bytes_156,
3170 QP_CONTEXT_QPC_BYTES_156_RNR_RETRY_COUNT_INIT_M,
3171 QP_CONTEXT_QPC_BYTES_156_RNR_RETRY_COUNT_INIT_S,
3172 attr->rnr_retry);
3173 roce_set_field(context->qpc_bytes_156,
3174 QP_CONTEXT_QPC_BYTES_156_PORT_NUM_M,
3175 QP_CONTEXT_QPC_BYTES_156_PORT_NUM_S,
3176 hr_qp->phy_port);
3177 roce_set_field(context->qpc_bytes_156,
3178 QP_CONTEXT_QPC_BYTES_156_SL_M,
3179 QP_CONTEXT_QPC_BYTES_156_SL_S,
3180 rdma_ah_get_sl(&attr->ah_attr));
3181 hr_qp->sl = rdma_ah_get_sl(&attr->ah_attr);
3182 roce_set_field(context->qpc_bytes_156,
3183 QP_CONTEXT_QPC_BYTES_156_INITIATOR_DEPTH_M,
3184 QP_CONTEXT_QPC_BYTES_156_INITIATOR_DEPTH_S,
3185 ilog2((unsigned int)attr->max_rd_atomic));
3186 roce_set_field(context->qpc_bytes_156,
3187 QP_CONTEXT_QPC_BYTES_156_ACK_REQ_IND_M,
3188 QP_CONTEXT_QPC_BYTES_156_ACK_REQ_IND_S, 0);
3189 context->pkt_use_len = 0;
3190
3191 roce_set_field(context->qpc_bytes_164,
3192 QP_CONTEXT_QPC_BYTES_164_SQ_PSN_M,
3193 QP_CONTEXT_QPC_BYTES_164_SQ_PSN_S, attr->sq_psn);
3194 roce_set_field(context->qpc_bytes_164,
3195 QP_CONTEXT_QPC_BYTES_164_IRRL_HEAD_M,
3196 QP_CONTEXT_QPC_BYTES_164_IRRL_HEAD_S, 0);
3197
3198 roce_set_field(context->qpc_bytes_168,
3199 QP_CONTEXT_QPC_BYTES_168_RETRY_SQ_PSN_M,
3200 QP_CONTEXT_QPC_BYTES_168_RETRY_SQ_PSN_S,
3201 attr->sq_psn);
3202 roce_set_field(context->qpc_bytes_168,
3203 QP_CONTEXT_QPC_BYTES_168_SGE_USE_FLA_M,
3204 QP_CONTEXT_QPC_BYTES_168_SGE_USE_FLA_S, 0);
3205 roce_set_field(context->qpc_bytes_168,
3206 QP_CONTEXT_QPC_BYTES_168_DB_TYPE_M,
3207 QP_CONTEXT_QPC_BYTES_168_DB_TYPE_S, 0);
3208 roce_set_bit(context->qpc_bytes_168,
3209 QP_CONTEXT_QPC_BYTES_168_MSG_LP_IND_S, 0);
3210 roce_set_bit(context->qpc_bytes_168,
3211 QP_CONTEXT_QPC_BYTES_168_CSDB_LP_IND_S, 0);
3212 roce_set_bit(context->qpc_bytes_168,
3213 QP_CONTEXT_QPC_BYTES_168_QP_ERR_FLG_S, 0);
3214 context->sge_use_len = 0;
3215
3216 roce_set_field(context->qpc_bytes_176,
3217 QP_CONTEXT_QPC_BYTES_176_DB_CUR_INDEX_M,
3218 QP_CONTEXT_QPC_BYTES_176_DB_CUR_INDEX_S, 0);
3219 roce_set_field(context->qpc_bytes_176,
3220 QP_CONTEXT_QPC_BYTES_176_RETRY_DB_CUR_INDEX_M,
3221 QP_CONTEXT_QPC_BYTES_176_RETRY_DB_CUR_INDEX_S,
3222 0);
3223 roce_set_field(context->qpc_bytes_180,
3224 QP_CONTEXT_QPC_BYTES_180_SQ_CUR_INDEX_M,
3225 QP_CONTEXT_QPC_BYTES_180_SQ_CUR_INDEX_S, 0);
3226 roce_set_field(context->qpc_bytes_180,
3227 QP_CONTEXT_QPC_BYTES_180_SQ_HEAD_M,
3228 QP_CONTEXT_QPC_BYTES_180_SQ_HEAD_S, 0);
3229
3230 context->tx_cur_sq_wqe_ba_l = cpu_to_le32((u32)(mtts[0]));
3231
3232 roce_set_field(context->qpc_bytes_188,
3233 QP_CONTEXT_QPC_BYTES_188_TX_CUR_SQ_WQE_BA_H_M,
3234 QP_CONTEXT_QPC_BYTES_188_TX_CUR_SQ_WQE_BA_H_S,
3235 (mtts[0]) >> 32);
3236 roce_set_bit(context->qpc_bytes_188,
3237 QP_CONTEXT_QPC_BYTES_188_PKT_RETRY_FLG_S, 0);
3238 roce_set_field(context->qpc_bytes_188,
3239 QP_CONTEXT_QPC_BYTES_188_TX_RETRY_CUR_INDEX_M,
3240 QP_CONTEXT_QPC_BYTES_188_TX_RETRY_CUR_INDEX_S,
3241 0);
3242 } else if (!((cur_state == IB_QPS_INIT && new_state == IB_QPS_RESET) ||
3243 (cur_state == IB_QPS_INIT && new_state == IB_QPS_ERR) ||
3244 (cur_state == IB_QPS_RTR && new_state == IB_QPS_RESET) ||
3245 (cur_state == IB_QPS_RTR && new_state == IB_QPS_ERR) ||
3246 (cur_state == IB_QPS_RTS && new_state == IB_QPS_RESET) ||
3247 (cur_state == IB_QPS_RTS && new_state == IB_QPS_ERR) ||
3248 (cur_state == IB_QPS_ERR && new_state == IB_QPS_RESET) ||
3249 (cur_state == IB_QPS_ERR && new_state == IB_QPS_ERR))) {
3250 dev_err(dev, "not support this status migration\n");
3251 goto out;
3252 }
3253
3254 /* Every status migrate must change state */
3255 roce_set_field(context->qpc_bytes_144,
3256 QP_CONTEXT_QPC_BYTES_144_QP_STATE_M,
3257 QP_CONTEXT_QPC_BYTES_144_QP_STATE_S, new_state);
3258
3259 /* SW pass context to HW */
3260 ret = hns_roce_v1_qp_modify(hr_dev, &hr_qp->mtt,
3261 to_hns_roce_state(cur_state),
3262 to_hns_roce_state(new_state), context,
3263 hr_qp);
3264 if (ret) {
3265 dev_err(dev, "hns_roce_qp_modify failed\n");
3266 goto out;
3267 }
3268
3269 /*
3270 * Use rst2init to instead of init2init with drv,
3271 * need to hw to flash RQ HEAD by DB again
3272 */
3273 if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) {
3274 /* Memory barrier */
3275 wmb();
3276
3277 roce_set_field(doorbell[0], RQ_DOORBELL_U32_4_RQ_HEAD_M,
3278 RQ_DOORBELL_U32_4_RQ_HEAD_S, hr_qp->rq.head);
3279 roce_set_field(doorbell[1], RQ_DOORBELL_U32_8_QPN_M,
3280 RQ_DOORBELL_U32_8_QPN_S, hr_qp->qpn);
3281 roce_set_field(doorbell[1], RQ_DOORBELL_U32_8_CMD_M,
3282 RQ_DOORBELL_U32_8_CMD_S, 1);
3283 roce_set_bit(doorbell[1], RQ_DOORBELL_U32_8_HW_SYNC_S, 1);
3284
3285 if (ibqp->uobject) {
3286 hr_qp->rq.db_reg_l = hr_dev->reg_base +
3287 hr_dev->odb_offset +
3288 DB_REG_OFFSET * hr_dev->priv_uar.index;
3289 }
3290
3291 hns_roce_write64_k(doorbell, hr_qp->rq.db_reg_l);
3292 }
3293
3294 hr_qp->state = new_state;
3295
3296 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
3297 hr_qp->resp_depth = attr->max_dest_rd_atomic;
3298 if (attr_mask & IB_QP_PORT) {
3299 hr_qp->port = attr->port_num - 1;
3300 hr_qp->phy_port = hr_dev->iboe.phy_port[hr_qp->port];
3301 }
3302
3303 if (new_state == IB_QPS_RESET && !ibqp->uobject) {
3304 hns_roce_v1_cq_clean(to_hr_cq(ibqp->recv_cq), hr_qp->qpn,
3305 ibqp->srq ? to_hr_srq(ibqp->srq) : NULL);
3306 if (ibqp->send_cq != ibqp->recv_cq)
3307 hns_roce_v1_cq_clean(to_hr_cq(ibqp->send_cq),
3308 hr_qp->qpn, NULL);
3309
3310 hr_qp->rq.head = 0;
3311 hr_qp->rq.tail = 0;
3312 hr_qp->sq.head = 0;
3313 hr_qp->sq.tail = 0;
3314 }
3315 out:
3316 kfree(context);
3317 return ret;
3318 }
3319
3320 static int hns_roce_v1_modify_qp(struct ib_qp *ibqp,
3321 const struct ib_qp_attr *attr, int attr_mask,
3322 enum ib_qp_state cur_state,
3323 enum ib_qp_state new_state)
3324 {
3325
3326 if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI)
3327 return hns_roce_v1_m_sqp(ibqp, attr, attr_mask, cur_state,
3328 new_state);
3329 else
3330 return hns_roce_v1_m_qp(ibqp, attr, attr_mask, cur_state,
3331 new_state);
3332 }
3333
3334 static enum ib_qp_state to_ib_qp_state(enum hns_roce_qp_state state)
3335 {
3336 switch (state) {
3337 case HNS_ROCE_QP_STATE_RST:
3338 return IB_QPS_RESET;
3339 case HNS_ROCE_QP_STATE_INIT:
3340 return IB_QPS_INIT;
3341 case HNS_ROCE_QP_STATE_RTR:
3342 return IB_QPS_RTR;
3343 case HNS_ROCE_QP_STATE_RTS:
3344 return IB_QPS_RTS;
3345 case HNS_ROCE_QP_STATE_SQD:
3346 return IB_QPS_SQD;
3347 case HNS_ROCE_QP_STATE_ERR:
3348 return IB_QPS_ERR;
3349 default:
3350 return IB_QPS_ERR;
3351 }
3352 }
3353
3354 static int hns_roce_v1_query_qpc(struct hns_roce_dev *hr_dev,
3355 struct hns_roce_qp *hr_qp,
3356 struct hns_roce_qp_context *hr_context)
3357 {
3358 struct hns_roce_cmd_mailbox *mailbox;
3359 int ret;
3360
3361 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
3362 if (IS_ERR(mailbox))
3363 return PTR_ERR(mailbox);
3364
3365 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, hr_qp->qpn, 0,
3366 HNS_ROCE_CMD_QUERY_QP,
3367 HNS_ROCE_CMD_TIMEOUT_MSECS);
3368 if (!ret)
3369 memcpy(hr_context, mailbox->buf, sizeof(*hr_context));
3370 else
3371 dev_err(&hr_dev->pdev->dev, "QUERY QP cmd process error\n");
3372
3373 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
3374
3375 return ret;
3376 }
3377
3378 static int hns_roce_v1_q_sqp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
3379 int qp_attr_mask,
3380 struct ib_qp_init_attr *qp_init_attr)
3381 {
3382 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
3383 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
3384 struct hns_roce_sqp_context context;
3385 u32 addr;
3386
3387 mutex_lock(&hr_qp->mutex);
3388
3389 if (hr_qp->state == IB_QPS_RESET) {
3390 qp_attr->qp_state = IB_QPS_RESET;
3391 goto done;
3392 }
3393
3394 addr = ROCEE_QP1C_CFG0_0_REG +
3395 hr_qp->port * sizeof(struct hns_roce_sqp_context);
3396 context.qp1c_bytes_4 = cpu_to_le32(roce_read(hr_dev, addr));
3397 context.sq_rq_bt_l = cpu_to_le32(roce_read(hr_dev, addr + 1));
3398 context.qp1c_bytes_12 = cpu_to_le32(roce_read(hr_dev, addr + 2));
3399 context.qp1c_bytes_16 = cpu_to_le32(roce_read(hr_dev, addr + 3));
3400 context.qp1c_bytes_20 = cpu_to_le32(roce_read(hr_dev, addr + 4));
3401 context.cur_rq_wqe_ba_l = cpu_to_le32(roce_read(hr_dev, addr + 5));
3402 context.qp1c_bytes_28 = cpu_to_le32(roce_read(hr_dev, addr + 6));
3403 context.qp1c_bytes_32 = cpu_to_le32(roce_read(hr_dev, addr + 7));
3404 context.cur_sq_wqe_ba_l = cpu_to_le32(roce_read(hr_dev, addr + 8));
3405 context.qp1c_bytes_40 = cpu_to_le32(roce_read(hr_dev, addr + 9));
3406
3407 hr_qp->state = roce_get_field(context.qp1c_bytes_4,
3408 QP1C_BYTES_4_QP_STATE_M,
3409 QP1C_BYTES_4_QP_STATE_S);
3410 qp_attr->qp_state = hr_qp->state;
3411 qp_attr->path_mtu = IB_MTU_256;
3412 qp_attr->path_mig_state = IB_MIG_ARMED;
3413 qp_attr->qkey = QKEY_VAL;
3414 qp_attr->ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE;
3415 qp_attr->rq_psn = 0;
3416 qp_attr->sq_psn = 0;
3417 qp_attr->dest_qp_num = 1;
3418 qp_attr->qp_access_flags = 6;
3419
3420 qp_attr->pkey_index = roce_get_field(context.qp1c_bytes_20,
3421 QP1C_BYTES_20_PKEY_IDX_M,
3422 QP1C_BYTES_20_PKEY_IDX_S);
3423 qp_attr->port_num = hr_qp->port + 1;
3424 qp_attr->sq_draining = 0;
3425 qp_attr->max_rd_atomic = 0;
3426 qp_attr->max_dest_rd_atomic = 0;
3427 qp_attr->min_rnr_timer = 0;
3428 qp_attr->timeout = 0;
3429 qp_attr->retry_cnt = 0;
3430 qp_attr->rnr_retry = 0;
3431 qp_attr->alt_timeout = 0;
3432
3433 done:
3434 qp_attr->cur_qp_state = qp_attr->qp_state;
3435 qp_attr->cap.max_recv_wr = hr_qp->rq.wqe_cnt;
3436 qp_attr->cap.max_recv_sge = hr_qp->rq.max_gs;
3437 qp_attr->cap.max_send_wr = hr_qp->sq.wqe_cnt;
3438 qp_attr->cap.max_send_sge = hr_qp->sq.max_gs;
3439 qp_attr->cap.max_inline_data = 0;
3440 qp_init_attr->cap = qp_attr->cap;
3441 qp_init_attr->create_flags = 0;
3442
3443 mutex_unlock(&hr_qp->mutex);
3444
3445 return 0;
3446 }
3447
3448 static int hns_roce_v1_q_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
3449 int qp_attr_mask,
3450 struct ib_qp_init_attr *qp_init_attr)
3451 {
3452 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
3453 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
3454 struct device *dev = &hr_dev->pdev->dev;
3455 struct hns_roce_qp_context *context;
3456 int tmp_qp_state = 0;
3457 int ret = 0;
3458 int state;
3459
3460 context = kzalloc(sizeof(*context), GFP_KERNEL);
3461 if (!context)
3462 return -ENOMEM;
3463
3464 memset(qp_attr, 0, sizeof(*qp_attr));
3465 memset(qp_init_attr, 0, sizeof(*qp_init_attr));
3466
3467 mutex_lock(&hr_qp->mutex);
3468
3469 if (hr_qp->state == IB_QPS_RESET) {
3470 qp_attr->qp_state = IB_QPS_RESET;
3471 goto done;
3472 }
3473
3474 ret = hns_roce_v1_query_qpc(hr_dev, hr_qp, context);
3475 if (ret) {
3476 dev_err(dev, "query qpc error\n");
3477 ret = -EINVAL;
3478 goto out;
3479 }
3480
3481 state = roce_get_field(context->qpc_bytes_144,
3482 QP_CONTEXT_QPC_BYTES_144_QP_STATE_M,
3483 QP_CONTEXT_QPC_BYTES_144_QP_STATE_S);
3484 tmp_qp_state = (int)to_ib_qp_state((enum hns_roce_qp_state)state);
3485 if (tmp_qp_state == -1) {
3486 dev_err(dev, "to_ib_qp_state error\n");
3487 ret = -EINVAL;
3488 goto out;
3489 }
3490 hr_qp->state = (u8)tmp_qp_state;
3491 qp_attr->qp_state = (enum ib_qp_state)hr_qp->state;
3492 qp_attr->path_mtu = (enum ib_mtu)roce_get_field(context->qpc_bytes_48,
3493 QP_CONTEXT_QPC_BYTES_48_MTU_M,
3494 QP_CONTEXT_QPC_BYTES_48_MTU_S);
3495 qp_attr->path_mig_state = IB_MIG_ARMED;
3496 qp_attr->ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE;
3497 if (hr_qp->ibqp.qp_type == IB_QPT_UD)
3498 qp_attr->qkey = QKEY_VAL;
3499
3500 qp_attr->rq_psn = roce_get_field(context->qpc_bytes_88,
3501 QP_CONTEXT_QPC_BYTES_88_RX_REQ_EPSN_M,
3502 QP_CONTEXT_QPC_BYTES_88_RX_REQ_EPSN_S);
3503 qp_attr->sq_psn = (u32)roce_get_field(context->qpc_bytes_164,
3504 QP_CONTEXT_QPC_BYTES_164_SQ_PSN_M,
3505 QP_CONTEXT_QPC_BYTES_164_SQ_PSN_S);
3506 qp_attr->dest_qp_num = (u8)roce_get_field(context->qpc_bytes_36,
3507 QP_CONTEXT_QPC_BYTES_36_DEST_QP_M,
3508 QP_CONTEXT_QPC_BYTES_36_DEST_QP_S);
3509 qp_attr->qp_access_flags = ((roce_get_bit(context->qpc_bytes_4,
3510 QP_CONTEXT_QPC_BYTE_4_RDMA_READ_ENABLE_S)) << 2) |
3511 ((roce_get_bit(context->qpc_bytes_4,
3512 QP_CONTEXT_QPC_BYTE_4_RDMA_WRITE_ENABLE_S)) << 1) |
3513 ((roce_get_bit(context->qpc_bytes_4,
3514 QP_CONTEXT_QPC_BYTE_4_ATOMIC_OPERATION_ENABLE_S)) << 3);
3515
3516 if (hr_qp->ibqp.qp_type == IB_QPT_RC ||
3517 hr_qp->ibqp.qp_type == IB_QPT_UC) {
3518 struct ib_global_route *grh =
3519 rdma_ah_retrieve_grh(&qp_attr->ah_attr);
3520
3521 rdma_ah_set_sl(&qp_attr->ah_attr,
3522 roce_get_field(context->qpc_bytes_156,
3523 QP_CONTEXT_QPC_BYTES_156_SL_M,
3524 QP_CONTEXT_QPC_BYTES_156_SL_S));
3525 rdma_ah_set_ah_flags(&qp_attr->ah_attr, IB_AH_GRH);
3526 grh->flow_label =
3527 roce_get_field(context->qpc_bytes_48,
3528 QP_CONTEXT_QPC_BYTES_48_FLOWLABEL_M,
3529 QP_CONTEXT_QPC_BYTES_48_FLOWLABEL_S);
3530 grh->sgid_index =
3531 roce_get_field(context->qpc_bytes_36,
3532 QP_CONTEXT_QPC_BYTES_36_SGID_INDEX_M,
3533 QP_CONTEXT_QPC_BYTES_36_SGID_INDEX_S);
3534 grh->hop_limit =
3535 roce_get_field(context->qpc_bytes_44,
3536 QP_CONTEXT_QPC_BYTES_44_HOPLMT_M,
3537 QP_CONTEXT_QPC_BYTES_44_HOPLMT_S);
3538 grh->traffic_class =
3539 roce_get_field(context->qpc_bytes_48,
3540 QP_CONTEXT_QPC_BYTES_48_TCLASS_M,
3541 QP_CONTEXT_QPC_BYTES_48_TCLASS_S);
3542
3543 memcpy(grh->dgid.raw, context->dgid,
3544 sizeof(grh->dgid.raw));
3545 }
3546
3547 qp_attr->pkey_index = roce_get_field(context->qpc_bytes_12,
3548 QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_M,
3549 QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_S);
3550 qp_attr->port_num = hr_qp->port + 1;
3551 qp_attr->sq_draining = 0;
3552 qp_attr->max_rd_atomic = 1 << roce_get_field(context->qpc_bytes_156,
3553 QP_CONTEXT_QPC_BYTES_156_INITIATOR_DEPTH_M,
3554 QP_CONTEXT_QPC_BYTES_156_INITIATOR_DEPTH_S);
3555 qp_attr->max_dest_rd_atomic = 1 << roce_get_field(context->qpc_bytes_32,
3556 QP_CONTEXT_QPC_BYTES_32_RESPONDER_RESOURCES_M,
3557 QP_CONTEXT_QPC_BYTES_32_RESPONDER_RESOURCES_S);
3558 qp_attr->min_rnr_timer = (u8)(roce_get_field(context->qpc_bytes_24,
3559 QP_CONTEXT_QPC_BYTES_24_MINIMUM_RNR_NAK_TIMER_M,
3560 QP_CONTEXT_QPC_BYTES_24_MINIMUM_RNR_NAK_TIMER_S));
3561 qp_attr->timeout = (u8)(roce_get_field(context->qpc_bytes_156,
3562 QP_CONTEXT_QPC_BYTES_156_ACK_TIMEOUT_M,
3563 QP_CONTEXT_QPC_BYTES_156_ACK_TIMEOUT_S));
3564 qp_attr->retry_cnt = roce_get_field(context->qpc_bytes_148,
3565 QP_CONTEXT_QPC_BYTES_148_RETRY_COUNT_M,
3566 QP_CONTEXT_QPC_BYTES_148_RETRY_COUNT_S);
3567 qp_attr->rnr_retry = (u8)le32_to_cpu(context->rnr_retry);
3568
3569 done:
3570 qp_attr->cur_qp_state = qp_attr->qp_state;
3571 qp_attr->cap.max_recv_wr = hr_qp->rq.wqe_cnt;
3572 qp_attr->cap.max_recv_sge = hr_qp->rq.max_gs;
3573
3574 if (!ibqp->uobject) {
3575 qp_attr->cap.max_send_wr = hr_qp->sq.wqe_cnt;
3576 qp_attr->cap.max_send_sge = hr_qp->sq.max_gs;
3577 } else {
3578 qp_attr->cap.max_send_wr = 0;
3579 qp_attr->cap.max_send_sge = 0;
3580 }
3581
3582 qp_init_attr->cap = qp_attr->cap;
3583
3584 out:
3585 mutex_unlock(&hr_qp->mutex);
3586 kfree(context);
3587 return ret;
3588 }
3589
3590 static int hns_roce_v1_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
3591 int qp_attr_mask,
3592 struct ib_qp_init_attr *qp_init_attr)
3593 {
3594 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
3595
3596 return hr_qp->doorbell_qpn <= 1 ?
3597 hns_roce_v1_q_sqp(ibqp, qp_attr, qp_attr_mask, qp_init_attr) :
3598 hns_roce_v1_q_qp(ibqp, qp_attr, qp_attr_mask, qp_init_attr);
3599 }
3600
3601 int hns_roce_v1_destroy_qp(struct ib_qp *ibqp, struct ib_udata *udata)
3602 {
3603 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
3604 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
3605 struct hns_roce_cq *send_cq, *recv_cq;
3606 int ret;
3607
3608 ret = hns_roce_v1_modify_qp(ibqp, NULL, 0, hr_qp->state, IB_QPS_RESET);
3609 if (ret)
3610 return ret;
3611
3612 send_cq = hr_qp->ibqp.send_cq ? to_hr_cq(hr_qp->ibqp.send_cq) : NULL;
3613 recv_cq = hr_qp->ibqp.recv_cq ? to_hr_cq(hr_qp->ibqp.recv_cq) : NULL;
3614
3615 hns_roce_lock_cqs(send_cq, recv_cq);
3616 if (!udata) {
3617 if (recv_cq)
3618 __hns_roce_v1_cq_clean(recv_cq, hr_qp->qpn,
3619 (hr_qp->ibqp.srq ?
3620 to_hr_srq(hr_qp->ibqp.srq) :
3621 NULL));
3622
3623 if (send_cq && send_cq != recv_cq)
3624 __hns_roce_v1_cq_clean(send_cq, hr_qp->qpn, NULL);
3625 }
3626 hns_roce_unlock_cqs(send_cq, recv_cq);
3627
3628 hns_roce_qp_remove(hr_dev, hr_qp);
3629 hns_roce_qp_free(hr_dev, hr_qp);
3630
3631 /* RC QP, release QPN */
3632 if (hr_qp->ibqp.qp_type == IB_QPT_RC)
3633 hns_roce_release_range_qp(hr_dev, hr_qp->qpn, 1);
3634
3635 hns_roce_mtt_cleanup(hr_dev, &hr_qp->mtt);
3636
3637 ib_umem_release(hr_qp->umem);
3638 if (!udata) {
3639 kfree(hr_qp->sq.wrid);
3640 kfree(hr_qp->rq.wrid);
3641
3642 hns_roce_buf_free(hr_dev, hr_qp->buff_size, &hr_qp->hr_buf);
3643 }
3644
3645 kfree(hr_qp);
3646 return 0;
3647 }
3648
3649 static void hns_roce_v1_destroy_cq(struct ib_cq *ibcq, struct ib_udata *udata)
3650 {
3651 struct hns_roce_dev *hr_dev = to_hr_dev(ibcq->device);
3652 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq);
3653 struct device *dev = &hr_dev->pdev->dev;
3654 u32 cqe_cnt_ori;
3655 u32 cqe_cnt_cur;
3656 int wait_time = 0;
3657
3658 hns_roce_free_cqc(hr_dev, hr_cq);
3659
3660 /*
3661 * Before freeing cq buffer, we need to ensure that the outstanding CQE
3662 * have been written by checking the CQE counter.
3663 */
3664 cqe_cnt_ori = roce_read(hr_dev, ROCEE_SCAEP_WR_CQE_CNT);
3665 while (1) {
3666 if (roce_read(hr_dev, ROCEE_CAEP_CQE_WCMD_EMPTY) &
3667 HNS_ROCE_CQE_WCMD_EMPTY_BIT)
3668 break;
3669
3670 cqe_cnt_cur = roce_read(hr_dev, ROCEE_SCAEP_WR_CQE_CNT);
3671 if ((cqe_cnt_cur - cqe_cnt_ori) >= HNS_ROCE_MIN_CQE_CNT)
3672 break;
3673
3674 msleep(HNS_ROCE_EACH_FREE_CQ_WAIT_MSECS);
3675 if (wait_time > HNS_ROCE_MAX_FREE_CQ_WAIT_CNT) {
3676 dev_warn(dev, "Destroy cq 0x%lx timeout!\n",
3677 hr_cq->cqn);
3678 break;
3679 }
3680 wait_time++;
3681 }
3682
3683 hns_roce_mtt_cleanup(hr_dev, &hr_cq->mtt);
3684
3685 ib_umem_release(hr_cq->umem);
3686 if (!udata) {
3687 /* Free the buff of stored cq */
3688 hns_roce_buf_free(hr_dev, hr_cq->buf.size, &hr_cq->buf);
3689 }
3690 }
3691
3692 static void set_eq_cons_index_v1(struct hns_roce_eq *eq, int req_not)
3693 {
3694 roce_raw_write((eq->cons_index & HNS_ROCE_V1_CONS_IDX_M) |
3695 (req_not << eq->log_entries), eq->doorbell);
3696 }
3697
3698 static void hns_roce_v1_wq_catas_err_handle(struct hns_roce_dev *hr_dev,
3699 struct hns_roce_aeqe *aeqe, int qpn)
3700 {
3701 struct device *dev = &hr_dev->pdev->dev;
3702
3703 dev_warn(dev, "Local Work Queue Catastrophic Error.\n");
3704 switch (roce_get_field(aeqe->asyn, HNS_ROCE_AEQE_U32_4_EVENT_SUB_TYPE_M,
3705 HNS_ROCE_AEQE_U32_4_EVENT_SUB_TYPE_S)) {
3706 case HNS_ROCE_LWQCE_QPC_ERROR:
3707 dev_warn(dev, "QP %d, QPC error.\n", qpn);
3708 break;
3709 case HNS_ROCE_LWQCE_MTU_ERROR:
3710 dev_warn(dev, "QP %d, MTU error.\n", qpn);
3711 break;
3712 case HNS_ROCE_LWQCE_WQE_BA_ADDR_ERROR:
3713 dev_warn(dev, "QP %d, WQE BA addr error.\n", qpn);
3714 break;
3715 case HNS_ROCE_LWQCE_WQE_ADDR_ERROR:
3716 dev_warn(dev, "QP %d, WQE addr error.\n", qpn);
3717 break;
3718 case HNS_ROCE_LWQCE_SQ_WQE_SHIFT_ERROR:
3719 dev_warn(dev, "QP %d, WQE shift error\n", qpn);
3720 break;
3721 case HNS_ROCE_LWQCE_SL_ERROR:
3722 dev_warn(dev, "QP %d, SL error.\n", qpn);
3723 break;
3724 case HNS_ROCE_LWQCE_PORT_ERROR:
3725 dev_warn(dev, "QP %d, port error.\n", qpn);
3726 break;
3727 default:
3728 break;
3729 }
3730 }
3731
3732 static void hns_roce_v1_local_wq_access_err_handle(struct hns_roce_dev *hr_dev,
3733 struct hns_roce_aeqe *aeqe,
3734 int qpn)
3735 {
3736 struct device *dev = &hr_dev->pdev->dev;
3737
3738 dev_warn(dev, "Local Access Violation Work Queue Error.\n");
3739 switch (roce_get_field(aeqe->asyn, HNS_ROCE_AEQE_U32_4_EVENT_SUB_TYPE_M,
3740 HNS_ROCE_AEQE_U32_4_EVENT_SUB_TYPE_S)) {
3741 case HNS_ROCE_LAVWQE_R_KEY_VIOLATION:
3742 dev_warn(dev, "QP %d, R_key violation.\n", qpn);
3743 break;
3744 case HNS_ROCE_LAVWQE_LENGTH_ERROR:
3745 dev_warn(dev, "QP %d, length error.\n", qpn);
3746 break;
3747 case HNS_ROCE_LAVWQE_VA_ERROR:
3748 dev_warn(dev, "QP %d, VA error.\n", qpn);
3749 break;
3750 case HNS_ROCE_LAVWQE_PD_ERROR:
3751 dev_err(dev, "QP %d, PD error.\n", qpn);
3752 break;
3753 case HNS_ROCE_LAVWQE_RW_ACC_ERROR:
3754 dev_warn(dev, "QP %d, rw acc error.\n", qpn);
3755 break;
3756 case HNS_ROCE_LAVWQE_KEY_STATE_ERROR:
3757 dev_warn(dev, "QP %d, key state error.\n", qpn);
3758 break;
3759 case HNS_ROCE_LAVWQE_MR_OPERATION_ERROR:
3760 dev_warn(dev, "QP %d, MR operation error.\n", qpn);
3761 break;
3762 default:
3763 break;
3764 }
3765 }
3766
3767 static void hns_roce_v1_qp_err_handle(struct hns_roce_dev *hr_dev,
3768 struct hns_roce_aeqe *aeqe,
3769 int event_type)
3770 {
3771 struct device *dev = &hr_dev->pdev->dev;
3772 int phy_port;
3773 int qpn;
3774
3775 qpn = roce_get_field(aeqe->event.qp_event.qp,
3776 HNS_ROCE_AEQE_EVENT_QP_EVENT_QP_QPN_M,
3777 HNS_ROCE_AEQE_EVENT_QP_EVENT_QP_QPN_S);
3778 phy_port = roce_get_field(aeqe->event.qp_event.qp,
3779 HNS_ROCE_AEQE_EVENT_QP_EVENT_PORT_NUM_M,
3780 HNS_ROCE_AEQE_EVENT_QP_EVENT_PORT_NUM_S);
3781 if (qpn <= 1)
3782 qpn = HNS_ROCE_MAX_PORTS * qpn + phy_port;
3783
3784 switch (event_type) {
3785 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR:
3786 dev_warn(dev, "Invalid Req Local Work Queue Error.\n"
3787 "QP %d, phy_port %d.\n", qpn, phy_port);
3788 break;
3789 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR:
3790 hns_roce_v1_wq_catas_err_handle(hr_dev, aeqe, qpn);
3791 break;
3792 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR:
3793 hns_roce_v1_local_wq_access_err_handle(hr_dev, aeqe, qpn);
3794 break;
3795 default:
3796 break;
3797 }
3798
3799 hns_roce_qp_event(hr_dev, qpn, event_type);
3800 }
3801
3802 static void hns_roce_v1_cq_err_handle(struct hns_roce_dev *hr_dev,
3803 struct hns_roce_aeqe *aeqe,
3804 int event_type)
3805 {
3806 struct device *dev = &hr_dev->pdev->dev;
3807 u32 cqn;
3808
3809 cqn = roce_get_field(aeqe->event.cq_event.cq,
3810 HNS_ROCE_AEQE_EVENT_CQ_EVENT_CQ_CQN_M,
3811 HNS_ROCE_AEQE_EVENT_CQ_EVENT_CQ_CQN_S);
3812
3813 switch (event_type) {
3814 case HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR:
3815 dev_warn(dev, "CQ 0x%x access err.\n", cqn);
3816 break;
3817 case HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW:
3818 dev_warn(dev, "CQ 0x%x overflow\n", cqn);
3819 break;
3820 case HNS_ROCE_EVENT_TYPE_CQ_ID_INVALID:
3821 dev_warn(dev, "CQ 0x%x ID invalid.\n", cqn);
3822 break;
3823 default:
3824 break;
3825 }
3826
3827 hns_roce_cq_event(hr_dev, cqn, event_type);
3828 }
3829
3830 static void hns_roce_v1_db_overflow_handle(struct hns_roce_dev *hr_dev,
3831 struct hns_roce_aeqe *aeqe)
3832 {
3833 struct device *dev = &hr_dev->pdev->dev;
3834
3835 switch (roce_get_field(aeqe->asyn, HNS_ROCE_AEQE_U32_4_EVENT_SUB_TYPE_M,
3836 HNS_ROCE_AEQE_U32_4_EVENT_SUB_TYPE_S)) {
3837 case HNS_ROCE_DB_SUBTYPE_SDB_OVF:
3838 dev_warn(dev, "SDB overflow.\n");
3839 break;
3840 case HNS_ROCE_DB_SUBTYPE_SDB_ALM_OVF:
3841 dev_warn(dev, "SDB almost overflow.\n");
3842 break;
3843 case HNS_ROCE_DB_SUBTYPE_SDB_ALM_EMP:
3844 dev_warn(dev, "SDB almost empty.\n");
3845 break;
3846 case HNS_ROCE_DB_SUBTYPE_ODB_OVF:
3847 dev_warn(dev, "ODB overflow.\n");
3848 break;
3849 case HNS_ROCE_DB_SUBTYPE_ODB_ALM_OVF:
3850 dev_warn(dev, "ODB almost overflow.\n");
3851 break;
3852 case HNS_ROCE_DB_SUBTYPE_ODB_ALM_EMP:
3853 dev_warn(dev, "SDB almost empty.\n");
3854 break;
3855 default:
3856 break;
3857 }
3858 }
3859
3860 static struct hns_roce_aeqe *get_aeqe_v1(struct hns_roce_eq *eq, u32 entry)
3861 {
3862 unsigned long off = (entry & (eq->entries - 1)) *
3863 HNS_ROCE_AEQ_ENTRY_SIZE;
3864
3865 return (struct hns_roce_aeqe *)((u8 *)
3866 (eq->buf_list[off / HNS_ROCE_BA_SIZE].buf) +
3867 off % HNS_ROCE_BA_SIZE);
3868 }
3869
3870 static struct hns_roce_aeqe *next_aeqe_sw_v1(struct hns_roce_eq *eq)
3871 {
3872 struct hns_roce_aeqe *aeqe = get_aeqe_v1(eq, eq->cons_index);
3873
3874 return (roce_get_bit(aeqe->asyn, HNS_ROCE_AEQE_U32_4_OWNER_S) ^
3875 !!(eq->cons_index & eq->entries)) ? aeqe : NULL;
3876 }
3877
3878 static int hns_roce_v1_aeq_int(struct hns_roce_dev *hr_dev,
3879 struct hns_roce_eq *eq)
3880 {
3881 struct device *dev = &hr_dev->pdev->dev;
3882 struct hns_roce_aeqe *aeqe;
3883 int aeqes_found = 0;
3884 int event_type;
3885
3886 while ((aeqe = next_aeqe_sw_v1(eq))) {
3887
3888 /* Make sure we read the AEQ entry after we have checked the
3889 * ownership bit
3890 */
3891 dma_rmb();
3892
3893 dev_dbg(dev, "aeqe = %pK, aeqe->asyn.event_type = 0x%lx\n",
3894 aeqe,
3895 roce_get_field(aeqe->asyn,
3896 HNS_ROCE_AEQE_U32_4_EVENT_TYPE_M,
3897 HNS_ROCE_AEQE_U32_4_EVENT_TYPE_S));
3898 event_type = roce_get_field(aeqe->asyn,
3899 HNS_ROCE_AEQE_U32_4_EVENT_TYPE_M,
3900 HNS_ROCE_AEQE_U32_4_EVENT_TYPE_S);
3901 switch (event_type) {
3902 case HNS_ROCE_EVENT_TYPE_PATH_MIG:
3903 dev_warn(dev, "PATH MIG not supported\n");
3904 break;
3905 case HNS_ROCE_EVENT_TYPE_COMM_EST:
3906 dev_warn(dev, "COMMUNICATION established\n");
3907 break;
3908 case HNS_ROCE_EVENT_TYPE_SQ_DRAINED:
3909 dev_warn(dev, "SQ DRAINED not supported\n");
3910 break;
3911 case HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED:
3912 dev_warn(dev, "PATH MIG failed\n");
3913 break;
3914 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR:
3915 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR:
3916 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR:
3917 hns_roce_v1_qp_err_handle(hr_dev, aeqe, event_type);
3918 break;
3919 case HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH:
3920 case HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR:
3921 case HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH:
3922 dev_warn(dev, "SRQ not support!\n");
3923 break;
3924 case HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR:
3925 case HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW:
3926 case HNS_ROCE_EVENT_TYPE_CQ_ID_INVALID:
3927 hns_roce_v1_cq_err_handle(hr_dev, aeqe, event_type);
3928 break;
3929 case HNS_ROCE_EVENT_TYPE_PORT_CHANGE:
3930 dev_warn(dev, "port change.\n");
3931 break;
3932 case HNS_ROCE_EVENT_TYPE_MB:
3933 hns_roce_cmd_event(hr_dev,
3934 le16_to_cpu(aeqe->event.cmd.token),
3935 aeqe->event.cmd.status,
3936 le64_to_cpu(aeqe->event.cmd.out_param
3937 ));
3938 break;
3939 case HNS_ROCE_EVENT_TYPE_DB_OVERFLOW:
3940 hns_roce_v1_db_overflow_handle(hr_dev, aeqe);
3941 break;
3942 case HNS_ROCE_EVENT_TYPE_CEQ_OVERFLOW:
3943 dev_warn(dev, "CEQ 0x%lx overflow.\n",
3944 roce_get_field(aeqe->event.ce_event.ceqe,
3945 HNS_ROCE_AEQE_EVENT_CE_EVENT_CEQE_CEQN_M,
3946 HNS_ROCE_AEQE_EVENT_CE_EVENT_CEQE_CEQN_S));
3947 break;
3948 default:
3949 dev_warn(dev, "Unhandled event %d on EQ %d at idx %u.\n",
3950 event_type, eq->eqn, eq->cons_index);
3951 break;
3952 }
3953
3954 eq->cons_index++;
3955 aeqes_found = 1;
3956
3957 if (eq->cons_index > 2 * hr_dev->caps.aeqe_depth - 1) {
3958 dev_warn(dev, "cons_index overflow, set back to 0.\n");
3959 eq->cons_index = 0;
3960 }
3961 }
3962
3963 set_eq_cons_index_v1(eq, 0);
3964
3965 return aeqes_found;
3966 }
3967
3968 static struct hns_roce_ceqe *get_ceqe_v1(struct hns_roce_eq *eq, u32 entry)
3969 {
3970 unsigned long off = (entry & (eq->entries - 1)) *
3971 HNS_ROCE_CEQ_ENTRY_SIZE;
3972
3973 return (struct hns_roce_ceqe *)((u8 *)
3974 (eq->buf_list[off / HNS_ROCE_BA_SIZE].buf) +
3975 off % HNS_ROCE_BA_SIZE);
3976 }
3977
3978 static struct hns_roce_ceqe *next_ceqe_sw_v1(struct hns_roce_eq *eq)
3979 {
3980 struct hns_roce_ceqe *ceqe = get_ceqe_v1(eq, eq->cons_index);
3981
3982 return (!!(roce_get_bit(ceqe->comp,
3983 HNS_ROCE_CEQE_CEQE_COMP_OWNER_S))) ^
3984 (!!(eq->cons_index & eq->entries)) ? ceqe : NULL;
3985 }
3986
3987 static int hns_roce_v1_ceq_int(struct hns_roce_dev *hr_dev,
3988 struct hns_roce_eq *eq)
3989 {
3990 struct hns_roce_ceqe *ceqe;
3991 int ceqes_found = 0;
3992 u32 cqn;
3993
3994 while ((ceqe = next_ceqe_sw_v1(eq))) {
3995
3996 /* Make sure we read CEQ entry after we have checked the
3997 * ownership bit
3998 */
3999 dma_rmb();
4000
4001 cqn = roce_get_field(ceqe->comp,
4002 HNS_ROCE_CEQE_CEQE_COMP_CQN_M,
4003 HNS_ROCE_CEQE_CEQE_COMP_CQN_S);
4004 hns_roce_cq_completion(hr_dev, cqn);
4005
4006 ++eq->cons_index;
4007 ceqes_found = 1;
4008
4009 if (eq->cons_index >
4010 EQ_DEPTH_COEFF * hr_dev->caps.ceqe_depth - 1) {
4011 dev_warn(&eq->hr_dev->pdev->dev,
4012 "cons_index overflow, set back to 0.\n");
4013 eq->cons_index = 0;
4014 }
4015 }
4016
4017 set_eq_cons_index_v1(eq, 0);
4018
4019 return ceqes_found;
4020 }
4021
4022 static irqreturn_t hns_roce_v1_msix_interrupt_eq(int irq, void *eq_ptr)
4023 {
4024 struct hns_roce_eq *eq = eq_ptr;
4025 struct hns_roce_dev *hr_dev = eq->hr_dev;
4026 int int_work = 0;
4027
4028 if (eq->type_flag == HNS_ROCE_CEQ)
4029 /* CEQ irq routine, CEQ is pulse irq, not clear */
4030 int_work = hns_roce_v1_ceq_int(hr_dev, eq);
4031 else
4032 /* AEQ irq routine, AEQ is pulse irq, not clear */
4033 int_work = hns_roce_v1_aeq_int(hr_dev, eq);
4034
4035 return IRQ_RETVAL(int_work);
4036 }
4037
4038 static irqreturn_t hns_roce_v1_msix_interrupt_abn(int irq, void *dev_id)
4039 {
4040 struct hns_roce_dev *hr_dev = dev_id;
4041 struct device *dev = &hr_dev->pdev->dev;
4042 int int_work = 0;
4043 u32 caepaemask_val;
4044 u32 cealmovf_val;
4045 u32 caepaest_val;
4046 u32 aeshift_val;
4047 u32 ceshift_val;
4048 u32 cemask_val;
4049 __le32 tmp;
4050 int i;
4051
4052 /*
4053 * Abnormal interrupt:
4054 * AEQ overflow, ECC multi-bit err, CEQ overflow must clear
4055 * interrupt, mask irq, clear irq, cancel mask operation
4056 */
4057 aeshift_val = roce_read(hr_dev, ROCEE_CAEP_AEQC_AEQE_SHIFT_REG);
4058 tmp = cpu_to_le32(aeshift_val);
4059
4060 /* AEQE overflow */
4061 if (roce_get_bit(tmp,
4062 ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQ_ALM_OVF_INT_ST_S) == 1) {
4063 dev_warn(dev, "AEQ overflow!\n");
4064
4065 /* Set mask */
4066 caepaemask_val = roce_read(hr_dev, ROCEE_CAEP_AE_MASK_REG);
4067 tmp = cpu_to_le32(caepaemask_val);
4068 roce_set_bit(tmp, ROCEE_CAEP_AE_MASK_CAEP_AEQ_ALM_OVF_MASK_S,
4069 HNS_ROCE_INT_MASK_ENABLE);
4070 caepaemask_val = le32_to_cpu(tmp);
4071 roce_write(hr_dev, ROCEE_CAEP_AE_MASK_REG, caepaemask_val);
4072
4073 /* Clear int state(INT_WC : write 1 clear) */
4074 caepaest_val = roce_read(hr_dev, ROCEE_CAEP_AE_ST_REG);
4075 tmp = cpu_to_le32(caepaest_val);
4076 roce_set_bit(tmp, ROCEE_CAEP_AE_ST_CAEP_AEQ_ALM_OVF_S, 1);
4077 caepaest_val = le32_to_cpu(tmp);
4078 roce_write(hr_dev, ROCEE_CAEP_AE_ST_REG, caepaest_val);
4079
4080 /* Clear mask */
4081 caepaemask_val = roce_read(hr_dev, ROCEE_CAEP_AE_MASK_REG);
4082 tmp = cpu_to_le32(caepaemask_val);
4083 roce_set_bit(tmp, ROCEE_CAEP_AE_MASK_CAEP_AEQ_ALM_OVF_MASK_S,
4084 HNS_ROCE_INT_MASK_DISABLE);
4085 caepaemask_val = le32_to_cpu(tmp);
4086 roce_write(hr_dev, ROCEE_CAEP_AE_MASK_REG, caepaemask_val);
4087 }
4088
4089 /* CEQ almost overflow */
4090 for (i = 0; i < hr_dev->caps.num_comp_vectors; i++) {
4091 ceshift_val = roce_read(hr_dev, ROCEE_CAEP_CEQC_SHIFT_0_REG +
4092 i * CEQ_REG_OFFSET);
4093 tmp = cpu_to_le32(ceshift_val);
4094
4095 if (roce_get_bit(tmp,
4096 ROCEE_CAEP_CEQC_SHIFT_CAEP_CEQ_ALM_OVF_INT_ST_S) == 1) {
4097 dev_warn(dev, "CEQ[%d] almost overflow!\n", i);
4098 int_work++;
4099
4100 /* Set mask */
4101 cemask_val = roce_read(hr_dev,
4102 ROCEE_CAEP_CE_IRQ_MASK_0_REG +
4103 i * CEQ_REG_OFFSET);
4104 tmp = cpu_to_le32(cemask_val);
4105 roce_set_bit(tmp,
4106 ROCEE_CAEP_CE_IRQ_MASK_CAEP_CEQ_ALM_OVF_MASK_S,
4107 HNS_ROCE_INT_MASK_ENABLE);
4108 cemask_val = le32_to_cpu(tmp);
4109 roce_write(hr_dev, ROCEE_CAEP_CE_IRQ_MASK_0_REG +
4110 i * CEQ_REG_OFFSET, cemask_val);
4111
4112 /* Clear int state(INT_WC : write 1 clear) */
4113 cealmovf_val = roce_read(hr_dev,
4114 ROCEE_CAEP_CEQ_ALM_OVF_0_REG +
4115 i * CEQ_REG_OFFSET);
4116 tmp = cpu_to_le32(cealmovf_val);
4117 roce_set_bit(tmp,
4118 ROCEE_CAEP_CEQ_ALM_OVF_CAEP_CEQ_ALM_OVF_S,
4119 1);
4120 cealmovf_val = le32_to_cpu(tmp);
4121 roce_write(hr_dev, ROCEE_CAEP_CEQ_ALM_OVF_0_REG +
4122 i * CEQ_REG_OFFSET, cealmovf_val);
4123
4124 /* Clear mask */
4125 cemask_val = roce_read(hr_dev,
4126 ROCEE_CAEP_CE_IRQ_MASK_0_REG +
4127 i * CEQ_REG_OFFSET);
4128 tmp = cpu_to_le32(cemask_val);
4129 roce_set_bit(tmp,
4130 ROCEE_CAEP_CE_IRQ_MASK_CAEP_CEQ_ALM_OVF_MASK_S,
4131 HNS_ROCE_INT_MASK_DISABLE);
4132 cemask_val = le32_to_cpu(tmp);
4133 roce_write(hr_dev, ROCEE_CAEP_CE_IRQ_MASK_0_REG +
4134 i * CEQ_REG_OFFSET, cemask_val);
4135 }
4136 }
4137
4138 /* ECC multi-bit error alarm */
4139 dev_warn(dev, "ECC UCERR ALARM: 0x%x, 0x%x, 0x%x\n",
4140 roce_read(hr_dev, ROCEE_ECC_UCERR_ALM0_REG),
4141 roce_read(hr_dev, ROCEE_ECC_UCERR_ALM1_REG),
4142 roce_read(hr_dev, ROCEE_ECC_UCERR_ALM2_REG));
4143
4144 dev_warn(dev, "ECC CERR ALARM: 0x%x, 0x%x, 0x%x\n",
4145 roce_read(hr_dev, ROCEE_ECC_CERR_ALM0_REG),
4146 roce_read(hr_dev, ROCEE_ECC_CERR_ALM1_REG),
4147 roce_read(hr_dev, ROCEE_ECC_CERR_ALM2_REG));
4148
4149 return IRQ_RETVAL(int_work);
4150 }
4151
4152 static void hns_roce_v1_int_mask_enable(struct hns_roce_dev *hr_dev)
4153 {
4154 u32 aemask_val;
4155 int masken = 0;
4156 __le32 tmp;
4157 int i;
4158
4159 /* AEQ INT */
4160 aemask_val = roce_read(hr_dev, ROCEE_CAEP_AE_MASK_REG);
4161 tmp = cpu_to_le32(aemask_val);
4162 roce_set_bit(tmp, ROCEE_CAEP_AE_MASK_CAEP_AEQ_ALM_OVF_MASK_S,
4163 masken);
4164 roce_set_bit(tmp, ROCEE_CAEP_AE_MASK_CAEP_AE_IRQ_MASK_S, masken);
4165 aemask_val = le32_to_cpu(tmp);
4166 roce_write(hr_dev, ROCEE_CAEP_AE_MASK_REG, aemask_val);
4167
4168 /* CEQ INT */
4169 for (i = 0; i < hr_dev->caps.num_comp_vectors; i++) {
4170 /* IRQ mask */
4171 roce_write(hr_dev, ROCEE_CAEP_CE_IRQ_MASK_0_REG +
4172 i * CEQ_REG_OFFSET, masken);
4173 }
4174 }
4175
4176 static void hns_roce_v1_free_eq(struct hns_roce_dev *hr_dev,
4177 struct hns_roce_eq *eq)
4178 {
4179 int npages = (PAGE_ALIGN(eq->eqe_size * eq->entries) +
4180 HNS_ROCE_BA_SIZE - 1) / HNS_ROCE_BA_SIZE;
4181 int i;
4182
4183 if (!eq->buf_list)
4184 return;
4185
4186 for (i = 0; i < npages; ++i)
4187 dma_free_coherent(&hr_dev->pdev->dev, HNS_ROCE_BA_SIZE,
4188 eq->buf_list[i].buf, eq->buf_list[i].map);
4189
4190 kfree(eq->buf_list);
4191 }
4192
4193 static void hns_roce_v1_enable_eq(struct hns_roce_dev *hr_dev, int eq_num,
4194 int enable_flag)
4195 {
4196 void __iomem *eqc = hr_dev->eq_table.eqc_base[eq_num];
4197 __le32 tmp;
4198 u32 val;
4199
4200 val = readl(eqc);
4201 tmp = cpu_to_le32(val);
4202
4203 if (enable_flag)
4204 roce_set_field(tmp,
4205 ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_STATE_M,
4206 ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_STATE_S,
4207 HNS_ROCE_EQ_STAT_VALID);
4208 else
4209 roce_set_field(tmp,
4210 ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_STATE_M,
4211 ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_STATE_S,
4212 HNS_ROCE_EQ_STAT_INVALID);
4213
4214 val = le32_to_cpu(tmp);
4215 writel(val, eqc);
4216 }
4217
4218 static int hns_roce_v1_create_eq(struct hns_roce_dev *hr_dev,
4219 struct hns_roce_eq *eq)
4220 {
4221 void __iomem *eqc = hr_dev->eq_table.eqc_base[eq->eqn];
4222 struct device *dev = &hr_dev->pdev->dev;
4223 dma_addr_t tmp_dma_addr;
4224 u32 eqconsindx_val = 0;
4225 u32 eqcuridx_val = 0;
4226 u32 eqshift_val = 0;
4227 __le32 tmp2 = 0;
4228 __le32 tmp1 = 0;
4229 __le32 tmp = 0;
4230 int num_bas;
4231 int ret;
4232 int i;
4233
4234 num_bas = (PAGE_ALIGN(eq->entries * eq->eqe_size) +
4235 HNS_ROCE_BA_SIZE - 1) / HNS_ROCE_BA_SIZE;
4236
4237 if ((eq->entries * eq->eqe_size) > HNS_ROCE_BA_SIZE) {
4238 dev_err(dev, "[error]eq buf %d gt ba size(%d) need bas=%d\n",
4239 (eq->entries * eq->eqe_size), HNS_ROCE_BA_SIZE,
4240 num_bas);
4241 return -EINVAL;
4242 }
4243
4244 eq->buf_list = kcalloc(num_bas, sizeof(*eq->buf_list), GFP_KERNEL);
4245 if (!eq->buf_list)
4246 return -ENOMEM;
4247
4248 for (i = 0; i < num_bas; ++i) {
4249 eq->buf_list[i].buf = dma_alloc_coherent(dev, HNS_ROCE_BA_SIZE,
4250 &tmp_dma_addr,
4251 GFP_KERNEL);
4252 if (!eq->buf_list[i].buf) {
4253 ret = -ENOMEM;
4254 goto err_out_free_pages;
4255 }
4256
4257 eq->buf_list[i].map = tmp_dma_addr;
4258 }
4259 eq->cons_index = 0;
4260 roce_set_field(tmp, ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_STATE_M,
4261 ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_STATE_S,
4262 HNS_ROCE_EQ_STAT_INVALID);
4263 roce_set_field(tmp, ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_AEQE_SHIFT_M,
4264 ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_AEQE_SHIFT_S,
4265 eq->log_entries);
4266 eqshift_val = le32_to_cpu(tmp);
4267 writel(eqshift_val, eqc);
4268
4269 /* Configure eq extended address 12~44bit */
4270 writel((u32)(eq->buf_list[0].map >> 12), eqc + 4);
4271
4272 /*
4273 * Configure eq extended address 45~49 bit.
4274 * 44 = 32 + 12, When evaluating addr to hardware, shift 12 because of
4275 * using 4K page, and shift more 32 because of
4276 * caculating the high 32 bit value evaluated to hardware.
4277 */
4278 roce_set_field(tmp1, ROCEE_CAEP_AEQE_CUR_IDX_CAEP_AEQ_BT_H_M,
4279 ROCEE_CAEP_AEQE_CUR_IDX_CAEP_AEQ_BT_H_S,
4280 eq->buf_list[0].map >> 44);
4281 roce_set_field(tmp1, ROCEE_CAEP_AEQE_CUR_IDX_CAEP_AEQE_CUR_IDX_M,
4282 ROCEE_CAEP_AEQE_CUR_IDX_CAEP_AEQE_CUR_IDX_S, 0);
4283 eqcuridx_val = le32_to_cpu(tmp1);
4284 writel(eqcuridx_val, eqc + 8);
4285
4286 /* Configure eq consumer index */
4287 roce_set_field(tmp2, ROCEE_CAEP_AEQE_CONS_IDX_CAEP_AEQE_CONS_IDX_M,
4288 ROCEE_CAEP_AEQE_CONS_IDX_CAEP_AEQE_CONS_IDX_S, 0);
4289 eqconsindx_val = le32_to_cpu(tmp2);
4290 writel(eqconsindx_val, eqc + 0xc);
4291
4292 return 0;
4293
4294 err_out_free_pages:
4295 for (i -= 1; i >= 0; i--)
4296 dma_free_coherent(dev, HNS_ROCE_BA_SIZE, eq->buf_list[i].buf,
4297 eq->buf_list[i].map);
4298
4299 kfree(eq->buf_list);
4300 return ret;
4301 }
4302
4303 static int hns_roce_v1_init_eq_table(struct hns_roce_dev *hr_dev)
4304 {
4305 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table;
4306 struct device *dev = &hr_dev->pdev->dev;
4307 struct hns_roce_eq *eq;
4308 int irq_num;
4309 int eq_num;
4310 int ret;
4311 int i, j;
4312
4313 eq_num = hr_dev->caps.num_comp_vectors + hr_dev->caps.num_aeq_vectors;
4314 irq_num = eq_num + hr_dev->caps.num_other_vectors;
4315
4316 eq_table->eq = kcalloc(eq_num, sizeof(*eq_table->eq), GFP_KERNEL);
4317 if (!eq_table->eq)
4318 return -ENOMEM;
4319
4320 eq_table->eqc_base = kcalloc(eq_num, sizeof(*eq_table->eqc_base),
4321 GFP_KERNEL);
4322 if (!eq_table->eqc_base) {
4323 ret = -ENOMEM;
4324 goto err_eqc_base_alloc_fail;
4325 }
4326
4327 for (i = 0; i < eq_num; i++) {
4328 eq = &eq_table->eq[i];
4329 eq->hr_dev = hr_dev;
4330 eq->eqn = i;
4331 eq->irq = hr_dev->irq[i];
4332 eq->log_page_size = PAGE_SHIFT;
4333
4334 if (i < hr_dev->caps.num_comp_vectors) {
4335 /* CEQ */
4336 eq_table->eqc_base[i] = hr_dev->reg_base +
4337 ROCEE_CAEP_CEQC_SHIFT_0_REG +
4338 CEQ_REG_OFFSET * i;
4339 eq->type_flag = HNS_ROCE_CEQ;
4340 eq->doorbell = hr_dev->reg_base +
4341 ROCEE_CAEP_CEQC_CONS_IDX_0_REG +
4342 CEQ_REG_OFFSET * i;
4343 eq->entries = hr_dev->caps.ceqe_depth;
4344 eq->log_entries = ilog2(eq->entries);
4345 eq->eqe_size = HNS_ROCE_CEQ_ENTRY_SIZE;
4346 } else {
4347 /* AEQ */
4348 eq_table->eqc_base[i] = hr_dev->reg_base +
4349 ROCEE_CAEP_AEQC_AEQE_SHIFT_REG;
4350 eq->type_flag = HNS_ROCE_AEQ;
4351 eq->doorbell = hr_dev->reg_base +
4352 ROCEE_CAEP_AEQE_CONS_IDX_REG;
4353 eq->entries = hr_dev->caps.aeqe_depth;
4354 eq->log_entries = ilog2(eq->entries);
4355 eq->eqe_size = HNS_ROCE_AEQ_ENTRY_SIZE;
4356 }
4357 }
4358
4359 /* Disable irq */
4360 hns_roce_v1_int_mask_enable(hr_dev);
4361
4362 /* Configure ce int interval */
4363 roce_write(hr_dev, ROCEE_CAEP_CE_INTERVAL_CFG_REG,
4364 HNS_ROCE_CEQ_DEFAULT_INTERVAL);
4365
4366 /* Configure ce int burst num */
4367 roce_write(hr_dev, ROCEE_CAEP_CE_BURST_NUM_CFG_REG,
4368 HNS_ROCE_CEQ_DEFAULT_BURST_NUM);
4369
4370 for (i = 0; i < eq_num; i++) {
4371 ret = hns_roce_v1_create_eq(hr_dev, &eq_table->eq[i]);
4372 if (ret) {
4373 dev_err(dev, "eq create failed\n");
4374 goto err_create_eq_fail;
4375 }
4376 }
4377
4378 for (j = 0; j < irq_num; j++) {
4379 if (j < eq_num)
4380 ret = request_irq(hr_dev->irq[j],
4381 hns_roce_v1_msix_interrupt_eq, 0,
4382 hr_dev->irq_names[j],
4383 &eq_table->eq[j]);
4384 else
4385 ret = request_irq(hr_dev->irq[j],
4386 hns_roce_v1_msix_interrupt_abn, 0,
4387 hr_dev->irq_names[j], hr_dev);
4388
4389 if (ret) {
4390 dev_err(dev, "request irq error!\n");
4391 goto err_request_irq_fail;
4392 }
4393 }
4394
4395 for (i = 0; i < eq_num; i++)
4396 hns_roce_v1_enable_eq(hr_dev, i, EQ_ENABLE);
4397
4398 return 0;
4399
4400 err_request_irq_fail:
4401 for (j -= 1; j >= 0; j--)
4402 free_irq(hr_dev->irq[j], &eq_table->eq[j]);
4403
4404 err_create_eq_fail:
4405 for (i -= 1; i >= 0; i--)
4406 hns_roce_v1_free_eq(hr_dev, &eq_table->eq[i]);
4407
4408 kfree(eq_table->eqc_base);
4409
4410 err_eqc_base_alloc_fail:
4411 kfree(eq_table->eq);
4412
4413 return ret;
4414 }
4415
4416 static void hns_roce_v1_cleanup_eq_table(struct hns_roce_dev *hr_dev)
4417 {
4418 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table;
4419 int irq_num;
4420 int eq_num;
4421 int i;
4422
4423 eq_num = hr_dev->caps.num_comp_vectors + hr_dev->caps.num_aeq_vectors;
4424 irq_num = eq_num + hr_dev->caps.num_other_vectors;
4425 for (i = 0; i < eq_num; i++) {
4426 /* Disable EQ */
4427 hns_roce_v1_enable_eq(hr_dev, i, EQ_DISABLE);
4428
4429 free_irq(hr_dev->irq[i], &eq_table->eq[i]);
4430
4431 hns_roce_v1_free_eq(hr_dev, &eq_table->eq[i]);
4432 }
4433 for (i = eq_num; i < irq_num; i++)
4434 free_irq(hr_dev->irq[i], hr_dev);
4435
4436 kfree(eq_table->eqc_base);
4437 kfree(eq_table->eq);
4438 }
4439
4440 static const struct ib_device_ops hns_roce_v1_dev_ops = {
4441 .destroy_qp = hns_roce_v1_destroy_qp,
4442 .modify_cq = hns_roce_v1_modify_cq,
4443 .poll_cq = hns_roce_v1_poll_cq,
4444 .post_recv = hns_roce_v1_post_recv,
4445 .post_send = hns_roce_v1_post_send,
4446 .query_qp = hns_roce_v1_query_qp,
4447 .req_notify_cq = hns_roce_v1_req_notify_cq,
4448 };
4449
4450 static const struct hns_roce_hw hns_roce_hw_v1 = {
4451 .reset = hns_roce_v1_reset,
4452 .hw_profile = hns_roce_v1_profile,
4453 .hw_init = hns_roce_v1_init,
4454 .hw_exit = hns_roce_v1_exit,
4455 .post_mbox = hns_roce_v1_post_mbox,
4456 .chk_mbox = hns_roce_v1_chk_mbox,
4457 .set_gid = hns_roce_v1_set_gid,
4458 .set_mac = hns_roce_v1_set_mac,
4459 .set_mtu = hns_roce_v1_set_mtu,
4460 .write_mtpt = hns_roce_v1_write_mtpt,
4461 .write_cqc = hns_roce_v1_write_cqc,
4462 .modify_cq = hns_roce_v1_modify_cq,
4463 .clear_hem = hns_roce_v1_clear_hem,
4464 .modify_qp = hns_roce_v1_modify_qp,
4465 .query_qp = hns_roce_v1_query_qp,
4466 .destroy_qp = hns_roce_v1_destroy_qp,
4467 .post_send = hns_roce_v1_post_send,
4468 .post_recv = hns_roce_v1_post_recv,
4469 .req_notify_cq = hns_roce_v1_req_notify_cq,
4470 .poll_cq = hns_roce_v1_poll_cq,
4471 .dereg_mr = hns_roce_v1_dereg_mr,
4472 .destroy_cq = hns_roce_v1_destroy_cq,
4473 .init_eq = hns_roce_v1_init_eq_table,
4474 .cleanup_eq = hns_roce_v1_cleanup_eq_table,
4475 .hns_roce_dev_ops = &hns_roce_v1_dev_ops,
4476 };
4477
4478 static const struct of_device_id hns_roce_of_match[] = {
4479 { .compatible = "hisilicon,hns-roce-v1", .data = &hns_roce_hw_v1, },
4480 {},
4481 };
4482 MODULE_DEVICE_TABLE(of, hns_roce_of_match);
4483
4484 static const struct acpi_device_id hns_roce_acpi_match[] = {
4485 { "HISI00D1", (kernel_ulong_t)&hns_roce_hw_v1 },
4486 {},
4487 };
4488 MODULE_DEVICE_TABLE(acpi, hns_roce_acpi_match);
4489
4490 static struct
4491 platform_device *hns_roce_find_pdev(struct fwnode_handle *fwnode)
4492 {
4493 struct device *dev;
4494
4495 /* get the 'device' corresponding to the matching 'fwnode' */
4496 dev = bus_find_device_by_fwnode(&platform_bus_type, fwnode);
4497 /* get the platform device */
4498 return dev ? to_platform_device(dev) : NULL;
4499 }
4500
4501 static int hns_roce_get_cfg(struct hns_roce_dev *hr_dev)
4502 {
4503 struct device *dev = &hr_dev->pdev->dev;
4504 struct platform_device *pdev = NULL;
4505 struct net_device *netdev = NULL;
4506 struct device_node *net_node;
4507 int port_cnt = 0;
4508 u8 phy_port;
4509 int ret;
4510 int i;
4511
4512 /* check if we are compatible with the underlying SoC */
4513 if (dev_of_node(dev)) {
4514 const struct of_device_id *of_id;
4515
4516 of_id = of_match_node(hns_roce_of_match, dev->of_node);
4517 if (!of_id) {
4518 dev_err(dev, "device is not compatible!\n");
4519 return -ENXIO;
4520 }
4521 hr_dev->hw = (const struct hns_roce_hw *)of_id->data;
4522 if (!hr_dev->hw) {
4523 dev_err(dev, "couldn't get H/W specific DT data!\n");
4524 return -ENXIO;
4525 }
4526 } else if (is_acpi_device_node(dev->fwnode)) {
4527 const struct acpi_device_id *acpi_id;
4528
4529 acpi_id = acpi_match_device(hns_roce_acpi_match, dev);
4530 if (!acpi_id) {
4531 dev_err(dev, "device is not compatible!\n");
4532 return -ENXIO;
4533 }
4534 hr_dev->hw = (const struct hns_roce_hw *) acpi_id->driver_data;
4535 if (!hr_dev->hw) {
4536 dev_err(dev, "couldn't get H/W specific ACPI data!\n");
4537 return -ENXIO;
4538 }
4539 } else {
4540 dev_err(dev, "can't read compatibility data from DT or ACPI\n");
4541 return -ENXIO;
4542 }
4543
4544 /* get the mapped register base address */
4545 hr_dev->reg_base = devm_platform_ioremap_resource(hr_dev->pdev, 0);
4546 if (IS_ERR(hr_dev->reg_base))
4547 return PTR_ERR(hr_dev->reg_base);
4548
4549 /* read the node_guid of IB device from the DT or ACPI */
4550 ret = device_property_read_u8_array(dev, "node-guid",
4551 (u8 *)&hr_dev->ib_dev.node_guid,
4552 GUID_LEN);
4553 if (ret) {
4554 dev_err(dev, "couldn't get node_guid from DT or ACPI!\n");
4555 return ret;
4556 }
4557
4558 /* get the RoCE associated ethernet ports or netdevices */
4559 for (i = 0; i < HNS_ROCE_MAX_PORTS; i++) {
4560 if (dev_of_node(dev)) {
4561 net_node = of_parse_phandle(dev->of_node, "eth-handle",
4562 i);
4563 if (!net_node)
4564 continue;
4565 pdev = of_find_device_by_node(net_node);
4566 } else if (is_acpi_device_node(dev->fwnode)) {
4567 struct fwnode_reference_args args;
4568
4569 ret = acpi_node_get_property_reference(dev->fwnode,
4570 "eth-handle",
4571 i, &args);
4572 if (ret)
4573 continue;
4574 pdev = hns_roce_find_pdev(args.fwnode);
4575 } else {
4576 dev_err(dev, "cannot read data from DT or ACPI\n");
4577 return -ENXIO;
4578 }
4579
4580 if (pdev) {
4581 netdev = platform_get_drvdata(pdev);
4582 phy_port = (u8)i;
4583 if (netdev) {
4584 hr_dev->iboe.netdevs[port_cnt] = netdev;
4585 hr_dev->iboe.phy_port[port_cnt] = phy_port;
4586 } else {
4587 dev_err(dev, "no netdev found with pdev %s\n",
4588 pdev->name);
4589 return -ENODEV;
4590 }
4591 port_cnt++;
4592 }
4593 }
4594
4595 if (port_cnt == 0) {
4596 dev_err(dev, "unable to get eth-handle for available ports!\n");
4597 return -EINVAL;
4598 }
4599
4600 hr_dev->caps.num_ports = port_cnt;
4601
4602 /* cmd issue mode: 0 is poll, 1 is event */
4603 hr_dev->cmd_mod = 1;
4604 hr_dev->loop_idc = 0;
4605 hr_dev->sdb_offset = ROCEE_DB_SQ_L_0_REG;
4606 hr_dev->odb_offset = ROCEE_DB_OTHERS_L_0_REG;
4607
4608 /* read the interrupt names from the DT or ACPI */
4609 ret = device_property_read_string_array(dev, "interrupt-names",
4610 hr_dev->irq_names,
4611 HNS_ROCE_V1_MAX_IRQ_NUM);
4612 if (ret < 0) {
4613 dev_err(dev, "couldn't get interrupt names from DT or ACPI!\n");
4614 return ret;
4615 }
4616
4617 /* fetch the interrupt numbers */
4618 for (i = 0; i < HNS_ROCE_V1_MAX_IRQ_NUM; i++) {
4619 hr_dev->irq[i] = platform_get_irq(hr_dev->pdev, i);
4620 if (hr_dev->irq[i] <= 0)
4621 return -EINVAL;
4622 }
4623
4624 return 0;
4625 }
4626
4627 /**
4628 * hns_roce_probe - RoCE driver entrance
4629 * @pdev: pointer to platform device
4630 * Return : int
4631 *
4632 */
4633 static int hns_roce_probe(struct platform_device *pdev)
4634 {
4635 int ret;
4636 struct hns_roce_dev *hr_dev;
4637 struct device *dev = &pdev->dev;
4638
4639 hr_dev = ib_alloc_device(hns_roce_dev, ib_dev);
4640 if (!hr_dev)
4641 return -ENOMEM;
4642
4643 hr_dev->priv = kzalloc(sizeof(struct hns_roce_v1_priv), GFP_KERNEL);
4644 if (!hr_dev->priv) {
4645 ret = -ENOMEM;
4646 goto error_failed_kzalloc;
4647 }
4648
4649 hr_dev->pdev = pdev;
4650 hr_dev->dev = dev;
4651 platform_set_drvdata(pdev, hr_dev);
4652
4653 if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64ULL)) &&
4654 dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32ULL))) {
4655 dev_err(dev, "Not usable DMA addressing mode\n");
4656 ret = -EIO;
4657 goto error_failed_get_cfg;
4658 }
4659
4660 ret = hns_roce_get_cfg(hr_dev);
4661 if (ret) {
4662 dev_err(dev, "Get Configuration failed!\n");
4663 goto error_failed_get_cfg;
4664 }
4665
4666 ret = hns_roce_init(hr_dev);
4667 if (ret) {
4668 dev_err(dev, "RoCE engine init failed!\n");
4669 goto error_failed_get_cfg;
4670 }
4671
4672 return 0;
4673
4674 error_failed_get_cfg:
4675 kfree(hr_dev->priv);
4676
4677 error_failed_kzalloc:
4678 ib_dealloc_device(&hr_dev->ib_dev);
4679
4680 return ret;
4681 }
4682
4683 /**
4684 * hns_roce_remove - remove RoCE device
4685 * @pdev: pointer to platform device
4686 */
4687 static int hns_roce_remove(struct platform_device *pdev)
4688 {
4689 struct hns_roce_dev *hr_dev = platform_get_drvdata(pdev);
4690
4691 hns_roce_exit(hr_dev);
4692 kfree(hr_dev->priv);
4693 ib_dealloc_device(&hr_dev->ib_dev);
4694
4695 return 0;
4696 }
4697
4698 static struct platform_driver hns_roce_driver = {
4699 .probe = hns_roce_probe,
4700 .remove = hns_roce_remove,
4701 .driver = {
4702 .name = DRV_NAME,
4703 .of_match_table = hns_roce_of_match,
4704 .acpi_match_table = ACPI_PTR(hns_roce_acpi_match),
4705 },
4706 };
4707
4708 module_platform_driver(hns_roce_driver);
4709
4710 MODULE_LICENSE("Dual BSD/GPL");
4711 MODULE_AUTHOR("Wei Hu <xavier.huwei@huawei.com>");
4712 MODULE_AUTHOR("Nenglong Zhao <zhaonenglong@hisilicon.com>");
4713 MODULE_AUTHOR("Lijun Ou <oulijun@huawei.com>");
4714 MODULE_DESCRIPTION("Hisilicon Hip06 Family RoCE Driver");
Linux with added FPC-III support