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treewide: remove redundant IS_ERR() before error code check
[linux/fpc-iii.git] / drivers / isdn / hardware / mISDN / hfcpci.c
blobabdf787c1a716d78e2b134164139b3007b3cc800
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 *
4 * hfcpci.c low level driver for CCD's hfc-pci based cards
5 *
6 * Author Werner Cornelius (werner@isdn4linux.de)
7 * based on existing driver for CCD hfc ISA cards
8 * type approval valid for HFC-S PCI A based card
9 *
10 * Copyright 1999 by Werner Cornelius (werner@isdn-development.de)
11 * Copyright 2008 by Karsten Keil <kkeil@novell.com>
12 *
13 * Module options:
14 *
15 * debug:
16 * NOTE: only one poll value must be given for all cards
17 * See hfc_pci.h for debug flags.
18 *
19 * poll:
20 * NOTE: only one poll value must be given for all cards
21 * Give the number of samples for each fifo process.
22 * By default 128 is used. Decrease to reduce delay, increase to
23 * reduce cpu load. If unsure, don't mess with it!
24 * A value of 128 will use controller's interrupt. Other values will
25 * use kernel timer, because the controller will not allow lower values
26 * than 128.
27 * Also note that the value depends on the kernel timer frequency.
28 * If kernel uses a frequency of 1000 Hz, steps of 8 samples are possible.
29 * If the kernel uses 100 Hz, steps of 80 samples are possible.
30 * If the kernel uses 300 Hz, steps of about 26 samples are possible.
31 */
32
33 #include <linux/interrupt.h>
34 #include <linux/module.h>
35 #include <linux/pci.h>
36 #include <linux/delay.h>
37 #include <linux/mISDNhw.h>
38 #include <linux/slab.h>
39
40 #include "hfc_pci.h"
41
42 static const char *hfcpci_revision = "2.0";
43
44 static int HFC_cnt;
45 static uint debug;
46 static uint poll, tics;
47 static struct timer_list hfc_tl;
48 static unsigned long hfc_jiffies;
49
50 MODULE_AUTHOR("Karsten Keil");
51 MODULE_LICENSE("GPL");
52 module_param(debug, uint, S_IRUGO | S_IWUSR);
53 module_param(poll, uint, S_IRUGO | S_IWUSR);
54
55 enum {
56 HFC_CCD_2BD0,
57 HFC_CCD_B000,
58 HFC_CCD_B006,
59 HFC_CCD_B007,
60 HFC_CCD_B008,
61 HFC_CCD_B009,
62 HFC_CCD_B00A,
63 HFC_CCD_B00B,
64 HFC_CCD_B00C,
65 HFC_CCD_B100,
66 HFC_CCD_B700,
67 HFC_CCD_B701,
68 HFC_ASUS_0675,
69 HFC_BERKOM_A1T,
70 HFC_BERKOM_TCONCEPT,
71 HFC_ANIGMA_MC145575,
72 HFC_ZOLTRIX_2BD0,
73 HFC_DIGI_DF_M_IOM2_E,
74 HFC_DIGI_DF_M_E,
75 HFC_DIGI_DF_M_IOM2_A,
76 HFC_DIGI_DF_M_A,
77 HFC_ABOCOM_2BD1,
78 HFC_SITECOM_DC105V2,
79 };
80
81 struct hfcPCI_hw {
82 unsigned char cirm;
83 unsigned char ctmt;
84 unsigned char clkdel;
85 unsigned char states;
86 unsigned char conn;
87 unsigned char mst_m;
88 unsigned char int_m1;
89 unsigned char int_m2;
90 unsigned char sctrl;
91 unsigned char sctrl_r;
92 unsigned char sctrl_e;
93 unsigned char trm;
94 unsigned char fifo_en;
95 unsigned char bswapped;
96 unsigned char protocol;
97 int nt_timer;
98 unsigned char __iomem *pci_io; /* start of PCI IO memory */
99 dma_addr_t dmahandle;
100 void *fifos; /* FIFO memory */
101 int last_bfifo_cnt[2];
102 /* marker saving last b-fifo frame count */
103 struct timer_list timer;
104 };
105
106 #define HFC_CFG_MASTER 1
107 #define HFC_CFG_SLAVE 2
108 #define HFC_CFG_PCM 3
109 #define HFC_CFG_2HFC 4
110 #define HFC_CFG_SLAVEHFC 5
111 #define HFC_CFG_NEG_F0 6
112 #define HFC_CFG_SW_DD_DU 7
113
114 #define FLG_HFC_TIMER_T1 16
115 #define FLG_HFC_TIMER_T3 17
116
117 #define NT_T1_COUNT 1120 /* number of 3.125ms interrupts (3.5s) */
118 #define NT_T3_COUNT 31 /* number of 3.125ms interrupts (97 ms) */
119 #define CLKDEL_TE 0x0e /* CLKDEL in TE mode */
120 #define CLKDEL_NT 0x6c /* CLKDEL in NT mode */
121
122
123 struct hfc_pci {
124 u_char subtype;
125 u_char chanlimit;
126 u_char initdone;
127 u_long cfg;
128 u_int irq;
129 u_int irqcnt;
130 struct pci_dev *pdev;
131 struct hfcPCI_hw hw;
132 spinlock_t lock; /* card lock */
133 struct dchannel dch;
134 struct bchannel bch[2];
135 };
136
137 /* Interface functions */
138 static void
139 enable_hwirq(struct hfc_pci *hc)
140 {
141 hc->hw.int_m2 |= HFCPCI_IRQ_ENABLE;
142 Write_hfc(hc, HFCPCI_INT_M2, hc->hw.int_m2);
143 }
144
145 static void
146 disable_hwirq(struct hfc_pci *hc)
147 {
148 hc->hw.int_m2 &= ~((u_char)HFCPCI_IRQ_ENABLE);
149 Write_hfc(hc, HFCPCI_INT_M2, hc->hw.int_m2);
150 }
151
152 /*
153 * free hardware resources used by driver
154 */
155 static void
156 release_io_hfcpci(struct hfc_pci *hc)
157 {
158 /* disable memory mapped ports + busmaster */
159 pci_write_config_word(hc->pdev, PCI_COMMAND, 0);
160 del_timer(&hc->hw.timer);
161 pci_free_consistent(hc->pdev, 0x8000, hc->hw.fifos, hc->hw.dmahandle);
162 iounmap(hc->hw.pci_io);
163 }
164
165 /*
166 * set mode (NT or TE)
167 */
168 static void
169 hfcpci_setmode(struct hfc_pci *hc)
170 {
171 if (hc->hw.protocol == ISDN_P_NT_S0) {
172 hc->hw.clkdel = CLKDEL_NT; /* ST-Bit delay for NT-Mode */
173 hc->hw.sctrl |= SCTRL_MODE_NT; /* NT-MODE */
174 hc->hw.states = 1; /* G1 */
175 } else {
176 hc->hw.clkdel = CLKDEL_TE; /* ST-Bit delay for TE-Mode */
177 hc->hw.sctrl &= ~SCTRL_MODE_NT; /* TE-MODE */
178 hc->hw.states = 2; /* F2 */
179 }
180 Write_hfc(hc, HFCPCI_CLKDEL, hc->hw.clkdel);
181 Write_hfc(hc, HFCPCI_STATES, HFCPCI_LOAD_STATE | hc->hw.states);
182 udelay(10);
183 Write_hfc(hc, HFCPCI_STATES, hc->hw.states | 0x40); /* Deactivate */
184 Write_hfc(hc, HFCPCI_SCTRL, hc->hw.sctrl);
185 }
186
187 /*
188 * function called to reset the HFC PCI chip. A complete software reset of chip
189 * and fifos is done.
190 */
191 static void
192 reset_hfcpci(struct hfc_pci *hc)
193 {
194 u_char val;
195 int cnt = 0;
196
197 printk(KERN_DEBUG "reset_hfcpci: entered\n");
198 val = Read_hfc(hc, HFCPCI_CHIP_ID);
199 printk(KERN_INFO "HFC_PCI: resetting HFC ChipId(%x)\n", val);
200 /* enable memory mapped ports, disable busmaster */
201 pci_write_config_word(hc->pdev, PCI_COMMAND, PCI_ENA_MEMIO);
202 disable_hwirq(hc);
203 /* enable memory ports + busmaster */
204 pci_write_config_word(hc->pdev, PCI_COMMAND,
205 PCI_ENA_MEMIO + PCI_ENA_MASTER);
206 val = Read_hfc(hc, HFCPCI_STATUS);
207 printk(KERN_DEBUG "HFC-PCI status(%x) before reset\n", val);
208 hc->hw.cirm = HFCPCI_RESET; /* Reset On */
209 Write_hfc(hc, HFCPCI_CIRM, hc->hw.cirm);
210 set_current_state(TASK_UNINTERRUPTIBLE);
211 mdelay(10); /* Timeout 10ms */
212 hc->hw.cirm = 0; /* Reset Off */
213 Write_hfc(hc, HFCPCI_CIRM, hc->hw.cirm);
214 val = Read_hfc(hc, HFCPCI_STATUS);
215 printk(KERN_DEBUG "HFC-PCI status(%x) after reset\n", val);
216 while (cnt < 50000) { /* max 50000 us */
217 udelay(5);
218 cnt += 5;
219 val = Read_hfc(hc, HFCPCI_STATUS);
220 if (!(val & 2))
221 break;
222 }
223 printk(KERN_DEBUG "HFC-PCI status(%x) after %dus\n", val, cnt);
224
225 hc->hw.fifo_en = 0x30; /* only D fifos enabled */
226
227 hc->hw.bswapped = 0; /* no exchange */
228 hc->hw.ctmt = HFCPCI_TIM3_125 | HFCPCI_AUTO_TIMER;
229 hc->hw.trm = HFCPCI_BTRANS_THRESMASK; /* no echo connect , threshold */
230 hc->hw.sctrl = 0x40; /* set tx_lo mode, error in datasheet ! */
231 hc->hw.sctrl_r = 0;
232 hc->hw.sctrl_e = HFCPCI_AUTO_AWAKE; /* S/T Auto awake */
233 hc->hw.mst_m = 0;
234 if (test_bit(HFC_CFG_MASTER, &hc->cfg))
235 hc->hw.mst_m |= HFCPCI_MASTER; /* HFC Master Mode */
236 if (test_bit(HFC_CFG_NEG_F0, &hc->cfg))
237 hc->hw.mst_m |= HFCPCI_F0_NEGATIV;
238 Write_hfc(hc, HFCPCI_FIFO_EN, hc->hw.fifo_en);
239 Write_hfc(hc, HFCPCI_TRM, hc->hw.trm);
240 Write_hfc(hc, HFCPCI_SCTRL_E, hc->hw.sctrl_e);
241 Write_hfc(hc, HFCPCI_CTMT, hc->hw.ctmt);
242
243 hc->hw.int_m1 = HFCPCI_INTS_DTRANS | HFCPCI_INTS_DREC |
244 HFCPCI_INTS_L1STATE | HFCPCI_INTS_TIMER;
245 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
246
247 /* Clear already pending ints */
248 val = Read_hfc(hc, HFCPCI_INT_S1);
249
250 /* set NT/TE mode */
251 hfcpci_setmode(hc);
252
253 Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
254 Write_hfc(hc, HFCPCI_SCTRL_R, hc->hw.sctrl_r);
255
256 /*
257 * Init GCI/IOM2 in master mode
258 * Slots 0 and 1 are set for B-chan 1 and 2
259 * D- and monitor/CI channel are not enabled
260 * STIO1 is used as output for data, B1+B2 from ST->IOM+HFC
261 * STIO2 is used as data input, B1+B2 from IOM->ST
262 * ST B-channel send disabled -> continuous 1s
263 * The IOM slots are always enabled
264 */
265 if (test_bit(HFC_CFG_PCM, &hc->cfg)) {
266 /* set data flow directions: connect B1,B2: HFC to/from PCM */
267 hc->hw.conn = 0x09;
268 } else {
269 hc->hw.conn = 0x36; /* set data flow directions */
270 if (test_bit(HFC_CFG_SW_DD_DU, &hc->cfg)) {
271 Write_hfc(hc, HFCPCI_B1_SSL, 0xC0);
272 Write_hfc(hc, HFCPCI_B2_SSL, 0xC1);
273 Write_hfc(hc, HFCPCI_B1_RSL, 0xC0);
274 Write_hfc(hc, HFCPCI_B2_RSL, 0xC1);
275 } else {
276 Write_hfc(hc, HFCPCI_B1_SSL, 0x80);
277 Write_hfc(hc, HFCPCI_B2_SSL, 0x81);
278 Write_hfc(hc, HFCPCI_B1_RSL, 0x80);
279 Write_hfc(hc, HFCPCI_B2_RSL, 0x81);
280 }
281 }
282 Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn);
283 val = Read_hfc(hc, HFCPCI_INT_S2);
284 }
285
286 /*
287 * Timer function called when kernel timer expires
288 */
289 static void
290 hfcpci_Timer(struct timer_list *t)
291 {
292 struct hfc_pci *hc = from_timer(hc, t, hw.timer);
293 hc->hw.timer.expires = jiffies + 75;
294 /* WD RESET */
295 /*
296 * WriteReg(hc, HFCD_DATA, HFCD_CTMT, hc->hw.ctmt | 0x80);
297 * add_timer(&hc->hw.timer);
298 */
299 }
300
301
302 /*
303 * select a b-channel entry matching and active
304 */
305 static struct bchannel *
306 Sel_BCS(struct hfc_pci *hc, int channel)
307 {
308 if (test_bit(FLG_ACTIVE, &hc->bch[0].Flags) &&
309 (hc->bch[0].nr & channel))
310 return &hc->bch[0];
311 else if (test_bit(FLG_ACTIVE, &hc->bch[1].Flags) &&
312 (hc->bch[1].nr & channel))
313 return &hc->bch[1];
314 else
315 return NULL;
316 }
317
318 /*
319 * clear the desired B-channel rx fifo
320 */
321 static void
322 hfcpci_clear_fifo_rx(struct hfc_pci *hc, int fifo)
323 {
324 u_char fifo_state;
325 struct bzfifo *bzr;
326
327 if (fifo) {
328 bzr = &((union fifo_area *)(hc->hw.fifos))->b_chans.rxbz_b2;
329 fifo_state = hc->hw.fifo_en & HFCPCI_FIFOEN_B2RX;
330 } else {
331 bzr = &((union fifo_area *)(hc->hw.fifos))->b_chans.rxbz_b1;
332 fifo_state = hc->hw.fifo_en & HFCPCI_FIFOEN_B1RX;
333 }
334 if (fifo_state)
335 hc->hw.fifo_en ^= fifo_state;
336 Write_hfc(hc, HFCPCI_FIFO_EN, hc->hw.fifo_en);
337 hc->hw.last_bfifo_cnt[fifo] = 0;
338 bzr->f1 = MAX_B_FRAMES;
339 bzr->f2 = bzr->f1; /* init F pointers to remain constant */
340 bzr->za[MAX_B_FRAMES].z1 = cpu_to_le16(B_FIFO_SIZE + B_SUB_VAL - 1);
341 bzr->za[MAX_B_FRAMES].z2 = cpu_to_le16(
342 le16_to_cpu(bzr->za[MAX_B_FRAMES].z1));
343 if (fifo_state)
344 hc->hw.fifo_en |= fifo_state;
345 Write_hfc(hc, HFCPCI_FIFO_EN, hc->hw.fifo_en);
346 }
347
348 /*
349 * clear the desired B-channel tx fifo
350 */
351 static void hfcpci_clear_fifo_tx(struct hfc_pci *hc, int fifo)
352 {
353 u_char fifo_state;
354 struct bzfifo *bzt;
355
356 if (fifo) {
357 bzt = &((union fifo_area *)(hc->hw.fifos))->b_chans.txbz_b2;
358 fifo_state = hc->hw.fifo_en & HFCPCI_FIFOEN_B2TX;
359 } else {
360 bzt = &((union fifo_area *)(hc->hw.fifos))->b_chans.txbz_b1;
361 fifo_state = hc->hw.fifo_en & HFCPCI_FIFOEN_B1TX;
362 }
363 if (fifo_state)
364 hc->hw.fifo_en ^= fifo_state;
365 Write_hfc(hc, HFCPCI_FIFO_EN, hc->hw.fifo_en);
366 if (hc->bch[fifo].debug & DEBUG_HW_BCHANNEL)
367 printk(KERN_DEBUG "hfcpci_clear_fifo_tx%d f1(%x) f2(%x) "
368 "z1(%x) z2(%x) state(%x)\n",
369 fifo, bzt->f1, bzt->f2,
370 le16_to_cpu(bzt->za[MAX_B_FRAMES].z1),
371 le16_to_cpu(bzt->za[MAX_B_FRAMES].z2),
372 fifo_state);
373 bzt->f2 = MAX_B_FRAMES;
374 bzt->f1 = bzt->f2; /* init F pointers to remain constant */
375 bzt->za[MAX_B_FRAMES].z1 = cpu_to_le16(B_FIFO_SIZE + B_SUB_VAL - 1);
376 bzt->za[MAX_B_FRAMES].z2 = cpu_to_le16(B_FIFO_SIZE + B_SUB_VAL - 2);
377 if (fifo_state)
378 hc->hw.fifo_en |= fifo_state;
379 Write_hfc(hc, HFCPCI_FIFO_EN, hc->hw.fifo_en);
380 if (hc->bch[fifo].debug & DEBUG_HW_BCHANNEL)
381 printk(KERN_DEBUG
382 "hfcpci_clear_fifo_tx%d f1(%x) f2(%x) z1(%x) z2(%x)\n",
383 fifo, bzt->f1, bzt->f2,
384 le16_to_cpu(bzt->za[MAX_B_FRAMES].z1),
385 le16_to_cpu(bzt->za[MAX_B_FRAMES].z2));
386 }
387
388 /*
389 * read a complete B-frame out of the buffer
390 */
391 static void
392 hfcpci_empty_bfifo(struct bchannel *bch, struct bzfifo *bz,
393 u_char *bdata, int count)
394 {
395 u_char *ptr, *ptr1, new_f2;
396 int maxlen, new_z2;
397 struct zt *zp;
398
399 if ((bch->debug & DEBUG_HW_BCHANNEL) && !(bch->debug & DEBUG_HW_BFIFO))
400 printk(KERN_DEBUG "hfcpci_empty_fifo\n");
401 zp = &bz->za[bz->f2]; /* point to Z-Regs */
402 new_z2 = le16_to_cpu(zp->z2) + count; /* new position in fifo */
403 if (new_z2 >= (B_FIFO_SIZE + B_SUB_VAL))
404 new_z2 -= B_FIFO_SIZE; /* buffer wrap */
405 new_f2 = (bz->f2 + 1) & MAX_B_FRAMES;
406 if ((count > MAX_DATA_SIZE + 3) || (count < 4) ||
407 (*(bdata + (le16_to_cpu(zp->z1) - B_SUB_VAL)))) {
408 if (bch->debug & DEBUG_HW)
409 printk(KERN_DEBUG "hfcpci_empty_fifo: incoming packet "
410 "invalid length %d or crc\n", count);
411 #ifdef ERROR_STATISTIC
412 bch->err_inv++;
413 #endif
414 bz->za[new_f2].z2 = cpu_to_le16(new_z2);
415 bz->f2 = new_f2; /* next buffer */
416 } else {
417 bch->rx_skb = mI_alloc_skb(count - 3, GFP_ATOMIC);
418 if (!bch->rx_skb) {
419 printk(KERN_WARNING "HFCPCI: receive out of memory\n");
420 return;
421 }
422 count -= 3;
423 ptr = skb_put(bch->rx_skb, count);
424
425 if (le16_to_cpu(zp->z2) + count <= B_FIFO_SIZE + B_SUB_VAL)
426 maxlen = count; /* complete transfer */
427 else
428 maxlen = B_FIFO_SIZE + B_SUB_VAL -
429 le16_to_cpu(zp->z2); /* maximum */
430
431 ptr1 = bdata + (le16_to_cpu(zp->z2) - B_SUB_VAL);
432 /* start of data */
433 memcpy(ptr, ptr1, maxlen); /* copy data */
434 count -= maxlen;
435
436 if (count) { /* rest remaining */
437 ptr += maxlen;
438 ptr1 = bdata; /* start of buffer */
439 memcpy(ptr, ptr1, count); /* rest */
440 }
441 bz->za[new_f2].z2 = cpu_to_le16(new_z2);
442 bz->f2 = new_f2; /* next buffer */
443 recv_Bchannel(bch, MISDN_ID_ANY, false);
444 }
445 }
446
447 /*
448 * D-channel receive procedure
449 */
450 static int
451 receive_dmsg(struct hfc_pci *hc)
452 {
453 struct dchannel *dch = &hc->dch;
454 int maxlen;
455 int rcnt, total;
456 int count = 5;
457 u_char *ptr, *ptr1;
458 struct dfifo *df;
459 struct zt *zp;
460
461 df = &((union fifo_area *)(hc->hw.fifos))->d_chan.d_rx;
462 while (((df->f1 & D_FREG_MASK) != (df->f2 & D_FREG_MASK)) && count--) {
463 zp = &df->za[df->f2 & D_FREG_MASK];
464 rcnt = le16_to_cpu(zp->z1) - le16_to_cpu(zp->z2);
465 if (rcnt < 0)
466 rcnt += D_FIFO_SIZE;
467 rcnt++;
468 if (dch->debug & DEBUG_HW_DCHANNEL)
469 printk(KERN_DEBUG
470 "hfcpci recd f1(%d) f2(%d) z1(%x) z2(%x) cnt(%d)\n",
471 df->f1, df->f2,
472 le16_to_cpu(zp->z1),
473 le16_to_cpu(zp->z2),
474 rcnt);
475
476 if ((rcnt > MAX_DFRAME_LEN + 3) || (rcnt < 4) ||
477 (df->data[le16_to_cpu(zp->z1)])) {
478 if (dch->debug & DEBUG_HW)
479 printk(KERN_DEBUG
480 "empty_fifo hfcpci packet inv. len "
481 "%d or crc %d\n",
482 rcnt,
483 df->data[le16_to_cpu(zp->z1)]);
484 #ifdef ERROR_STATISTIC
485 cs->err_rx++;
486 #endif
487 df->f2 = ((df->f2 + 1) & MAX_D_FRAMES) |
488 (MAX_D_FRAMES + 1); /* next buffer */
489 df->za[df->f2 & D_FREG_MASK].z2 =
490 cpu_to_le16((le16_to_cpu(zp->z2) + rcnt) &
491 (D_FIFO_SIZE - 1));
492 } else {
493 dch->rx_skb = mI_alloc_skb(rcnt - 3, GFP_ATOMIC);
494 if (!dch->rx_skb) {
495 printk(KERN_WARNING
496 "HFC-PCI: D receive out of memory\n");
497 break;
498 }
499 total = rcnt;
500 rcnt -= 3;
501 ptr = skb_put(dch->rx_skb, rcnt);
502
503 if (le16_to_cpu(zp->z2) + rcnt <= D_FIFO_SIZE)
504 maxlen = rcnt; /* complete transfer */
505 else
506 maxlen = D_FIFO_SIZE - le16_to_cpu(zp->z2);
507 /* maximum */
508
509 ptr1 = df->data + le16_to_cpu(zp->z2);
510 /* start of data */
511 memcpy(ptr, ptr1, maxlen); /* copy data */
512 rcnt -= maxlen;
513
514 if (rcnt) { /* rest remaining */
515 ptr += maxlen;
516 ptr1 = df->data; /* start of buffer */
517 memcpy(ptr, ptr1, rcnt); /* rest */
518 }
519 df->f2 = ((df->f2 + 1) & MAX_D_FRAMES) |
520 (MAX_D_FRAMES + 1); /* next buffer */
521 df->za[df->f2 & D_FREG_MASK].z2 = cpu_to_le16((
522 le16_to_cpu(zp->z2) + total) & (D_FIFO_SIZE - 1));
523 recv_Dchannel(dch);
524 }
525 }
526 return 1;
527 }
528
529 /*
530 * check for transparent receive data and read max one 'poll' size if avail
531 */
532 static void
533 hfcpci_empty_fifo_trans(struct bchannel *bch, struct bzfifo *rxbz,
534 struct bzfifo *txbz, u_char *bdata)
535 {
536 __le16 *z1r, *z2r, *z1t, *z2t;
537 int new_z2, fcnt_rx, fcnt_tx, maxlen;
538 u_char *ptr, *ptr1;
539
540 z1r = &rxbz->za[MAX_B_FRAMES].z1; /* pointer to z reg */
541 z2r = z1r + 1;
542 z1t = &txbz->za[MAX_B_FRAMES].z1;
543 z2t = z1t + 1;
544
545 fcnt_rx = le16_to_cpu(*z1r) - le16_to_cpu(*z2r);
546 if (!fcnt_rx)
547 return; /* no data avail */
548
549 if (fcnt_rx <= 0)
550 fcnt_rx += B_FIFO_SIZE; /* bytes actually buffered */
551 new_z2 = le16_to_cpu(*z2r) + fcnt_rx; /* new position in fifo */
552 if (new_z2 >= (B_FIFO_SIZE + B_SUB_VAL))
553 new_z2 -= B_FIFO_SIZE; /* buffer wrap */
554
555 fcnt_tx = le16_to_cpu(*z2t) - le16_to_cpu(*z1t);
556 if (fcnt_tx <= 0)
557 fcnt_tx += B_FIFO_SIZE;
558 /* fcnt_tx contains available bytes in tx-fifo */
559 fcnt_tx = B_FIFO_SIZE - fcnt_tx;
560 /* remaining bytes to send (bytes in tx-fifo) */
561
562 if (test_bit(FLG_RX_OFF, &bch->Flags)) {
563 bch->dropcnt += fcnt_rx;
564 *z2r = cpu_to_le16(new_z2);
565 return;
566 }
567 maxlen = bchannel_get_rxbuf(bch, fcnt_rx);
568 if (maxlen < 0) {
569 pr_warn("B%d: No bufferspace for %d bytes\n", bch->nr, fcnt_rx);
570 } else {
571 ptr = skb_put(bch->rx_skb, fcnt_rx);
572 if (le16_to_cpu(*z2r) + fcnt_rx <= B_FIFO_SIZE + B_SUB_VAL)
573 maxlen = fcnt_rx; /* complete transfer */
574 else
575 maxlen = B_FIFO_SIZE + B_SUB_VAL - le16_to_cpu(*z2r);
576 /* maximum */
577
578 ptr1 = bdata + (le16_to_cpu(*z2r) - B_SUB_VAL);
579 /* start of data */
580 memcpy(ptr, ptr1, maxlen); /* copy data */
581 fcnt_rx -= maxlen;
582
583 if (fcnt_rx) { /* rest remaining */
584 ptr += maxlen;
585 ptr1 = bdata; /* start of buffer */
586 memcpy(ptr, ptr1, fcnt_rx); /* rest */
587 }
588 recv_Bchannel(bch, fcnt_tx, false); /* bch, id, !force */
589 }
590 *z2r = cpu_to_le16(new_z2); /* new position */
591 }
592
593 /*
594 * B-channel main receive routine
595 */
596 static void
597 main_rec_hfcpci(struct bchannel *bch)
598 {
599 struct hfc_pci *hc = bch->hw;
600 int rcnt, real_fifo;
601 int receive = 0, count = 5;
602 struct bzfifo *txbz, *rxbz;
603 u_char *bdata;
604 struct zt *zp;
605
606 if ((bch->nr & 2) && (!hc->hw.bswapped)) {
607 rxbz = &((union fifo_area *)(hc->hw.fifos))->b_chans.rxbz_b2;
608 txbz = &((union fifo_area *)(hc->hw.fifos))->b_chans.txbz_b2;
609 bdata = ((union fifo_area *)(hc->hw.fifos))->b_chans.rxdat_b2;
610 real_fifo = 1;
611 } else {
612 rxbz = &((union fifo_area *)(hc->hw.fifos))->b_chans.rxbz_b1;
613 txbz = &((union fifo_area *)(hc->hw.fifos))->b_chans.txbz_b1;
614 bdata = ((union fifo_area *)(hc->hw.fifos))->b_chans.rxdat_b1;
615 real_fifo = 0;
616 }
617 Begin:
618 count--;
619 if (rxbz->f1 != rxbz->f2) {
620 if (bch->debug & DEBUG_HW_BCHANNEL)
621 printk(KERN_DEBUG "hfcpci rec ch(%x) f1(%d) f2(%d)\n",
622 bch->nr, rxbz->f1, rxbz->f2);
623 zp = &rxbz->za[rxbz->f2];
624
625 rcnt = le16_to_cpu(zp->z1) - le16_to_cpu(zp->z2);
626 if (rcnt < 0)
627 rcnt += B_FIFO_SIZE;
628 rcnt++;
629 if (bch->debug & DEBUG_HW_BCHANNEL)
630 printk(KERN_DEBUG
631 "hfcpci rec ch(%x) z1(%x) z2(%x) cnt(%d)\n",
632 bch->nr, le16_to_cpu(zp->z1),
633 le16_to_cpu(zp->z2), rcnt);
634 hfcpci_empty_bfifo(bch, rxbz, bdata, rcnt);
635 rcnt = rxbz->f1 - rxbz->f2;
636 if (rcnt < 0)
637 rcnt += MAX_B_FRAMES + 1;
638 if (hc->hw.last_bfifo_cnt[real_fifo] > rcnt + 1) {
639 rcnt = 0;
640 hfcpci_clear_fifo_rx(hc, real_fifo);
641 }
642 hc->hw.last_bfifo_cnt[real_fifo] = rcnt;
643 if (rcnt > 1)
644 receive = 1;
645 else
646 receive = 0;
647 } else if (test_bit(FLG_TRANSPARENT, &bch->Flags)) {
648 hfcpci_empty_fifo_trans(bch, rxbz, txbz, bdata);
649 return;
650 } else
651 receive = 0;
652 if (count && receive)
653 goto Begin;
654
655 }
656
657 /*
658 * D-channel send routine
659 */
660 static void
661 hfcpci_fill_dfifo(struct hfc_pci *hc)
662 {
663 struct dchannel *dch = &hc->dch;
664 int fcnt;
665 int count, new_z1, maxlen;
666 struct dfifo *df;
667 u_char *src, *dst, new_f1;
668
669 if ((dch->debug & DEBUG_HW_DCHANNEL) && !(dch->debug & DEBUG_HW_DFIFO))
670 printk(KERN_DEBUG "%s\n", __func__);
671
672 if (!dch->tx_skb)
673 return;
674 count = dch->tx_skb->len - dch->tx_idx;
675 if (count <= 0)
676 return;
677 df = &((union fifo_area *) (hc->hw.fifos))->d_chan.d_tx;
678
679 if (dch->debug & DEBUG_HW_DFIFO)
680 printk(KERN_DEBUG "%s:f1(%d) f2(%d) z1(f1)(%x)\n", __func__,
681 df->f1, df->f2,
682 le16_to_cpu(df->za[df->f1 & D_FREG_MASK].z1));
683 fcnt = df->f1 - df->f2; /* frame count actually buffered */
684 if (fcnt < 0)
685 fcnt += (MAX_D_FRAMES + 1); /* if wrap around */
686 if (fcnt > (MAX_D_FRAMES - 1)) {
687 if (dch->debug & DEBUG_HW_DCHANNEL)
688 printk(KERN_DEBUG
689 "hfcpci_fill_Dfifo more as 14 frames\n");
690 #ifdef ERROR_STATISTIC
691 cs->err_tx++;
692 #endif
693 return;
694 }
695 /* now determine free bytes in FIFO buffer */
696 maxlen = le16_to_cpu(df->za[df->f2 & D_FREG_MASK].z2) -
697 le16_to_cpu(df->za[df->f1 & D_FREG_MASK].z1) - 1;
698 if (maxlen <= 0)
699 maxlen += D_FIFO_SIZE; /* count now contains available bytes */
700
701 if (dch->debug & DEBUG_HW_DCHANNEL)
702 printk(KERN_DEBUG "hfcpci_fill_Dfifo count(%d/%d)\n",
703 count, maxlen);
704 if (count > maxlen) {
705 if (dch->debug & DEBUG_HW_DCHANNEL)
706 printk(KERN_DEBUG "hfcpci_fill_Dfifo no fifo mem\n");
707 return;
708 }
709 new_z1 = (le16_to_cpu(df->za[df->f1 & D_FREG_MASK].z1) + count) &
710 (D_FIFO_SIZE - 1);
711 new_f1 = ((df->f1 + 1) & D_FREG_MASK) | (D_FREG_MASK + 1);
712 src = dch->tx_skb->data + dch->tx_idx; /* source pointer */
713 dst = df->data + le16_to_cpu(df->za[df->f1 & D_FREG_MASK].z1);
714 maxlen = D_FIFO_SIZE - le16_to_cpu(df->za[df->f1 & D_FREG_MASK].z1);
715 /* end fifo */
716 if (maxlen > count)
717 maxlen = count; /* limit size */
718 memcpy(dst, src, maxlen); /* first copy */
719
720 count -= maxlen; /* remaining bytes */
721 if (count) {
722 dst = df->data; /* start of buffer */
723 src += maxlen; /* new position */
724 memcpy(dst, src, count);
725 }
726 df->za[new_f1 & D_FREG_MASK].z1 = cpu_to_le16(new_z1);
727 /* for next buffer */
728 df->za[df->f1 & D_FREG_MASK].z1 = cpu_to_le16(new_z1);
729 /* new pos actual buffer */
730 df->f1 = new_f1; /* next frame */
731 dch->tx_idx = dch->tx_skb->len;
732 }
733
734 /*
735 * B-channel send routine
736 */
737 static void
738 hfcpci_fill_fifo(struct bchannel *bch)
739 {
740 struct hfc_pci *hc = bch->hw;
741 int maxlen, fcnt;
742 int count, new_z1;
743 struct bzfifo *bz;
744 u_char *bdata;
745 u_char new_f1, *src, *dst;
746 __le16 *z1t, *z2t;
747
748 if ((bch->debug & DEBUG_HW_BCHANNEL) && !(bch->debug & DEBUG_HW_BFIFO))
749 printk(KERN_DEBUG "%s\n", __func__);
750 if ((!bch->tx_skb) || bch->tx_skb->len == 0) {
751 if (!test_bit(FLG_FILLEMPTY, &bch->Flags) &&
752 !test_bit(FLG_TRANSPARENT, &bch->Flags))
753 return;
754 count = HFCPCI_FILLEMPTY;
755 } else {
756 count = bch->tx_skb->len - bch->tx_idx;
757 }
758 if ((bch->nr & 2) && (!hc->hw.bswapped)) {
759 bz = &((union fifo_area *)(hc->hw.fifos))->b_chans.txbz_b2;
760 bdata = ((union fifo_area *)(hc->hw.fifos))->b_chans.txdat_b2;
761 } else {
762 bz = &((union fifo_area *)(hc->hw.fifos))->b_chans.txbz_b1;
763 bdata = ((union fifo_area *)(hc->hw.fifos))->b_chans.txdat_b1;
764 }
765
766 if (test_bit(FLG_TRANSPARENT, &bch->Flags)) {
767 z1t = &bz->za[MAX_B_FRAMES].z1;
768 z2t = z1t + 1;
769 if (bch->debug & DEBUG_HW_BCHANNEL)
770 printk(KERN_DEBUG "hfcpci_fill_fifo_trans ch(%x) "
771 "cnt(%d) z1(%x) z2(%x)\n", bch->nr, count,
772 le16_to_cpu(*z1t), le16_to_cpu(*z2t));
773 fcnt = le16_to_cpu(*z2t) - le16_to_cpu(*z1t);
774 if (fcnt <= 0)
775 fcnt += B_FIFO_SIZE;
776 if (test_bit(FLG_FILLEMPTY, &bch->Flags)) {
777 /* fcnt contains available bytes in fifo */
778 if (count > fcnt)
779 count = fcnt;
780 new_z1 = le16_to_cpu(*z1t) + count;
781 /* new buffer Position */
782 if (new_z1 >= (B_FIFO_SIZE + B_SUB_VAL))
783 new_z1 -= B_FIFO_SIZE; /* buffer wrap */
784 dst = bdata + (le16_to_cpu(*z1t) - B_SUB_VAL);
785 maxlen = (B_FIFO_SIZE + B_SUB_VAL) - le16_to_cpu(*z1t);
786 /* end of fifo */
787 if (bch->debug & DEBUG_HW_BFIFO)
788 printk(KERN_DEBUG "hfcpci_FFt fillempty "
789 "fcnt(%d) maxl(%d) nz1(%x) dst(%p)\n",
790 fcnt, maxlen, new_z1, dst);
791 if (maxlen > count)
792 maxlen = count; /* limit size */
793 memset(dst, bch->fill[0], maxlen); /* first copy */
794 count -= maxlen; /* remaining bytes */
795 if (count) {
796 dst = bdata; /* start of buffer */
797 memset(dst, bch->fill[0], count);
798 }
799 *z1t = cpu_to_le16(new_z1); /* now send data */
800 return;
801 }
802 /* fcnt contains available bytes in fifo */
803 fcnt = B_FIFO_SIZE - fcnt;
804 /* remaining bytes to send (bytes in fifo) */
805
806 next_t_frame:
807 count = bch->tx_skb->len - bch->tx_idx;
808 /* maximum fill shall be poll*2 */
809 if (count > (poll << 1) - fcnt)
810 count = (poll << 1) - fcnt;
811 if (count <= 0)
812 return;
813 /* data is suitable for fifo */
814 new_z1 = le16_to_cpu(*z1t) + count;
815 /* new buffer Position */
816 if (new_z1 >= (B_FIFO_SIZE + B_SUB_VAL))
817 new_z1 -= B_FIFO_SIZE; /* buffer wrap */
818 src = bch->tx_skb->data + bch->tx_idx;
819 /* source pointer */
820 dst = bdata + (le16_to_cpu(*z1t) - B_SUB_VAL);
821 maxlen = (B_FIFO_SIZE + B_SUB_VAL) - le16_to_cpu(*z1t);
822 /* end of fifo */
823 if (bch->debug & DEBUG_HW_BFIFO)
824 printk(KERN_DEBUG "hfcpci_FFt fcnt(%d) "
825 "maxl(%d) nz1(%x) dst(%p)\n",
826 fcnt, maxlen, new_z1, dst);
827 fcnt += count;
828 bch->tx_idx += count;
829 if (maxlen > count)
830 maxlen = count; /* limit size */
831 memcpy(dst, src, maxlen); /* first copy */
832 count -= maxlen; /* remaining bytes */
833 if (count) {
834 dst = bdata; /* start of buffer */
835 src += maxlen; /* new position */
836 memcpy(dst, src, count);
837 }
838 *z1t = cpu_to_le16(new_z1); /* now send data */
839 if (bch->tx_idx < bch->tx_skb->len)
840 return;
841 dev_kfree_skb(bch->tx_skb);
842 if (get_next_bframe(bch))
843 goto next_t_frame;
844 return;
845 }
846 if (bch->debug & DEBUG_HW_BCHANNEL)
847 printk(KERN_DEBUG
848 "%s: ch(%x) f1(%d) f2(%d) z1(f1)(%x)\n",
849 __func__, bch->nr, bz->f1, bz->f2,
850 bz->za[bz->f1].z1);
851 fcnt = bz->f1 - bz->f2; /* frame count actually buffered */
852 if (fcnt < 0)
853 fcnt += (MAX_B_FRAMES + 1); /* if wrap around */
854 if (fcnt > (MAX_B_FRAMES - 1)) {
855 if (bch->debug & DEBUG_HW_BCHANNEL)
856 printk(KERN_DEBUG
857 "hfcpci_fill_Bfifo more as 14 frames\n");
858 return;
859 }
860 /* now determine free bytes in FIFO buffer */
861 maxlen = le16_to_cpu(bz->za[bz->f2].z2) -
862 le16_to_cpu(bz->za[bz->f1].z1) - 1;
863 if (maxlen <= 0)
864 maxlen += B_FIFO_SIZE; /* count now contains available bytes */
865
866 if (bch->debug & DEBUG_HW_BCHANNEL)
867 printk(KERN_DEBUG "hfcpci_fill_fifo ch(%x) count(%d/%d)\n",
868 bch->nr, count, maxlen);
869
870 if (maxlen < count) {
871 if (bch->debug & DEBUG_HW_BCHANNEL)
872 printk(KERN_DEBUG "hfcpci_fill_fifo no fifo mem\n");
873 return;
874 }
875 new_z1 = le16_to_cpu(bz->za[bz->f1].z1) + count;
876 /* new buffer Position */
877 if (new_z1 >= (B_FIFO_SIZE + B_SUB_VAL))
878 new_z1 -= B_FIFO_SIZE; /* buffer wrap */
879
880 new_f1 = ((bz->f1 + 1) & MAX_B_FRAMES);
881 src = bch->tx_skb->data + bch->tx_idx; /* source pointer */
882 dst = bdata + (le16_to_cpu(bz->za[bz->f1].z1) - B_SUB_VAL);
883 maxlen = (B_FIFO_SIZE + B_SUB_VAL) - le16_to_cpu(bz->za[bz->f1].z1);
884 /* end fifo */
885 if (maxlen > count)
886 maxlen = count; /* limit size */
887 memcpy(dst, src, maxlen); /* first copy */
888
889 count -= maxlen; /* remaining bytes */
890 if (count) {
891 dst = bdata; /* start of buffer */
892 src += maxlen; /* new position */
893 memcpy(dst, src, count);
894 }
895 bz->za[new_f1].z1 = cpu_to_le16(new_z1); /* for next buffer */
896 bz->f1 = new_f1; /* next frame */
897 dev_kfree_skb(bch->tx_skb);
898 get_next_bframe(bch);
899 }
900
901
902
903 /*
904 * handle L1 state changes TE
905 */
906
907 static void
908 ph_state_te(struct dchannel *dch)
909 {
910 if (dch->debug)
911 printk(KERN_DEBUG "%s: TE newstate %x\n",
912 __func__, dch->state);
913 switch (dch->state) {
914 case 0:
915 l1_event(dch->l1, HW_RESET_IND);
916 break;
917 case 3:
918 l1_event(dch->l1, HW_DEACT_IND);
919 break;
920 case 5:
921 case 8:
922 l1_event(dch->l1, ANYSIGNAL);
923 break;
924 case 6:
925 l1_event(dch->l1, INFO2);
926 break;
927 case 7:
928 l1_event(dch->l1, INFO4_P8);
929 break;
930 }
931 }
932
933 /*
934 * handle L1 state changes NT
935 */
936
937 static void
938 handle_nt_timer3(struct dchannel *dch) {
939 struct hfc_pci *hc = dch->hw;
940
941 test_and_clear_bit(FLG_HFC_TIMER_T3, &dch->Flags);
942 hc->hw.int_m1 &= ~HFCPCI_INTS_TIMER;
943 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
944 hc->hw.nt_timer = 0;
945 test_and_set_bit(FLG_ACTIVE, &dch->Flags);
946 if (test_bit(HFC_CFG_MASTER, &hc->cfg))
947 hc->hw.mst_m |= HFCPCI_MASTER;
948 Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
949 _queue_data(&dch->dev.D, PH_ACTIVATE_IND,
950 MISDN_ID_ANY, 0, NULL, GFP_ATOMIC);
951 }
952
953 static void
954 ph_state_nt(struct dchannel *dch)
955 {
956 struct hfc_pci *hc = dch->hw;
957
958 if (dch->debug)
959 printk(KERN_DEBUG "%s: NT newstate %x\n",
960 __func__, dch->state);
961 switch (dch->state) {
962 case 2:
963 if (hc->hw.nt_timer < 0) {
964 hc->hw.nt_timer = 0;
965 test_and_clear_bit(FLG_HFC_TIMER_T3, &dch->Flags);
966 test_and_clear_bit(FLG_HFC_TIMER_T1, &dch->Flags);
967 hc->hw.int_m1 &= ~HFCPCI_INTS_TIMER;
968 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
969 /* Clear already pending ints */
970 (void) Read_hfc(hc, HFCPCI_INT_S1);
971 Write_hfc(hc, HFCPCI_STATES, 4 | HFCPCI_LOAD_STATE);
972 udelay(10);
973 Write_hfc(hc, HFCPCI_STATES, 4);
974 dch->state = 4;
975 } else if (hc->hw.nt_timer == 0) {
976 hc->hw.int_m1 |= HFCPCI_INTS_TIMER;
977 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
978 hc->hw.nt_timer = NT_T1_COUNT;
979 hc->hw.ctmt &= ~HFCPCI_AUTO_TIMER;
980 hc->hw.ctmt |= HFCPCI_TIM3_125;
981 Write_hfc(hc, HFCPCI_CTMT, hc->hw.ctmt |
982 HFCPCI_CLTIMER);
983 test_and_clear_bit(FLG_HFC_TIMER_T3, &dch->Flags);
984 test_and_set_bit(FLG_HFC_TIMER_T1, &dch->Flags);
985 /* allow G2 -> G3 transition */
986 Write_hfc(hc, HFCPCI_STATES, 2 | HFCPCI_NT_G2_G3);
987 } else {
988 Write_hfc(hc, HFCPCI_STATES, 2 | HFCPCI_NT_G2_G3);
989 }
990 break;
991 case 1:
992 hc->hw.nt_timer = 0;
993 test_and_clear_bit(FLG_HFC_TIMER_T3, &dch->Flags);
994 test_and_clear_bit(FLG_HFC_TIMER_T1, &dch->Flags);
995 hc->hw.int_m1 &= ~HFCPCI_INTS_TIMER;
996 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
997 test_and_clear_bit(FLG_ACTIVE, &dch->Flags);
998 hc->hw.mst_m &= ~HFCPCI_MASTER;
999 Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
1000 test_and_clear_bit(FLG_L2_ACTIVATED, &dch->Flags);
1001 _queue_data(&dch->dev.D, PH_DEACTIVATE_IND,
1002 MISDN_ID_ANY, 0, NULL, GFP_ATOMIC);
1003 break;
1004 case 4:
1005 hc->hw.nt_timer = 0;
1006 test_and_clear_bit(FLG_HFC_TIMER_T3, &dch->Flags);
1007 test_and_clear_bit(FLG_HFC_TIMER_T1, &dch->Flags);
1008 hc->hw.int_m1 &= ~HFCPCI_INTS_TIMER;
1009 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
1010 break;
1011 case 3:
1012 if (!test_and_set_bit(FLG_HFC_TIMER_T3, &dch->Flags)) {
1013 if (!test_and_clear_bit(FLG_L2_ACTIVATED,
1014 &dch->Flags)) {
1015 handle_nt_timer3(dch);
1016 break;
1017 }
1018 test_and_clear_bit(FLG_HFC_TIMER_T1, &dch->Flags);
1019 hc->hw.int_m1 |= HFCPCI_INTS_TIMER;
1020 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
1021 hc->hw.nt_timer = NT_T3_COUNT;
1022 hc->hw.ctmt &= ~HFCPCI_AUTO_TIMER;
1023 hc->hw.ctmt |= HFCPCI_TIM3_125;
1024 Write_hfc(hc, HFCPCI_CTMT, hc->hw.ctmt |
1025 HFCPCI_CLTIMER);
1026 }
1027 break;
1028 }
1029 }
1030
1031 static void
1032 ph_state(struct dchannel *dch)
1033 {
1034 struct hfc_pci *hc = dch->hw;
1035
1036 if (hc->hw.protocol == ISDN_P_NT_S0) {
1037 if (test_bit(FLG_HFC_TIMER_T3, &dch->Flags) &&
1038 hc->hw.nt_timer < 0)
1039 handle_nt_timer3(dch);
1040 else
1041 ph_state_nt(dch);
1042 } else
1043 ph_state_te(dch);
1044 }
1045
1046 /*
1047 * Layer 1 callback function
1048 */
1049 static int
1050 hfc_l1callback(struct dchannel *dch, u_int cmd)
1051 {
1052 struct hfc_pci *hc = dch->hw;
1053
1054 switch (cmd) {
1055 case INFO3_P8:
1056 case INFO3_P10:
1057 if (test_bit(HFC_CFG_MASTER, &hc->cfg))
1058 hc->hw.mst_m |= HFCPCI_MASTER;
1059 Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
1060 break;
1061 case HW_RESET_REQ:
1062 Write_hfc(hc, HFCPCI_STATES, HFCPCI_LOAD_STATE | 3);
1063 /* HFC ST 3 */
1064 udelay(6);
1065 Write_hfc(hc, HFCPCI_STATES, 3); /* HFC ST 2 */
1066 if (test_bit(HFC_CFG_MASTER, &hc->cfg))
1067 hc->hw.mst_m |= HFCPCI_MASTER;
1068 Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
1069 Write_hfc(hc, HFCPCI_STATES, HFCPCI_ACTIVATE |
1070 HFCPCI_DO_ACTION);
1071 l1_event(dch->l1, HW_POWERUP_IND);
1072 break;
1073 case HW_DEACT_REQ:
1074 hc->hw.mst_m &= ~HFCPCI_MASTER;
1075 Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
1076 skb_queue_purge(&dch->squeue);
1077 if (dch->tx_skb) {
1078 dev_kfree_skb(dch->tx_skb);
1079 dch->tx_skb = NULL;
1080 }
1081 dch->tx_idx = 0;
1082 if (dch->rx_skb) {
1083 dev_kfree_skb(dch->rx_skb);
1084 dch->rx_skb = NULL;
1085 }
1086 test_and_clear_bit(FLG_TX_BUSY, &dch->Flags);
1087 if (test_and_clear_bit(FLG_BUSY_TIMER, &dch->Flags))
1088 del_timer(&dch->timer);
1089 break;
1090 case HW_POWERUP_REQ:
1091 Write_hfc(hc, HFCPCI_STATES, HFCPCI_DO_ACTION);
1092 break;
1093 case PH_ACTIVATE_IND:
1094 test_and_set_bit(FLG_ACTIVE, &dch->Flags);
1095 _queue_data(&dch->dev.D, cmd, MISDN_ID_ANY, 0, NULL,
1096 GFP_ATOMIC);
1097 break;
1098 case PH_DEACTIVATE_IND:
1099 test_and_clear_bit(FLG_ACTIVE, &dch->Flags);
1100 _queue_data(&dch->dev.D, cmd, MISDN_ID_ANY, 0, NULL,
1101 GFP_ATOMIC);
1102 break;
1103 default:
1104 if (dch->debug & DEBUG_HW)
1105 printk(KERN_DEBUG "%s: unknown command %x\n",
1106 __func__, cmd);
1107 return -1;
1108 }
1109 return 0;
1110 }
1111
1112 /*
1113 * Interrupt handler
1114 */
1115 static inline void
1116 tx_birq(struct bchannel *bch)
1117 {
1118 if (bch->tx_skb && bch->tx_idx < bch->tx_skb->len)
1119 hfcpci_fill_fifo(bch);
1120 else {
1121 dev_kfree_skb(bch->tx_skb);
1122 if (get_next_bframe(bch))
1123 hfcpci_fill_fifo(bch);
1124 }
1125 }
1126
1127 static inline void
1128 tx_dirq(struct dchannel *dch)
1129 {
1130 if (dch->tx_skb && dch->tx_idx < dch->tx_skb->len)
1131 hfcpci_fill_dfifo(dch->hw);
1132 else {
1133 dev_kfree_skb(dch->tx_skb);
1134 if (get_next_dframe(dch))
1135 hfcpci_fill_dfifo(dch->hw);
1136 }
1137 }
1138
1139 static irqreturn_t
1140 hfcpci_int(int intno, void *dev_id)
1141 {
1142 struct hfc_pci *hc = dev_id;
1143 u_char exval;
1144 struct bchannel *bch;
1145 u_char val, stat;
1146
1147 spin_lock(&hc->lock);
1148 if (!(hc->hw.int_m2 & 0x08)) {
1149 spin_unlock(&hc->lock);
1150 return IRQ_NONE; /* not initialised */
1151 }
1152 stat = Read_hfc(hc, HFCPCI_STATUS);
1153 if (HFCPCI_ANYINT & stat) {
1154 val = Read_hfc(hc, HFCPCI_INT_S1);
1155 if (hc->dch.debug & DEBUG_HW_DCHANNEL)
1156 printk(KERN_DEBUG
1157 "HFC-PCI: stat(%02x) s1(%02x)\n", stat, val);
1158 } else {
1159 /* shared */
1160 spin_unlock(&hc->lock);
1161 return IRQ_NONE;
1162 }
1163 hc->irqcnt++;
1164
1165 if (hc->dch.debug & DEBUG_HW_DCHANNEL)
1166 printk(KERN_DEBUG "HFC-PCI irq %x\n", val);
1167 val &= hc->hw.int_m1;
1168 if (val & 0x40) { /* state machine irq */
1169 exval = Read_hfc(hc, HFCPCI_STATES) & 0xf;
1170 if (hc->dch.debug & DEBUG_HW_DCHANNEL)
1171 printk(KERN_DEBUG "ph_state chg %d->%d\n",
1172 hc->dch.state, exval);
1173 hc->dch.state = exval;
1174 schedule_event(&hc->dch, FLG_PHCHANGE);
1175 val &= ~0x40;
1176 }
1177 if (val & 0x80) { /* timer irq */
1178 if (hc->hw.protocol == ISDN_P_NT_S0) {
1179 if ((--hc->hw.nt_timer) < 0)
1180 schedule_event(&hc->dch, FLG_PHCHANGE);
1181 }
1182 val &= ~0x80;
1183 Write_hfc(hc, HFCPCI_CTMT, hc->hw.ctmt | HFCPCI_CLTIMER);
1184 }
1185 if (val & 0x08) { /* B1 rx */
1186 bch = Sel_BCS(hc, hc->hw.bswapped ? 2 : 1);
1187 if (bch)
1188 main_rec_hfcpci(bch);
1189 else if (hc->dch.debug)
1190 printk(KERN_DEBUG "hfcpci spurious 0x08 IRQ\n");
1191 }
1192 if (val & 0x10) { /* B2 rx */
1193 bch = Sel_BCS(hc, 2);
1194 if (bch)
1195 main_rec_hfcpci(bch);
1196 else if (hc->dch.debug)
1197 printk(KERN_DEBUG "hfcpci spurious 0x10 IRQ\n");
1198 }
1199 if (val & 0x01) { /* B1 tx */
1200 bch = Sel_BCS(hc, hc->hw.bswapped ? 2 : 1);
1201 if (bch)
1202 tx_birq(bch);
1203 else if (hc->dch.debug)
1204 printk(KERN_DEBUG "hfcpci spurious 0x01 IRQ\n");
1205 }
1206 if (val & 0x02) { /* B2 tx */
1207 bch = Sel_BCS(hc, 2);
1208 if (bch)
1209 tx_birq(bch);
1210 else if (hc->dch.debug)
1211 printk(KERN_DEBUG "hfcpci spurious 0x02 IRQ\n");
1212 }
1213 if (val & 0x20) /* D rx */
1214 receive_dmsg(hc);
1215 if (val & 0x04) { /* D tx */
1216 if (test_and_clear_bit(FLG_BUSY_TIMER, &hc->dch.Flags))
1217 del_timer(&hc->dch.timer);
1218 tx_dirq(&hc->dch);
1219 }
1220 spin_unlock(&hc->lock);
1221 return IRQ_HANDLED;
1222 }
1223
1224 /*
1225 * timer callback for D-chan busy resolution. Currently no function
1226 */
1227 static void
1228 hfcpci_dbusy_timer(struct timer_list *t)
1229 {
1230 }
1231
1232 /*
1233 * activate/deactivate hardware for selected channels and mode
1234 */
1235 static int
1236 mode_hfcpci(struct bchannel *bch, int bc, int protocol)
1237 {
1238 struct hfc_pci *hc = bch->hw;
1239 int fifo2;
1240 u_char rx_slot = 0, tx_slot = 0, pcm_mode;
1241
1242 if (bch->debug & DEBUG_HW_BCHANNEL)
1243 printk(KERN_DEBUG
1244 "HFCPCI bchannel protocol %x-->%x ch %x-->%x\n",
1245 bch->state, protocol, bch->nr, bc);
1246
1247 fifo2 = bc;
1248 pcm_mode = (bc >> 24) & 0xff;
1249 if (pcm_mode) { /* PCM SLOT USE */
1250 if (!test_bit(HFC_CFG_PCM, &hc->cfg))
1251 printk(KERN_WARNING
1252 "%s: pcm channel id without HFC_CFG_PCM\n",
1253 __func__);
1254 rx_slot = (bc >> 8) & 0xff;
1255 tx_slot = (bc >> 16) & 0xff;
1256 bc = bc & 0xff;
1257 } else if (test_bit(HFC_CFG_PCM, &hc->cfg) && (protocol > ISDN_P_NONE))
1258 printk(KERN_WARNING "%s: no pcm channel id but HFC_CFG_PCM\n",
1259 __func__);
1260 if (hc->chanlimit > 1) {
1261 hc->hw.bswapped = 0; /* B1 and B2 normal mode */
1262 hc->hw.sctrl_e &= ~0x80;
1263 } else {
1264 if (bc & 2) {
1265 if (protocol != ISDN_P_NONE) {
1266 hc->hw.bswapped = 1; /* B1 and B2 exchanged */
1267 hc->hw.sctrl_e |= 0x80;
1268 } else {
1269 hc->hw.bswapped = 0; /* B1 and B2 normal mode */
1270 hc->hw.sctrl_e &= ~0x80;
1271 }
1272 fifo2 = 1;
1273 } else {
1274 hc->hw.bswapped = 0; /* B1 and B2 normal mode */
1275 hc->hw.sctrl_e &= ~0x80;
1276 }
1277 }
1278 switch (protocol) {
1279 case (-1): /* used for init */
1280 bch->state = -1;
1281 bch->nr = bc;
1282 /* fall through */
1283 case (ISDN_P_NONE):
1284 if (bch->state == ISDN_P_NONE)
1285 return 0;
1286 if (bc & 2) {
1287 hc->hw.sctrl &= ~SCTRL_B2_ENA;
1288 hc->hw.sctrl_r &= ~SCTRL_B2_ENA;
1289 } else {
1290 hc->hw.sctrl &= ~SCTRL_B1_ENA;
1291 hc->hw.sctrl_r &= ~SCTRL_B1_ENA;
1292 }
1293 if (fifo2 & 2) {
1294 hc->hw.fifo_en &= ~HFCPCI_FIFOEN_B2;
1295 hc->hw.int_m1 &= ~(HFCPCI_INTS_B2TRANS |
1296 HFCPCI_INTS_B2REC);
1297 } else {
1298 hc->hw.fifo_en &= ~HFCPCI_FIFOEN_B1;
1299 hc->hw.int_m1 &= ~(HFCPCI_INTS_B1TRANS |
1300 HFCPCI_INTS_B1REC);
1301 }
1302 #ifdef REVERSE_BITORDER
1303 if (bch->nr & 2)
1304 hc->hw.cirm &= 0x7f;
1305 else
1306 hc->hw.cirm &= 0xbf;
1307 #endif
1308 bch->state = ISDN_P_NONE;
1309 bch->nr = bc;
1310 test_and_clear_bit(FLG_HDLC, &bch->Flags);
1311 test_and_clear_bit(FLG_TRANSPARENT, &bch->Flags);
1312 break;
1313 case (ISDN_P_B_RAW):
1314 bch->state = protocol;
1315 bch->nr = bc;
1316 hfcpci_clear_fifo_rx(hc, (fifo2 & 2) ? 1 : 0);
1317 hfcpci_clear_fifo_tx(hc, (fifo2 & 2) ? 1 : 0);
1318 if (bc & 2) {
1319 hc->hw.sctrl |= SCTRL_B2_ENA;
1320 hc->hw.sctrl_r |= SCTRL_B2_ENA;
1321 #ifdef REVERSE_BITORDER
1322 hc->hw.cirm |= 0x80;
1323 #endif
1324 } else {
1325 hc->hw.sctrl |= SCTRL_B1_ENA;
1326 hc->hw.sctrl_r |= SCTRL_B1_ENA;
1327 #ifdef REVERSE_BITORDER
1328 hc->hw.cirm |= 0x40;
1329 #endif
1330 }
1331 if (fifo2 & 2) {
1332 hc->hw.fifo_en |= HFCPCI_FIFOEN_B2;
1333 if (!tics)
1334 hc->hw.int_m1 |= (HFCPCI_INTS_B2TRANS |
1335 HFCPCI_INTS_B2REC);
1336 hc->hw.ctmt |= 2;
1337 hc->hw.conn &= ~0x18;
1338 } else {
1339 hc->hw.fifo_en |= HFCPCI_FIFOEN_B1;
1340 if (!tics)
1341 hc->hw.int_m1 |= (HFCPCI_INTS_B1TRANS |
1342 HFCPCI_INTS_B1REC);
1343 hc->hw.ctmt |= 1;
1344 hc->hw.conn &= ~0x03;
1345 }
1346 test_and_set_bit(FLG_TRANSPARENT, &bch->Flags);
1347 break;
1348 case (ISDN_P_B_HDLC):
1349 bch->state = protocol;
1350 bch->nr = bc;
1351 hfcpci_clear_fifo_rx(hc, (fifo2 & 2) ? 1 : 0);
1352 hfcpci_clear_fifo_tx(hc, (fifo2 & 2) ? 1 : 0);
1353 if (bc & 2) {
1354 hc->hw.sctrl |= SCTRL_B2_ENA;
1355 hc->hw.sctrl_r |= SCTRL_B2_ENA;
1356 } else {
1357 hc->hw.sctrl |= SCTRL_B1_ENA;
1358 hc->hw.sctrl_r |= SCTRL_B1_ENA;
1359 }
1360 if (fifo2 & 2) {
1361 hc->hw.last_bfifo_cnt[1] = 0;
1362 hc->hw.fifo_en |= HFCPCI_FIFOEN_B2;
1363 hc->hw.int_m1 |= (HFCPCI_INTS_B2TRANS |
1364 HFCPCI_INTS_B2REC);
1365 hc->hw.ctmt &= ~2;
1366 hc->hw.conn &= ~0x18;
1367 } else {
1368 hc->hw.last_bfifo_cnt[0] = 0;
1369 hc->hw.fifo_en |= HFCPCI_FIFOEN_B1;
1370 hc->hw.int_m1 |= (HFCPCI_INTS_B1TRANS |
1371 HFCPCI_INTS_B1REC);
1372 hc->hw.ctmt &= ~1;
1373 hc->hw.conn &= ~0x03;
1374 }
1375 test_and_set_bit(FLG_HDLC, &bch->Flags);
1376 break;
1377 default:
1378 printk(KERN_DEBUG "prot not known %x\n", protocol);
1379 return -ENOPROTOOPT;
1380 }
1381 if (test_bit(HFC_CFG_PCM, &hc->cfg)) {
1382 if ((protocol == ISDN_P_NONE) ||
1383 (protocol == -1)) { /* init case */
1384 rx_slot = 0;
1385 tx_slot = 0;
1386 } else {
1387 if (test_bit(HFC_CFG_SW_DD_DU, &hc->cfg)) {
1388 rx_slot |= 0xC0;
1389 tx_slot |= 0xC0;
1390 } else {
1391 rx_slot |= 0x80;
1392 tx_slot |= 0x80;
1393 }
1394 }
1395 if (bc & 2) {
1396 hc->hw.conn &= 0xc7;
1397 hc->hw.conn |= 0x08;
1398 printk(KERN_DEBUG "%s: Write_hfc: B2_SSL 0x%x\n",
1399 __func__, tx_slot);
1400 printk(KERN_DEBUG "%s: Write_hfc: B2_RSL 0x%x\n",
1401 __func__, rx_slot);
1402 Write_hfc(hc, HFCPCI_B2_SSL, tx_slot);
1403 Write_hfc(hc, HFCPCI_B2_RSL, rx_slot);
1404 } else {
1405 hc->hw.conn &= 0xf8;
1406 hc->hw.conn |= 0x01;
1407 printk(KERN_DEBUG "%s: Write_hfc: B1_SSL 0x%x\n",
1408 __func__, tx_slot);
1409 printk(KERN_DEBUG "%s: Write_hfc: B1_RSL 0x%x\n",
1410 __func__, rx_slot);
1411 Write_hfc(hc, HFCPCI_B1_SSL, tx_slot);
1412 Write_hfc(hc, HFCPCI_B1_RSL, rx_slot);
1413 }
1414 }
1415 Write_hfc(hc, HFCPCI_SCTRL_E, hc->hw.sctrl_e);
1416 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
1417 Write_hfc(hc, HFCPCI_FIFO_EN, hc->hw.fifo_en);
1418 Write_hfc(hc, HFCPCI_SCTRL, hc->hw.sctrl);
1419 Write_hfc(hc, HFCPCI_SCTRL_R, hc->hw.sctrl_r);
1420 Write_hfc(hc, HFCPCI_CTMT, hc->hw.ctmt);
1421 Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn);
1422 #ifdef REVERSE_BITORDER
1423 Write_hfc(hc, HFCPCI_CIRM, hc->hw.cirm);
1424 #endif
1425 return 0;
1426 }
1427
1428 static int
1429 set_hfcpci_rxtest(struct bchannel *bch, int protocol, int chan)
1430 {
1431 struct hfc_pci *hc = bch->hw;
1432
1433 if (bch->debug & DEBUG_HW_BCHANNEL)
1434 printk(KERN_DEBUG
1435 "HFCPCI bchannel test rx protocol %x-->%x ch %x-->%x\n",
1436 bch->state, protocol, bch->nr, chan);
1437 if (bch->nr != chan) {
1438 printk(KERN_DEBUG
1439 "HFCPCI rxtest wrong channel parameter %x/%x\n",
1440 bch->nr, chan);
1441 return -EINVAL;
1442 }
1443 switch (protocol) {
1444 case (ISDN_P_B_RAW):
1445 bch->state = protocol;
1446 hfcpci_clear_fifo_rx(hc, (chan & 2) ? 1 : 0);
1447 if (chan & 2) {
1448 hc->hw.sctrl_r |= SCTRL_B2_ENA;
1449 hc->hw.fifo_en |= HFCPCI_FIFOEN_B2RX;
1450 if (!tics)
1451 hc->hw.int_m1 |= HFCPCI_INTS_B2REC;
1452 hc->hw.ctmt |= 2;
1453 hc->hw.conn &= ~0x18;
1454 #ifdef REVERSE_BITORDER
1455 hc->hw.cirm |= 0x80;
1456 #endif
1457 } else {
1458 hc->hw.sctrl_r |= SCTRL_B1_ENA;
1459 hc->hw.fifo_en |= HFCPCI_FIFOEN_B1RX;
1460 if (!tics)
1461 hc->hw.int_m1 |= HFCPCI_INTS_B1REC;
1462 hc->hw.ctmt |= 1;
1463 hc->hw.conn &= ~0x03;
1464 #ifdef REVERSE_BITORDER
1465 hc->hw.cirm |= 0x40;
1466 #endif
1467 }
1468 break;
1469 case (ISDN_P_B_HDLC):
1470 bch->state = protocol;
1471 hfcpci_clear_fifo_rx(hc, (chan & 2) ? 1 : 0);
1472 if (chan & 2) {
1473 hc->hw.sctrl_r |= SCTRL_B2_ENA;
1474 hc->hw.last_bfifo_cnt[1] = 0;
1475 hc->hw.fifo_en |= HFCPCI_FIFOEN_B2RX;
1476 hc->hw.int_m1 |= HFCPCI_INTS_B2REC;
1477 hc->hw.ctmt &= ~2;
1478 hc->hw.conn &= ~0x18;
1479 } else {
1480 hc->hw.sctrl_r |= SCTRL_B1_ENA;
1481 hc->hw.last_bfifo_cnt[0] = 0;
1482 hc->hw.fifo_en |= HFCPCI_FIFOEN_B1RX;
1483 hc->hw.int_m1 |= HFCPCI_INTS_B1REC;
1484 hc->hw.ctmt &= ~1;
1485 hc->hw.conn &= ~0x03;
1486 }
1487 break;
1488 default:
1489 printk(KERN_DEBUG "prot not known %x\n", protocol);
1490 return -ENOPROTOOPT;
1491 }
1492 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
1493 Write_hfc(hc, HFCPCI_FIFO_EN, hc->hw.fifo_en);
1494 Write_hfc(hc, HFCPCI_SCTRL_R, hc->hw.sctrl_r);
1495 Write_hfc(hc, HFCPCI_CTMT, hc->hw.ctmt);
1496 Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn);
1497 #ifdef REVERSE_BITORDER
1498 Write_hfc(hc, HFCPCI_CIRM, hc->hw.cirm);
1499 #endif
1500 return 0;
1501 }
1502
1503 static void
1504 deactivate_bchannel(struct bchannel *bch)
1505 {
1506 struct hfc_pci *hc = bch->hw;
1507 u_long flags;
1508
1509 spin_lock_irqsave(&hc->lock, flags);
1510 mISDN_clear_bchannel(bch);
1511 mode_hfcpci(bch, bch->nr, ISDN_P_NONE);
1512 spin_unlock_irqrestore(&hc->lock, flags);
1513 }
1514
1515 /*
1516 * Layer 1 B-channel hardware access
1517 */
1518 static int
1519 channel_bctrl(struct bchannel *bch, struct mISDN_ctrl_req *cq)
1520 {
1521 return mISDN_ctrl_bchannel(bch, cq);
1522 }
1523 static int
1524 hfc_bctrl(struct mISDNchannel *ch, u_int cmd, void *arg)
1525 {
1526 struct bchannel *bch = container_of(ch, struct bchannel, ch);
1527 struct hfc_pci *hc = bch->hw;
1528 int ret = -EINVAL;
1529 u_long flags;
1530
1531 if (bch->debug & DEBUG_HW)
1532 printk(KERN_DEBUG "%s: cmd:%x %p\n", __func__, cmd, arg);
1533 switch (cmd) {
1534 case HW_TESTRX_RAW:
1535 spin_lock_irqsave(&hc->lock, flags);
1536 ret = set_hfcpci_rxtest(bch, ISDN_P_B_RAW, (int)(long)arg);
1537 spin_unlock_irqrestore(&hc->lock, flags);
1538 break;
1539 case HW_TESTRX_HDLC:
1540 spin_lock_irqsave(&hc->lock, flags);
1541 ret = set_hfcpci_rxtest(bch, ISDN_P_B_HDLC, (int)(long)arg);
1542 spin_unlock_irqrestore(&hc->lock, flags);
1543 break;
1544 case HW_TESTRX_OFF:
1545 spin_lock_irqsave(&hc->lock, flags);
1546 mode_hfcpci(bch, bch->nr, ISDN_P_NONE);
1547 spin_unlock_irqrestore(&hc->lock, flags);
1548 ret = 0;
1549 break;
1550 case CLOSE_CHANNEL:
1551 test_and_clear_bit(FLG_OPEN, &bch->Flags);
1552 deactivate_bchannel(bch);
1553 ch->protocol = ISDN_P_NONE;
1554 ch->peer = NULL;
1555 module_put(THIS_MODULE);
1556 ret = 0;
1557 break;
1558 case CONTROL_CHANNEL:
1559 ret = channel_bctrl(bch, arg);
1560 break;
1561 default:
1562 printk(KERN_WARNING "%s: unknown prim(%x)\n",
1563 __func__, cmd);
1564 }
1565 return ret;
1566 }
1567
1568 /*
1569 * Layer2 -> Layer 1 Dchannel data
1570 */
1571 static int
1572 hfcpci_l2l1D(struct mISDNchannel *ch, struct sk_buff *skb)
1573 {
1574 struct mISDNdevice *dev = container_of(ch, struct mISDNdevice, D);
1575 struct dchannel *dch = container_of(dev, struct dchannel, dev);
1576 struct hfc_pci *hc = dch->hw;
1577 int ret = -EINVAL;
1578 struct mISDNhead *hh = mISDN_HEAD_P(skb);
1579 unsigned int id;
1580 u_long flags;
1581
1582 switch (hh->prim) {
1583 case PH_DATA_REQ:
1584 spin_lock_irqsave(&hc->lock, flags);
1585 ret = dchannel_senddata(dch, skb);
1586 if (ret > 0) { /* direct TX */
1587 id = hh->id; /* skb can be freed */
1588 hfcpci_fill_dfifo(dch->hw);
1589 ret = 0;
1590 spin_unlock_irqrestore(&hc->lock, flags);
1591 queue_ch_frame(ch, PH_DATA_CNF, id, NULL);
1592 } else
1593 spin_unlock_irqrestore(&hc->lock, flags);
1594 return ret;
1595 case PH_ACTIVATE_REQ:
1596 spin_lock_irqsave(&hc->lock, flags);
1597 if (hc->hw.protocol == ISDN_P_NT_S0) {
1598 ret = 0;
1599 if (test_bit(HFC_CFG_MASTER, &hc->cfg))
1600 hc->hw.mst_m |= HFCPCI_MASTER;
1601 Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
1602 if (test_bit(FLG_ACTIVE, &dch->Flags)) {
1603 spin_unlock_irqrestore(&hc->lock, flags);
1604 _queue_data(&dch->dev.D, PH_ACTIVATE_IND,
1605 MISDN_ID_ANY, 0, NULL, GFP_ATOMIC);
1606 break;
1607 }
1608 test_and_set_bit(FLG_L2_ACTIVATED, &dch->Flags);
1609 Write_hfc(hc, HFCPCI_STATES, HFCPCI_ACTIVATE |
1610 HFCPCI_DO_ACTION | 1);
1611 } else
1612 ret = l1_event(dch->l1, hh->prim);
1613 spin_unlock_irqrestore(&hc->lock, flags);
1614 break;
1615 case PH_DEACTIVATE_REQ:
1616 test_and_clear_bit(FLG_L2_ACTIVATED, &dch->Flags);
1617 spin_lock_irqsave(&hc->lock, flags);
1618 if (hc->hw.protocol == ISDN_P_NT_S0) {
1619 /* prepare deactivation */
1620 Write_hfc(hc, HFCPCI_STATES, 0x40);
1621 skb_queue_purge(&dch->squeue);
1622 if (dch->tx_skb) {
1623 dev_kfree_skb(dch->tx_skb);
1624 dch->tx_skb = NULL;
1625 }
1626 dch->tx_idx = 0;
1627 if (dch->rx_skb) {
1628 dev_kfree_skb(dch->rx_skb);
1629 dch->rx_skb = NULL;
1630 }
1631 test_and_clear_bit(FLG_TX_BUSY, &dch->Flags);
1632 if (test_and_clear_bit(FLG_BUSY_TIMER, &dch->Flags))
1633 del_timer(&dch->timer);
1634 #ifdef FIXME
1635 if (test_and_clear_bit(FLG_L1_BUSY, &dch->Flags))
1636 dchannel_sched_event(&hc->dch, D_CLEARBUSY);
1637 #endif
1638 hc->hw.mst_m &= ~HFCPCI_MASTER;
1639 Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
1640 ret = 0;
1641 } else {
1642 ret = l1_event(dch->l1, hh->prim);
1643 }
1644 spin_unlock_irqrestore(&hc->lock, flags);
1645 break;
1646 }
1647 if (!ret)
1648 dev_kfree_skb(skb);
1649 return ret;
1650 }
1651
1652 /*
1653 * Layer2 -> Layer 1 Bchannel data
1654 */
1655 static int
1656 hfcpci_l2l1B(struct mISDNchannel *ch, struct sk_buff *skb)
1657 {
1658 struct bchannel *bch = container_of(ch, struct bchannel, ch);
1659 struct hfc_pci *hc = bch->hw;
1660 int ret = -EINVAL;
1661 struct mISDNhead *hh = mISDN_HEAD_P(skb);
1662 unsigned long flags;
1663
1664 switch (hh->prim) {
1665 case PH_DATA_REQ:
1666 spin_lock_irqsave(&hc->lock, flags);
1667 ret = bchannel_senddata(bch, skb);
1668 if (ret > 0) { /* direct TX */
1669 hfcpci_fill_fifo(bch);
1670 ret = 0;
1671 }
1672 spin_unlock_irqrestore(&hc->lock, flags);
1673 return ret;
1674 case PH_ACTIVATE_REQ:
1675 spin_lock_irqsave(&hc->lock, flags);
1676 if (!test_and_set_bit(FLG_ACTIVE, &bch->Flags))
1677 ret = mode_hfcpci(bch, bch->nr, ch->protocol);
1678 else
1679 ret = 0;
1680 spin_unlock_irqrestore(&hc->lock, flags);
1681 if (!ret)
1682 _queue_data(ch, PH_ACTIVATE_IND, MISDN_ID_ANY, 0,
1683 NULL, GFP_KERNEL);
1684 break;
1685 case PH_DEACTIVATE_REQ:
1686 deactivate_bchannel(bch);
1687 _queue_data(ch, PH_DEACTIVATE_IND, MISDN_ID_ANY, 0,
1688 NULL, GFP_KERNEL);
1689 ret = 0;
1690 break;
1691 }
1692 if (!ret)
1693 dev_kfree_skb(skb);
1694 return ret;
1695 }
1696
1697 /*
1698 * called for card init message
1699 */
1700
1701 static void
1702 inithfcpci(struct hfc_pci *hc)
1703 {
1704 printk(KERN_DEBUG "inithfcpci: entered\n");
1705 timer_setup(&hc->dch.timer, hfcpci_dbusy_timer, 0);
1706 hc->chanlimit = 2;
1707 mode_hfcpci(&hc->bch[0], 1, -1);
1708 mode_hfcpci(&hc->bch[1], 2, -1);
1709 }
1710
1711
1712 static int
1713 init_card(struct hfc_pci *hc)
1714 {
1715 int cnt = 3;
1716 u_long flags;
1717
1718 printk(KERN_DEBUG "init_card: entered\n");
1719
1720
1721 spin_lock_irqsave(&hc->lock, flags);
1722 disable_hwirq(hc);
1723 spin_unlock_irqrestore(&hc->lock, flags);
1724 if (request_irq(hc->irq, hfcpci_int, IRQF_SHARED, "HFC PCI", hc)) {
1725 printk(KERN_WARNING
1726 "mISDN: couldn't get interrupt %d\n", hc->irq);
1727 return -EIO;
1728 }
1729 spin_lock_irqsave(&hc->lock, flags);
1730 reset_hfcpci(hc);
1731 while (cnt) {
1732 inithfcpci(hc);
1733 /*
1734 * Finally enable IRQ output
1735 * this is only allowed, if an IRQ routine is already
1736 * established for this HFC, so don't do that earlier
1737 */
1738 enable_hwirq(hc);
1739 spin_unlock_irqrestore(&hc->lock, flags);
1740 /* Timeout 80ms */
1741 set_current_state(TASK_UNINTERRUPTIBLE);
1742 schedule_timeout((80 * HZ) / 1000);
1743 printk(KERN_INFO "HFC PCI: IRQ %d count %d\n",
1744 hc->irq, hc->irqcnt);
1745 /* now switch timer interrupt off */
1746 spin_lock_irqsave(&hc->lock, flags);
1747 hc->hw.int_m1 &= ~HFCPCI_INTS_TIMER;
1748 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
1749 /* reinit mode reg */
1750 Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
1751 if (!hc->irqcnt) {
1752 printk(KERN_WARNING
1753 "HFC PCI: IRQ(%d) getting no interrupts "
1754 "during init %d\n", hc->irq, 4 - cnt);
1755 if (cnt == 1)
1756 break;
1757 else {
1758 reset_hfcpci(hc);
1759 cnt--;
1760 }
1761 } else {
1762 spin_unlock_irqrestore(&hc->lock, flags);
1763 hc->initdone = 1;
1764 return 0;
1765 }
1766 }
1767 disable_hwirq(hc);
1768 spin_unlock_irqrestore(&hc->lock, flags);
1769 free_irq(hc->irq, hc);
1770 return -EIO;
1771 }
1772
1773 static int
1774 channel_ctrl(struct hfc_pci *hc, struct mISDN_ctrl_req *cq)
1775 {
1776 int ret = 0;
1777 u_char slot;
1778
1779 switch (cq->op) {
1780 case MISDN_CTRL_GETOP:
1781 cq->op = MISDN_CTRL_LOOP | MISDN_CTRL_CONNECT |
1782 MISDN_CTRL_DISCONNECT | MISDN_CTRL_L1_TIMER3;
1783 break;
1784 case MISDN_CTRL_LOOP:
1785 /* channel 0 disabled loop */
1786 if (cq->channel < 0 || cq->channel > 2) {
1787 ret = -EINVAL;
1788 break;
1789 }
1790 if (cq->channel & 1) {
1791 if (test_bit(HFC_CFG_SW_DD_DU, &hc->cfg))
1792 slot = 0xC0;
1793 else
1794 slot = 0x80;
1795 printk(KERN_DEBUG "%s: Write_hfc: B1_SSL/RSL 0x%x\n",
1796 __func__, slot);
1797 Write_hfc(hc, HFCPCI_B1_SSL, slot);
1798 Write_hfc(hc, HFCPCI_B1_RSL, slot);
1799 hc->hw.conn = (hc->hw.conn & ~7) | 6;
1800 Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn);
1801 }
1802 if (cq->channel & 2) {
1803 if (test_bit(HFC_CFG_SW_DD_DU, &hc->cfg))
1804 slot = 0xC1;
1805 else
1806 slot = 0x81;
1807 printk(KERN_DEBUG "%s: Write_hfc: B2_SSL/RSL 0x%x\n",
1808 __func__, slot);
1809 Write_hfc(hc, HFCPCI_B2_SSL, slot);
1810 Write_hfc(hc, HFCPCI_B2_RSL, slot);
1811 hc->hw.conn = (hc->hw.conn & ~0x38) | 0x30;
1812 Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn);
1813 }
1814 if (cq->channel & 3)
1815 hc->hw.trm |= 0x80; /* enable IOM-loop */
1816 else {
1817 hc->hw.conn = (hc->hw.conn & ~0x3f) | 0x09;
1818 Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn);
1819 hc->hw.trm &= 0x7f; /* disable IOM-loop */
1820 }
1821 Write_hfc(hc, HFCPCI_TRM, hc->hw.trm);
1822 break;
1823 case MISDN_CTRL_CONNECT:
1824 if (cq->channel == cq->p1) {
1825 ret = -EINVAL;
1826 break;
1827 }
1828 if (cq->channel < 1 || cq->channel > 2 ||
1829 cq->p1 < 1 || cq->p1 > 2) {
1830 ret = -EINVAL;
1831 break;
1832 }
1833 if (test_bit(HFC_CFG_SW_DD_DU, &hc->cfg))
1834 slot = 0xC0;
1835 else
1836 slot = 0x80;
1837 printk(KERN_DEBUG "%s: Write_hfc: B1_SSL/RSL 0x%x\n",
1838 __func__, slot);
1839 Write_hfc(hc, HFCPCI_B1_SSL, slot);
1840 Write_hfc(hc, HFCPCI_B2_RSL, slot);
1841 if (test_bit(HFC_CFG_SW_DD_DU, &hc->cfg))
1842 slot = 0xC1;
1843 else
1844 slot = 0x81;
1845 printk(KERN_DEBUG "%s: Write_hfc: B2_SSL/RSL 0x%x\n",
1846 __func__, slot);
1847 Write_hfc(hc, HFCPCI_B2_SSL, slot);
1848 Write_hfc(hc, HFCPCI_B1_RSL, slot);
1849 hc->hw.conn = (hc->hw.conn & ~0x3f) | 0x36;
1850 Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn);
1851 hc->hw.trm |= 0x80;
1852 Write_hfc(hc, HFCPCI_TRM, hc->hw.trm);
1853 break;
1854 case MISDN_CTRL_DISCONNECT:
1855 hc->hw.conn = (hc->hw.conn & ~0x3f) | 0x09;
1856 Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn);
1857 hc->hw.trm &= 0x7f; /* disable IOM-loop */
1858 break;
1859 case MISDN_CTRL_L1_TIMER3:
1860 ret = l1_event(hc->dch.l1, HW_TIMER3_VALUE | (cq->p1 & 0xff));
1861 break;
1862 default:
1863 printk(KERN_WARNING "%s: unknown Op %x\n",
1864 __func__, cq->op);
1865 ret = -EINVAL;
1866 break;
1867 }
1868 return ret;
1869 }
1870
1871 static int
1872 open_dchannel(struct hfc_pci *hc, struct mISDNchannel *ch,
1873 struct channel_req *rq)
1874 {
1875 int err = 0;
1876
1877 if (debug & DEBUG_HW_OPEN)
1878 printk(KERN_DEBUG "%s: dev(%d) open from %p\n", __func__,
1879 hc->dch.dev.id, __builtin_return_address(0));
1880 if (rq->protocol == ISDN_P_NONE)
1881 return -EINVAL;
1882 if (rq->adr.channel == 1) {
1883 /* TODO: E-Channel */
1884 return -EINVAL;
1885 }
1886 if (!hc->initdone) {
1887 if (rq->protocol == ISDN_P_TE_S0) {
1888 err = create_l1(&hc->dch, hfc_l1callback);
1889 if (err)
1890 return err;
1891 }
1892 hc->hw.protocol = rq->protocol;
1893 ch->protocol = rq->protocol;
1894 err = init_card(hc);
1895 if (err)
1896 return err;
1897 } else {
1898 if (rq->protocol != ch->protocol) {
1899 if (hc->hw.protocol == ISDN_P_TE_S0)
1900 l1_event(hc->dch.l1, CLOSE_CHANNEL);
1901 if (rq->protocol == ISDN_P_TE_S0) {
1902 err = create_l1(&hc->dch, hfc_l1callback);
1903 if (err)
1904 return err;
1905 }
1906 hc->hw.protocol = rq->protocol;
1907 ch->protocol = rq->protocol;
1908 hfcpci_setmode(hc);
1909 }
1910 }
1911
1912 if (((ch->protocol == ISDN_P_NT_S0) && (hc->dch.state == 3)) ||
1913 ((ch->protocol == ISDN_P_TE_S0) && (hc->dch.state == 7))) {
1914 _queue_data(ch, PH_ACTIVATE_IND, MISDN_ID_ANY,
1915 0, NULL, GFP_KERNEL);
1916 }
1917 rq->ch = ch;
1918 if (!try_module_get(THIS_MODULE))
1919 printk(KERN_WARNING "%s:cannot get module\n", __func__);
1920 return 0;
1921 }
1922
1923 static int
1924 open_bchannel(struct hfc_pci *hc, struct channel_req *rq)
1925 {
1926 struct bchannel *bch;
1927
1928 if (rq->adr.channel == 0 || rq->adr.channel > 2)
1929 return -EINVAL;
1930 if (rq->protocol == ISDN_P_NONE)
1931 return -EINVAL;
1932 bch = &hc->bch[rq->adr.channel - 1];
1933 if (test_and_set_bit(FLG_OPEN, &bch->Flags))
1934 return -EBUSY; /* b-channel can be only open once */
1935 bch->ch.protocol = rq->protocol;
1936 rq->ch = &bch->ch; /* TODO: E-channel */
1937 if (!try_module_get(THIS_MODULE))
1938 printk(KERN_WARNING "%s:cannot get module\n", __func__);
1939 return 0;
1940 }
1941
1942 /*
1943 * device control function
1944 */
1945 static int
1946 hfc_dctrl(struct mISDNchannel *ch, u_int cmd, void *arg)
1947 {
1948 struct mISDNdevice *dev = container_of(ch, struct mISDNdevice, D);
1949 struct dchannel *dch = container_of(dev, struct dchannel, dev);
1950 struct hfc_pci *hc = dch->hw;
1951 struct channel_req *rq;
1952 int err = 0;
1953
1954 if (dch->debug & DEBUG_HW)
1955 printk(KERN_DEBUG "%s: cmd:%x %p\n",
1956 __func__, cmd, arg);
1957 switch (cmd) {
1958 case OPEN_CHANNEL:
1959 rq = arg;
1960 if ((rq->protocol == ISDN_P_TE_S0) ||
1961 (rq->protocol == ISDN_P_NT_S0))
1962 err = open_dchannel(hc, ch, rq);
1963 else
1964 err = open_bchannel(hc, rq);
1965 break;
1966 case CLOSE_CHANNEL:
1967 if (debug & DEBUG_HW_OPEN)
1968 printk(KERN_DEBUG "%s: dev(%d) close from %p\n",
1969 __func__, hc->dch.dev.id,
1970 __builtin_return_address(0));
1971 module_put(THIS_MODULE);
1972 break;
1973 case CONTROL_CHANNEL:
1974 err = channel_ctrl(hc, arg);
1975 break;
1976 default:
1977 if (dch->debug & DEBUG_HW)
1978 printk(KERN_DEBUG "%s: unknown command %x\n",
1979 __func__, cmd);
1980 return -EINVAL;
1981 }
1982 return err;
1983 }
1984
1985 static int
1986 setup_hw(struct hfc_pci *hc)
1987 {
1988 void *buffer;
1989
1990 printk(KERN_INFO "mISDN: HFC-PCI driver %s\n", hfcpci_revision);
1991 hc->hw.cirm = 0;
1992 hc->dch.state = 0;
1993 pci_set_master(hc->pdev);
1994 if (!hc->irq) {
1995 printk(KERN_WARNING "HFC-PCI: No IRQ for PCI card found\n");
1996 return 1;
1997 }
1998 hc->hw.pci_io =
1999 (char __iomem *)(unsigned long)hc->pdev->resource[1].start;
2000
2001 if (!hc->hw.pci_io) {
2002 printk(KERN_WARNING "HFC-PCI: No IO-Mem for PCI card found\n");
2003 return 1;
2004 }
2005 /* Allocate memory for FIFOS */
2006 /* the memory needs to be on a 32k boundary within the first 4G */
2007 pci_set_dma_mask(hc->pdev, 0xFFFF8000);
2008 buffer = pci_alloc_consistent(hc->pdev, 0x8000, &hc->hw.dmahandle);
2009 /* We silently assume the address is okay if nonzero */
2010 if (!buffer) {
2011 printk(KERN_WARNING
2012 "HFC-PCI: Error allocating memory for FIFO!\n");
2013 return 1;
2014 }
2015 hc->hw.fifos = buffer;
2016 pci_write_config_dword(hc->pdev, 0x80, hc->hw.dmahandle);
2017 hc->hw.pci_io = ioremap((ulong) hc->hw.pci_io, 256);
2018 if (unlikely(!hc->hw.pci_io)) {
2019 printk(KERN_WARNING
2020 "HFC-PCI: Error in ioremap for PCI!\n");
2021 pci_free_consistent(hc->pdev, 0x8000, hc->hw.fifos,
2022 hc->hw.dmahandle);
2023 return 1;
2024 }
2025
2026 printk(KERN_INFO
2027 "HFC-PCI: defined at mem %#lx fifo %p(%pad) IRQ %d HZ %d\n",
2028 (u_long) hc->hw.pci_io, hc->hw.fifos,
2029 &hc->hw.dmahandle, hc->irq, HZ);
2030
2031 /* enable memory mapped ports, disable busmaster */
2032 pci_write_config_word(hc->pdev, PCI_COMMAND, PCI_ENA_MEMIO);
2033 hc->hw.int_m2 = 0;
2034 disable_hwirq(hc);
2035 hc->hw.int_m1 = 0;
2036 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
2037 /* At this point the needed PCI config is done */
2038 /* fifos are still not enabled */
2039 timer_setup(&hc->hw.timer, hfcpci_Timer, 0);
2040 /* default PCM master */
2041 test_and_set_bit(HFC_CFG_MASTER, &hc->cfg);
2042 return 0;
2043 }
2044
2045 static void
2046 release_card(struct hfc_pci *hc) {
2047 u_long flags;
2048
2049 spin_lock_irqsave(&hc->lock, flags);
2050 hc->hw.int_m2 = 0; /* interrupt output off ! */
2051 disable_hwirq(hc);
2052 mode_hfcpci(&hc->bch[0], 1, ISDN_P_NONE);
2053 mode_hfcpci(&hc->bch[1], 2, ISDN_P_NONE);
2054 if (hc->dch.timer.function != NULL) {
2055 del_timer(&hc->dch.timer);
2056 hc->dch.timer.function = NULL;
2057 }
2058 spin_unlock_irqrestore(&hc->lock, flags);
2059 if (hc->hw.protocol == ISDN_P_TE_S0)
2060 l1_event(hc->dch.l1, CLOSE_CHANNEL);
2061 if (hc->initdone)
2062 free_irq(hc->irq, hc);
2063 release_io_hfcpci(hc); /* must release after free_irq! */
2064 mISDN_unregister_device(&hc->dch.dev);
2065 mISDN_freebchannel(&hc->bch[1]);
2066 mISDN_freebchannel(&hc->bch[0]);
2067 mISDN_freedchannel(&hc->dch);
2068 pci_set_drvdata(hc->pdev, NULL);
2069 kfree(hc);
2070 }
2071
2072 static int
2073 setup_card(struct hfc_pci *card)
2074 {
2075 int err = -EINVAL;
2076 u_int i;
2077 char name[MISDN_MAX_IDLEN];
2078
2079 card->dch.debug = debug;
2080 spin_lock_init(&card->lock);
2081 mISDN_initdchannel(&card->dch, MAX_DFRAME_LEN_L1, ph_state);
2082 card->dch.hw = card;
2083 card->dch.dev.Dprotocols = (1 << ISDN_P_TE_S0) | (1 << ISDN_P_NT_S0);
2084 card->dch.dev.Bprotocols = (1 << (ISDN_P_B_RAW & ISDN_P_B_MASK)) |
2085 (1 << (ISDN_P_B_HDLC & ISDN_P_B_MASK));
2086 card->dch.dev.D.send = hfcpci_l2l1D;
2087 card->dch.dev.D.ctrl = hfc_dctrl;
2088 card->dch.dev.nrbchan = 2;
2089 for (i = 0; i < 2; i++) {
2090 card->bch[i].nr = i + 1;
2091 set_channelmap(i + 1, card->dch.dev.channelmap);
2092 card->bch[i].debug = debug;
2093 mISDN_initbchannel(&card->bch[i], MAX_DATA_MEM, poll >> 1);
2094 card->bch[i].hw = card;
2095 card->bch[i].ch.send = hfcpci_l2l1B;
2096 card->bch[i].ch.ctrl = hfc_bctrl;
2097 card->bch[i].ch.nr = i + 1;
2098 list_add(&card->bch[i].ch.list, &card->dch.dev.bchannels);
2099 }
2100 err = setup_hw(card);
2101 if (err)
2102 goto error;
2103 snprintf(name, MISDN_MAX_IDLEN - 1, "hfc-pci.%d", HFC_cnt + 1);
2104 err = mISDN_register_device(&card->dch.dev, &card->pdev->dev, name);
2105 if (err)
2106 goto error;
2107 HFC_cnt++;
2108 printk(KERN_INFO "HFC %d cards installed\n", HFC_cnt);
2109 return 0;
2110 error:
2111 mISDN_freebchannel(&card->bch[1]);
2112 mISDN_freebchannel(&card->bch[0]);
2113 mISDN_freedchannel(&card->dch);
2114 kfree(card);
2115 return err;
2116 }
2117
2118 /* private data in the PCI devices list */
2119 struct _hfc_map {
2120 u_int subtype;
2121 u_int flag;
2122 char *name;
2123 };
2124
2125 static const struct _hfc_map hfc_map[] =
2126 {
2127 {HFC_CCD_2BD0, 0, "CCD/Billion/Asuscom 2BD0"},
2128 {HFC_CCD_B000, 0, "Billion B000"},
2129 {HFC_CCD_B006, 0, "Billion B006"},
2130 {HFC_CCD_B007, 0, "Billion B007"},
2131 {HFC_CCD_B008, 0, "Billion B008"},
2132 {HFC_CCD_B009, 0, "Billion B009"},
2133 {HFC_CCD_B00A, 0, "Billion B00A"},
2134 {HFC_CCD_B00B, 0, "Billion B00B"},
2135 {HFC_CCD_B00C, 0, "Billion B00C"},
2136 {HFC_CCD_B100, 0, "Seyeon B100"},
2137 {HFC_CCD_B700, 0, "Primux II S0 B700"},
2138 {HFC_CCD_B701, 0, "Primux II S0 NT B701"},
2139 {HFC_ABOCOM_2BD1, 0, "Abocom/Magitek 2BD1"},
2140 {HFC_ASUS_0675, 0, "Asuscom/Askey 675"},
2141 {HFC_BERKOM_TCONCEPT, 0, "German telekom T-Concept"},
2142 {HFC_BERKOM_A1T, 0, "German telekom A1T"},
2143 {HFC_ANIGMA_MC145575, 0, "Motorola MC145575"},
2144 {HFC_ZOLTRIX_2BD0, 0, "Zoltrix 2BD0"},
2145 {HFC_DIGI_DF_M_IOM2_E, 0,
2146 "Digi International DataFire Micro V IOM2 (Europe)"},
2147 {HFC_DIGI_DF_M_E, 0,
2148 "Digi International DataFire Micro V (Europe)"},
2149 {HFC_DIGI_DF_M_IOM2_A, 0,
2150 "Digi International DataFire Micro V IOM2 (North America)"},
2151 {HFC_DIGI_DF_M_A, 0,
2152 "Digi International DataFire Micro V (North America)"},
2153 {HFC_SITECOM_DC105V2, 0, "Sitecom Connectivity DC-105 ISDN TA"},
2154 {},
2155 };
2156
2157 static const struct pci_device_id hfc_ids[] =
2158 {
2159 { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_2BD0),
2160 (unsigned long) &hfc_map[0] },
2161 { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_B000),
2162 (unsigned long) &hfc_map[1] },
2163 { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_B006),
2164 (unsigned long) &hfc_map[2] },
2165 { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_B007),
2166 (unsigned long) &hfc_map[3] },
2167 { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_B008),
2168 (unsigned long) &hfc_map[4] },
2169 { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_B009),
2170 (unsigned long) &hfc_map[5] },
2171 { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_B00A),
2172 (unsigned long) &hfc_map[6] },
2173 { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_B00B),
2174 (unsigned long) &hfc_map[7] },
2175 { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_B00C),
2176 (unsigned long) &hfc_map[8] },
2177 { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_B100),
2178 (unsigned long) &hfc_map[9] },
2179 { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_B700),
2180 (unsigned long) &hfc_map[10] },
2181 { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_B701),
2182 (unsigned long) &hfc_map[11] },
2183 { PCI_VDEVICE(ABOCOM, PCI_DEVICE_ID_ABOCOM_2BD1),
2184 (unsigned long) &hfc_map[12] },
2185 { PCI_VDEVICE(ASUSTEK, PCI_DEVICE_ID_ASUSTEK_0675),
2186 (unsigned long) &hfc_map[13] },
2187 { PCI_VDEVICE(BERKOM, PCI_DEVICE_ID_BERKOM_T_CONCEPT),
2188 (unsigned long) &hfc_map[14] },
2189 { PCI_VDEVICE(BERKOM, PCI_DEVICE_ID_BERKOM_A1T),
2190 (unsigned long) &hfc_map[15] },
2191 { PCI_VDEVICE(ANIGMA, PCI_DEVICE_ID_ANIGMA_MC145575),
2192 (unsigned long) &hfc_map[16] },
2193 { PCI_VDEVICE(ZOLTRIX, PCI_DEVICE_ID_ZOLTRIX_2BD0),
2194 (unsigned long) &hfc_map[17] },
2195 { PCI_VDEVICE(DIGI, PCI_DEVICE_ID_DIGI_DF_M_IOM2_E),
2196 (unsigned long) &hfc_map[18] },
2197 { PCI_VDEVICE(DIGI, PCI_DEVICE_ID_DIGI_DF_M_E),
2198 (unsigned long) &hfc_map[19] },
2199 { PCI_VDEVICE(DIGI, PCI_DEVICE_ID_DIGI_DF_M_IOM2_A),
2200 (unsigned long) &hfc_map[20] },
2201 { PCI_VDEVICE(DIGI, PCI_DEVICE_ID_DIGI_DF_M_A),
2202 (unsigned long) &hfc_map[21] },
2203 { PCI_VDEVICE(SITECOM, PCI_DEVICE_ID_SITECOM_DC105V2),
2204 (unsigned long) &hfc_map[22] },
2205 {},
2206 };
2207
2208 static int
2209 hfc_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
2210 {
2211 int err = -ENOMEM;
2212 struct hfc_pci *card;
2213 struct _hfc_map *m = (struct _hfc_map *)ent->driver_data;
2214
2215 card = kzalloc(sizeof(struct hfc_pci), GFP_KERNEL);
2216 if (!card) {
2217 printk(KERN_ERR "No kmem for HFC card\n");
2218 return err;
2219 }
2220 card->pdev = pdev;
2221 card->subtype = m->subtype;
2222 err = pci_enable_device(pdev);
2223 if (err) {
2224 kfree(card);
2225 return err;
2226 }
2227
2228 printk(KERN_INFO "mISDN_hfcpci: found adapter %s at %s\n",
2229 m->name, pci_name(pdev));
2230
2231 card->irq = pdev->irq;
2232 pci_set_drvdata(pdev, card);
2233 err = setup_card(card);
2234 if (err)
2235 pci_set_drvdata(pdev, NULL);
2236 return err;
2237 }
2238
2239 static void
2240 hfc_remove_pci(struct pci_dev *pdev)
2241 {
2242 struct hfc_pci *card = pci_get_drvdata(pdev);
2243
2244 if (card)
2245 release_card(card);
2246 else
2247 if (debug)
2248 printk(KERN_DEBUG "%s: drvdata already removed\n",
2249 __func__);
2250 }
2251
2252
2253 static struct pci_driver hfc_driver = {
2254 .name = "hfcpci",
2255 .probe = hfc_probe,
2256 .remove = hfc_remove_pci,
2257 .id_table = hfc_ids,
2258 };
2259
2260 static int
2261 _hfcpci_softirq(struct device *dev, void *unused)
2262 {
2263 struct hfc_pci *hc = dev_get_drvdata(dev);
2264 struct bchannel *bch;
2265 if (hc == NULL)
2266 return 0;
2267
2268 if (hc->hw.int_m2 & HFCPCI_IRQ_ENABLE) {
2269 spin_lock(&hc->lock);
2270 bch = Sel_BCS(hc, hc->hw.bswapped ? 2 : 1);
2271 if (bch && bch->state == ISDN_P_B_RAW) { /* B1 rx&tx */
2272 main_rec_hfcpci(bch);
2273 tx_birq(bch);
2274 }
2275 bch = Sel_BCS(hc, hc->hw.bswapped ? 1 : 2);
2276 if (bch && bch->state == ISDN_P_B_RAW) { /* B2 rx&tx */
2277 main_rec_hfcpci(bch);
2278 tx_birq(bch);
2279 }
2280 spin_unlock(&hc->lock);
2281 }
2282 return 0;
2283 }
2284
2285 static void
2286 hfcpci_softirq(struct timer_list *unused)
2287 {
2288 WARN_ON_ONCE(driver_for_each_device(&hfc_driver.driver, NULL, NULL,
2289 _hfcpci_softirq) != 0);
2290
2291 /* if next event would be in the past ... */
2292 if ((s32)(hfc_jiffies + tics - jiffies) <= 0)
2293 hfc_jiffies = jiffies + 1;
2294 else
2295 hfc_jiffies += tics;
2296 hfc_tl.expires = hfc_jiffies;
2297 add_timer(&hfc_tl);
2298 }
2299
2300 static int __init
2301 HFC_init(void)
2302 {
2303 int err;
2304
2305 if (!poll)
2306 poll = HFCPCI_BTRANS_THRESHOLD;
2307
2308 if (poll != HFCPCI_BTRANS_THRESHOLD) {
2309 tics = (poll * HZ) / 8000;
2310 if (tics < 1)
2311 tics = 1;
2312 poll = (tics * 8000) / HZ;
2313 if (poll > 256 || poll < 8) {
2314 printk(KERN_ERR "%s: Wrong poll value %d not in range "
2315 "of 8..256.\n", __func__, poll);
2316 err = -EINVAL;
2317 return err;
2318 }
2319 }
2320 if (poll != HFCPCI_BTRANS_THRESHOLD) {
2321 printk(KERN_INFO "%s: Using alternative poll value of %d\n",
2322 __func__, poll);
2323 timer_setup(&hfc_tl, hfcpci_softirq, 0);
2324 hfc_tl.expires = jiffies + tics;
2325 hfc_jiffies = hfc_tl.expires;
2326 add_timer(&hfc_tl);
2327 } else
2328 tics = 0; /* indicate the use of controller's timer */
2329
2330 err = pci_register_driver(&hfc_driver);
2331 if (err) {
2332 if (timer_pending(&hfc_tl))
2333 del_timer(&hfc_tl);
2334 }
2335
2336 return err;
2337 }
2338
2339 static void __exit
2340 HFC_cleanup(void)
2341 {
2342 if (timer_pending(&hfc_tl))
2343 del_timer(&hfc_tl);
2344
2345 pci_unregister_driver(&hfc_driver);
2346 }
2347
2348 module_init(HFC_init);
2349 module_exit(HFC_cleanup);
2350
2351 MODULE_DEVICE_TABLE(pci, hfc_ids);
Linux with added FPC-III support