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treewide: remove redundant IS_ERR() before error code check
[linux/fpc-iii.git] / drivers / media / dvb-frontends / mxl5xx.c
blob290b9eab099ff756227753f3bc220fb146118f09
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Driver for the MaxLinear MxL5xx family of tuners/demods
4 *
5 * Copyright (C) 2014-2015 Ralph Metzler <rjkm@metzlerbros.de>
6 * Marcus Metzler <mocm@metzlerbros.de>
7 * developed for Digital Devices GmbH
8 *
9 * based on code:
10 * Copyright (c) 2011-2013 MaxLinear, Inc. All rights reserved
11 * which was released under GPL V2
12 *
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License
15 * version 2, as published by the Free Software Foundation.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 */
22
23 #include <linux/kernel.h>
24 #include <linux/module.h>
25 #include <linux/moduleparam.h>
26 #include <linux/init.h>
27 #include <linux/delay.h>
28 #include <linux/firmware.h>
29 #include <linux/i2c.h>
30 #include <linux/version.h>
31 #include <linux/mutex.h>
32 #include <linux/vmalloc.h>
33 #include <asm/div64.h>
34 #include <asm/unaligned.h>
35
36 #include <media/dvb_frontend.h>
37 #include "mxl5xx.h"
38 #include "mxl5xx_regs.h"
39 #include "mxl5xx_defs.h"
40
41 #define BYTE0(v) ((v >> 0) & 0xff)
42 #define BYTE1(v) ((v >> 8) & 0xff)
43 #define BYTE2(v) ((v >> 16) & 0xff)
44 #define BYTE3(v) ((v >> 24) & 0xff)
45
46 static LIST_HEAD(mxllist);
47
48 struct mxl_base {
49 struct list_head mxllist;
50 struct list_head mxls;
51
52 u8 adr;
53 struct i2c_adapter *i2c;
54
55 u32 count;
56 u32 type;
57 u32 sku_type;
58 u32 chipversion;
59 u32 clock;
60 u32 fwversion;
61
62 u8 *ts_map;
63 u8 can_clkout;
64 u8 chan_bond;
65 u8 demod_num;
66 u8 tuner_num;
67
68 unsigned long next_tune;
69
70 struct mutex i2c_lock;
71 struct mutex status_lock;
72 struct mutex tune_lock;
73
74 u8 buf[MXL_HYDRA_OEM_MAX_CMD_BUFF_LEN];
75
76 u32 cmd_size;
77 u8 cmd_data[MAX_CMD_DATA];
78 };
79
80 struct mxl {
81 struct list_head mxl;
82
83 struct mxl_base *base;
84 struct dvb_frontend fe;
85 struct device *i2cdev;
86 u32 demod;
87 u32 tuner;
88 u32 tuner_in_use;
89 u8 xbar[3];
90
91 unsigned long tune_time;
92 };
93
94 static void convert_endian(u8 flag, u32 size, u8 *d)
95 {
96 u32 i;
97
98 if (!flag)
99 return;
100 for (i = 0; i < (size & ~3); i += 4) {
101 d[i + 0] ^= d[i + 3];
102 d[i + 3] ^= d[i + 0];
103 d[i + 0] ^= d[i + 3];
104
105 d[i + 1] ^= d[i + 2];
106 d[i + 2] ^= d[i + 1];
107 d[i + 1] ^= d[i + 2];
108 }
109
110 switch (size & 3) {
111 case 0:
112 case 1:
113 /* do nothing */
114 break;
115 case 2:
116 d[i + 0] ^= d[i + 1];
117 d[i + 1] ^= d[i + 0];
118 d[i + 0] ^= d[i + 1];
119 break;
120
121 case 3:
122 d[i + 0] ^= d[i + 2];
123 d[i + 2] ^= d[i + 0];
124 d[i + 0] ^= d[i + 2];
125 break;
126 }
127
128 }
129
130 static int i2c_write(struct i2c_adapter *adap, u8 adr,
131 u8 *data, u32 len)
132 {
133 struct i2c_msg msg = {.addr = adr, .flags = 0,
134 .buf = data, .len = len};
135
136 return (i2c_transfer(adap, &msg, 1) == 1) ? 0 : -1;
137 }
138
139 static int i2c_read(struct i2c_adapter *adap, u8 adr,
140 u8 *data, u32 len)
141 {
142 struct i2c_msg msg = {.addr = adr, .flags = I2C_M_RD,
143 .buf = data, .len = len};
144
145 return (i2c_transfer(adap, &msg, 1) == 1) ? 0 : -1;
146 }
147
148 static int i2cread(struct mxl *state, u8 *data, int len)
149 {
150 return i2c_read(state->base->i2c, state->base->adr, data, len);
151 }
152
153 static int i2cwrite(struct mxl *state, u8 *data, int len)
154 {
155 return i2c_write(state->base->i2c, state->base->adr, data, len);
156 }
157
158 static int read_register_unlocked(struct mxl *state, u32 reg, u32 *val)
159 {
160 int stat;
161 u8 data[MXL_HYDRA_REG_SIZE_IN_BYTES + MXL_HYDRA_I2C_HDR_SIZE] = {
162 MXL_HYDRA_PLID_REG_READ, 0x04,
163 GET_BYTE(reg, 0), GET_BYTE(reg, 1),
164 GET_BYTE(reg, 2), GET_BYTE(reg, 3),
165 };
166
167 stat = i2cwrite(state, data,
168 MXL_HYDRA_REG_SIZE_IN_BYTES + MXL_HYDRA_I2C_HDR_SIZE);
169 if (stat)
170 dev_err(state->i2cdev, "i2c read error 1\n");
171 if (!stat)
172 stat = i2cread(state, (u8 *) val,
173 MXL_HYDRA_REG_SIZE_IN_BYTES);
174 le32_to_cpus(val);
175 if (stat)
176 dev_err(state->i2cdev, "i2c read error 2\n");
177 return stat;
178 }
179
180 #define DMA_I2C_INTERRUPT_ADDR 0x8000011C
181 #define DMA_INTR_PROT_WR_CMP 0x08
182
183 static int send_command(struct mxl *state, u32 size, u8 *buf)
184 {
185 int stat;
186 u32 val, count = 10;
187
188 mutex_lock(&state->base->i2c_lock);
189 if (state->base->fwversion > 0x02010109) {
190 read_register_unlocked(state, DMA_I2C_INTERRUPT_ADDR, &val);
191 if (DMA_INTR_PROT_WR_CMP & val)
192 dev_info(state->i2cdev, "%s busy\n", __func__);
193 while ((DMA_INTR_PROT_WR_CMP & val) && --count) {
194 mutex_unlock(&state->base->i2c_lock);
195 usleep_range(1000, 2000);
196 mutex_lock(&state->base->i2c_lock);
197 read_register_unlocked(state, DMA_I2C_INTERRUPT_ADDR,
198 &val);
199 }
200 if (!count) {
201 dev_info(state->i2cdev, "%s busy\n", __func__);
202 mutex_unlock(&state->base->i2c_lock);
203 return -EBUSY;
204 }
205 }
206 stat = i2cwrite(state, buf, size);
207 mutex_unlock(&state->base->i2c_lock);
208 return stat;
209 }
210
211 static int write_register(struct mxl *state, u32 reg, u32 val)
212 {
213 int stat;
214 u8 data[MXL_HYDRA_REG_WRITE_LEN] = {
215 MXL_HYDRA_PLID_REG_WRITE, 0x08,
216 BYTE0(reg), BYTE1(reg), BYTE2(reg), BYTE3(reg),
217 BYTE0(val), BYTE1(val), BYTE2(val), BYTE3(val),
218 };
219 mutex_lock(&state->base->i2c_lock);
220 stat = i2cwrite(state, data, sizeof(data));
221 mutex_unlock(&state->base->i2c_lock);
222 if (stat)
223 dev_err(state->i2cdev, "i2c write error\n");
224 return stat;
225 }
226
227 static int write_firmware_block(struct mxl *state,
228 u32 reg, u32 size, u8 *reg_data_ptr)
229 {
230 int stat;
231 u8 *buf = state->base->buf;
232
233 mutex_lock(&state->base->i2c_lock);
234 buf[0] = MXL_HYDRA_PLID_REG_WRITE;
235 buf[1] = size + 4;
236 buf[2] = GET_BYTE(reg, 0);
237 buf[3] = GET_BYTE(reg, 1);
238 buf[4] = GET_BYTE(reg, 2);
239 buf[5] = GET_BYTE(reg, 3);
240 memcpy(&buf[6], reg_data_ptr, size);
241 stat = i2cwrite(state, buf,
242 MXL_HYDRA_I2C_HDR_SIZE +
243 MXL_HYDRA_REG_SIZE_IN_BYTES + size);
244 mutex_unlock(&state->base->i2c_lock);
245 if (stat)
246 dev_err(state->i2cdev, "fw block write failed\n");
247 return stat;
248 }
249
250 static int read_register(struct mxl *state, u32 reg, u32 *val)
251 {
252 int stat;
253 u8 data[MXL_HYDRA_REG_SIZE_IN_BYTES + MXL_HYDRA_I2C_HDR_SIZE] = {
254 MXL_HYDRA_PLID_REG_READ, 0x04,
255 GET_BYTE(reg, 0), GET_BYTE(reg, 1),
256 GET_BYTE(reg, 2), GET_BYTE(reg, 3),
257 };
258
259 mutex_lock(&state->base->i2c_lock);
260 stat = i2cwrite(state, data,
261 MXL_HYDRA_REG_SIZE_IN_BYTES + MXL_HYDRA_I2C_HDR_SIZE);
262 if (stat)
263 dev_err(state->i2cdev, "i2c read error 1\n");
264 if (!stat)
265 stat = i2cread(state, (u8 *) val,
266 MXL_HYDRA_REG_SIZE_IN_BYTES);
267 mutex_unlock(&state->base->i2c_lock);
268 le32_to_cpus(val);
269 if (stat)
270 dev_err(state->i2cdev, "i2c read error 2\n");
271 return stat;
272 }
273
274 static int read_register_block(struct mxl *state, u32 reg, u32 size, u8 *data)
275 {
276 int stat;
277 u8 *buf = state->base->buf;
278
279 mutex_lock(&state->base->i2c_lock);
280
281 buf[0] = MXL_HYDRA_PLID_REG_READ;
282 buf[1] = size + 4;
283 buf[2] = GET_BYTE(reg, 0);
284 buf[3] = GET_BYTE(reg, 1);
285 buf[4] = GET_BYTE(reg, 2);
286 buf[5] = GET_BYTE(reg, 3);
287 stat = i2cwrite(state, buf,
288 MXL_HYDRA_I2C_HDR_SIZE + MXL_HYDRA_REG_SIZE_IN_BYTES);
289 if (!stat) {
290 stat = i2cread(state, data, size);
291 convert_endian(MXL_ENABLE_BIG_ENDIAN, size, data);
292 }
293 mutex_unlock(&state->base->i2c_lock);
294 return stat;
295 }
296
297 static int read_by_mnemonic(struct mxl *state,
298 u32 reg, u8 lsbloc, u8 numofbits, u32 *val)
299 {
300 u32 data = 0, mask = 0;
301 int stat;
302
303 stat = read_register(state, reg, &data);
304 if (stat)
305 return stat;
306 mask = MXL_GET_REG_MASK_32(lsbloc, numofbits);
307 data &= mask;
308 data >>= lsbloc;
309 *val = data;
310 return 0;
311 }
312
313
314 static int update_by_mnemonic(struct mxl *state,
315 u32 reg, u8 lsbloc, u8 numofbits, u32 val)
316 {
317 u32 data, mask;
318 int stat;
319
320 stat = read_register(state, reg, &data);
321 if (stat)
322 return stat;
323 mask = MXL_GET_REG_MASK_32(lsbloc, numofbits);
324 data = (data & ~mask) | ((val << lsbloc) & mask);
325 stat = write_register(state, reg, data);
326 return stat;
327 }
328
329 static int firmware_is_alive(struct mxl *state)
330 {
331 u32 hb0, hb1;
332
333 if (read_register(state, HYDRA_HEAR_BEAT, &hb0))
334 return 0;
335 msleep(20);
336 if (read_register(state, HYDRA_HEAR_BEAT, &hb1))
337 return 0;
338 if (hb1 == hb0)
339 return 0;
340 return 1;
341 }
342
343 static int init(struct dvb_frontend *fe)
344 {
345 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
346
347 /* init fe stats */
348 p->strength.len = 1;
349 p->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
350 p->cnr.len = 1;
351 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
352 p->pre_bit_error.len = 1;
353 p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
354 p->pre_bit_count.len = 1;
355 p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
356 p->post_bit_error.len = 1;
357 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
358 p->post_bit_count.len = 1;
359 p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
360
361 return 0;
362 }
363
364 static void release(struct dvb_frontend *fe)
365 {
366 struct mxl *state = fe->demodulator_priv;
367
368 list_del(&state->mxl);
369 /* Release one frontend, two more shall take its place! */
370 state->base->count--;
371 if (state->base->count == 0) {
372 list_del(&state->base->mxllist);
373 kfree(state->base);
374 }
375 kfree(state);
376 }
377
378 static enum dvbfe_algo get_algo(struct dvb_frontend *fe)
379 {
380 return DVBFE_ALGO_HW;
381 }
382
383 static u32 gold2root(u32 gold)
384 {
385 u32 x, g, tmp = gold;
386
387 if (tmp >= 0x3ffff)
388 tmp = 0;
389 for (g = 0, x = 1; g < tmp; g++)
390 x = (((x ^ (x >> 7)) & 1) << 17) | (x >> 1);
391 return x;
392 }
393
394 static int cfg_scrambler(struct mxl *state, u32 gold)
395 {
396 u32 root;
397 u8 buf[26] = {
398 MXL_HYDRA_PLID_CMD_WRITE, 24,
399 0, MXL_HYDRA_DEMOD_SCRAMBLE_CODE_CMD, 0, 0,
400 state->demod, 0, 0, 0,
401 0, 0, 0, 0, 0, 0, 0, 0,
402 0, 0, 0, 0, 1, 0, 0, 0,
403 };
404
405 root = gold2root(gold);
406
407 buf[25] = (root >> 24) & 0xff;
408 buf[24] = (root >> 16) & 0xff;
409 buf[23] = (root >> 8) & 0xff;
410 buf[22] = root & 0xff;
411
412 return send_command(state, sizeof(buf), buf);
413 }
414
415 static int cfg_demod_abort_tune(struct mxl *state)
416 {
417 struct MXL_HYDRA_DEMOD_ABORT_TUNE_T abort_tune_cmd;
418 u8 cmd_size = sizeof(abort_tune_cmd);
419 u8 cmd_buff[MXL_HYDRA_OEM_MAX_CMD_BUFF_LEN];
420
421 abort_tune_cmd.demod_id = state->demod;
422 BUILD_HYDRA_CMD(MXL_HYDRA_ABORT_TUNE_CMD, MXL_CMD_WRITE,
423 cmd_size, &abort_tune_cmd, cmd_buff);
424 return send_command(state, cmd_size + MXL_HYDRA_CMD_HEADER_SIZE,
425 &cmd_buff[0]);
426 }
427
428 static int send_master_cmd(struct dvb_frontend *fe,
429 struct dvb_diseqc_master_cmd *cmd)
430 {
431 /*struct mxl *state = fe->demodulator_priv;*/
432
433 return 0; /*CfgDemodAbortTune(state);*/
434 }
435
436 static int set_parameters(struct dvb_frontend *fe)
437 {
438 struct mxl *state = fe->demodulator_priv;
439 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
440 struct MXL_HYDRA_DEMOD_PARAM_T demod_chan_cfg;
441 u8 cmd_size = sizeof(demod_chan_cfg);
442 u8 cmd_buff[MXL_HYDRA_OEM_MAX_CMD_BUFF_LEN];
443 u32 srange = 10;
444 int stat;
445
446 if (p->frequency < 950000 || p->frequency > 2150000)
447 return -EINVAL;
448 if (p->symbol_rate < 1000000 || p->symbol_rate > 45000000)
449 return -EINVAL;
450
451 /* CfgDemodAbortTune(state); */
452
453 switch (p->delivery_system) {
454 case SYS_DSS:
455 demod_chan_cfg.standard = MXL_HYDRA_DSS;
456 demod_chan_cfg.roll_off = MXL_HYDRA_ROLLOFF_AUTO;
457 break;
458 case SYS_DVBS:
459 srange = p->symbol_rate / 1000000;
460 if (srange > 10)
461 srange = 10;
462 demod_chan_cfg.standard = MXL_HYDRA_DVBS;
463 demod_chan_cfg.roll_off = MXL_HYDRA_ROLLOFF_0_35;
464 demod_chan_cfg.modulation_scheme = MXL_HYDRA_MOD_QPSK;
465 demod_chan_cfg.pilots = MXL_HYDRA_PILOTS_OFF;
466 break;
467 case SYS_DVBS2:
468 demod_chan_cfg.standard = MXL_HYDRA_DVBS2;
469 demod_chan_cfg.roll_off = MXL_HYDRA_ROLLOFF_AUTO;
470 demod_chan_cfg.modulation_scheme = MXL_HYDRA_MOD_AUTO;
471 demod_chan_cfg.pilots = MXL_HYDRA_PILOTS_AUTO;
472 cfg_scrambler(state, p->scrambling_sequence_index);
473 break;
474 default:
475 return -EINVAL;
476 }
477 demod_chan_cfg.tuner_index = state->tuner;
478 demod_chan_cfg.demod_index = state->demod;
479 demod_chan_cfg.frequency_in_hz = p->frequency * 1000;
480 demod_chan_cfg.symbol_rate_in_hz = p->symbol_rate;
481 demod_chan_cfg.max_carrier_offset_in_mhz = srange;
482 demod_chan_cfg.spectrum_inversion = MXL_HYDRA_SPECTRUM_AUTO;
483 demod_chan_cfg.fec_code_rate = MXL_HYDRA_FEC_AUTO;
484
485 mutex_lock(&state->base->tune_lock);
486 if (time_after(jiffies + msecs_to_jiffies(200),
487 state->base->next_tune))
488 while (time_before(jiffies, state->base->next_tune))
489 usleep_range(10000, 11000);
490 state->base->next_tune = jiffies + msecs_to_jiffies(100);
491 state->tuner_in_use = state->tuner;
492 BUILD_HYDRA_CMD(MXL_HYDRA_DEMOD_SET_PARAM_CMD, MXL_CMD_WRITE,
493 cmd_size, &demod_chan_cfg, cmd_buff);
494 stat = send_command(state, cmd_size + MXL_HYDRA_CMD_HEADER_SIZE,
495 &cmd_buff[0]);
496 mutex_unlock(&state->base->tune_lock);
497 return stat;
498 }
499
500 static int enable_tuner(struct mxl *state, u32 tuner, u32 enable);
501
502 static int sleep(struct dvb_frontend *fe)
503 {
504 struct mxl *state = fe->demodulator_priv;
505 struct mxl *p;
506
507 cfg_demod_abort_tune(state);
508 if (state->tuner_in_use != 0xffffffff) {
509 mutex_lock(&state->base->tune_lock);
510 state->tuner_in_use = 0xffffffff;
511 list_for_each_entry(p, &state->base->mxls, mxl) {
512 if (p->tuner_in_use == state->tuner)
513 break;
514 }
515 if (&p->mxl == &state->base->mxls)
516 enable_tuner(state, state->tuner, 0);
517 mutex_unlock(&state->base->tune_lock);
518 }
519 return 0;
520 }
521
522 static int read_snr(struct dvb_frontend *fe)
523 {
524 struct mxl *state = fe->demodulator_priv;
525 int stat;
526 u32 reg_data = 0;
527 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
528
529 mutex_lock(&state->base->status_lock);
530 HYDRA_DEMOD_STATUS_LOCK(state, state->demod);
531 stat = read_register(state, (HYDRA_DMD_SNR_ADDR_OFFSET +
532 HYDRA_DMD_STATUS_OFFSET(state->demod)),
533 &reg_data);
534 HYDRA_DEMOD_STATUS_UNLOCK(state, state->demod);
535 mutex_unlock(&state->base->status_lock);
536
537 p->cnr.stat[0].scale = FE_SCALE_DECIBEL;
538 p->cnr.stat[0].svalue = (s16)reg_data * 10;
539
540 return stat;
541 }
542
543 static int read_ber(struct dvb_frontend *fe)
544 {
545 struct mxl *state = fe->demodulator_priv;
546 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
547 u32 reg[8];
548
549 mutex_lock(&state->base->status_lock);
550 HYDRA_DEMOD_STATUS_LOCK(state, state->demod);
551 read_register_block(state,
552 (HYDRA_DMD_DVBS_1ST_CORR_RS_ERRORS_ADDR_OFFSET +
553 HYDRA_DMD_STATUS_OFFSET(state->demod)),
554 (4 * sizeof(u32)),
555 (u8 *) &reg[0]);
556 HYDRA_DEMOD_STATUS_UNLOCK(state, state->demod);
557
558 switch (p->delivery_system) {
559 case SYS_DSS:
560 case SYS_DVBS:
561 p->pre_bit_error.stat[0].scale = FE_SCALE_COUNTER;
562 p->pre_bit_error.stat[0].uvalue = reg[2];
563 p->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER;
564 p->pre_bit_count.stat[0].uvalue = reg[3];
565 break;
566 default:
567 break;
568 }
569
570 read_register_block(state,
571 (HYDRA_DMD_DVBS2_CRC_ERRORS_ADDR_OFFSET +
572 HYDRA_DMD_STATUS_OFFSET(state->demod)),
573 (7 * sizeof(u32)),
574 (u8 *) &reg[0]);
575
576 switch (p->delivery_system) {
577 case SYS_DSS:
578 case SYS_DVBS:
579 p->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
580 p->post_bit_error.stat[0].uvalue = reg[5];
581 p->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
582 p->post_bit_count.stat[0].uvalue = reg[6];
583 break;
584 case SYS_DVBS2:
585 p->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
586 p->post_bit_error.stat[0].uvalue = reg[1];
587 p->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
588 p->post_bit_count.stat[0].uvalue = reg[2];
589 break;
590 default:
591 break;
592 }
593
594 mutex_unlock(&state->base->status_lock);
595
596 return 0;
597 }
598
599 static int read_signal_strength(struct dvb_frontend *fe)
600 {
601 struct mxl *state = fe->demodulator_priv;
602 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
603 int stat;
604 u32 reg_data = 0;
605
606 mutex_lock(&state->base->status_lock);
607 HYDRA_DEMOD_STATUS_LOCK(state, state->demod);
608 stat = read_register(state, (HYDRA_DMD_STATUS_INPUT_POWER_ADDR +
609 HYDRA_DMD_STATUS_OFFSET(state->demod)),
610 &reg_data);
611 HYDRA_DEMOD_STATUS_UNLOCK(state, state->demod);
612 mutex_unlock(&state->base->status_lock);
613
614 p->strength.stat[0].scale = FE_SCALE_DECIBEL;
615 p->strength.stat[0].svalue = (s16) reg_data * 10; /* fix scale */
616
617 return stat;
618 }
619
620 static int read_status(struct dvb_frontend *fe, enum fe_status *status)
621 {
622 struct mxl *state = fe->demodulator_priv;
623 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
624 u32 reg_data = 0;
625
626 mutex_lock(&state->base->status_lock);
627 HYDRA_DEMOD_STATUS_LOCK(state, state->demod);
628 read_register(state, (HYDRA_DMD_LOCK_STATUS_ADDR_OFFSET +
629 HYDRA_DMD_STATUS_OFFSET(state->demod)),
630 &reg_data);
631 HYDRA_DEMOD_STATUS_UNLOCK(state, state->demod);
632 mutex_unlock(&state->base->status_lock);
633
634 *status = (reg_data == 1) ? 0x1f : 0;
635
636 /* signal statistics */
637
638 /* signal strength is always available */
639 read_signal_strength(fe);
640
641 if (*status & FE_HAS_CARRIER)
642 read_snr(fe);
643 else
644 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
645
646 if (*status & FE_HAS_SYNC)
647 read_ber(fe);
648 else {
649 p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
650 p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
651 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
652 p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
653 }
654
655 return 0;
656 }
657
658 static int tune(struct dvb_frontend *fe, bool re_tune,
659 unsigned int mode_flags,
660 unsigned int *delay, enum fe_status *status)
661 {
662 struct mxl *state = fe->demodulator_priv;
663 int r = 0;
664
665 *delay = HZ / 2;
666 if (re_tune) {
667 r = set_parameters(fe);
668 if (r)
669 return r;
670 state->tune_time = jiffies;
671 }
672
673 return read_status(fe, status);
674 }
675
676 static enum fe_code_rate conv_fec(enum MXL_HYDRA_FEC_E fec)
677 {
678 enum fe_code_rate fec2fec[11] = {
679 FEC_NONE, FEC_1_2, FEC_3_5, FEC_2_3,
680 FEC_3_4, FEC_4_5, FEC_5_6, FEC_6_7,
681 FEC_7_8, FEC_8_9, FEC_9_10
682 };
683
684 if (fec > MXL_HYDRA_FEC_9_10)
685 return FEC_NONE;
686 return fec2fec[fec];
687 }
688
689 static int get_frontend(struct dvb_frontend *fe,
690 struct dtv_frontend_properties *p)
691 {
692 struct mxl *state = fe->demodulator_priv;
693 u32 reg_data[MXL_DEMOD_CHAN_PARAMS_BUFF_SIZE];
694 u32 freq;
695
696 mutex_lock(&state->base->status_lock);
697 HYDRA_DEMOD_STATUS_LOCK(state, state->demod);
698 read_register_block(state,
699 (HYDRA_DMD_STANDARD_ADDR_OFFSET +
700 HYDRA_DMD_STATUS_OFFSET(state->demod)),
701 (MXL_DEMOD_CHAN_PARAMS_BUFF_SIZE * 4), /* 25 * 4 bytes */
702 (u8 *) &reg_data[0]);
703 /* read demod channel parameters */
704 read_register_block(state,
705 (HYDRA_DMD_STATUS_CENTER_FREQ_IN_KHZ_ADDR +
706 HYDRA_DMD_STATUS_OFFSET(state->demod)),
707 (4), /* 4 bytes */
708 (u8 *) &freq);
709 HYDRA_DEMOD_STATUS_UNLOCK(state, state->demod);
710 mutex_unlock(&state->base->status_lock);
711
712 dev_dbg(state->i2cdev, "freq=%u delsys=%u srate=%u\n",
713 freq * 1000, reg_data[DMD_STANDARD_ADDR],
714 reg_data[DMD_SYMBOL_RATE_ADDR]);
715 p->symbol_rate = reg_data[DMD_SYMBOL_RATE_ADDR];
716 p->frequency = freq;
717 /*
718 * p->delivery_system =
719 * (MXL_HYDRA_BCAST_STD_E) regData[DMD_STANDARD_ADDR];
720 * p->inversion =
721 * (MXL_HYDRA_SPECTRUM_E) regData[DMD_SPECTRUM_INVERSION_ADDR];
722 * freqSearchRangeKHz =
723 * (regData[DMD_FREQ_SEARCH_RANGE_IN_KHZ_ADDR]);
724 */
725
726 p->fec_inner = conv_fec(reg_data[DMD_FEC_CODE_RATE_ADDR]);
727 switch (p->delivery_system) {
728 case SYS_DSS:
729 break;
730 case SYS_DVBS2:
731 switch ((enum MXL_HYDRA_PILOTS_E)
732 reg_data[DMD_DVBS2_PILOT_ON_OFF_ADDR]) {
733 case MXL_HYDRA_PILOTS_OFF:
734 p->pilot = PILOT_OFF;
735 break;
736 case MXL_HYDRA_PILOTS_ON:
737 p->pilot = PILOT_ON;
738 break;
739 default:
740 break;
741 }
742 /* Fall through */
743 case SYS_DVBS:
744 switch ((enum MXL_HYDRA_MODULATION_E)
745 reg_data[DMD_MODULATION_SCHEME_ADDR]) {
746 case MXL_HYDRA_MOD_QPSK:
747 p->modulation = QPSK;
748 break;
749 case MXL_HYDRA_MOD_8PSK:
750 p->modulation = PSK_8;
751 break;
752 default:
753 break;
754 }
755 switch ((enum MXL_HYDRA_ROLLOFF_E)
756 reg_data[DMD_SPECTRUM_ROLL_OFF_ADDR]) {
757 case MXL_HYDRA_ROLLOFF_0_20:
758 p->rolloff = ROLLOFF_20;
759 break;
760 case MXL_HYDRA_ROLLOFF_0_35:
761 p->rolloff = ROLLOFF_35;
762 break;
763 case MXL_HYDRA_ROLLOFF_0_25:
764 p->rolloff = ROLLOFF_25;
765 break;
766 default:
767 break;
768 }
769 break;
770 default:
771 return -EINVAL;
772 }
773 return 0;
774 }
775
776 static int set_input(struct dvb_frontend *fe, int input)
777 {
778 struct mxl *state = fe->demodulator_priv;
779
780 state->tuner = input;
781 return 0;
782 }
783
784 static const struct dvb_frontend_ops mxl_ops = {
785 .delsys = { SYS_DVBS, SYS_DVBS2, SYS_DSS },
786 .info = {
787 .name = "MaxLinear MxL5xx DVB-S/S2 tuner-demodulator",
788 .frequency_min_hz = 300 * MHz,
789 .frequency_max_hz = 2350 * MHz,
790 .symbol_rate_min = 1000000,
791 .symbol_rate_max = 45000000,
792 .caps = FE_CAN_INVERSION_AUTO |
793 FE_CAN_FEC_AUTO |
794 FE_CAN_QPSK |
795 FE_CAN_2G_MODULATION
796 },
797 .init = init,
798 .release = release,
799 .get_frontend_algo = get_algo,
800 .tune = tune,
801 .read_status = read_status,
802 .sleep = sleep,
803 .get_frontend = get_frontend,
804 .diseqc_send_master_cmd = send_master_cmd,
805 };
806
807 static struct mxl_base *match_base(struct i2c_adapter *i2c, u8 adr)
808 {
809 struct mxl_base *p;
810
811 list_for_each_entry(p, &mxllist, mxllist)
812 if (p->i2c == i2c && p->adr == adr)
813 return p;
814 return NULL;
815 }
816
817 static void cfg_dev_xtal(struct mxl *state, u32 freq, u32 cap, u32 enable)
818 {
819 if (state->base->can_clkout || !enable)
820 update_by_mnemonic(state, 0x90200054, 23, 1, enable);
821
822 if (freq == 24000000)
823 write_register(state, HYDRA_CRYSTAL_SETTING, 0);
824 else
825 write_register(state, HYDRA_CRYSTAL_SETTING, 1);
826
827 write_register(state, HYDRA_CRYSTAL_CAP, cap);
828 }
829
830 static u32 get_big_endian(u8 num_of_bits, const u8 buf[])
831 {
832 u32 ret_value = 0;
833
834 switch (num_of_bits) {
835 case 24:
836 ret_value = (((u32) buf[0]) << 16) |
837 (((u32) buf[1]) << 8) | buf[2];
838 break;
839 case 32:
840 ret_value = (((u32) buf[0]) << 24) |
841 (((u32) buf[1]) << 16) |
842 (((u32) buf[2]) << 8) | buf[3];
843 break;
844 default:
845 break;
846 }
847
848 return ret_value;
849 }
850
851 static int write_fw_segment(struct mxl *state,
852 u32 mem_addr, u32 total_size, u8 *data_ptr)
853 {
854 int status;
855 u32 data_count = 0;
856 u32 size = 0;
857 u32 orig_size = 0;
858 u8 *w_buf_ptr = NULL;
859 u32 block_size = ((MXL_HYDRA_OEM_MAX_BLOCK_WRITE_LENGTH -
860 (MXL_HYDRA_I2C_HDR_SIZE +
861 MXL_HYDRA_REG_SIZE_IN_BYTES)) / 4) * 4;
862 u8 w_msg_buffer[MXL_HYDRA_OEM_MAX_BLOCK_WRITE_LENGTH -
863 (MXL_HYDRA_I2C_HDR_SIZE + MXL_HYDRA_REG_SIZE_IN_BYTES)];
864
865 do {
866 size = orig_size = (((u32)(data_count + block_size)) > total_size) ?
867 (total_size - data_count) : block_size;
868
869 if (orig_size & 3)
870 size = (orig_size + 4) & ~3;
871 w_buf_ptr = &w_msg_buffer[0];
872 memset((void *) w_buf_ptr, 0, size);
873 memcpy((void *) w_buf_ptr, (void *) data_ptr, orig_size);
874 convert_endian(1, size, w_buf_ptr);
875 status = write_firmware_block(state, mem_addr, size, w_buf_ptr);
876 if (status)
877 return status;
878 data_count += size;
879 mem_addr += size;
880 data_ptr += size;
881 } while (data_count < total_size);
882
883 return status;
884 }
885
886 static int do_firmware_download(struct mxl *state, u8 *mbin_buffer_ptr,
887 u32 mbin_buffer_size)
888
889 {
890 int status;
891 u32 index = 0;
892 u32 seg_length = 0;
893 u32 seg_address = 0;
894 struct MBIN_FILE_T *mbin_ptr = (struct MBIN_FILE_T *)mbin_buffer_ptr;
895 struct MBIN_SEGMENT_T *segment_ptr;
896 enum MXL_BOOL_E xcpu_fw_flag = MXL_FALSE;
897
898 if (mbin_ptr->header.id != MBIN_FILE_HEADER_ID) {
899 dev_err(state->i2cdev, "%s: Invalid file header ID (%c)\n",
900 __func__, mbin_ptr->header.id);
901 return -EINVAL;
902 }
903 status = write_register(state, FW_DL_SIGN_ADDR, 0);
904 if (status)
905 return status;
906 segment_ptr = (struct MBIN_SEGMENT_T *) (&mbin_ptr->data[0]);
907 for (index = 0; index < mbin_ptr->header.num_segments; index++) {
908 if (segment_ptr->header.id != MBIN_SEGMENT_HEADER_ID) {
909 dev_err(state->i2cdev, "%s: Invalid segment header ID (%c)\n",
910 __func__, segment_ptr->header.id);
911 return -EINVAL;
912 }
913 seg_length = get_big_endian(24,
914 &(segment_ptr->header.len24[0]));
915 seg_address = get_big_endian(32,
916 &(segment_ptr->header.address[0]));
917
918 if (state->base->type == MXL_HYDRA_DEVICE_568) {
919 if ((((seg_address & 0x90760000) == 0x90760000) ||
920 ((seg_address & 0x90740000) == 0x90740000)) &&
921 (xcpu_fw_flag == MXL_FALSE)) {
922 update_by_mnemonic(state, 0x8003003C, 0, 1, 1);
923 msleep(200);
924 write_register(state, 0x90720000, 0);
925 usleep_range(10000, 11000);
926 xcpu_fw_flag = MXL_TRUE;
927 }
928 status = write_fw_segment(state, seg_address,
929 seg_length,
930 (u8 *) segment_ptr->data);
931 } else {
932 if (((seg_address & 0x90760000) != 0x90760000) &&
933 ((seg_address & 0x90740000) != 0x90740000))
934 status = write_fw_segment(state, seg_address,
935 seg_length, (u8 *) segment_ptr->data);
936 }
937 if (status)
938 return status;
939 segment_ptr = (struct MBIN_SEGMENT_T *)
940 &(segment_ptr->data[((seg_length + 3) / 4) * 4]);
941 }
942 return status;
943 }
944
945 static int check_fw(struct mxl *state, u8 *mbin, u32 mbin_len)
946 {
947 struct MBIN_FILE_HEADER_T *fh = (struct MBIN_FILE_HEADER_T *) mbin;
948 u32 flen = (fh->image_size24[0] << 16) |
949 (fh->image_size24[1] << 8) | fh->image_size24[2];
950 u8 *fw, cs = 0;
951 u32 i;
952
953 if (fh->id != 'M' || fh->fmt_version != '1' || flen > 0x3FFF0) {
954 dev_info(state->i2cdev, "Invalid FW Header\n");
955 return -1;
956 }
957 fw = mbin + sizeof(struct MBIN_FILE_HEADER_T);
958 for (i = 0; i < flen; i += 1)
959 cs += fw[i];
960 if (cs != fh->image_checksum) {
961 dev_info(state->i2cdev, "Invalid FW Checksum\n");
962 return -1;
963 }
964 return 0;
965 }
966
967 static int firmware_download(struct mxl *state, u8 *mbin, u32 mbin_len)
968 {
969 int status;
970 u32 reg_data = 0;
971 struct MXL_HYDRA_SKU_COMMAND_T dev_sku_cfg;
972 u8 cmd_size = sizeof(struct MXL_HYDRA_SKU_COMMAND_T);
973 u8 cmd_buff[sizeof(struct MXL_HYDRA_SKU_COMMAND_T) + 6];
974
975 if (check_fw(state, mbin, mbin_len))
976 return -1;
977
978 /* put CPU into reset */
979 status = update_by_mnemonic(state, 0x8003003C, 0, 1, 0);
980 if (status)
981 return status;
982 usleep_range(1000, 2000);
983
984 /* Reset TX FIFO's, BBAND, XBAR */
985 status = write_register(state, HYDRA_RESET_TRANSPORT_FIFO_REG,
986 HYDRA_RESET_TRANSPORT_FIFO_DATA);
987 if (status)
988 return status;
989 status = write_register(state, HYDRA_RESET_BBAND_REG,
990 HYDRA_RESET_BBAND_DATA);
991 if (status)
992 return status;
993 status = write_register(state, HYDRA_RESET_XBAR_REG,
994 HYDRA_RESET_XBAR_DATA);
995 if (status)
996 return status;
997
998 /* Disable clock to Baseband, Wideband, SerDes,
999 * Alias ext & Transport modules
1000 */
1001 status = write_register(state, HYDRA_MODULES_CLK_2_REG,
1002 HYDRA_DISABLE_CLK_2);
1003 if (status)
1004 return status;
1005 /* Clear Software & Host interrupt status - (Clear on read) */
1006 status = read_register(state, HYDRA_PRCM_ROOT_CLK_REG, &reg_data);
1007 if (status)
1008 return status;
1009 status = do_firmware_download(state, mbin, mbin_len);
1010 if (status)
1011 return status;
1012
1013 if (state->base->type == MXL_HYDRA_DEVICE_568) {
1014 usleep_range(10000, 11000);
1015
1016 /* bring XCPU out of reset */
1017 status = write_register(state, 0x90720000, 1);
1018 if (status)
1019 return status;
1020 msleep(500);
1021
1022 /* Enable XCPU UART message processing in MCPU */
1023 status = write_register(state, 0x9076B510, 1);
1024 if (status)
1025 return status;
1026 } else {
1027 /* Bring CPU out of reset */
1028 status = update_by_mnemonic(state, 0x8003003C, 0, 1, 1);
1029 if (status)
1030 return status;
1031 /* Wait until FW boots */
1032 msleep(150);
1033 }
1034
1035 /* Initialize XPT XBAR */
1036 status = write_register(state, XPT_DMD0_BASEADDR, 0x76543210);
1037 if (status)
1038 return status;
1039
1040 if (!firmware_is_alive(state))
1041 return -1;
1042
1043 dev_info(state->i2cdev, "Hydra FW alive. Hail!\n");
1044
1045 /* sometimes register values are wrong shortly
1046 * after first heart beats
1047 */
1048 msleep(50);
1049
1050 dev_sku_cfg.sku_type = state->base->sku_type;
1051 BUILD_HYDRA_CMD(MXL_HYDRA_DEV_CFG_SKU_CMD, MXL_CMD_WRITE,
1052 cmd_size, &dev_sku_cfg, cmd_buff);
1053 status = send_command(state, cmd_size + MXL_HYDRA_CMD_HEADER_SIZE,
1054 &cmd_buff[0]);
1055
1056 return status;
1057 }
1058
1059 static int cfg_ts_pad_mux(struct mxl *state, enum MXL_BOOL_E enable_serial_ts)
1060 {
1061 int status = 0;
1062 u32 pad_mux_value = 0;
1063
1064 if (enable_serial_ts == MXL_TRUE) {
1065 pad_mux_value = 0;
1066 if ((state->base->type == MXL_HYDRA_DEVICE_541) ||
1067 (state->base->type == MXL_HYDRA_DEVICE_541S))
1068 pad_mux_value = 2;
1069 } else {
1070 if ((state->base->type == MXL_HYDRA_DEVICE_581) ||
1071 (state->base->type == MXL_HYDRA_DEVICE_581S))
1072 pad_mux_value = 2;
1073 else
1074 pad_mux_value = 3;
1075 }
1076
1077 switch (state->base->type) {
1078 case MXL_HYDRA_DEVICE_561:
1079 case MXL_HYDRA_DEVICE_581:
1080 case MXL_HYDRA_DEVICE_541:
1081 case MXL_HYDRA_DEVICE_541S:
1082 case MXL_HYDRA_DEVICE_561S:
1083 case MXL_HYDRA_DEVICE_581S:
1084 status |= update_by_mnemonic(state, 0x90000170, 24, 3,
1085 pad_mux_value);
1086 status |= update_by_mnemonic(state, 0x90000170, 28, 3,
1087 pad_mux_value);
1088 status |= update_by_mnemonic(state, 0x90000174, 0, 3,
1089 pad_mux_value);
1090 status |= update_by_mnemonic(state, 0x90000174, 4, 3,
1091 pad_mux_value);
1092 status |= update_by_mnemonic(state, 0x90000174, 8, 3,
1093 pad_mux_value);
1094 status |= update_by_mnemonic(state, 0x90000174, 12, 3,
1095 pad_mux_value);
1096 status |= update_by_mnemonic(state, 0x90000174, 16, 3,
1097 pad_mux_value);
1098 status |= update_by_mnemonic(state, 0x90000174, 20, 3,
1099 pad_mux_value);
1100 status |= update_by_mnemonic(state, 0x90000174, 24, 3,
1101 pad_mux_value);
1102 status |= update_by_mnemonic(state, 0x90000174, 28, 3,
1103 pad_mux_value);
1104 status |= update_by_mnemonic(state, 0x90000178, 0, 3,
1105 pad_mux_value);
1106 status |= update_by_mnemonic(state, 0x90000178, 4, 3,
1107 pad_mux_value);
1108 status |= update_by_mnemonic(state, 0x90000178, 8, 3,
1109 pad_mux_value);
1110 break;
1111
1112 case MXL_HYDRA_DEVICE_544:
1113 case MXL_HYDRA_DEVICE_542:
1114 status |= update_by_mnemonic(state, 0x9000016C, 4, 3, 1);
1115 status |= update_by_mnemonic(state, 0x9000016C, 8, 3, 0);
1116 status |= update_by_mnemonic(state, 0x9000016C, 12, 3, 0);
1117 status |= update_by_mnemonic(state, 0x9000016C, 16, 3, 0);
1118 status |= update_by_mnemonic(state, 0x90000170, 0, 3, 0);
1119 status |= update_by_mnemonic(state, 0x90000178, 12, 3, 1);
1120 status |= update_by_mnemonic(state, 0x90000178, 16, 3, 1);
1121 status |= update_by_mnemonic(state, 0x90000178, 20, 3, 1);
1122 status |= update_by_mnemonic(state, 0x90000178, 24, 3, 1);
1123 status |= update_by_mnemonic(state, 0x9000017C, 0, 3, 1);
1124 status |= update_by_mnemonic(state, 0x9000017C, 4, 3, 1);
1125 if (enable_serial_ts == MXL_ENABLE) {
1126 status |= update_by_mnemonic(state,
1127 0x90000170, 4, 3, 0);
1128 status |= update_by_mnemonic(state,
1129 0x90000170, 8, 3, 0);
1130 status |= update_by_mnemonic(state,
1131 0x90000170, 12, 3, 0);
1132 status |= update_by_mnemonic(state,
1133 0x90000170, 16, 3, 0);
1134 status |= update_by_mnemonic(state,
1135 0x90000170, 20, 3, 1);
1136 status |= update_by_mnemonic(state,
1137 0x90000170, 24, 3, 1);
1138 status |= update_by_mnemonic(state,
1139 0x90000170, 28, 3, 2);
1140 status |= update_by_mnemonic(state,
1141 0x90000174, 0, 3, 2);
1142 status |= update_by_mnemonic(state,
1143 0x90000174, 4, 3, 2);
1144 status |= update_by_mnemonic(state,
1145 0x90000174, 8, 3, 2);
1146 status |= update_by_mnemonic(state,
1147 0x90000174, 12, 3, 2);
1148 status |= update_by_mnemonic(state,
1149 0x90000174, 16, 3, 2);
1150 status |= update_by_mnemonic(state,
1151 0x90000174, 20, 3, 2);
1152 status |= update_by_mnemonic(state,
1153 0x90000174, 24, 3, 2);
1154 status |= update_by_mnemonic(state,
1155 0x90000174, 28, 3, 2);
1156 status |= update_by_mnemonic(state,
1157 0x90000178, 0, 3, 2);
1158 status |= update_by_mnemonic(state,
1159 0x90000178, 4, 3, 2);
1160 status |= update_by_mnemonic(state,
1161 0x90000178, 8, 3, 2);
1162 } else {
1163 status |= update_by_mnemonic(state,
1164 0x90000170, 4, 3, 3);
1165 status |= update_by_mnemonic(state,
1166 0x90000170, 8, 3, 3);
1167 status |= update_by_mnemonic(state,
1168 0x90000170, 12, 3, 3);
1169 status |= update_by_mnemonic(state,
1170 0x90000170, 16, 3, 3);
1171 status |= update_by_mnemonic(state,
1172 0x90000170, 20, 3, 3);
1173 status |= update_by_mnemonic(state,
1174 0x90000170, 24, 3, 3);
1175 status |= update_by_mnemonic(state,
1176 0x90000170, 28, 3, 3);
1177 status |= update_by_mnemonic(state,
1178 0x90000174, 0, 3, 3);
1179 status |= update_by_mnemonic(state,
1180 0x90000174, 4, 3, 3);
1181 status |= update_by_mnemonic(state,
1182 0x90000174, 8, 3, 3);
1183 status |= update_by_mnemonic(state,
1184 0x90000174, 12, 3, 3);
1185 status |= update_by_mnemonic(state,
1186 0x90000174, 16, 3, 3);
1187 status |= update_by_mnemonic(state,
1188 0x90000174, 20, 3, 1);
1189 status |= update_by_mnemonic(state,
1190 0x90000174, 24, 3, 1);
1191 status |= update_by_mnemonic(state,
1192 0x90000174, 28, 3, 1);
1193 status |= update_by_mnemonic(state,
1194 0x90000178, 0, 3, 1);
1195 status |= update_by_mnemonic(state,
1196 0x90000178, 4, 3, 1);
1197 status |= update_by_mnemonic(state,
1198 0x90000178, 8, 3, 1);
1199 }
1200 break;
1201
1202 case MXL_HYDRA_DEVICE_568:
1203 if (enable_serial_ts == MXL_FALSE) {
1204 status |= update_by_mnemonic(state,
1205 0x9000016C, 8, 3, 5);
1206 status |= update_by_mnemonic(state,
1207 0x9000016C, 12, 3, 5);
1208 status |= update_by_mnemonic(state,
1209 0x9000016C, 16, 3, 5);
1210 status |= update_by_mnemonic(state,
1211 0x9000016C, 20, 3, 5);
1212 status |= update_by_mnemonic(state,
1213 0x9000016C, 24, 3, 5);
1214 status |= update_by_mnemonic(state,
1215 0x9000016C, 28, 3, 5);
1216 status |= update_by_mnemonic(state,
1217 0x90000170, 0, 3, 5);
1218 status |= update_by_mnemonic(state,
1219 0x90000170, 4, 3, 5);
1220 status |= update_by_mnemonic(state,
1221 0x90000170, 8, 3, 5);
1222 status |= update_by_mnemonic(state,
1223 0x90000170, 12, 3, 5);
1224 status |= update_by_mnemonic(state,
1225 0x90000170, 16, 3, 5);
1226 status |= update_by_mnemonic(state,
1227 0x90000170, 20, 3, 5);
1228
1229 status |= update_by_mnemonic(state,
1230 0x90000170, 24, 3, pad_mux_value);
1231 status |= update_by_mnemonic(state,
1232 0x90000174, 0, 3, pad_mux_value);
1233 status |= update_by_mnemonic(state,
1234 0x90000174, 4, 3, pad_mux_value);
1235 status |= update_by_mnemonic(state,
1236 0x90000174, 8, 3, pad_mux_value);
1237 status |= update_by_mnemonic(state,
1238 0x90000174, 12, 3, pad_mux_value);
1239 status |= update_by_mnemonic(state,
1240 0x90000174, 16, 3, pad_mux_value);
1241 status |= update_by_mnemonic(state,
1242 0x90000174, 20, 3, pad_mux_value);
1243 status |= update_by_mnemonic(state,
1244 0x90000174, 24, 3, pad_mux_value);
1245 status |= update_by_mnemonic(state,
1246 0x90000174, 28, 3, pad_mux_value);
1247 status |= update_by_mnemonic(state,
1248 0x90000178, 0, 3, pad_mux_value);
1249 status |= update_by_mnemonic(state,
1250 0x90000178, 4, 3, pad_mux_value);
1251
1252 status |= update_by_mnemonic(state,
1253 0x90000178, 8, 3, 5);
1254 status |= update_by_mnemonic(state,
1255 0x90000178, 12, 3, 5);
1256 status |= update_by_mnemonic(state,
1257 0x90000178, 16, 3, 5);
1258 status |= update_by_mnemonic(state,
1259 0x90000178, 20, 3, 5);
1260 status |= update_by_mnemonic(state,
1261 0x90000178, 24, 3, 5);
1262 status |= update_by_mnemonic(state,
1263 0x90000178, 28, 3, 5);
1264 status |= update_by_mnemonic(state,
1265 0x9000017C, 0, 3, 5);
1266 status |= update_by_mnemonic(state,
1267 0x9000017C, 4, 3, 5);
1268 } else {
1269 status |= update_by_mnemonic(state,
1270 0x90000170, 4, 3, pad_mux_value);
1271 status |= update_by_mnemonic(state,
1272 0x90000170, 8, 3, pad_mux_value);
1273 status |= update_by_mnemonic(state,
1274 0x90000170, 12, 3, pad_mux_value);
1275 status |= update_by_mnemonic(state,
1276 0x90000170, 16, 3, pad_mux_value);
1277 status |= update_by_mnemonic(state,
1278 0x90000170, 20, 3, pad_mux_value);
1279 status |= update_by_mnemonic(state,
1280 0x90000170, 24, 3, pad_mux_value);
1281 status |= update_by_mnemonic(state,
1282 0x90000170, 28, 3, pad_mux_value);
1283 status |= update_by_mnemonic(state,
1284 0x90000174, 0, 3, pad_mux_value);
1285 status |= update_by_mnemonic(state,
1286 0x90000174, 4, 3, pad_mux_value);
1287 status |= update_by_mnemonic(state,
1288 0x90000174, 8, 3, pad_mux_value);
1289 status |= update_by_mnemonic(state,
1290 0x90000174, 12, 3, pad_mux_value);
1291 }
1292 break;
1293
1294
1295 case MXL_HYDRA_DEVICE_584:
1296 default:
1297 status |= update_by_mnemonic(state,
1298 0x90000170, 4, 3, pad_mux_value);
1299 status |= update_by_mnemonic(state,
1300 0x90000170, 8, 3, pad_mux_value);
1301 status |= update_by_mnemonic(state,
1302 0x90000170, 12, 3, pad_mux_value);
1303 status |= update_by_mnemonic(state,
1304 0x90000170, 16, 3, pad_mux_value);
1305 status |= update_by_mnemonic(state,
1306 0x90000170, 20, 3, pad_mux_value);
1307 status |= update_by_mnemonic(state,
1308 0x90000170, 24, 3, pad_mux_value);
1309 status |= update_by_mnemonic(state,
1310 0x90000170, 28, 3, pad_mux_value);
1311 status |= update_by_mnemonic(state,
1312 0x90000174, 0, 3, pad_mux_value);
1313 status |= update_by_mnemonic(state,
1314 0x90000174, 4, 3, pad_mux_value);
1315 status |= update_by_mnemonic(state,
1316 0x90000174, 8, 3, pad_mux_value);
1317 status |= update_by_mnemonic(state,
1318 0x90000174, 12, 3, pad_mux_value);
1319 break;
1320 }
1321 return status;
1322 }
1323
1324 static int set_drive_strength(struct mxl *state,
1325 enum MXL_HYDRA_TS_DRIVE_STRENGTH_E ts_drive_strength)
1326 {
1327 int stat = 0;
1328 u32 val;
1329
1330 read_register(state, 0x90000194, &val);
1331 dev_info(state->i2cdev, "DIGIO = %08x\n", val);
1332 dev_info(state->i2cdev, "set drive_strength = %u\n", ts_drive_strength);
1333
1334
1335 stat |= update_by_mnemonic(state, 0x90000194, 0, 3, ts_drive_strength);
1336 stat |= update_by_mnemonic(state, 0x90000194, 20, 3, ts_drive_strength);
1337 stat |= update_by_mnemonic(state, 0x90000194, 24, 3, ts_drive_strength);
1338 stat |= update_by_mnemonic(state, 0x90000198, 12, 3, ts_drive_strength);
1339 stat |= update_by_mnemonic(state, 0x90000198, 16, 3, ts_drive_strength);
1340 stat |= update_by_mnemonic(state, 0x90000198, 20, 3, ts_drive_strength);
1341 stat |= update_by_mnemonic(state, 0x90000198, 24, 3, ts_drive_strength);
1342 stat |= update_by_mnemonic(state, 0x9000019C, 0, 3, ts_drive_strength);
1343 stat |= update_by_mnemonic(state, 0x9000019C, 4, 3, ts_drive_strength);
1344 stat |= update_by_mnemonic(state, 0x9000019C, 8, 3, ts_drive_strength);
1345 stat |= update_by_mnemonic(state, 0x9000019C, 24, 3, ts_drive_strength);
1346 stat |= update_by_mnemonic(state, 0x9000019C, 28, 3, ts_drive_strength);
1347 stat |= update_by_mnemonic(state, 0x900001A0, 0, 3, ts_drive_strength);
1348 stat |= update_by_mnemonic(state, 0x900001A0, 4, 3, ts_drive_strength);
1349 stat |= update_by_mnemonic(state, 0x900001A0, 20, 3, ts_drive_strength);
1350 stat |= update_by_mnemonic(state, 0x900001A0, 24, 3, ts_drive_strength);
1351 stat |= update_by_mnemonic(state, 0x900001A0, 28, 3, ts_drive_strength);
1352
1353 return stat;
1354 }
1355
1356 static int enable_tuner(struct mxl *state, u32 tuner, u32 enable)
1357 {
1358 int stat = 0;
1359 struct MXL_HYDRA_TUNER_CMD ctrl_tuner_cmd;
1360 u8 cmd_size = sizeof(ctrl_tuner_cmd);
1361 u8 cmd_buff[MXL_HYDRA_OEM_MAX_CMD_BUFF_LEN];
1362 u32 val, count = 10;
1363
1364 ctrl_tuner_cmd.tuner_id = tuner;
1365 ctrl_tuner_cmd.enable = enable;
1366 BUILD_HYDRA_CMD(MXL_HYDRA_TUNER_ACTIVATE_CMD, MXL_CMD_WRITE,
1367 cmd_size, &ctrl_tuner_cmd, cmd_buff);
1368 stat = send_command(state, cmd_size + MXL_HYDRA_CMD_HEADER_SIZE,
1369 &cmd_buff[0]);
1370 if (stat)
1371 return stat;
1372 read_register(state, HYDRA_TUNER_ENABLE_COMPLETE, &val);
1373 while (--count && ((val >> tuner) & 1) != enable) {
1374 msleep(20);
1375 read_register(state, HYDRA_TUNER_ENABLE_COMPLETE, &val);
1376 }
1377 if (!count)
1378 return -1;
1379 read_register(state, HYDRA_TUNER_ENABLE_COMPLETE, &val);
1380 dev_dbg(state->i2cdev, "tuner %u ready = %u\n",
1381 tuner, (val >> tuner) & 1);
1382
1383 return 0;
1384 }
1385
1386
1387 static int config_ts(struct mxl *state, enum MXL_HYDRA_DEMOD_ID_E demod_id,
1388 struct MXL_HYDRA_MPEGOUT_PARAM_T *mpeg_out_param_ptr)
1389 {
1390 int status = 0;
1391 u32 nco_count_min = 0;
1392 u32 clk_type = 0;
1393
1394 struct MXL_REG_FIELD_T xpt_sync_polarity[MXL_HYDRA_DEMOD_MAX] = {
1395 {0x90700010, 8, 1}, {0x90700010, 9, 1},
1396 {0x90700010, 10, 1}, {0x90700010, 11, 1},
1397 {0x90700010, 12, 1}, {0x90700010, 13, 1},
1398 {0x90700010, 14, 1}, {0x90700010, 15, 1} };
1399 struct MXL_REG_FIELD_T xpt_clock_polarity[MXL_HYDRA_DEMOD_MAX] = {
1400 {0x90700010, 16, 1}, {0x90700010, 17, 1},
1401 {0x90700010, 18, 1}, {0x90700010, 19, 1},
1402 {0x90700010, 20, 1}, {0x90700010, 21, 1},
1403 {0x90700010, 22, 1}, {0x90700010, 23, 1} };
1404 struct MXL_REG_FIELD_T xpt_valid_polarity[MXL_HYDRA_DEMOD_MAX] = {
1405 {0x90700014, 0, 1}, {0x90700014, 1, 1},
1406 {0x90700014, 2, 1}, {0x90700014, 3, 1},
1407 {0x90700014, 4, 1}, {0x90700014, 5, 1},
1408 {0x90700014, 6, 1}, {0x90700014, 7, 1} };
1409 struct MXL_REG_FIELD_T xpt_ts_clock_phase[MXL_HYDRA_DEMOD_MAX] = {
1410 {0x90700018, 0, 3}, {0x90700018, 4, 3},
1411 {0x90700018, 8, 3}, {0x90700018, 12, 3},
1412 {0x90700018, 16, 3}, {0x90700018, 20, 3},
1413 {0x90700018, 24, 3}, {0x90700018, 28, 3} };
1414 struct MXL_REG_FIELD_T xpt_lsb_first[MXL_HYDRA_DEMOD_MAX] = {
1415 {0x9070000C, 16, 1}, {0x9070000C, 17, 1},
1416 {0x9070000C, 18, 1}, {0x9070000C, 19, 1},
1417 {0x9070000C, 20, 1}, {0x9070000C, 21, 1},
1418 {0x9070000C, 22, 1}, {0x9070000C, 23, 1} };
1419 struct MXL_REG_FIELD_T xpt_sync_byte[MXL_HYDRA_DEMOD_MAX] = {
1420 {0x90700010, 0, 1}, {0x90700010, 1, 1},
1421 {0x90700010, 2, 1}, {0x90700010, 3, 1},
1422 {0x90700010, 4, 1}, {0x90700010, 5, 1},
1423 {0x90700010, 6, 1}, {0x90700010, 7, 1} };
1424 struct MXL_REG_FIELD_T xpt_enable_output[MXL_HYDRA_DEMOD_MAX] = {
1425 {0x9070000C, 0, 1}, {0x9070000C, 1, 1},
1426 {0x9070000C, 2, 1}, {0x9070000C, 3, 1},
1427 {0x9070000C, 4, 1}, {0x9070000C, 5, 1},
1428 {0x9070000C, 6, 1}, {0x9070000C, 7, 1} };
1429 struct MXL_REG_FIELD_T xpt_err_replace_sync[MXL_HYDRA_DEMOD_MAX] = {
1430 {0x9070000C, 24, 1}, {0x9070000C, 25, 1},
1431 {0x9070000C, 26, 1}, {0x9070000C, 27, 1},
1432 {0x9070000C, 28, 1}, {0x9070000C, 29, 1},
1433 {0x9070000C, 30, 1}, {0x9070000C, 31, 1} };
1434 struct MXL_REG_FIELD_T xpt_err_replace_valid[MXL_HYDRA_DEMOD_MAX] = {
1435 {0x90700014, 8, 1}, {0x90700014, 9, 1},
1436 {0x90700014, 10, 1}, {0x90700014, 11, 1},
1437 {0x90700014, 12, 1}, {0x90700014, 13, 1},
1438 {0x90700014, 14, 1}, {0x90700014, 15, 1} };
1439 struct MXL_REG_FIELD_T xpt_continuous_clock[MXL_HYDRA_DEMOD_MAX] = {
1440 {0x907001D4, 0, 1}, {0x907001D4, 1, 1},
1441 {0x907001D4, 2, 1}, {0x907001D4, 3, 1},
1442 {0x907001D4, 4, 1}, {0x907001D4, 5, 1},
1443 {0x907001D4, 6, 1}, {0x907001D4, 7, 1} };
1444 struct MXL_REG_FIELD_T xpt_nco_clock_rate[MXL_HYDRA_DEMOD_MAX] = {
1445 {0x90700044, 16, 80}, {0x90700044, 16, 81},
1446 {0x90700044, 16, 82}, {0x90700044, 16, 83},
1447 {0x90700044, 16, 84}, {0x90700044, 16, 85},
1448 {0x90700044, 16, 86}, {0x90700044, 16, 87} };
1449
1450 demod_id = state->base->ts_map[demod_id];
1451
1452 if (mpeg_out_param_ptr->enable == MXL_ENABLE) {
1453 if (mpeg_out_param_ptr->mpeg_mode ==
1454 MXL_HYDRA_MPEG_MODE_PARALLEL) {
1455 } else {
1456 cfg_ts_pad_mux(state, MXL_TRUE);
1457 update_by_mnemonic(state,
1458 0x90700010, 27, 1, MXL_FALSE);
1459 }
1460 }
1461
1462 nco_count_min =
1463 (u32)(MXL_HYDRA_NCO_CLK / mpeg_out_param_ptr->max_mpeg_clk_rate);
1464
1465 if (state->base->chipversion >= 2) {
1466 status |= update_by_mnemonic(state,
1467 xpt_nco_clock_rate[demod_id].reg_addr, /* Reg Addr */
1468 xpt_nco_clock_rate[demod_id].lsb_pos, /* LSB pos */
1469 xpt_nco_clock_rate[demod_id].num_of_bits, /* Num of bits */
1470 nco_count_min); /* Data */
1471 } else
1472 update_by_mnemonic(state, 0x90700044, 16, 8, nco_count_min);
1473
1474 if (mpeg_out_param_ptr->mpeg_clk_type == MXL_HYDRA_MPEG_CLK_CONTINUOUS)
1475 clk_type = 1;
1476
1477 if (mpeg_out_param_ptr->mpeg_mode < MXL_HYDRA_MPEG_MODE_PARALLEL) {
1478 status |= update_by_mnemonic(state,
1479 xpt_continuous_clock[demod_id].reg_addr,
1480 xpt_continuous_clock[demod_id].lsb_pos,
1481 xpt_continuous_clock[demod_id].num_of_bits,
1482 clk_type);
1483 } else
1484 update_by_mnemonic(state, 0x907001D4, 8, 1, clk_type);
1485
1486 status |= update_by_mnemonic(state,
1487 xpt_sync_polarity[demod_id].reg_addr,
1488 xpt_sync_polarity[demod_id].lsb_pos,
1489 xpt_sync_polarity[demod_id].num_of_bits,
1490 mpeg_out_param_ptr->mpeg_sync_pol);
1491
1492 status |= update_by_mnemonic(state,
1493 xpt_valid_polarity[demod_id].reg_addr,
1494 xpt_valid_polarity[demod_id].lsb_pos,
1495 xpt_valid_polarity[demod_id].num_of_bits,
1496 mpeg_out_param_ptr->mpeg_valid_pol);
1497
1498 status |= update_by_mnemonic(state,
1499 xpt_clock_polarity[demod_id].reg_addr,
1500 xpt_clock_polarity[demod_id].lsb_pos,
1501 xpt_clock_polarity[demod_id].num_of_bits,
1502 mpeg_out_param_ptr->mpeg_clk_pol);
1503
1504 status |= update_by_mnemonic(state,
1505 xpt_sync_byte[demod_id].reg_addr,
1506 xpt_sync_byte[demod_id].lsb_pos,
1507 xpt_sync_byte[demod_id].num_of_bits,
1508 mpeg_out_param_ptr->mpeg_sync_pulse_width);
1509
1510 status |= update_by_mnemonic(state,
1511 xpt_ts_clock_phase[demod_id].reg_addr,
1512 xpt_ts_clock_phase[demod_id].lsb_pos,
1513 xpt_ts_clock_phase[demod_id].num_of_bits,
1514 mpeg_out_param_ptr->mpeg_clk_phase);
1515
1516 status |= update_by_mnemonic(state,
1517 xpt_lsb_first[demod_id].reg_addr,
1518 xpt_lsb_first[demod_id].lsb_pos,
1519 xpt_lsb_first[demod_id].num_of_bits,
1520 mpeg_out_param_ptr->lsb_or_msb_first);
1521
1522 switch (mpeg_out_param_ptr->mpeg_error_indication) {
1523 case MXL_HYDRA_MPEG_ERR_REPLACE_SYNC:
1524 status |= update_by_mnemonic(state,
1525 xpt_err_replace_sync[demod_id].reg_addr,
1526 xpt_err_replace_sync[demod_id].lsb_pos,
1527 xpt_err_replace_sync[demod_id].num_of_bits,
1528 MXL_TRUE);
1529 status |= update_by_mnemonic(state,
1530 xpt_err_replace_valid[demod_id].reg_addr,
1531 xpt_err_replace_valid[demod_id].lsb_pos,
1532 xpt_err_replace_valid[demod_id].num_of_bits,
1533 MXL_FALSE);
1534 break;
1535
1536 case MXL_HYDRA_MPEG_ERR_REPLACE_VALID:
1537 status |= update_by_mnemonic(state,
1538 xpt_err_replace_sync[demod_id].reg_addr,
1539 xpt_err_replace_sync[demod_id].lsb_pos,
1540 xpt_err_replace_sync[demod_id].num_of_bits,
1541 MXL_FALSE);
1542
1543 status |= update_by_mnemonic(state,
1544 xpt_err_replace_valid[demod_id].reg_addr,
1545 xpt_err_replace_valid[demod_id].lsb_pos,
1546 xpt_err_replace_valid[demod_id].num_of_bits,
1547 MXL_TRUE);
1548 break;
1549
1550 case MXL_HYDRA_MPEG_ERR_INDICATION_DISABLED:
1551 default:
1552 status |= update_by_mnemonic(state,
1553 xpt_err_replace_sync[demod_id].reg_addr,
1554 xpt_err_replace_sync[demod_id].lsb_pos,
1555 xpt_err_replace_sync[demod_id].num_of_bits,
1556 MXL_FALSE);
1557
1558 status |= update_by_mnemonic(state,
1559 xpt_err_replace_valid[demod_id].reg_addr,
1560 xpt_err_replace_valid[demod_id].lsb_pos,
1561 xpt_err_replace_valid[demod_id].num_of_bits,
1562 MXL_FALSE);
1563
1564 break;
1565
1566 }
1567
1568 if (mpeg_out_param_ptr->mpeg_mode != MXL_HYDRA_MPEG_MODE_PARALLEL) {
1569 status |= update_by_mnemonic(state,
1570 xpt_enable_output[demod_id].reg_addr,
1571 xpt_enable_output[demod_id].lsb_pos,
1572 xpt_enable_output[demod_id].num_of_bits,
1573 mpeg_out_param_ptr->enable);
1574 }
1575 return status;
1576 }
1577
1578 static int config_mux(struct mxl *state)
1579 {
1580 update_by_mnemonic(state, 0x9070000C, 0, 1, 0);
1581 update_by_mnemonic(state, 0x9070000C, 1, 1, 0);
1582 update_by_mnemonic(state, 0x9070000C, 2, 1, 0);
1583 update_by_mnemonic(state, 0x9070000C, 3, 1, 0);
1584 update_by_mnemonic(state, 0x9070000C, 4, 1, 0);
1585 update_by_mnemonic(state, 0x9070000C, 5, 1, 0);
1586 update_by_mnemonic(state, 0x9070000C, 6, 1, 0);
1587 update_by_mnemonic(state, 0x9070000C, 7, 1, 0);
1588 update_by_mnemonic(state, 0x90700008, 0, 2, 1);
1589 update_by_mnemonic(state, 0x90700008, 2, 2, 1);
1590 return 0;
1591 }
1592
1593 static int load_fw(struct mxl *state, struct mxl5xx_cfg *cfg)
1594 {
1595 int stat = 0;
1596 u8 *buf;
1597
1598 if (cfg->fw)
1599 return firmware_download(state, cfg->fw, cfg->fw_len);
1600
1601 if (!cfg->fw_read)
1602 return -1;
1603
1604 buf = vmalloc(0x40000);
1605 if (!buf)
1606 return -ENOMEM;
1607
1608 cfg->fw_read(cfg->fw_priv, buf, 0x40000);
1609 stat = firmware_download(state, buf, 0x40000);
1610 vfree(buf);
1611
1612 return stat;
1613 }
1614
1615 static int validate_sku(struct mxl *state)
1616 {
1617 u32 pad_mux_bond = 0, prcm_chip_id = 0, prcm_so_cid = 0;
1618 int status;
1619 u32 type = state->base->type;
1620
1621 status = read_by_mnemonic(state, 0x90000190, 0, 3, &pad_mux_bond);
1622 status |= read_by_mnemonic(state, 0x80030000, 0, 12, &prcm_chip_id);
1623 status |= read_by_mnemonic(state, 0x80030004, 24, 8, &prcm_so_cid);
1624 if (status)
1625 return -1;
1626
1627 dev_info(state->i2cdev, "padMuxBond=%08x, prcmChipId=%08x, prcmSoCId=%08x\n",
1628 pad_mux_bond, prcm_chip_id, prcm_so_cid);
1629
1630 if (prcm_chip_id != 0x560) {
1631 switch (pad_mux_bond) {
1632 case MXL_HYDRA_SKU_ID_581:
1633 if (type == MXL_HYDRA_DEVICE_581)
1634 return 0;
1635 if (type == MXL_HYDRA_DEVICE_581S) {
1636 state->base->type = MXL_HYDRA_DEVICE_581;
1637 return 0;
1638 }
1639 break;
1640 case MXL_HYDRA_SKU_ID_584:
1641 if (type == MXL_HYDRA_DEVICE_584)
1642 return 0;
1643 break;
1644 case MXL_HYDRA_SKU_ID_544:
1645 if (type == MXL_HYDRA_DEVICE_544)
1646 return 0;
1647 if (type == MXL_HYDRA_DEVICE_542)
1648 return 0;
1649 break;
1650 case MXL_HYDRA_SKU_ID_582:
1651 if (type == MXL_HYDRA_DEVICE_582)
1652 return 0;
1653 break;
1654 default:
1655 return -1;
1656 }
1657 } else {
1658
1659 }
1660 return -1;
1661 }
1662
1663 static int get_fwinfo(struct mxl *state)
1664 {
1665 int status;
1666 u32 val = 0;
1667
1668 status = read_by_mnemonic(state, 0x90000190, 0, 3, &val);
1669 if (status)
1670 return status;
1671 dev_info(state->i2cdev, "chipID=%08x\n", val);
1672
1673 status = read_by_mnemonic(state, 0x80030004, 8, 8, &val);
1674 if (status)
1675 return status;
1676 dev_info(state->i2cdev, "chipVer=%08x\n", val);
1677
1678 status = read_register(state, HYDRA_FIRMWARE_VERSION, &val);
1679 if (status)
1680 return status;
1681 dev_info(state->i2cdev, "FWVer=%08x\n", val);
1682
1683 state->base->fwversion = val;
1684 return status;
1685 }
1686
1687
1688 static u8 ts_map1_to_1[MXL_HYDRA_DEMOD_MAX] = {
1689 MXL_HYDRA_DEMOD_ID_0,
1690 MXL_HYDRA_DEMOD_ID_1,
1691 MXL_HYDRA_DEMOD_ID_2,
1692 MXL_HYDRA_DEMOD_ID_3,
1693 MXL_HYDRA_DEMOD_ID_4,
1694 MXL_HYDRA_DEMOD_ID_5,
1695 MXL_HYDRA_DEMOD_ID_6,
1696 MXL_HYDRA_DEMOD_ID_7,
1697 };
1698
1699 static u8 ts_map54x[MXL_HYDRA_DEMOD_MAX] = {
1700 MXL_HYDRA_DEMOD_ID_2,
1701 MXL_HYDRA_DEMOD_ID_3,
1702 MXL_HYDRA_DEMOD_ID_4,
1703 MXL_HYDRA_DEMOD_ID_5,
1704 MXL_HYDRA_DEMOD_MAX,
1705 MXL_HYDRA_DEMOD_MAX,
1706 MXL_HYDRA_DEMOD_MAX,
1707 MXL_HYDRA_DEMOD_MAX,
1708 };
1709
1710 static int probe(struct mxl *state, struct mxl5xx_cfg *cfg)
1711 {
1712 u32 chipver;
1713 int fw, status, j;
1714 struct MXL_HYDRA_MPEGOUT_PARAM_T mpeg_interface_cfg;
1715
1716 state->base->ts_map = ts_map1_to_1;
1717
1718 switch (state->base->type) {
1719 case MXL_HYDRA_DEVICE_581:
1720 case MXL_HYDRA_DEVICE_581S:
1721 state->base->can_clkout = 1;
1722 state->base->demod_num = 8;
1723 state->base->tuner_num = 1;
1724 state->base->sku_type = MXL_HYDRA_SKU_TYPE_581;
1725 break;
1726 case MXL_HYDRA_DEVICE_582:
1727 state->base->can_clkout = 1;
1728 state->base->demod_num = 8;
1729 state->base->tuner_num = 3;
1730 state->base->sku_type = MXL_HYDRA_SKU_TYPE_582;
1731 break;
1732 case MXL_HYDRA_DEVICE_585:
1733 state->base->can_clkout = 0;
1734 state->base->demod_num = 8;
1735 state->base->tuner_num = 4;
1736 state->base->sku_type = MXL_HYDRA_SKU_TYPE_585;
1737 break;
1738 case MXL_HYDRA_DEVICE_544:
1739 state->base->can_clkout = 0;
1740 state->base->demod_num = 4;
1741 state->base->tuner_num = 4;
1742 state->base->sku_type = MXL_HYDRA_SKU_TYPE_544;
1743 state->base->ts_map = ts_map54x;
1744 break;
1745 case MXL_HYDRA_DEVICE_541:
1746 case MXL_HYDRA_DEVICE_541S:
1747 state->base->can_clkout = 0;
1748 state->base->demod_num = 4;
1749 state->base->tuner_num = 1;
1750 state->base->sku_type = MXL_HYDRA_SKU_TYPE_541;
1751 state->base->ts_map = ts_map54x;
1752 break;
1753 case MXL_HYDRA_DEVICE_561:
1754 case MXL_HYDRA_DEVICE_561S:
1755 state->base->can_clkout = 0;
1756 state->base->demod_num = 6;
1757 state->base->tuner_num = 1;
1758 state->base->sku_type = MXL_HYDRA_SKU_TYPE_561;
1759 break;
1760 case MXL_HYDRA_DEVICE_568:
1761 state->base->can_clkout = 0;
1762 state->base->demod_num = 8;
1763 state->base->tuner_num = 1;
1764 state->base->chan_bond = 1;
1765 state->base->sku_type = MXL_HYDRA_SKU_TYPE_568;
1766 break;
1767 case MXL_HYDRA_DEVICE_542:
1768 state->base->can_clkout = 1;
1769 state->base->demod_num = 4;
1770 state->base->tuner_num = 3;
1771 state->base->sku_type = MXL_HYDRA_SKU_TYPE_542;
1772 state->base->ts_map = ts_map54x;
1773 break;
1774 case MXL_HYDRA_DEVICE_TEST:
1775 case MXL_HYDRA_DEVICE_584:
1776 default:
1777 state->base->can_clkout = 0;
1778 state->base->demod_num = 8;
1779 state->base->tuner_num = 4;
1780 state->base->sku_type = MXL_HYDRA_SKU_TYPE_584;
1781 break;
1782 }
1783
1784 status = validate_sku(state);
1785 if (status)
1786 return status;
1787
1788 update_by_mnemonic(state, 0x80030014, 9, 1, 1);
1789 update_by_mnemonic(state, 0x8003003C, 12, 1, 1);
1790 status = read_by_mnemonic(state, 0x80030000, 12, 4, &chipver);
1791 if (status)
1792 state->base->chipversion = 0;
1793 else
1794 state->base->chipversion = (chipver == 2) ? 2 : 1;
1795 dev_info(state->i2cdev, "Hydra chip version %u\n",
1796 state->base->chipversion);
1797
1798 cfg_dev_xtal(state, cfg->clk, cfg->cap, 0);
1799
1800 fw = firmware_is_alive(state);
1801 if (!fw) {
1802 status = load_fw(state, cfg);
1803 if (status)
1804 return status;
1805 }
1806 get_fwinfo(state);
1807
1808 config_mux(state);
1809 mpeg_interface_cfg.enable = MXL_ENABLE;
1810 mpeg_interface_cfg.lsb_or_msb_first = MXL_HYDRA_MPEG_SERIAL_MSB_1ST;
1811 /* supports only (0-104&139)MHz */
1812 if (cfg->ts_clk)
1813 mpeg_interface_cfg.max_mpeg_clk_rate = cfg->ts_clk;
1814 else
1815 mpeg_interface_cfg.max_mpeg_clk_rate = 69; /* 139; */
1816 mpeg_interface_cfg.mpeg_clk_phase = MXL_HYDRA_MPEG_CLK_PHASE_SHIFT_0_DEG;
1817 mpeg_interface_cfg.mpeg_clk_pol = MXL_HYDRA_MPEG_CLK_IN_PHASE;
1818 /* MXL_HYDRA_MPEG_CLK_GAPPED; */
1819 mpeg_interface_cfg.mpeg_clk_type = MXL_HYDRA_MPEG_CLK_CONTINUOUS;
1820 mpeg_interface_cfg.mpeg_error_indication =
1821 MXL_HYDRA_MPEG_ERR_INDICATION_DISABLED;
1822 mpeg_interface_cfg.mpeg_mode = MXL_HYDRA_MPEG_MODE_SERIAL_3_WIRE;
1823 mpeg_interface_cfg.mpeg_sync_pol = MXL_HYDRA_MPEG_ACTIVE_HIGH;
1824 mpeg_interface_cfg.mpeg_sync_pulse_width = MXL_HYDRA_MPEG_SYNC_WIDTH_BIT;
1825 mpeg_interface_cfg.mpeg_valid_pol = MXL_HYDRA_MPEG_ACTIVE_HIGH;
1826
1827 for (j = 0; j < state->base->demod_num; j++) {
1828 status = config_ts(state, (enum MXL_HYDRA_DEMOD_ID_E) j,
1829 &mpeg_interface_cfg);
1830 if (status)
1831 return status;
1832 }
1833 set_drive_strength(state, 1);
1834 return 0;
1835 }
1836
1837 struct dvb_frontend *mxl5xx_attach(struct i2c_adapter *i2c,
1838 struct mxl5xx_cfg *cfg, u32 demod, u32 tuner,
1839 int (**fn_set_input)(struct dvb_frontend *, int))
1840 {
1841 struct mxl *state;
1842 struct mxl_base *base;
1843
1844 state = kzalloc(sizeof(struct mxl), GFP_KERNEL);
1845 if (!state)
1846 return NULL;
1847
1848 state->demod = demod;
1849 state->tuner = tuner;
1850 state->tuner_in_use = 0xffffffff;
1851 state->i2cdev = &i2c->dev;
1852
1853 base = match_base(i2c, cfg->adr);
1854 if (base) {
1855 base->count++;
1856 if (base->count > base->demod_num)
1857 goto fail;
1858 state->base = base;
1859 } else {
1860 base = kzalloc(sizeof(struct mxl_base), GFP_KERNEL);
1861 if (!base)
1862 goto fail;
1863 base->i2c = i2c;
1864 base->adr = cfg->adr;
1865 base->type = cfg->type;
1866 base->count = 1;
1867 mutex_init(&base->i2c_lock);
1868 mutex_init(&base->status_lock);
1869 mutex_init(&base->tune_lock);
1870 INIT_LIST_HEAD(&base->mxls);
1871
1872 state->base = base;
1873 if (probe(state, cfg) < 0) {
1874 kfree(base);
1875 goto fail;
1876 }
1877 list_add(&base->mxllist, &mxllist);
1878 }
1879 state->fe.ops = mxl_ops;
1880 state->xbar[0] = 4;
1881 state->xbar[1] = demod;
1882 state->xbar[2] = 8;
1883 state->fe.demodulator_priv = state;
1884 *fn_set_input = set_input;
1885
1886 list_add(&state->mxl, &base->mxls);
1887 return &state->fe;
1888
1889 fail:
1890 kfree(state);
1891 return NULL;
1892 }
1893 EXPORT_SYMBOL_GPL(mxl5xx_attach);
1894
1895 MODULE_DESCRIPTION("MaxLinear MxL5xx DVB-S/S2 tuner-demodulator driver");
1896 MODULE_AUTHOR("Ralph and Marcus Metzler, Metzler Brothers Systementwicklung GbR");
1897 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support