| blob | a74f30f2f78eda6106a80138d063f0b3535b5713 |
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3 * TW5864 driver - registers description
4 *
5 * Copyright (C) 2016 Bluecherry, LLC <maintainers@bluecherrydvr.com>
6 */
8 /* According to TW5864_datasheet_0.6d.pdf, tw5864b1-ds.pdf */
10 /* Register Description - Direct Map Space */
11 /* 0x0000 ~ 0x1ffc - H264 Register Map */
12 /* [15:0] The Version register for H264 core (Read Only) */
13 #define TW5864_H264REV 0x0000
15 #define TW5864_EMU 0x0004
16 /* Define controls in register TW5864_EMU */
17 /* DDR controller enabled */
18 #define TW5864_EMU_EN_DDR BIT(0)
19 /* Enable bit for Inter module */
20 #define TW5864_EMU_EN_ME BIT(1)
21 /* Enable bit for Sensor Interface module */
22 #define TW5864_EMU_EN_SEN BIT(2)
23 /* Enable bit for Host Burst Access */
24 #define TW5864_EMU_EN_BHOST BIT(3)
25 /* Enable bit for Loop Filter module */
26 #define TW5864_EMU_EN_LPF BIT(4)
27 /* Enable bit for PLBK module */
28 #define TW5864_EMU_EN_PLBK BIT(5)
29 /*
30 * Video Frame mapping in DDR
31 * 00 CIF
32 * 01 D1
33 * 10 Reserved
34 * 11 Reserved
35 *
36 */
37 #define TW5864_DSP_FRAME_TYPE (3 << 6)
38 #define TW5864_DSP_FRAME_TYPE_D1 BIT(6)
40 #define TW5864_UNDECLARED_H264REV_PART2 0x0008
42 #define TW5864_SLICE 0x000c
43 /* Define controls in register TW5864_SLICE */
44 /* VLC Slice end flag */
45 #define TW5864_VLC_SLICE_END BIT(0)
46 /* Master Slice End Flag */
47 #define TW5864_MAS_SLICE_END BIT(4)
48 /* Host to start a new slice Address */
49 #define TW5864_START_NSLICE BIT(15)
51 /*
52 * [15:0] Two bit for each channel (channel 0 ~ 7). Each two bits are the buffer
53 * pointer for the last encoded frame of the corresponding channel.
54 */
55 #define TW5864_ENC_BUF_PTR_REC1 0x0010
57 /* [5:0] DSP_MB_QP and [15:10] DSP_LPF_OFFSET */
58 #define TW5864_DSP_QP 0x0018
59 /* Define controls in register TW5864_DSP_QP */
60 /* [5:0] H264 QP Value for codec */
61 #define TW5864_DSP_MB_QP 0x003f
62 /*
63 * [15:10] H264 LPF_OFFSET Address
64 * (Default 0)
65 */
66 #define TW5864_DSP_LPF_OFFSET 0xfc00
68 #define TW5864_DSP_CODEC 0x001c
69 /* Define controls in register TW5864_DSP_CODEC */
70 /*
71 * 0: Encode (TW5864 Default)
72 * 1: Decode
73 */
74 #define TW5864_DSP_CODEC_MODE BIT(0)
75 /*
76 * 0->3 4 VLC data buffer in DDR (1M each)
77 * 0->7 8 VLC data buffer in DDR (512k each)
78 */
79 #define TW5864_VLC_BUF_ID (7 << 2)
80 /*
81 * 0 4CIF in 1 MB
82 * 1 1CIF in 1 MB
83 */
84 #define TW5864_CIF_MAP_MD BIT(6)
85 /*
86 * 0 2 falf D1 in 1 MB
87 * 1 1 half D1 in 1 MB
88 */
89 #define TW5864_HD1_MAP_MD BIT(7)
90 /* VLC Stream valid */
91 #define TW5864_VLC_VLD BIT(8)
92 /* MV Vector Valid */
93 #define TW5864_MV_VECT_VLD BIT(9)
94 /* MV Flag Valid */
95 #define TW5864_MV_FLAG_VLD BIT(10)
97 #define TW5864_DSP_SEN 0x0020
98 /* Define controls in register TW5864_DSP_SEN */
99 /* Org Buffer Base for Luma (default 0) */
100 #define TW5864_DSP_SEN_PIC_LU 0x000f
101 /* Org Buffer Base for Chroma (default 4) */
102 #define TW5864_DSP_SEN_PIC_CHM 0x00f0
103 /* Maximum Number of Buffers (default 4) */
104 #define TW5864_DSP_SEN_PIC_MAX 0x0700
105 /*
106 * Original Frame D1 or HD1 switch
107 * (Default 0)
108 */
109 #define TW5864_DSP_SEN_HFULL 0x1000
111 #define TW5864_DSP_REF_PIC 0x0024
112 /* Define controls in register TW5864_DSP_REF_PIC */
113 /* Ref Buffer Base for Luma (default 0) */
114 #define TW5864_DSP_REF_PIC_LU 0x000f
115 /* Ref Buffer Base for Chroma (default 4) */
116 #define TW5864_DSP_REF_PIC_CHM 0x00f0
117 /* Maximum Number of Buffers (default 4) */
118 #define TW5864_DSP_REF_PIC_MAX 0x0700
120 /* [15:0] SEN_EN_CH[n] SENIF original frame capture enable for each channel */
121 #define TW5864_SEN_EN_CH 0x0028
123 #define TW5864_DSP 0x002c
124 /* Define controls in register TW5864_DSP */
125 /* The ID for channel selected for encoding operation */
126 #define TW5864_DSP_ENC_CHN 0x000f
127 /* See DSP_MB_DELAY below */
128 #define TW5864_DSP_MB_WAIT 0x0010
129 /*
130 * DSP Chroma Switch
131 * 0 DDRB
132 * 1 DDRA
133 */
134 #define TW5864_DSP_CHROM_SW 0x0020
135 /* VLC Flow Control: 1 for enable */
136 #define TW5864_DSP_FLW_CNTL 0x0040
137 /*
138 * If DSP_MB_WAIT == 0, MB delay is DSP_MB_DELAY * 16
139 * If DSP_MB_DELAY == 1, MB delay is DSP_MB_DELAY * 128
140 */
141 #define TW5864_DSP_MB_DELAY 0x0f00
143 #define TW5864_DDR 0x0030
144 /* Define controls in register TW5864_DDR */
145 /* DDR Single Access Page Number */
146 #define TW5864_DDR_PAGE_CNTL 0x00ff
147 /* DDR-DPR Burst Read Enable */
148 #define TW5864_DDR_BRST_EN BIT(13)
149 /*
150 * DDR A/B Select as HOST access
151 * 0 Select DDRA
152 * 1 Select DDRB
153 */
154 #define TW5864_DDR_AB_SEL BIT(14)
155 /*
156 * DDR Access Mode Select
157 * 0 Single R/W Access (Host <-> DDR)
158 * 1 Burst R/W Access (Host <-> DPR)
159 */
160 #define TW5864_DDR_MODE BIT(15)
162 /* The original frame capture pointer. Two bits for each channel */
163 /* SENIF_ORG_FRM_PTR [15:0] */
164 #define TW5864_SENIF_ORG_FRM_PTR1 0x0038
165 /* SENIF_ORG_FRM_PTR [31:16] */
166 #define TW5864_SENIF_ORG_FRM_PTR2 0x003c
168 #define TW5864_DSP_SEN_MODE 0x0040
169 /* Define controls in register TW5864_DSP_SEN_MODE */
170 #define TW5864_DSP_SEN_MODE_CH0 0x000f
171 #define TW5864_DSP_SEN_MODE_CH1 0x00f0
173 /*
174 * [15:0]: ENC_BUF_PTR_REC[31:16] Two bit for each channel (channel 8 ~ 15).
175 * Each two bits are the buffer pointer for the last encoded frame of a channel
176 */
177 #define TW5864_ENC_BUF_PTR_REC2 0x004c
179 /* Current MV Flag Status Pointer for Channel n. (Read only) */
180 /*
181 * [1:0] CH0_MV_PTR, ..., [15:14] CH7_MV_PTR
182 */
183 #define TW5864_CH_MV_PTR1 0x0060
184 /*
185 * [1:0] CH8_MV_PTR, ..., [15:14] CH15_MV_PTR
186 */
187 #define TW5864_CH_MV_PTR2 0x0064
189 /*
190 * [15:0] Reset Current MV Flag Status Pointer for Channel n (one bit each)
191 */
192 #define TW5864_RST_MV_PTR 0x0068
193 #define TW5864_INTERLACING 0x0200
194 /* Define controls in register TW5864_INTERLACING */
195 /*
196 * Inter_Mode Start. 2-nd bit? A guess. Missing in datasheet. Without this bit
197 * set, the output video is interlaced (stripy).
198 */
199 #define TW5864_DSP_INTER_ST BIT(1)
200 /* Deinterlacer Enable */
201 #define TW5864_DI_EN BIT(2)
202 /*
203 * De-interlacer Mode
204 * 1 Shuffled frame
205 * 0 Normal Un-Shuffled Frame
206 */
207 #define TW5864_DI_MD BIT(3)
208 /*
209 * Down scale original frame in X direction
210 * 11: Un-used
211 * 10: down-sample to 1/4
212 * 01: down-sample to 1/2
213 * 00: down-sample disabled
214 */
215 #define TW5864_DSP_DWN_X (3 << 4)
216 /*
217 * Down scale original frame in Y direction
218 * 11: Un-used
219 * 10: down-sample to 1/4
220 * 01: down-sample to 1/2
221 * 00: down-sample disabled
222 */
223 #define TW5864_DSP_DWN_Y (3 << 6)
224 /*
225 * 1 Dual Stream
226 * 0 Single Stream
227 */
228 #define TW5864_DUAL_STR BIT(8)
230 #define TW5864_DSP_REF 0x0204
231 /* Define controls in register TW5864_DSP_REF */
232 /* Number of reference frame (Default 1 for TW5864B) */
233 #define TW5864_DSP_REF_FRM 0x000f
234 /* Window size */
235 #define TW5864_DSP_WIN_SIZE 0x02f0
237 #define TW5864_DSP_SKIP 0x0208
238 /* Define controls in register TW5864_DSP_SKIP */
239 /*
240 * Skip Offset Enable bit
241 * 0 DSP_SKIP_OFFSET value is not used (default 8)
242 * 1 DSP_SKIP_OFFSET value is used in HW
243 */
244 #define TW5864_DSP_SKIP_OFEN 0x0080
245 /* Skip mode cost offset (default 8) */
246 #define TW5864_DSP_SKIP_OFFSET 0x007f
248 #define TW5864_MOTION_SEARCH_ETC 0x020c
249 /* Define controls in register TW5864_MOTION_SEARCH_ETC */
250 /* Enable quarter pel search mode */
251 #define TW5864_QPEL_EN BIT(0)
252 /* Enable half pel search mode */
253 #define TW5864_HPEL_EN BIT(1)
254 /* Enable motion search mode */
255 #define TW5864_ME_EN BIT(2)
256 /* Enable Intra mode */
257 #define TW5864_INTRA_EN BIT(3)
258 /* Enable Skip Mode */
259 #define TW5864_SKIP_EN BIT(4)
260 /* Search Option (Default 2"b01) */
261 #define TW5864_SRCH_OPT (3 << 5)
263 #define TW5864_DSP_ENC_REC 0x0210
264 /* Define controls in register TW5864_DSP_ENC_REC */
265 /* Reference Buffer Pointer for encoding */
266 #define TW5864_DSP_ENC_REF_PTR 0x0007
267 /* Reconstruct Buffer pointer */
268 #define TW5864_DSP_REC_BUF_PTR 0x7000
270 /* [15:0] Lambda Value for H264 */
271 #define TW5864_DSP_REF_MVP_LAMBDA 0x0214
273 #define TW5864_DSP_PIC_MAX_MB 0x0218
274 /* Define controls in register TW5864_DSP_PIC_MAX_MB */
275 /* The MB number in Y direction for a frame */
276 #define TW5864_DSP_PIC_MAX_MB_Y 0x007f
277 /* The MB number in X direction for a frame */
278 #define TW5864_DSP_PIC_MAX_MB_X 0x7f00
280 /* The original frame pointer for encoding */
281 #define TW5864_DSP_ENC_ORG_PTR_REG 0x021c
282 /* Mask to use with TW5864_DSP_ENC_ORG_PTR */
283 #define TW5864_DSP_ENC_ORG_PTR_MASK 0x7000
284 /* Number of bits to shift with TW5864_DSP_ENC_ORG_PTR */
285 #define TW5864_DSP_ENC_ORG_PTR_SHIFT 12
287 /* DDR base address of OSD rectangle attribute data */
288 #define TW5864_DSP_OSD_ATTRI_BASE 0x0220
289 /* OSD enable bit for each channel */
290 #define TW5864_DSP_OSD_ENABLE 0x0228
292 /* 0x0280 ~ 0x029c – Motion Vector for 1st 4x4 Block, e.g., 80 (X), 84 (Y) */
293 #define TW5864_ME_MV_VEC1 0x0280
294 /* 0x02a0 ~ 0x02bc – Motion Vector for 2nd 4x4 Block, e.g., A0 (X), A4 (Y) */
295 #define TW5864_ME_MV_VEC2 0x02a0
296 /* 0x02c0 ~ 0x02dc – Motion Vector for 3rd 4x4 Block, e.g., C0 (X), C4 (Y) */
297 #define TW5864_ME_MV_VEC3 0x02c0
298 /* 0x02e0 ~ 0x02fc – Motion Vector for 4th 4x4 Block, e.g., E0 (X), E4 (Y) */
299 #define TW5864_ME_MV_VEC4 0x02e0
301 /*
302 * [5:0]
303 * if (intra16x16_cost < (intra4x4_cost+dsp_i4x4_offset))
304 * Intra_mode = intra16x16_mode
305 * Else
306 * Intra_mode = intra4x4_mode
307 */
308 #define TW5864_DSP_I4x4_OFFSET 0x040c
310 /*
311 * [6:4]
312 * 0x5 Only 4x4
313 * 0x6 Only 16x16
314 * 0x7 16x16 & 4x4
315 */
316 #define TW5864_DSP_INTRA_MODE 0x0410
317 #define TW5864_DSP_INTRA_MODE_SHIFT 4
318 #define TW5864_DSP_INTRA_MODE_MASK (7 << 4)
319 #define TW5864_DSP_INTRA_MODE_4x4 0x5
320 #define TW5864_DSP_INTRA_MODE_16x16 0x6
321 #define TW5864_DSP_INTRA_MODE_4x4_AND_16x16 0x7
322 /*
323 * [5:0] WEIGHT Factor for I4x4 cost calculation (QP dependent)
324 */
325 #define TW5864_DSP_I4x4_WEIGHT 0x0414
327 /*
328 * [7:0] Offset used to affect Intra/ME model decision
329 * If (me_cost < intra_cost + dsp_resid_mode_offset)
330 * Pred_Mode = me_mode
331 * Else
332 * Pred_mode = intra_mode
333 */
334 #define TW5864_DSP_RESID_MODE_OFFSET 0x0604
336 /* 0x0800 ~ 0x09ff - Quantization TABLE Values */
337 #define TW5864_QUAN_TAB 0x0800
339 /* Valid channel value [0; f], frame value [0; 3] */
340 #define TW5864_RT_CNTR_CH_FRM(channel, frame) \
341 (0x0c00 | (channel << 4) | (frame << 2))
343 #define TW5864_FRAME_BUS1 0x0d00
344 /*
345 * 1 Progressive in part A in bus n
346 * 0 Interlaced in part A in bus n
347 */
348 #define TW5864_PROG_A BIT(0)
349 /*
350 * 1 Progressive in part B in bus n
351 * 0 Interlaced in part B in bus n
352 */
353 #define TW5864_PROG_B BIT(1)
354 /*
355 * 1 Frame Mode in bus n
356 * 0 Field Mode in bus n
357 */
358 #define TW5864_FRAME BIT(2)
359 /*
360 * 0 4CIF in bus n
361 * 1 1D1 + 4 CIF in bus n
362 * 2 2D1 in bus n
363 */
364 #define TW5864_BUS_D1 (3 << 3)
365 /* Bus 1 goes in TW5864_FRAME_BUS1 in [4:0] */
366 /* Bus 2 goes in TW5864_FRAME_BUS1 in [12:8] */
367 #define TW5864_FRAME_BUS2 0x0d04
368 /* Bus 3 goes in TW5864_FRAME_BUS2 in [4:0] */
369 /* Bus 4 goes in TW5864_FRAME_BUS2 in [12:8] */
371 /* [15:0] Horizontal Mirror for channel n */
372 #define TW5864_SENIF_HOR_MIR 0x0d08
373 /* [15:0] Vertical Mirror for channel n */
374 #define TW5864_SENIF_VER_MIR 0x0d0c
376 /*
377 * FRAME_WIDTH_BUSn_A
378 * 0x15f: 4 CIF
379 * 0x2cf: 1 D1 + 3 CIF
380 * 0x2cf: 2 D1
381 * FRAME_WIDTH_BUSn_B
382 * 0x15f: 4 CIF
383 * 0x2cf: 1 D1 + 3 CIF
384 * 0x2cf: 2 D1
385 * FRAME_HEIGHT_BUSn_A
386 * 0x11f: 4CIF (PAL)
387 * 0x23f: 1D1 + 3CIF (PAL)
388 * 0x23f: 2 D1 (PAL)
389 * 0x0ef: 4CIF (NTSC)
390 * 0x1df: 1D1 + 3CIF (NTSC)
391 * 0x1df: 2 D1 (NTSC)
392 * FRAME_HEIGHT_BUSn_B
393 * 0x11f: 4CIF (PAL)
394 * 0x23f: 1D1 + 3CIF (PAL)
395 * 0x23f: 2 D1 (PAL)
396 * 0x0ef: 4CIF (NTSC)
397 * 0x1df: 1D1 + 3CIF (NTSC)
398 * 0x1df: 2 D1 (NTSC)
399 */
400 #define TW5864_FRAME_WIDTH_BUS_A(bus) (0x0d10 + 0x0010 * bus)
401 #define TW5864_FRAME_WIDTH_BUS_B(bus) (0x0d14 + 0x0010 * bus)
402 #define TW5864_FRAME_HEIGHT_BUS_A(bus) (0x0d18 + 0x0010 * bus)
403 #define TW5864_FRAME_HEIGHT_BUS_B(bus) (0x0d1c + 0x0010 * bus)
405 /*
406 * 1: the bus mapped Channel n Full D1
407 * 0: the bus mapped Channel n Half D1
408 */
409 #define TW5864_FULL_HALF_FLAG 0x0d50
411 /*
412 * 0 The bus mapped Channel select partA Mode
413 * 1 The bus mapped Channel select partB Mode
414 */
415 #define TW5864_FULL_HALF_MODE_SEL 0x0d54
417 #define TW5864_VLC 0x1000
418 /* Define controls in register TW5864_VLC */
419 /* QP Value used by H264 CAVLC */
420 #define TW5864_VLC_SLICE_QP 0x003f
421 /*
422 * Swap byte order of VLC stream in d-word.
423 * 1 Normal (VLC output= [31:0])
424 * 0 Swap (VLC output={[23:16],[31:24],[7:0], [15:8]})
425 */
426 #define TW5864_VLC_BYTE_SWP BIT(6)
427 /* Enable Adding 03 circuit for VLC stream */
428 #define TW5864_VLC_ADD03_EN BIT(7)
429 /* Number of bit for VLC bit Align */
430 #define TW5864_VLC_BIT_ALIGN_SHIFT 8
431 #define TW5864_VLC_BIT_ALIGN_MASK (0x1f << 8)
432 /*
433 * Synchronous Interface select for VLC Stream
434 * 1 CDC_VLCS_MAS read VLC stream
435 * 0 CPU read VLC stream
436 */
437 #define TW5864_VLC_INF_SEL BIT(13)
438 /* Enable VLC overflow control */
439 #define TW5864_VLC_OVFL_CNTL BIT(14)
440 /*
441 * 1 PCI Master Mode
442 * 0 Non PCI Master Mode
443 */
444 #define TW5864_VLC_PCI_SEL BIT(15)
445 /*
446 * 0 Enable Adding 03 to VLC header and stream
447 * 1 Disable Adding 03 to VLC header of "00000001"
448 */
449 #define TW5864_VLC_A03_DISAB BIT(16)
450 /*
451 * Status of VLC stream in DDR (one bit for each buffer)
452 * 1 VLC is ready in buffer n (HW set)
453 * 0 VLC is not ready in buffer n (SW clear)
454 */
455 #define TW5864_VLC_BUF_RDY_SHIFT 24
456 #define TW5864_VLC_BUF_RDY_MASK (0xff << 24)
458 /* Total number of bit in the slice */
459 #define TW5864_SLICE_TOTAL_BIT 0x1004
460 /* Total number of bit in the residue */
461 #define TW5864_RES_TOTAL_BIT 0x1008
463 #define TW5864_VLC_BUF 0x100c
464 /* Define controls in register TW5864_VLC_BUF */
465 /* VLC BK0 full status, write ‘1’ to clear */
466 #define TW5864_VLC_BK0_FULL BIT(0)
467 /* VLC BK1 full status, write ‘1’ to clear */
468 #define TW5864_VLC_BK1_FULL BIT(1)
469 /* VLC end slice status, write ‘1’ to clear */
470 #define TW5864_VLC_END_SLICE BIT(2)
471 /* VLC Buffer overflow status, write ‘1’ to clear */
472 #define TW5864_DSP_RD_OF BIT(3)
473 /* VLC string length in either buffer 0 or 1 at end of frame */
474 #define TW5864_VLC_STREAM_LEN_SHIFT 4
475 #define TW5864_VLC_STREAM_LEN_MASK (0x1ff << 4)
477 /* [15:0] Total coefficient number in a frame */
478 #define TW5864_TOTAL_COEF_NO 0x1010
479 /* [0] VLC Encoder Interrupt. Write ‘1’ to clear */
480 #define TW5864_VLC_DSP_INTR 0x1014
481 /* [31:0] VLC stream CRC checksum */
482 #define TW5864_VLC_STREAM_CRC 0x1018
484 #define TW5864_VLC_RD 0x101c
485 /* Define controls in register TW5864_VLC_RD */
486 /*
487 * 1 Read VLC lookup Memory
488 * 0 Read VLC Stream Memory
489 */
490 #define TW5864_VLC_RD_MEM BIT(0)
491 /*
492 * 1 Read VLC Stream Memory in burst mode
493 * 0 Read VLC Stream Memory in single mode
494 */
495 #define TW5864_VLC_RD_BRST BIT(1)
497 /* 0x2000 ~ 0x2ffc -- H264 Stream Memory Map */
498 /*
499 * A word is 4 bytes. I.e.,
500 * VLC_STREAM_MEM[0] address: 0x2000
501 * VLC_STREAM_MEM[1] address: 0x2004
502 * ...
503 * VLC_STREAM_MEM[3FF] address: 0x2ffc
504 */
505 #define TW5864_VLC_STREAM_MEM_START 0x2000
506 #define TW5864_VLC_STREAM_MEM_MAX_OFFSET 0x3ff
507 #define TW5864_VLC_STREAM_MEM(offset) (TW5864_VLC_STREAM_MEM_START + 4 * offset)
509 /* 0x4000 ~ 0x4ffc -- Audio Register Map */
510 /* [31:0] config 1ms cnt = Realtime clk/1000 */
511 #define TW5864_CFG_1MS_CNT 0x4000
513 #define TW5864_ADPCM 0x4004
514 /* Define controls in register TW5864_ADPCM */
515 /* ADPCM decoder enable */
516 #define TW5864_ADPCM_DEC BIT(0)
517 /* ADPCM input data enable */
518 #define TW5864_ADPCM_IN_DATA BIT(1)
519 /* ADPCM encoder enable */
520 #define TW5864_ADPCM_ENC BIT(2)
522 #define TW5864_AUD 0x4008
523 /* Define controls in register TW5864_AUD */
524 /* Record path PCM Audio enable bit for each channel */
525 #define TW5864_AUD_ORG_CH_EN 0x00ff
526 /* Speaker path PCM Audio Enable */
527 #define TW5864_SPK_ORG_EN BIT(16)
528 /*
529 * 0 16bit
530 * 1 8bit
531 */
532 #define TW5864_AD_BIT_MODE BIT(17)
533 #define TW5864_AUD_TYPE_SHIFT 18
534 /*
535 * 0 PCM
536 * 3 ADPCM
537 */
538 #define TW5864_AUD_TYPE (0xf << 18)
539 #define TW5864_AUD_SAMPLE_RATE_SHIFT 22
540 /*
541 * 0 8K
542 * 1 16K
543 */
544 #define TW5864_AUD_SAMPLE_RATE (3 << 22)
545 /* Channel ID used to select audio channel (0 to 16) for loopback */
546 #define TW5864_TESTLOOP_CHID_SHIFT 24
547 #define TW5864_TESTLOOP_CHID (0x1f << 24)
548 /* Enable AD Loopback Test */
549 #define TW5864_TEST_ADLOOP_EN BIT(30)
550 /*
551 * 0 Asynchronous Mode or PCI target mode
552 * 1 PCI Initiator Mode
553 */
554 #define TW5864_AUD_MODE BIT(31)
556 #define TW5864_AUD_ADPCM 0x400c
557 /* Define controls in register TW5864_AUD_ADPCM */
558 /* Record path ADPCM audio channel enable, one bit for each */
559 #define TW5864_AUD_ADPCM_CH_EN 0x00ff
560 /* Speaker path ADPCM audio channel enable */
561 #define TW5864_SPK_ADPCM_EN BIT(16)
563 #define TW5864_PC_BLOCK_ADPCM_RD_NO 0x4018
564 #define TW5864_PC_BLOCK_ADPCM_RD_NO_MASK 0x1f
566 /*
567 * For ADPCM_ENC_WR_PTR, ADPCM_ENC_RD_PTR (see below):
568 * Bit[2:0] ch0
569 * Bit[5:3] ch1
570 * Bit[8:6] ch2
571 * Bit[11:9] ch3
572 * Bit[14:12] ch4
573 * Bit[17:15] ch5
574 * Bit[20:18] ch6
575 * Bit[23:21] ch7
576 * Bit[26:24] ch8
577 * Bit[29:27] ch9
578 * Bit[32:30] ch10
579 * Bit[35:33] ch11
580 * Bit[38:36] ch12
581 * Bit[41:39] ch13
582 * Bit[44:42] ch14
583 * Bit[47:45] ch15
584 * Bit[50:48] ch16
585 */
586 #define TW5864_ADPCM_ENC_XX_MASK 0x3fff
587 #define TW5864_ADPCM_ENC_XX_PTR2_SHIFT 30
588 /* ADPCM_ENC_WR_PTR[29:0] */
589 #define TW5864_ADPCM_ENC_WR_PTR1 0x401c
590 /* ADPCM_ENC_WR_PTR[50:30] */
591 #define TW5864_ADPCM_ENC_WR_PTR2 0x4020
593 /* ADPCM_ENC_RD_PTR[29:0] */
594 #define TW5864_ADPCM_ENC_RD_PTR1 0x4024
595 /* ADPCM_ENC_RD_PTR[50:30] */
596 #define TW5864_ADPCM_ENC_RD_PTR2 0x4028
598 /* [3:0] rd ch0, [7:4] rd ch1, [11:8] wr ch0, [15:12] wr ch1 */
599 #define TW5864_ADPCM_DEC_RD_WR_PTR 0x402c
601 /*
602 * For TW5864_AD_ORIG_WR_PTR, TW5864_AD_ORIG_RD_PTR:
603 * Bit[3:0] ch0
604 * Bit[7:4] ch1
605 * Bit[11:8] ch2
606 * Bit[15:12] ch3
607 * Bit[19:16] ch4
608 * Bit[23:20] ch5
609 * Bit[27:24] ch6
610 * Bit[31:28] ch7
611 * Bit[35:32] ch8
612 * Bit[39:36] ch9
613 * Bit[43:40] ch10
614 * Bit[47:44] ch11
615 * Bit[51:48] ch12
616 * Bit[55:52] ch13
617 * Bit[59:56] ch14
618 * Bit[63:60] ch15
619 * Bit[67:64] ch16
620 */
621 /* AD_ORIG_WR_PTR[31:0] */
622 #define TW5864_AD_ORIG_WR_PTR1 0x4030
623 /* AD_ORIG_WR_PTR[63:32] */
624 #define TW5864_AD_ORIG_WR_PTR2 0x4034
625 /* AD_ORIG_WR_PTR[67:64] */
626 #define TW5864_AD_ORIG_WR_PTR3 0x4038
628 /* AD_ORIG_RD_PTR[31:0] */
629 #define TW5864_AD_ORIG_RD_PTR1 0x403c
630 /* AD_ORIG_RD_PTR[63:32] */
631 #define TW5864_AD_ORIG_RD_PTR2 0x4040
632 /* AD_ORIG_RD_PTR[67:64] */
633 #define TW5864_AD_ORIG_RD_PTR3 0x4044
635 #define TW5864_PC_BLOCK_ORIG_RD_NO 0x4048
636 #define TW5864_PC_BLOCK_ORIG_RD_NO_MASK 0x1f
638 #define TW5864_PCI_AUD 0x404c
639 /* Define controls in register TW5864_PCI_AUD */
640 /*
641 * The register is applicable to PCI initiator mode only. Used to select PCM(0)
642 * or ADPCM(1) audio data sent to PC. One bit for each channel
643 */
644 #define TW5864_PCI_DATA_SEL 0xffff
645 /*
646 * Audio flow control mode selection bit.
647 * 0 Flow control disabled. TW5864 continuously sends audio frame to PC
648 * (initiator mode)
649 * 1 Flow control enabled
650 */
651 #define TW5864_PCI_FLOW_EN BIT(16)
652 /*
653 * When PCI_FLOW_EN is set, PCI need to toggle this bit to send an audio frame
654 * to PC. One toggle to send one frame.
655 */
656 #define TW5864_PCI_AUD_FRM_EN BIT(17)
658 /* [1:0] CS valid to data valid CLK cycles when writing operation */
659 #define TW5864_CS2DAT_CNT 0x8000
660 /* [2:0] Data valid signal width by system clock cycles */
661 #define TW5864_DATA_VLD_WIDTH 0x8004
663 #define TW5864_SYNC 0x8008
664 /* Define controls in register TW5864_SYNC */
665 /*
666 * 0 vlc stream to syncrous port
667 * 1 vlc stream to ddr buffers
668 */
669 #define TW5864_SYNC_CFG BIT(7)
670 /*
671 * 0 SYNC Address sampled on Rising edge
672 * 1 SYNC Address sampled on Falling edge
673 */
674 #define TW5864_SYNC_ADR_EDGE BIT(0)
675 #define TW5864_VLC_STR_DELAY_SHIFT 1
676 /*
677 * 0 No system delay
678 * 1 One system clock delay
679 * 2 Two system clock delay
680 * 3 Three system clock delay
681 */
682 #define TW5864_VLC_STR_DELAY (3 << 1)
683 /*
684 * 0 Rising edge output
685 * 1 Falling edge output
686 */
687 #define TW5864_VLC_OUT_EDGE BIT(3)
689 /*
690 * [1:0]
691 * 2’b00 phase set to 180 degree
692 * 2’b01 phase set to 270 degree
693 * 2’b10 phase set to 0 degree
694 * 2’b11 phase set to 90 degree
695 */
696 #define TW5864_I2C_PHASE_CFG 0x800c
698 /*
699 * The system / DDR clock (166 MHz) is generated with an on-chip system clock
700 * PLL (SYSPLL) using input crystal clock of 27 MHz. The system clock PLL
701 * frequency is controlled with the following equation.
702 * CLK_OUT = CLK_IN * (M+1) / ((N+1) * P)
703 * SYSPLL_M M parameter
704 * SYSPLL_N N parameter
705 * SYSPLL_P P parameter
706 */
707 /* SYSPLL_M[7:0] */
708 #define TW5864_SYSPLL1 0x8018
709 /* Define controls in register TW5864_SYSPLL1 */
710 #define TW5864_SYSPLL_M_LOW 0x00ff
712 /* [2:0]: SYSPLL_M[10:8], [7:3]: SYSPLL_N[4:0] */
713 #define TW5864_SYSPLL2 0x8019
714 /* Define controls in register TW5864_SYSPLL2 */
715 #define TW5864_SYSPLL_M_HI 0x07
716 #define TW5864_SYSPLL_N_LOW_SHIFT 3
717 #define TW5864_SYSPLL_N_LOW (0x1f << 3)
719 /*
720 * [1:0]: SYSPLL_N[6:5], [3:2]: SYSPLL_P, [4]: SYSPLL_IREF, [7:5]: SYSPLL_CP_SEL
721 */
722 #define TW5864_SYSPLL3 0x8020
723 /* Define controls in register TW5864_SYSPLL3 */
724 #define TW5864_SYSPLL_N_HI 0x03
725 #define TW5864_SYSPLL_P_SHIFT 2
726 #define TW5864_SYSPLL_P (0x03 << 2)
727 /*
728 * SYSPLL bias current control
729 * 0 Lower current (default)
730 * 1 30% higher current
731 */
732 #define TW5864_SYSPLL_IREF BIT(4)
733 /*
734 * SYSPLL charge pump current selection
735 * 0 1,5 uA
736 * 1 4 uA
737 * 2 9 uA
738 * 3 19 uA
739 * 4 39 uA
740 * 5 79 uA
741 * 6 159 uA
742 * 7 319 uA
743 */
744 #define TW5864_SYSPLL_CP_SEL_SHIFT 5
745 #define TW5864_SYSPLL_CP_SEL (0x07 << 5)
747 /*
748 * [1:0]: SYSPLL_VCO, [3:2]: SYSPLL_LP_X8, [5:4]: SYSPLL_ICP_SEL,
749 * [6]: SYSPLL_LPF_5PF, [7]: SYSPLL_ED_SEL
750 */
751 #define TW5864_SYSPLL4 0x8021
752 /* Define controls in register TW5864_SYSPLL4 */
753 /*
754 * SYSPLL_VCO VCO Range selection
755 * 00 5 ~ 75 MHz
756 * 01 50 ~ 140 MHz
757 * 10 110 ~ 320 MHz
758 * 11 270 ~ 700 MHz
759 */
760 #define TW5864_SYSPLL_VCO 0x03
761 #define TW5864_SYSPLL_LP_X8_SHIFT 2
762 /*
763 * Loop resister
764 * 0 38.5K ohms
765 * 1 6.6K ohms (default)
766 * 2 2.2K ohms
767 * 3 1.1K ohms
768 */
769 #define TW5864_SYSPLL_LP_X8 (0x03 << 2)
770 #define TW5864_SYSPLL_ICP_SEL_SHIFT 4
771 /*
772 * PLL charge pump fine tune
773 * 00 x1 (default)
774 * 01 x1/2
775 * 10 x1/7
776 * 11 x1/8
777 */
778 #define TW5864_SYSPLL_ICP_SEL (0x03 << 4)
779 /*
780 * PLL low pass filter phase margin adjustment
781 * 0 no 5pF (default)
782 * 1 5pF added
783 */
784 #define TW5864_SYSPLL_LPF_5PF BIT(6)
785 /*
786 * PFD select edge for detection
787 * 0 Falling edge (default)
788 * 1 Rising edge
789 */
790 #define TW5864_SYSPLL_ED_SEL BIT(7)
792 /* [0]: SYSPLL_RST, [4]: SYSPLL_PD */
793 #define TW5864_SYSPLL5 0x8024
794 /* Define controls in register TW5864_SYSPLL5 */
795 /* Reset SYSPLL */
796 #define TW5864_SYSPLL_RST BIT(0)
797 /* Power down SYSPLL */
798 #define TW5864_SYSPLL_PD BIT(4)
800 #define TW5864_PLL_CFG 0x801c
801 /* Define controls in register TW5864_PLL_CFG */
802 /*
803 * Issue Soft Reset from Async Host Interface / PCI Interface clock domain.
804 * Become valid after sync to the xtal clock domain. This bit is set only if
805 * LOAD register bit is also set to 1.
806 */
807 #define TW5864_SRST BIT(0)
808 /*
809 * Issue SYSPLL (166 MHz) configuration latch from Async host interface / PCI
810 * Interface clock domain. The configuration setting becomes effective only if
811 * LOAD register bit is also set to 1.
812 */
813 #define TW5864_SYSPLL_CFG BIT(2)
814 /*
815 * Issue SPLL (108 MHz) configuration load from Async host interface / PCI
816 * Interface clock domain. The configuration setting becomes effective only if
817 * the LOAD register bit is also set to 1.
818 */
819 #define TW5864_SPLL_CFG BIT(4)
820 /*
821 * Set this bit to latch the SRST, SYSPLL_CFG, SPLL_CFG setting into the xtal
822 * clock domain to restart the PLL. This bit is self cleared.
823 */
824 #define TW5864_LOAD BIT(3)
826 /* SPLL_IREF, SPLL_LPX4, SPLL_CPX4, SPLL_PD, SPLL_DBG */
827 #define TW5864_SPLL 0x8028
829 /* 0x8800 ~ 0x88fc -- Interrupt Register Map */
830 /*
831 * Trigger mode of interrupt source 0 ~ 15
832 * 1 Edge trigger mode
833 * 0 Level trigger mode
834 */
835 #define TW5864_TRIGGER_MODE_L 0x8800
836 /* Trigger mode of interrupt source 16 ~ 31 */
837 #define TW5864_TRIGGER_MODE_H 0x8804
838 /* Enable of interrupt source 0 ~ 15 */
839 #define TW5864_INTR_ENABLE_L 0x8808
840 /* Enable of interrupt source 16 ~ 31 */
841 #define TW5864_INTR_ENABLE_H 0x880c
842 /* Clear interrupt command of interrupt source 0 ~ 15 */
843 #define TW5864_INTR_CLR_L 0x8810
844 /* Clear interrupt command of interrupt source 16 ~ 31 */
845 #define TW5864_INTR_CLR_H 0x8814
846 /*
847 * Assertion of interrupt source 0 ~ 15
848 * 1 High level or pos-edge is assertion
849 * 0 Low level or neg-edge is assertion
850 */
851 #define TW5864_INTR_ASSERT_L 0x8818
852 /* Assertion of interrupt source 16 ~ 31 */
853 #define TW5864_INTR_ASSERT_H 0x881c
854 /*
855 * Output level of interrupt
856 * 1 Interrupt output is high assertion
857 * 0 Interrupt output is low assertion
858 */
859 #define TW5864_INTR_OUT_LEVEL 0x8820
860 /*
861 * Status of interrupt source 0 ~ 15
862 * Bit[0]: VLC 4k RAM interrupt
863 * Bit[1]: BURST DDR RAM interrupt
864 * Bit[2]: MV DSP interrupt
865 * Bit[3]: video lost interrupt
866 * Bit[4]: gpio 0 interrupt
867 * Bit[5]: gpio 1 interrupt
868 * Bit[6]: gpio 2 interrupt
869 * Bit[7]: gpio 3 interrupt
870 * Bit[8]: gpio 4 interrupt
871 * Bit[9]: gpio 5 interrupt
872 * Bit[10]: gpio 6 interrupt
873 * Bit[11]: gpio 7 interrupt
874 * Bit[12]: JPEG interrupt
875 * Bit[13:15]: Reserved
876 */
877 #define TW5864_INTR_STATUS_L 0x8838
878 /*
879 * Status of interrupt source 16 ~ 31
880 * Bit[0]: Reserved
881 * Bit[1]: VLC done interrupt
882 * Bit[2]: Reserved
883 * Bit[3]: AD Vsync interrupt
884 * Bit[4]: Preview eof interrupt
885 * Bit[5]: Preview overflow interrupt
886 * Bit[6]: Timer interrupt
887 * Bit[7]: Reserved
888 * Bit[8]: Audio eof interrupt
889 * Bit[9]: I2C done interrupt
890 * Bit[10]: AD interrupt
891 * Bit[11:15]: Reserved
892 */
893 #define TW5864_INTR_STATUS_H 0x883c
895 /* Defines of interrupt bits, united for both low and high word registers */
896 #define TW5864_INTR_VLC_RAM BIT(0)
897 #define TW5864_INTR_BURST BIT(1)
898 #define TW5864_INTR_MV_DSP BIT(2)
899 #define TW5864_INTR_VIN_LOST BIT(3)
900 /* n belongs to [0; 7] */
901 #define TW5864_INTR_GPIO(n) (1 << (4 + n))
902 #define TW5864_INTR_JPEG BIT(12)
903 #define TW5864_INTR_VLC_DONE BIT(17)
904 #define TW5864_INTR_AD_VSYNC BIT(19)
905 #define TW5864_INTR_PV_EOF BIT(20)
906 #define TW5864_INTR_PV_OVERFLOW BIT(21)
907 #define TW5864_INTR_TIMER BIT(22)
908 #define TW5864_INTR_AUD_EOF BIT(24)
909 #define TW5864_INTR_I2C_DONE BIT(25)
910 #define TW5864_INTR_AD BIT(26)
912 /* 0x9000 ~ 0x920c -- Video Capture (VIF) Register Map */
913 /*
914 * H264EN_CH_STATUS[n] Status of Vsync synchronized H264EN_CH_EN (Read Only)
915 * 1 Channel Enabled
916 * 0 Channel Disabled
917 */
918 #define TW5864_H264EN_CH_STATUS 0x9000
919 /*
920 * [15:0] H264EN_CH_EN[n] H264 Encoding Path Enable for channel
921 * 1 Channel Enabled
922 * 0 Channel Disabled
923 */
924 #define TW5864_H264EN_CH_EN 0x9004
925 /*
926 * H264EN_CH_DNS[n] H264 Encoding Path Downscale Video Decoder Input for
927 * channel n
928 * 1 Downscale Y to 1/2
929 * 0 Does not downscale
930 */
931 #define TW5864_H264EN_CH_DNS 0x9008
932 /*
933 * H264EN_CH_PROG[n] H264 Encoding Path channel n is progressive
934 * 1 Progressive (Not valid for TW5864)
935 * 0 Interlaced (TW5864 default)
936 */
937 #define TW5864_H264EN_CH_PROG 0x900c
938 /*
939 * [3:0] H264EN_BUS_MAX_CH[n]
940 * H264 Encoding Path maximum number of channel on BUS n
941 * 0 Max 4 channels
942 * 1 Max 2 channels
943 */
944 #define TW5864_H264EN_BUS_MAX_CH 0x9010
946 /*
947 * H264EN_RATE_MAX_LINE_n H264 Encoding path Rate Mapping Maximum Line Number
948 * on Bus n
949 */
950 #define TW5864_H264EN_RATE_MAX_LINE_EVEN 0x1f
951 #define TW5864_H264EN_RATE_MAX_LINE_ODD_SHIFT 5
952 #define TW5864_H264EN_RATE_MAX_LINE_ODD (0x1f << 5)
953 /*
954 * [4:0] H264EN_RATE_MAX_LINE_0
955 * [9:5] H264EN_RATE_MAX_LINE_1
956 */
957 #define TW5864_H264EN_RATE_MAX_LINE_REG1 0x9014
958 /*
959 * [4:0] H264EN_RATE_MAX_LINE_2
960 * [9:5] H264EN_RATE_MAX_LINE_3
961 */
962 #define TW5864_H264EN_RATE_MAX_LINE_REG2 0x9018
964 /*
965 * H264EN_CHn_FMT H264 Encoding Path Format configuration of Channel n
966 * 00 D1 (For D1 and hD1 frame)
967 * 01 (Reserved)
968 * 10 (Reserved)
969 * 11 D1 with 1/2 size in X (for CIF frame)
970 * Note: To be used with 0x9008 register to configure the frame size
971 */
972 /*
973 * [1:0]: H264EN_CH0_FMT,
974 * ..., [15:14]: H264EN_CH7_FMT
975 */
976 #define TW5864_H264EN_CH_FMT_REG1 0x9020
977 /*
978 * [1:0]: H264EN_CH8_FMT (?),
979 * ..., [15:14]: H264EN_CH15_FMT (?)
980 */
981 #define TW5864_H264EN_CH_FMT_REG2 0x9024
983 /*
984 * H264EN_RATE_CNTL_BUSm_CHn H264 Encoding Path BUS m Rate Control for Channel n
985 */
986 #define TW5864_H264EN_RATE_CNTL_LO_WORD(bus, channel) \
987 (0x9100 + bus * 0x20 + channel * 0x08)
988 #define TW5864_H264EN_RATE_CNTL_HI_WORD(bus, channel) \
989 (0x9104 + bus * 0x20 + channel * 0x08)
991 /*
992 * H264EN_BUSm_MAP_CHn The 16-to-1 MUX configuration register for each encoding
993 * channel (total of 16 channels). Four bits for each channel.
994 */
995 #define TW5864_H264EN_BUS0_MAP 0x9200
996 #define TW5864_H264EN_BUS1_MAP 0x9204
997 #define TW5864_H264EN_BUS2_MAP 0x9208
998 #define TW5864_H264EN_BUS3_MAP 0x920c
1000 /* This register is not defined in datasheet, but used in reference driver */
1001 #define TW5864_UNDECLARED_ERROR_FLAGS_0x9218 0x9218
1003 #define TW5864_GPIO1 0x9800
1004 #define TW5864_GPIO2 0x9804
1005 /* Define controls in registers TW5864_GPIO1, TW5864_GPIO2 */
1006 /* GPIO DATA of Group n */
1007 #define TW5864_GPIO_DATA 0x00ff
1008 #define TW5864_GPIO_OEN_SHIFT 8
1009 /* GPIO Output Enable of Group n */
1010 #define TW5864_GPIO_OEN (0xff << 8)
1012 /* 0xa000 ~ 0xa8ff – DDR Controller Register Map */
1013 /* DDR Controller A */
1014 /*
1015 * [2:0] Data valid counter after read command to DDR. This is the delay value
1016 * to show how many cycles the data will be back from DDR after we issue a read
1017 * command.
1018 */
1019 #define TW5864_RD_ACK_VLD_MUX 0xa000
1021 #define TW5864_DDR_PERIODS 0xa004
1022 /* Define controls in register TW5864_DDR_PERIODS */
1023 /*
1024 * Tras value, the minimum cycle of active to precharge command period,
1025 * default is 7
1026 */
1027 #define TW5864_TRAS_CNT_MAX 0x000f
1028 /*
1029 * Trfc value, the minimum cycle of refresh to active or refresh command period,
1030 * default is 4"hf
1031 */
1032 #define TW5864_RFC_CNT_MAX_SHIFT 8
1033 #define TW5864_RFC_CNT_MAX (0x0f << 8)
1034 /*
1035 * Trcd value, the minimum cycle of active to internal read/write command
1036 * period, default is 4"h2
1037 */
1038 #define TW5864_TCD_CNT_MAX_SHIFT 4
1039 #define TW5864_TCD_CNT_MAX (0x0f << 4)
1040 /* Twr value, write recovery time, default is 4"h3 */
1041 #define TW5864_TWR_CNT_MAX_SHIFT 12
1042 #define TW5864_TWR_CNT_MAX (0x0f << 12)
1044 /*
1045 * [2:0] CAS latency, the delay cycle between internal read command and the
1046 * availability of the first bit of output data, default is 3
1047 */
1048 #define TW5864_CAS_LATENCY 0xa008
1049 /*
1050 * [15:0] Maximum average periodic refresh, the value is based on the current
1051 * frequency to match 7.8mcs
1052 */
1053 #define TW5864_DDR_REF_CNTR_MAX 0xa00c
1054 /*
1055 * DDR_ON_CHIP_MAP [1:0]
1056 * 0 256M DDR on board
1057 * 1 512M DDR on board
1058 * 2 1G DDR on board
1059 * DDR_ON_CHIP_MAP [2]
1060 * 0 Only one DDR chip
1061 * 1 Two DDR chips
1062 */
1063 #define TW5864_DDR_ON_CHIP_MAP 0xa01c
1064 #define TW5864_DDR_SELFTEST_MODE 0xa020
1065 /* Define controls in register TW5864_DDR_SELFTEST_MODE */
1066 /*
1067 * 0 Common read/write mode
1068 * 1 DDR self-test mode
1069 */
1070 #define TW5864_MASTER_MODE BIT(0)
1071 /*
1072 * 0 DDR self-test single read/write
1073 * 1 DDR self-test burst read/write
1074 */
1075 #define TW5864_SINGLE_PROC BIT(1)
1076 /*
1077 * 0 DDR self-test write command
1078 * 1 DDR self-test read command
1079 */
1080 #define TW5864_WRITE_FLAG BIT(2)
1081 #define TW5864_DATA_MODE_SHIFT 4
1082 /*
1083 * 0 write 32'haaaa5555 to DDR
1084 * 1 write 32'hffffffff to DDR
1085 * 2 write 32'hha5a55a5a to DDR
1086 * 3 write increasing data to DDR
1087 */
1088 #define TW5864_DATA_MODE (0x3 << 4)
1090 /* [7:0] The maximum data of one burst in DDR self-test mode */
1091 #define TW5864_BURST_CNTR_MAX 0xa024
1092 /* [15:0] The maximum burst counter (bit 15~0) in DDR self-test mode */
1093 #define TW5864_DDR_PROC_CNTR_MAX_L 0xa028
1094 /* The maximum burst counter (bit 31~16) in DDR self-test mode */
1095 #define TW5864_DDR_PROC_CNTR_MAX_H 0xa02c
1096 /* [0]: Start one DDR self-test */
1097 #define TW5864_DDR_SELF_TEST_CMD 0xa030
1098 /* The maximum error counter (bit 15 ~ 0) in DDR self-test */
1099 #define TW5864_ERR_CNTR_L 0xa034
1101 #define TW5864_ERR_CNTR_H_AND_FLAG 0xa038
1102 /* Define controls in register TW5864_ERR_CNTR_H_AND_FLAG */
1103 /* The maximum error counter (bit 30 ~ 16) in DDR self-test */
1104 #define TW5864_ERR_CNTR_H_MASK 0x3fff
1105 /* DDR self-test end flag */
1106 #define TW5864_END_FLAG 0x8000
1108 /*
1109 * DDR Controller B: same as 0xa000 ~ 0xa038, but add TW5864_DDR_B_OFFSET to all
1110 * addresses
1111 */
1112 #define TW5864_DDR_B_OFFSET 0x0800
1114 /* 0xb004 ~ 0xb018 – HW version/ARB12 Register Map */
1115 /* [15:0] Default is C013 */
1116 #define TW5864_HW_VERSION 0xb004
1118 #define TW5864_REQS_ENABLE 0xb010
1119 /* Define controls in register TW5864_REQS_ENABLE */
1120 /* Audio data in to DDR enable (default 1) */
1121 #define TW5864_AUD_DATA_IN_ENB BIT(0)
1122 /* Audio encode request to DDR enable (default 1) */
1123 #define TW5864_AUD_ENC_REQ_ENB BIT(1)
1124 /* Audio decode request0 to DDR enable (default 1) */
1125 #define TW5864_AUD_DEC_REQ0_ENB BIT(2)
1126 /* Audio decode request1 to DDR enable (default 1) */
1127 #define TW5864_AUD_DEC_REQ1_ENB BIT(3)
1128 /* VLC stream request to DDR enable (default 1) */
1129 #define TW5864_VLC_STRM_REQ_ENB BIT(4)
1130 /* H264 MV request to DDR enable (default 1) */
1131 #define TW5864_DVM_MV_REQ_ENB BIT(5)
1132 /* mux_core MVD request to DDR enable (default 1) */
1133 #define TW5864_MVD_REQ_ENB BIT(6)
1134 /* mux_core MVD temp data request to DDR enable (default 1) */
1135 #define TW5864_MVD_TMP_REQ_ENB BIT(7)
1136 /* JPEG request to DDR enable (default 1) */
1137 #define TW5864_JPEG_REQ_ENB BIT(8)
1138 /* mv_flag request to DDR enable (default 1) */
1139 #define TW5864_MV_FLAG_REQ_ENB BIT(9)
1141 #define TW5864_ARB12 0xb018
1142 /* Define controls in register TW5864_ARB12 */
1143 /* ARB12 Enable (default 1) */
1144 #define TW5864_ARB12_ENB BIT(15)
1145 /* ARB12 maximum value of time out counter (default 15"h1FF) */
1146 #define TW5864_ARB12_TIME_OUT_CNT 0x7fff
1148 /* 0xb800 ~ 0xb80c -- Indirect Access Register Map */
1149 /*
1150 * Spec says:
1151 * In order to access the indirect register space, the following procedure is
1152 * followed.
1153 * But reference driver implementation, and current driver, too, does it
1154 * differently.
1155 *
1156 * Write Registers:
1157 * (1) Write IND_DATA at 0xb804 ~ 0xb807
1158 * (2) Read BUSY flag from 0xb803. Wait until BUSY signal is 0.
1159 * (3) Write IND_ADDR at 0xb800 ~ 0xb801. Set R/W to "1", ENABLE to "1"
1160 * Read Registers:
1161 * (1) Read BUSY flag from 0xb803. Wait until BUSY signal is 0.
1162 * (2) Write IND_ADDR at 0xb800 ~ 0xb801. Set R/W to "0", ENABLE to "1"
1163 * (3) Read BUSY flag from 0xb803. Wait until BUSY signal is 0.
1164 * (4) Read IND_DATA from 0xb804 ~ 0xb807
1165 */
1166 #define TW5864_IND_CTL 0xb800
1167 /* Define controls in register TW5864_IND_CTL */
1168 /* Address used to access indirect register space */
1169 #define TW5864_IND_ADDR 0x0000ffff
1170 /* Wait until this bit is "0" before using indirect access */
1171 #define TW5864_BUSY BIT(31)
1172 /* Activate the indirect access. This bit is self cleared */
1173 #define TW5864_ENABLE BIT(25)
1174 /* Read/Write command */
1175 #define TW5864_RW BIT(24)
1177 /* [31:0] Data used to read/write indirect register space */
1178 #define TW5864_IND_DATA 0xb804
1180 /* 0xc000 ~ 0xc7fc -- Preview Register Map */
1181 /* Mostly skipped this section. */
1182 /*
1183 * [15:0] Status of Vsync Synchronized PCI_PV_CH_EN (Read Only)
1184 * 1 Channel Enabled
1185 * 0 Channel Disabled
1186 */
1187 #define TW5864_PCI_PV_CH_STATUS 0xc000
1188 /*
1189 * [15:0] PCI Preview Path Enable for channel n
1190 * 1 Channel Enable
1191 * 0 Channel Disable
1192 */
1193 #define TW5864_PCI_PV_CH_EN 0xc004
1195 /* 0xc800 ~ 0xc804 -- JPEG Capture Register Map */
1196 /* Skipped. */
1197 /* 0xd000 ~ 0xd0fc -- JPEG Control Register Map */
1198 /* Skipped. */
1200 /* 0xe000 ~ 0xfc04 – Motion Vector Register Map */
1202 /* ME Motion Vector data (Four Byte Each) 0xe000 ~ 0xe7fc */
1203 #define TW5864_ME_MV_VEC_START 0xe000
1204 #define TW5864_ME_MV_VEC_MAX_OFFSET 0x1ff
1205 #define TW5864_ME_MV_VEC(offset) (TW5864_ME_MV_VEC_START + 4 * offset)
1207 #define TW5864_MV 0xfc00
1208 /* Define controls in register TW5864_MV */
1209 /* mv bank0 full status , write "1" to clear */
1210 #define TW5864_MV_BK0_FULL BIT(0)
1211 /* mv bank1 full status , write "1" to clear */
1212 #define TW5864_MV_BK1_FULL BIT(1)
1213 /* slice end status; write "1" to clear */
1214 #define TW5864_MV_EOF BIT(2)
1215 /* mv encode interrupt status; write "1" to clear */
1216 #define TW5864_MV_DSP_INTR BIT(3)
1217 /* mv write memory overflow, write "1" to clear */
1218 #define TW5864_DSP_WR_OF BIT(4)
1219 #define TW5864_MV_LEN_SHIFT 5
1220 /* mv stream length */
1221 #define TW5864_MV_LEN (0xff << 5)
1222 /* The configured status bit written into bit 15 of 0xfc04 */
1223 #define TW5864_MPI_DDR_SEL BIT(13)
1225 #define TW5864_MPI_DDR_SEL_REG 0xfc04
1226 /* Define controls in register TW5864_MPI_DDR_SEL_REG */
1227 /*
1228 * SW configure register
1229 * 0 MV is saved in internal DPR
1230 * 1 MV is saved in DDR
1231 */
1232 #define TW5864_MPI_DDR_SEL2 BIT(15)
1234 /* 0x18000 ~ 0x181fc – PCI Master/Slave Control Map */
1235 #define TW5864_PCI_INTR_STATUS 0x18000
1236 /* Define controls in register TW5864_PCI_INTR_STATUS */
1237 /* vlc done */
1238 #define TW5864_VLC_DONE_INTR BIT(1)
1239 /* ad vsync */
1240 #define TW5864_AD_VSYNC_INTR BIT(3)
1241 /* preview eof */
1242 #define TW5864_PREV_EOF_INTR BIT(4)
1243 /* preview overflow interrupt */
1244 #define TW5864_PREV_OVERFLOW_INTR BIT(5)
1245 /* timer interrupt */
1246 #define TW5864_TIMER_INTR BIT(6)
1247 /* audio eof */
1248 #define TW5864_AUDIO_EOF_INTR BIT(8)
1249 /* IIC done */
1250 #define TW5864_IIC_DONE_INTR BIT(24)
1251 /* ad interrupt (e.g.: video lost, video format changed) */
1252 #define TW5864_AD_INTR_REG BIT(25)
1254 #define TW5864_PCI_INTR_CTL 0x18004
1255 /* Define controls in register TW5864_PCI_INTR_CTL */
1256 /* master enable */
1257 #define TW5864_PCI_MAST_ENB BIT(0)
1258 /* mvd&vlc master enable */
1259 #define TW5864_MVD_VLC_MAST_ENB 0x06
1260 /* (Need to set 0 in TW5864A) */
1261 #define TW5864_AD_MAST_ENB BIT(3)
1262 /* preview master enable */
1263 #define TW5864_PREV_MAST_ENB BIT(4)
1264 /* preview overflow enable */
1265 #define TW5864_PREV_OVERFLOW_ENB BIT(5)
1266 /* timer interrupt enable */
1267 #define TW5864_TIMER_INTR_ENB BIT(6)
1268 /* JPEG master (push mode) enable */
1269 #define TW5864_JPEG_MAST_ENB BIT(7)
1270 #define TW5864_AU_MAST_ENB_CHN_SHIFT 8
1271 /* audio master channel enable */
1272 #define TW5864_AU_MAST_ENB_CHN (0xffff << 8)
1273 /* IIC interrupt enable */
1274 #define TW5864_IIC_INTR_ENB BIT(24)
1275 /* ad interrupt enable */
1276 #define TW5864_AD_INTR_ENB BIT(25)
1277 /* target burst enable */
1278 #define TW5864_PCI_TAR_BURST_ENB BIT(26)
1279 /* vlc stream burst enable */
1280 #define TW5864_PCI_VLC_BURST_ENB BIT(27)
1281 /* ddr burst enable (1 enable, and must set DDR_BRST_EN) */
1282 #define TW5864_PCI_DDR_BURST_ENB BIT(28)
1284 /*
1285 * Because preview and audio have 16 channels separately, so using this
1286 * registers to indicate interrupt status for every channels. This is secondary
1287 * interrupt status register. OR operating of the PREV_INTR_REG is
1288 * PREV_EOF_INTR, OR operating of the AU_INTR_REG bits is AUDIO_EOF_INTR
1289 */
1290 #define TW5864_PREV_AND_AU_INTR 0x18008
1291 /* Define controls in register TW5864_PREV_AND_AU_INTR */
1292 /* preview eof interrupt flag */
1293 #define TW5864_PREV_INTR_REG 0x0000ffff
1294 #define TW5864_AU_INTR_REG_SHIFT 16
1295 /* audio eof interrupt flag */
1296 #define TW5864_AU_INTR_REG (0xffff << 16)
1298 #define TW5864_MASTER_ENB_REG 0x1800c
1299 /* Define controls in register TW5864_MASTER_ENB_REG */
1300 /* master enable */
1301 #define TW5864_PCI_VLC_INTR_ENB BIT(1)
1302 /* mvd and vlc master enable */
1303 #define TW5864_PCI_PREV_INTR_ENB BIT(4)
1304 /* ad vsync master enable */
1305 #define TW5864_PCI_PREV_OF_INTR_ENB BIT(5)
1306 /* jpeg master enable */
1307 #define TW5864_PCI_JPEG_INTR_ENB BIT(7)
1308 /* preview master enable */
1309 #define TW5864_PCI_AUD_INTR_ENB BIT(8)
1311 /*
1312 * Every channel of preview and audio have ping-pong buffers in system memory,
1313 * this register is the buffer flag to notify software which buffer is been
1314 * operated.
1315 */
1316 #define TW5864_PREV_AND_AU_BUF_FLAG 0x18010
1317 /* Define controls in register TW5864_PREV_AND_AU_BUF_FLAG */
1318 /* preview buffer A/B flag */
1319 #define TW5864_PREV_BUF_FLAG 0xffff
1320 #define TW5864_AUDIO_BUF_FLAG_SHIFT 16
1321 /* audio buffer A/B flag */
1322 #define TW5864_AUDIO_BUF_FLAG (0xffff << 16)
1324 #define TW5864_IIC 0x18014
1325 /* Define controls in register TW5864_IIC */
1326 /* register data */
1327 #define TW5864_IIC_DATA 0x00ff
1328 #define TW5864_IIC_REG_ADDR_SHIFT 8
1329 /* register addr */
1330 #define TW5864_IIC_REG_ADDR (0xff << 8)
1331 /* rd/wr flag rd=1,wr=0 */
1332 #define TW5864_IIC_RW BIT(16)
1333 #define TW5864_IIC_DEV_ADDR_SHIFT 17
1334 /* device addr */
1335 #define TW5864_IIC_DEV_ADDR (0x7f << 17)
1336 /*
1337 * iic done, software kick off one time iic transaction through setting this
1338 * bit to 1. Then poll this bit, value 1 indicate iic transaction have
1339 * completed, if read, valid data have been stored in iic_data
1340 */
1341 #define TW5864_IIC_DONE BIT(24)
1343 #define TW5864_RST_AND_IF_INFO 0x18018
1344 /* Define controls in register TW5864_RST_AND_IF_INFO */
1345 /* application software soft reset */
1346 #define TW5864_APP_SOFT_RST BIT(0)
1347 #define TW5864_PCI_INF_VERSION_SHIFT 16
1348 /* PCI interface version, read only */
1349 #define TW5864_PCI_INF_VERSION (0xffff << 16)
1351 /* vlc stream crc value, it is calculated in pci module */
1352 #define TW5864_VLC_CRC_REG 0x1801c
1353 /*
1354 * vlc max length, it is defined by software based on software assign memory
1355 * space for vlc
1356 */
1357 #define TW5864_VLC_MAX_LENGTH 0x18020
1358 /* vlc length of one frame */
1359 #define TW5864_VLC_LENGTH 0x18024
1360 /* vlc original crc value */
1361 #define TW5864_VLC_INTRA_CRC_I_REG 0x18028
1362 /* vlc original crc value */
1363 #define TW5864_VLC_INTRA_CRC_O_REG 0x1802c
1364 /* mv stream crc value, it is calculated in pci module */
1365 #define TW5864_VLC_PAR_CRC_REG 0x18030
1366 /* mv length */
1367 #define TW5864_VLC_PAR_LENGTH_REG 0x18034
1368 /* mv original crc value */
1369 #define TW5864_VLC_PAR_I_REG 0x18038
1370 /* mv original crc value */
1371 #define TW5864_VLC_PAR_O_REG 0x1803c
1373 /*
1374 * Configuration register for 9[or 10] CIFs or 1D1+15QCIF Preview mode.
1375 * PREV_PCI_ENB_CHN[0] Enable 9th preview channel (9CIF prev) or 1D1 channel in
1376 * (1D1+15QCIF prev)
1377 * PREV_PCI_ENB_CHN[1] Enable 10th preview channel
1378 */
1379 #define TW5864_PREV_PCI_ENB_CHN 0x18040
1380 /* Description skipped. */
1381 #define TW5864_PREV_FRAME_FORMAT_IN 0x18044
1382 /* IIC enable */
1383 #define TW5864_IIC_ENB 0x18048
1384 /*
1385 * Timer interrupt interval
1386 * 0 1ms
1387 * 1 2ms
1388 * 2 4ms
1389 * 3 8ms
1390 */
1391 #define TW5864_PCI_INTTM_SCALE 0x1804c
1393 /*
1394 * The above register is pci base address registers. Application software will
1395 * initialize them to tell chip where the corresponding stream will be dumped
1396 * to. Application software will select appropriate base address interval based
1397 * on the stream length.
1398 */
1399 /* VLC stream base address */
1400 #define TW5864_VLC_STREAM_BASE_ADDR 0x18080
1401 /* MV stream base address */
1402 #define TW5864_MV_STREAM_BASE_ADDR 0x18084
1403 /* 0x180a0 – 0x180bc: audio burst base address. Skipped. */
1404 /* 0x180c0 ~ 0x180dc – JPEG Push Mode Buffer Base Address. Skipped. */
1405 /* 0x18100 – 0x1817c: preview burst base address. Skipped. */
1407 /* 0x80000 ~ 0x87fff -- DDR Burst RW Register Map */
1408 #define TW5864_DDR_CTL 0x80000
1409 /* Define controls in register TW5864_DDR_CTL */
1410 #define TW5864_BRST_LENGTH_SHIFT 2
1411 /* Length of 32-bit data burst */
1412 #define TW5864_BRST_LENGTH (0x3fff << 2)
1413 /*
1414 * Burst Read/Write
1415 * 0 Read Burst from DDR
1416 * 1 Write Burst to DDR
1417 */
1418 #define TW5864_BRST_RW BIT(16)
1419 /* Begin a new DDR Burst. This bit is self cleared */
1420 #define TW5864_NEW_BRST_CMD BIT(17)
1421 /* DDR Burst End Flag */
1422 #define TW5864_BRST_END BIT(24)
1423 /* Enable Error Interrupt for Single DDR Access */
1424 #define TW5864_SING_ERR_INTR BIT(25)
1425 /* Enable Error Interrupt for Burst DDR Access */
1426 #define TW5864_BRST_ERR_INTR BIT(26)
1427 /* Enable Interrupt for End of DDR Burst Access */
1428 #define TW5864_BRST_END_INTR BIT(27)
1429 /* DDR Single Access Error Flag */
1430 #define TW5864_SINGLE_ERR BIT(28)
1431 /* DDR Single Access Busy Flag */
1432 #define TW5864_SINGLE_BUSY BIT(29)
1433 /* DDR Burst Access Error Flag */
1434 #define TW5864_BRST_ERR BIT(30)
1435 /* DDR Burst Access Busy Flag */
1436 #define TW5864_BRST_BUSY BIT(31)
1438 /* [27:0] DDR Access Address. Bit [1:0] has to be 0 */
1439 #define TW5864_DDR_ADDR 0x80004
1440 /* DDR Access Internal Buffer Address. Bit [1:0] has to be 0 */
1441 #define TW5864_DPR_BUF_ADDR 0x80008
1442 /* SRAM Buffer MPI Access Space. Totally 16 KB */
1443 #define TW5864_DPR_BUF_START 0x84000
1444 /* 0x84000 - 0x87ffc */
1445 #define TW5864_DPR_BUF_SIZE 0x4000
1447 /* Indirect Map Space */
1448 /*
1449 * The indirect space is accessed through 0xb800 ~ 0xb807 registers in direct
1450 * access space
1451 */
1452 /* Analog Video / Audio Decoder / Encoder */
1453 /* Allowed channel values: [0; 3] */
1454 /* Read-only register */
1455 #define TW5864_INDIR_VIN_0(channel) (0x000 + channel * 0x010)
1456 /* Define controls in register TW5864_INDIR_VIN_0 */
1457 /*
1458 * 1 Video not present. (sync is not detected in number of consecutive line
1459 * periods specified by MISSCNT register)
1460 * 0 Video detected.
1461 */
1462 #define TW5864_INDIR_VIN_0_VDLOSS BIT(7)
1463 /*
1464 * 1 Horizontal sync PLL is locked to the incoming video source.
1465 * 0 Horizontal sync PLL is not locked.
1466 */
1467 #define TW5864_INDIR_VIN_0_HLOCK BIT(6)
1468 /*
1469 * 1 Sub-carrier PLL is locked to the incoming video source.
1470 * 0 Sub-carrier PLL is not locked.
1471 */
1472 #define TW5864_INDIR_VIN_0_SLOCK BIT(5)
1473 /*
1474 * 1 Even field is being decoded.
1475 * 0 Odd field is being decoded.
1476 */
1477 #define TW5864_INDIR_VIN_0_FLD BIT(4)
1478 /*
1479 * 1 Vertical logic is locked to the incoming video source.
1480 * 0 Vertical logic is not locked.
1481 */
1482 #define TW5864_INDIR_VIN_0_VLOCK BIT(3)
1483 /*
1484 * 1 No color burst signal detected.
1485 * 0 Color burst signal detected.
1486 */
1487 #define TW5864_INDIR_VIN_0_MONO BIT(1)
1488 /*
1489 * 0 60Hz source detected
1490 * 1 50Hz source detected
1491 * The actual vertical scanning frequency depends on the current standard
1492 * invoked.
1493 */
1494 #define TW5864_INDIR_VIN_0_DET50 BIT(0)
1496 #define TW5864_INDIR_VIN_1(channel) (0x001 + channel * 0x010)
1497 /* VCR signal indicator. Read-only. */
1498 #define TW5864_INDIR_VIN_1_VCR BIT(7)
1499 /* Weak signal indicator 2. Read-only. */
1500 #define TW5864_INDIR_VIN_1_WKAIR BIT(6)
1501 /* Weak signal indicator controlled by WKTH. Read-only. */
1502 #define TW5864_INDIR_VIN_1_WKAIR1 BIT(5)
1503 /*
1504 * 1 = Standard signal
1505 * 0 = Non-standard signal
1506 * Read-only
1507 */
1508 #define TW5864_INDIR_VIN_1_VSTD BIT(4)
1509 /*
1510 * 1 = Non-interlaced signal
1511 * 0 = interlaced signal
1512 * Read-only
1513 */
1514 #define TW5864_INDIR_VIN_1_NINTL BIT(3)
1515 /*
1516 * Vertical Sharpness Control. Writable.
1517 * 0 = None (default)
1518 * 7 = Highest
1519 * **Note: VSHP must be set to ‘0’ if COMB = 0
1520 */
1521 #define TW5864_INDIR_VIN_1_VSHP 0x07
1523 /* HDELAY_XY[7:0] */
1524 #define TW5864_INDIR_VIN_2_HDELAY_XY_LO(channel) (0x002 + channel * 0x010)
1525 /* HACTIVE_XY[7:0] */
1526 #define TW5864_INDIR_VIN_3_HACTIVE_XY_LO(channel) (0x003 + channel * 0x010)
1527 /* VDELAY_XY[7:0] */
1528 #define TW5864_INDIR_VIN_4_VDELAY_XY_LO(channel) (0x004 + channel * 0x010)
1529 /* VACTIVE_XY[7:0] */
1530 #define TW5864_INDIR_VIN_5_VACTIVE_XY_LO(channel) (0x005 + channel * 0x010)
1532 #define TW5864_INDIR_VIN_6(channel) (0x006 + channel * 0x010)
1533 /* Define controls in register TW5864_INDIR_VIN_6 */
1534 #define TW5864_INDIR_VIN_6_HDELAY_XY_HI 0x03
1535 #define TW5864_INDIR_VIN_6_HACTIVE_XY_HI_SHIFT 2
1536 #define TW5864_INDIR_VIN_6_HACTIVE_XY_HI (0x03 << 2)
1537 #define TW5864_INDIR_VIN_6_VDELAY_XY_HI BIT(4)
1538 #define TW5864_INDIR_VIN_6_VACTIVE_XY_HI BIT(5)
1540 /*
1541 * HDELAY_XY This 10bit register defines the starting location of horizontal
1542 * active pixel for display / record path. A unit is 1 pixel. The default value
1543 * is 0x00f for NTSC and 0x00a for PAL.
1544 *
1545 * HACTIVE_XY This 10bit register defines the number of horizontal active pixel
1546 * for display / record path. A unit is 1 pixel. The default value is decimal
1547 * 720.
1548 *
1549 * VDELAY_XY This 9bit register defines the starting location of vertical
1550 * active for display / record path. A unit is 1 line. The default value is
1551 * decimal 6.
1552 *
1553 * VACTIVE_XY This 9bit register defines the number of vertical active lines
1554 * for display / record path. A unit is 1 line. The default value is decimal
1555 * 240.
1556 */
1558 /* HUE These bits control the color hue as 2's complement number. They have
1559 * value from +36o (7Fh) to -36o (80h) with an increment of 2.8o. The 2 LSB has
1560 * no effect. The positive value gives greenish tone and negative value gives
1561 * purplish tone. The default value is 0o (00h). This is effective only on NTSC
1562 * system. The default is 00h.
1563 */
1564 #define TW5864_INDIR_VIN_7_HUE(channel) (0x007 + channel * 0x010)
1566 #define TW5864_INDIR_VIN_8(channel) (0x008 + channel * 0x010)
1567 /* Define controls in register TW5864_INDIR_VIN_8 */
1568 /*
1569 * This bit controls the center frequency of the peaking filter.
1570 * The corresponding gain adjustment is HFLT.
1571 * 0 Low
1572 * 1 center
1573 */
1574 #define TW5864_INDIR_VIN_8_SCURVE BIT(7)
1575 /* CTI level selection. The default is 1.
1576 * 0 None
1577 * 3 Highest
1578 */
1579 #define TW5864_INDIR_VIN_8_CTI_SHIFT 4
1580 #define TW5864_INDIR_VIN_8_CTI (0x03 << 4)
1582 /*
1583 * These bits control the amount of sharpness enhancement on the luminance
1584 * signals. There are 16 levels of control with "0" having no effect on the
1585 * output image. 1 through 15 provides sharpness enhancement with "F" being the
1586 * strongest. The default is 1.
1587 */
1588 #define TW5864_INDIR_VIN_8_SHARPNESS 0x0f
1590 /*
1591 * These bits control the luminance contrast gain. A value of 100 (64h) has a
1592 * gain of 1. The range adjustment is from 0% to 255% at 1% per step. The
1593 * default is 64h.
1594 */
1595 #define TW5864_INDIR_VIN_9_CNTRST(channel) (0x009 + channel * 0x010)
1597 /*
1598 * These bits control the brightness. They have value of –128 to 127 in 2's
1599 * complement form. Positive value increases brightness. A value 0 has no
1600 * effect on the data. The default is 00h.
1601 */
1602 #define TW5864_INDIR_VIN_A_BRIGHT(channel) (0x00a + channel * 0x010)
1604 /*
1605 * These bits control the digital gain adjustment to the U (or Cb) component of
1606 * the digital video signal. The color saturation can be adjusted by adjusting
1607 * the U and V color gain components by the same amount in the normal
1608 * situation. The U and V can also be adjusted independently to provide greater
1609 * flexibility. The range of adjustment is 0 to 200%. A value of 128 (80h) has
1610 * gain of 100%. The default is 80h.
1611 */
1612 #define TW5864_INDIR_VIN_B_SAT_U(channel) (0x00b + channel * 0x010)
1614 /*
1615 * These bits control the digital gain adjustment to the V (or Cr) component of
1616 * the digital video signal. The color saturation can be adjusted by adjusting
1617 * the U and V color gain components by the same amount in the normal
1618 * situation. The U and V can also be adjusted independently to provide greater
1619 * flexibility. The range of adjustment is 0 to 200%. A value of 128 (80h) has
1620 * gain of 100%. The default is 80h.
1621 */
1622 #define TW5864_INDIR_VIN_C_SAT_V(channel) (0x00c + channel * 0x010)
1624 /* Read-only */
1625 #define TW5864_INDIR_VIN_D(channel) (0x00d + channel * 0x010)
1626 /* Define controls in register TW5864_INDIR_VIN_D */
1627 /* Macrovision color stripe detection may be un-reliable */
1628 #define TW5864_INDIR_VIN_D_CSBAD BIT(3)
1629 /* Macrovision AGC pulse detected */
1630 #define TW5864_INDIR_VIN_D_MCVSN BIT(2)
1631 /* Macrovision color stripe protection burst detected */
1632 #define TW5864_INDIR_VIN_D_CSTRIPE BIT(1)
1633 /*
1634 * This bit is valid only when color stripe protection is detected, i.e. if
1635 * CSTRIPE=1,
1636 * 1 Type 2 color stripe protection
1637 * 0 Type 3 color stripe protection
1638 */
1639 #define TW5864_INDIR_VIN_D_CTYPE2 BIT(0)
1641 /* Read-only */
1642 #define TW5864_INDIR_VIN_E(channel) (0x00e + channel * 0x010)
1643 /* Define controls in register TW5864_INDIR_VIN_E */
1644 /*
1645 * Read-only.
1646 * 0 Idle
1647 * 1 Detection in progress
1648 */
1649 #define TW5864_INDIR_VIN_E_DETSTUS BIT(7)
1650 /*
1651 * STDNOW Current standard invoked
1652 * 0 NTSC (M)
1653 * 1 PAL (B, D, G, H, I)
1654 * 2 SECAM
1655 * 3 NTSC4.43
1656 * 4 PAL (M)
1657 * 5 PAL (CN)
1658 * 6 PAL 60
1659 * 7 Not valid
1660 */
1661 #define TW5864_INDIR_VIN_E_STDNOW_SHIFT 4
1662 #define TW5864_INDIR_VIN_E_STDNOW (0x07 << 4)
1664 /*
1665 * 1 Disable the shadow registers
1666 * 0 Enable VACTIVE and HDELAY shadow registers value depending on STANDARD.
1667 * (Default)
1668 */
1669 #define TW5864_INDIR_VIN_E_ATREG BIT(3)
1670 /*
1671 * STANDARD Standard selection
1672 * 0 NTSC (M)
1673 * 1 PAL (B, D, G, H, I)
1674 * 2 SECAM
1675 * 3 NTSC4.43
1676 * 4 PAL (M)
1677 * 5 PAL (CN)
1678 * 6 PAL 60
1679 * 7 Auto detection (Default)
1680 */
1681 #define TW5864_INDIR_VIN_E_STANDARD 0x07
1683 #define TW5864_INDIR_VIN_F(channel) (0x00f + channel * 0x010)
1684 /* Define controls in register TW5864_INDIR_VIN_F */
1685 /*
1686 * 1 Writing 1 to this bit will manually initiate the auto format detection
1687 * process. This bit is a self-clearing bit
1688 * 0 Manual initiation of auto format detection is done. (Default)
1689 */
1690 #define TW5864_INDIR_VIN_F_ATSTART BIT(7)
1691 /* Enable recognition of PAL60 (Default) */
1692 #define TW5864_INDIR_VIN_F_PAL60EN BIT(6)
1693 /* Enable recognition of PAL (CN). (Default) */
1694 #define TW5864_INDIR_VIN_F_PALCNEN BIT(5)
1695 /* Enable recognition of PAL (M). (Default) */
1696 #define TW5864_INDIR_VIN_F_PALMEN BIT(4)
1697 /* Enable recognition of NTSC 4.43. (Default) */
1698 #define TW5864_INDIR_VIN_F_NTSC44EN BIT(3)
1699 /* Enable recognition of SECAM. (Default) */
1700 #define TW5864_INDIR_VIN_F_SECAMEN BIT(2)
1701 /* Enable recognition of PAL (B, D, G, H, I). (Default) */
1702 #define TW5864_INDIR_VIN_F_PALBEN BIT(1)
1703 /* Enable recognition of NTSC (M). (Default) */
1704 #define TW5864_INDIR_VIN_F_NTSCEN BIT(0)
1706 /* Some registers skipped. */
1708 /* Use falling edge to sample VD1-VD4 from 54 MHz to 108 MHz */
1709 #define TW5864_INDIR_VD_108_POL 0x041
1710 #define TW5864_INDIR_VD_108_POL_VD12 BIT(0)
1711 #define TW5864_INDIR_VD_108_POL_VD34 BIT(1)
1712 #define TW5864_INDIR_VD_108_POL_BOTH \
1713 (TW5864_INDIR_VD_108_POL_VD12 | TW5864_INDIR_VD_108_POL_VD34)
1715 /* Some registers skipped. */
1717 /*
1718 * Audio Input ADC gain control
1719 * 0 0.25
1720 * 1 0.31
1721 * 2 0.38
1722 * 3 0.44
1723 * 4 0.50
1724 * 5 0.63
1725 * 6 0.75
1726 * 7 0.88
1727 * 8 1.00 (default)
1728 * 9 1.25
1729 * 10 1.50
1730 * 11 1.75
1731 * 12 2.00
1732 * 13 2.25
1733 * 14 2.50
1734 * 15 2.75
1735 */
1736 /* [3:0] channel 0, [7:4] channel 1 */
1737 #define TW5864_INDIR_AIGAIN1 0x060
1738 /* [3:0] channel 2, [7:4] channel 3 */
1739 #define TW5864_INDIR_AIGAIN2 0x061
1741 /* Some registers skipped */
1743 #define TW5864_INDIR_AIN_0x06D 0x06d
1744 /* Define controls in register TW5864_INDIR_AIN_0x06D */
1745 /*
1746 * LAWMD Select u-Law/A-Law/PCM/SB data output format on ADATR and ADATM pin.
1747 * 0 PCM output (default)
1748 * 1 SB (Signed MSB bit in PCM data is inverted) output
1749 * 2 u-Law output
1750 * 3 A-Law output
1751 */
1752 #define TW5864_INDIR_AIN_LAWMD_SHIFT 6
1753 #define TW5864_INDIR_AIN_LAWMD (0x03 << 6)
1754 /*
1755 * Disable the mixing ratio value for all audio.
1756 * 0 Apply individual mixing ratio value for each audio (default)
1757 * 1 Apply nominal value for all audio commonly
1758 */
1759 #define TW5864_INDIR_AIN_MIX_DERATIO BIT(5)
1760 /*
1761 * Enable the mute function for audio channel AINn when n is 0 to 3. It effects
1762 * only for mixing. When n = 4, it enable the mute function of the playback
1763 * audio input. It effects only for single chip or the last stage chip
1764 * 0 Normal
1765 * 1 Muted (default)
1766 */
1767 #define TW5864_INDIR_AIN_MIX_MUTE 0x1f
1769 /* Some registers skipped */
1771 #define TW5864_INDIR_AIN_0x0E3 0x0e3
1772 /* Define controls in register TW5864_INDIR_AIN_0x0E3 */
1773 /*
1774 * ADATP signal is coming from external ADPCM decoder, instead of on-chip ADPCM
1775 * decoder
1776 */
1777 #define TW5864_INDIR_AIN_0x0E3_EXT_ADATP BIT(7)
1778 /* ACLKP output signal polarity inverse */
1779 #define TW5864_INDIR_AIN_0x0E3_ACLKPPOLO BIT(6)
1780 /*
1781 * ACLKR input signal polarity inverse.
1782 * 0 Not inversed (Default)
1783 * 1 Inversed
1784 */
1785 #define TW5864_INDIR_AIN_0x0E3_ACLKRPOL BIT(5)
1786 /*
1787 * ACLKP input signal polarity inverse.
1788 * 0 Not inversed (Default)
1789 * 1 Inversed
1790 */
1791 #define TW5864_INDIR_AIN_0x0E3_ACLKPPOLI BIT(4)
1792 /*
1793 * ACKI [21:0] control automatic set up with AFMD registers
1794 * This mode is only effective when ACLKRMASTER=1
1795 * 0 ACKI [21:0] registers set up ACKI control
1796 * 1 ACKI control is automatically set up by AFMD register values
1797 */
1798 #define TW5864_INDIR_AIN_0x0E3_AFAUTO BIT(3)
1799 /*
1800 * AFAUTO control mode
1801 * 0 8kHz setting (Default)
1802 * 1 16kHz setting
1803 * 2 32kHz setting
1804 * 3 44.1kHz setting
1805 * 4 48kHz setting
1806 */
1807 #define TW5864_INDIR_AIN_0x0E3_AFMD 0x07
1809 #define TW5864_INDIR_AIN_0x0E4 0x0e4
1810 /* Define controls in register TW5864_INDIR_AIN_0x0ED */
1811 /*
1812 * 8bit I2S Record output mode.
1813 * 0 L/R half length separated output (Default).
1814 * 1 One continuous packed output equal to DSP output format.
1815 */
1816 #define TW5864_INDIR_AIN_0x0E4_I2S8MODE BIT(7)
1817 /*
1818 * Audio Clock Master ACLKR output wave format.
1819 * 0 High periods is one 27MHz clock period (default).
1820 * 1 Almost duty 50-50% clock output on ACLKR pin. If this mode is selected, two
1821 * times bigger number value need to be set up on the ACKI register. If
1822 * AFAUTO=1, ACKI control is automatically set up even if MASCKMD=1.
1823 */
1824 #define TW5864_INDIR_AIN_0x0E4_MASCKMD BIT(6)
1825 /* Playback ACLKP/ASYNP/ADATP input data MSB-LSB swapping */
1826 #define TW5864_INDIR_AIN_0x0E4_PBINSWAP BIT(5)
1827 /*
1828 * ASYNR input signal delay.
1829 * 0 No delay
1830 * 1 Add one 27MHz period delay in ASYNR signal input
1831 */
1832 #define TW5864_INDIR_AIN_0x0E4_ASYNRDLY BIT(4)
1833 /*
1834 * ASYNP input signal delay.
1835 * 0 no delay
1836 * 1 add one 27MHz period delay in ASYNP signal input
1837 */
1838 #define TW5864_INDIR_AIN_0x0E4_ASYNPDLY BIT(3)
1839 /*
1840 * ADATP input data delay by one ACLKP clock.
1841 * 0 No delay (Default). This is for I2S type 1T delay input interface.
1842 * 1 Add 1 ACLKP clock delay in ADATP input data. This is for left-justified
1843 * type 0T delay input interface.
1844 */
1845 #define TW5864_INDIR_AIN_0x0E4_ADATPDLY BIT(2)
1846 /*
1847 * Select u-Law/A-Law/PCM/SB data input format on ADATP pin.
1848 * 0 PCM input (Default)
1849 * 1 SB (Signed MSB bit in PCM data is inverted) input
1850 * 2 u-Law input
1851 * 3 A-Law input
1852 */
1853 #define TW5864_INDIR_AIN_0x0E4_INLAWMD 0x03
1855 /*
1856 * Enable state register updating and interrupt request of audio AIN5 detection
1857 * for each input
1858 */
1859 #define TW5864_INDIR_AIN_A5DETENA 0x0e5
1861 /* Some registers skipped */
1863 /*
1864 * [7:3]: DEV_ID The TW5864 product ID code is 01000
1865 * [2:0]: REV_ID The revision number is 0h
1866 */
1867 #define TW5864_INDIR_ID 0x0fe
1869 #define TW5864_INDIR_IN_PIC_WIDTH(channel) (0x200 + 4 * channel)
1870 #define TW5864_INDIR_IN_PIC_HEIGHT(channel) (0x201 + 4 * channel)
1871 #define TW5864_INDIR_OUT_PIC_WIDTH(channel) (0x202 + 4 * channel)
1872 #define TW5864_INDIR_OUT_PIC_HEIGHT(channel) (0x203 + 4 * channel)
1874 /* Some registers skipped */
1876 #define TW5864_INDIR_CROP_ETC 0x260
1877 /* Define controls in register TW5864_INDIR_CROP_ETC */
1878 /* Enable cropping from 720 to 704 */
1879 #define TW5864_INDIR_CROP_ETC_CROP_EN 0x4
1881 /*
1882 * Interrupt status register from the front-end. Write "1" to each bit to clear
1883 * the interrupt
1884 * 15:0 Motion detection interrupt for channel 0 ~ 15
1885 * 31:16 Night detection interrupt for channel 0 ~ 15
1886 * 47:32 Blind detection interrupt for channel 0 ~ 15
1887 * 63:48 No video interrupt for channel 0 ~ 15
1888 * 79:64 Line mode underflow interrupt for channel 0 ~ 15
1889 * 95:80 Line mode overflow interrupt for channel 0 ~ 15
1890 */
1891 /* 0x2d0~0x2d7: [63:0] bits */
1892 #define TW5864_INDIR_INTERRUPT1 0x2d0
1893 /* 0x2e0~0x2e3: [95:64] bits */
1894 #define TW5864_INDIR_INTERRUPT2 0x2e0
1896 /*
1897 * Interrupt mask register for interrupts in 0x2d0 ~ 0x2d7
1898 * 15:0 Motion detection interrupt for channel 0 ~ 15
1899 * 31:16 Night detection interrupt for channel 0 ~ 15
1900 * 47:32 Blind detection interrupt for channel 0 ~ 15
1901 * 63:48 No video interrupt for channel 0 ~ 15
1902 * 79:64 Line mode underflow interrupt for channel 0 ~ 15
1903 * 95:80 Line mode overflow interrupt for channel 0 ~ 15
1904 */
1905 /* 0x2d8~0x2df: [63:0] bits */
1906 #define TW5864_INDIR_INTERRUPT_MASK1 0x2d8
1907 /* 0x2e8~0x2eb: [95:64] bits */
1908 #define TW5864_INDIR_INTERRUPT_MASK2 0x2e8
1910 /* [11:0]: Interrupt summary register for interrupts & interrupt mask from in
1911 * 0x2d0 ~ 0x2d7 and 0x2d8 ~ 0x2df
1912 * bit 0: interrupt occurs in 0x2d0 & 0x2d8
1913 * bit 1: interrupt occurs in 0x2d1 & 0x2d9
1914 * bit 2: interrupt occurs in 0x2d2 & 0x2da
1915 * bit 3: interrupt occurs in 0x2d3 & 0x2db
1916 * bit 4: interrupt occurs in 0x2d4 & 0x2dc
1917 * bit 5: interrupt occurs in 0x2d5 & 0x2dd
1918 * bit 6: interrupt occurs in 0x2d6 & 0x2de
1919 * bit 7: interrupt occurs in 0x2d7 & 0x2df
1920 * bit 8: interrupt occurs in 0x2e0 & 0x2e8
1921 * bit 9: interrupt occurs in 0x2e1 & 0x2e9
1922 * bit 10: interrupt occurs in 0x2e2 & 0x2ea
1923 * bit 11: interrupt occurs in 0x2e3 & 0x2eb
1924 */
1925 #define TW5864_INDIR_INTERRUPT_SUMMARY 0x2f0
1927 /* Motion / Blind / Night Detection */
1928 /* valid value for channel is [0:15] */
1929 #define TW5864_INDIR_DETECTION_CTL0(channel) (0x300 + channel * 0x08)
1930 /* Define controls in register TW5864_INDIR_DETECTION_CTL0 */
1931 /*
1932 * Disable the motion and blind detection.
1933 * 0 Enable motion and blind detection (default)
1934 * 1 Disable motion and blind detection
1935 */
1936 #define TW5864_INDIR_DETECTION_CTL0_MD_DIS BIT(5)
1937 /*
1938 * Request to start motion detection on manual trigger mode
1939 * 0 None Operation (default)
1940 * 1 Request to start motion detection
1941 */
1942 #define TW5864_INDIR_DETECTION_CTL0_MD_STRB BIT(3)
1943 /*
1944 * Select the trigger mode of motion detection
1945 * 0 Automatic trigger mode of motion detection (default)
1946 * 1 Manual trigger mode for motion detection
1947 */
1948 #define TW5864_INDIR_DETECTION_CTL0_MD_STRB_EN BIT(2)
1949 /*
1950 * Define the threshold of cell for blind detection.
1951 * 0 Low threshold (More sensitive) (default)
1952 * : :
1953 * 3 High threshold (Less sensitive)
1954 */
1955 #define TW5864_INDIR_DETECTION_CTL0_BD_CELSENS 0x03
1957 #define TW5864_INDIR_DETECTION_CTL1(channel) (0x301 + channel * 0x08)
1958 /* Define controls in register TW5864_INDIR_DETECTION_CTL1 */
1959 /*
1960 * Control the temporal sensitivity of motion detector.
1961 * 0 More Sensitive (default)
1962 * : :
1963 * 15 Less Sensitive
1964 */
1965 #define TW5864_INDIR_DETECTION_CTL1_MD_TMPSENS_SHIFT 4
1966 #define TW5864_INDIR_DETECTION_CTL1_MD_TMPSENS (0x0f << 4)
1967 /*
1968 * Adjust the horizontal starting position for motion detection
1969 * 0 0 pixel (default)
1970 * : :
1971 * 15 15 pixels
1972 */
1973 #define TW5864_INDIR_DETECTION_CTL1_MD_PIXEL_OS 0x0f
1975 #define TW5864_INDIR_DETECTION_CTL2(channel) (0x302 + channel * 0x08)
1976 /* Define controls in register TW5864_INDIR_DETECTION_CTL2 */
1977 /*
1978 * Control the updating time of reference field for motion detection.
1979 * 0 Update reference field every field (default)
1980 * 1 Update reference field according to MD_SPEED
1981 */
1982 #define TW5864_INDIR_DETECTION_CTL2_MD_REFFLD BIT(7)
1983 /*
1984 * Select the field for motion detection.
1985 * 0 Detecting motion for only odd field (default)
1986 * 1 Detecting motion for only even field
1987 * 2 Detecting motion for any field
1988 * 3 Detecting motion for both odd and even field
1989 */
1990 #define TW5864_INDIR_DETECTION_CTL2_MD_FIELD_SHIFT 5
1991 #define TW5864_INDIR_DETECTION_CTL2_MD_FIELD (0x03 << 5)
1992 /*
1993 * Control the level sensitivity of motion detector.
1994 * 0 More sensitive (default)
1995 * : :
1996 * 15 Less sensitive
1997 */
1998 #define TW5864_INDIR_DETECTION_CTL2_MD_LVSENS 0x1f
2000 #define TW5864_INDIR_DETECTION_CTL3(channel) (0x303 + channel * 0x08)
2001 /* Define controls in register TW5864_INDIR_DETECTION_CTL3 */
2002 /*
2003 * Define the threshold of sub-cell number for motion detection.
2004 * 0 Motion is detected if 1 sub-cell has motion (More sensitive) (default)
2005 * 1 Motion is detected if 2 sub-cells have motion
2006 * 2 Motion is detected if 3 sub-cells have motion
2007 * 3 Motion is detected if 4 sub-cells have motion (Less sensitive)
2008 */
2009 #define TW5864_INDIR_DETECTION_CTL3_MD_CELSENS_SHIFT 6
2010 #define TW5864_INDIR_DETECTION_CTL3_MD_CELSENS (0x03 << 6)
2011 /*
2012 * Control the velocity of motion detector.
2013 * Large value is suitable for slow motion detection.
2014 * In MD_DUAL_EN = 1, MD_SPEED should be limited to 0 ~ 31.
2015 * 0 1 field intervals (default)
2016 * 1 2 field intervals
2017 * : :
2018 * 61 62 field intervals
2019 * 62 63 field intervals
2020 * 63 Not supported
2021 */
2022 #define TW5864_INDIR_DETECTION_CTL3_MD_SPEED 0x3f
2024 #define TW5864_INDIR_DETECTION_CTL4(channel) (0x304 + channel * 0x08)
2025 /* Define controls in register TW5864_INDIR_DETECTION_CTL4 */
2026 /*
2027 * Control the spatial sensitivity of motion detector.
2028 * 0 More Sensitive (default)
2029 * : :
2030 * 15 Less Sensitive
2031 */
2032 #define TW5864_INDIR_DETECTION_CTL4_MD_SPSENS_SHIFT 4
2033 #define TW5864_INDIR_DETECTION_CTL4_MD_SPSENS (0x0f << 4)
2034 /*
2035 * Define the threshold of level for blind detection.
2036 * 0 Low threshold (More sensitive) (default)
2037 * : :
2038 * 15 High threshold (Less sensitive)
2039 */
2040 #define TW5864_INDIR_DETECTION_CTL4_BD_LVSENS 0x0f
2042 #define TW5864_INDIR_DETECTION_CTL5(channel) (0x305 + channel * 0x08)
2043 /*
2044 * Define the threshold of temporal sensitivity for night detection.
2045 * 0 Low threshold (More sensitive) (default)
2046 * : :
2047 * 15 High threshold (Less sensitive)
2048 */
2049 #define TW5864_INDIR_DETECTION_CTL5_ND_TMPSENS_SHIFT 4
2050 #define TW5864_INDIR_DETECTION_CTL5_ND_TMPSENS (0x0f << 4)
2051 /*
2052 * Define the threshold of level for night detection.
2053 * 0 Low threshold (More sensitive) (default)
2054 * : :
2055 * 3 High threshold (Less sensitive)
2056 */
2057 #define TW5864_INDIR_DETECTION_CTL5_ND_LVSENS 0x0f
2059 /*
2060 * [11:0] The base address of the motion detection buffer. This address is in
2061 * unit of 64K bytes. The generated DDR address will be {MD_BASE_ADDR,
2062 * 16"h0000}. The default value should be 12"h000
2063 */
2064 #define TW5864_INDIR_MD_BASE_ADDR 0x380
2066 /*
2067 * This controls the channel of the motion detection result shown in register
2068 * 0x3a0 ~ 0x3b7. Before reading back motion result, always set this first.
2069 */
2070 #define TW5864_INDIR_RGR_MOTION_SEL 0x382
2072 /* [15:0] MD strobe has been performed at channel n (read only) */
2073 #define TW5864_INDIR_MD_STRB 0x386
2074 /* NO_VIDEO Detected from channel n (read only) */
2075 #define TW5864_INDIR_NOVID_DET 0x388
2076 /* Motion Detected from channel n (read only) */
2077 #define TW5864_INDIR_MD_DET 0x38a
2078 /* Blind Detected from channel n (read only) */
2079 #define TW5864_INDIR_BD_DET 0x38c
2080 /* Night Detected from channel n (read only) */
2081 #define TW5864_INDIR_ND_DET 0x38e
2083 /* 192 bit motion flag of the channel specified by RGR_MOTION_SEL in 0x382 */
2084 #define TW5864_INDIR_MOTION_FLAG 0x3a0
2085 #define TW5864_INDIR_MOTION_FLAG_BYTE_COUNT 24
2087 /*
2088 * [9:0] The motion cell count of a specific channel selected by 0x382. This is
2089 * for DI purpose
2090 */
2091 #define TW5864_INDIR_MD_DI_CNT 0x3b8
2092 /* The motion detection cell sensitivity for DI purpose */
2093 #define TW5864_INDIR_MD_DI_CELLSENS 0x3ba
2094 /* The motion detection threshold level for DI purpose */
2095 #define TW5864_INDIR_MD_DI_LVSENS 0x3bb
2097 /* 192 bit motion mask of the channel specified by MASK_CH_SEL in 0x3fe */
2098 #define TW5864_INDIR_MOTION_MASK 0x3e0
2099 #define TW5864_INDIR_MOTION_MASK_BYTE_COUNT 24
2101 /* [4:0] The channel selection to access masks in 0x3e0 ~ 0x3f7 */
2102 #define TW5864_INDIR_MASK_CH_SEL 0x3fe
2104 /* Clock PLL / Analog IP Control */
2105 /* Some registers skipped */
2107 #define TW5864_INDIR_DDRA_DLL_DQS_SEL0 0xee6
2108 #define TW5864_INDIR_DDRA_DLL_DQS_SEL1 0xee7
2109 #define TW5864_INDIR_DDRA_DLL_CLK90_SEL 0xee8
2110 #define TW5864_INDIR_DDRA_DLL_TEST_SEL_AND_TAP_S 0xee9
2112 #define TW5864_INDIR_DDRB_DLL_DQS_SEL0 0xeeb
2113 #define TW5864_INDIR_DDRB_DLL_DQS_SEL1 0xeec
2114 #define TW5864_INDIR_DDRB_DLL_CLK90_SEL 0xeed
2115 #define TW5864_INDIR_DDRB_DLL_TEST_SEL_AND_TAP_S 0xeee
2117 #define TW5864_INDIR_RESET 0xef0
2118 #define TW5864_INDIR_RESET_VD BIT(7)
2119 #define TW5864_INDIR_RESET_DLL BIT(6)
2120 #define TW5864_INDIR_RESET_MUX_CORE BIT(5)
2122 #define TW5864_INDIR_PV_VD_CK_POL 0xefd
2123 #define TW5864_INDIR_PV_VD_CK_POL_PV(channel) BIT(channel)
2124 #define TW5864_INDIR_PV_VD_CK_POL_VD(channel) BIT(channel + 4)
2126 #define TW5864_INDIR_CLK0_SEL 0xefe
2127 #define TW5864_INDIR_CLK0_SEL_VD_SHIFT 0
2128 #define TW5864_INDIR_CLK0_SEL_VD_MASK 0x3
2129 #define TW5864_INDIR_CLK0_SEL_PV_SHIFT 2
2130 #define TW5864_INDIR_CLK0_SEL_PV_MASK (0x3 << 2)
2131 #define TW5864_INDIR_CLK0_SEL_PV2_SHIFT 4
2132 #define TW5864_INDIR_CLK0_SEL_PV2_MASK (0x3 << 4)