drivers/media/platform/atmel/atmel-isc-regs.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 #ifndef __ATMEL_ISC_REGS_H
   3 #define __ATMEL_ISC_REGS_H
   4
   5 #include <linux/bitops.h>
   6
   7 /* ISC Control Enable Register 0 */
   8 #define ISC_CTRLEN      0x00000000
   9
  10 /* ISC Control Disable Register 0 */
  11 #define ISC_CTRLDIS     0x00000004
  12
  13 /* ISC Control Status Register 0 */
  14 #define ISC_CTRLSR      0x00000008
  15
  16 #define ISC_CTRL_CAPTURE        BIT(0)
  17 #define ISC_CTRL_UPPRO          BIT(1)
  18 #define ISC_CTRL_HISREQ         BIT(2)
  19 #define ISC_CTRL_HISCLR         BIT(3)
  20
  21 /* ISC Parallel Front End Configuration 0 Register */
  22 #define ISC_PFE_CFG0    0x0000000c
  23
  24 #define ISC_PFE_CFG0_HPOL_LOW   BIT(0)
  25 #define ISC_PFE_CFG0_VPOL_LOW   BIT(1)
  26 #define ISC_PFE_CFG0_PPOL_LOW   BIT(2)
  27 #define ISC_PFE_CFG0_CCIR656    BIT(9)
  28 #define ISC_PFE_CFG0_CCIR_CRC   BIT(10)
  29
  30 #define ISC_PFE_CFG0_MODE_PROGRESSIVE   (0x0 << 4)
  31 #define ISC_PFE_CFG0_MODE_MASK          GENMASK(6, 4)
  32
  33 #define ISC_PFE_CFG0_BPS_EIGHT  (0x4 << 28)
  34 #define ISC_PFG_CFG0_BPS_NINE   (0x3 << 28)
  35 #define ISC_PFG_CFG0_BPS_TEN    (0x2 << 28)
  36 #define ISC_PFG_CFG0_BPS_ELEVEN (0x1 << 28)
  37 #define ISC_PFG_CFG0_BPS_TWELVE (0x0 << 28)
  38 #define ISC_PFE_CFG0_BPS_MASK   GENMASK(30, 28)
  39
  40 #define ISC_PFE_CFG0_COLEN      BIT(12)
  41 #define ISC_PFE_CFG0_ROWEN      BIT(13)
  42
  43 /* ISC Parallel Front End Configuration 1 Register */
  44 #define ISC_PFE_CFG1    0x00000010
  45
  46 #define ISC_PFE_CFG1_COLMIN(v)          ((v))
  47 #define ISC_PFE_CFG1_COLMIN_MASK        GENMASK(15, 0)
  48 #define ISC_PFE_CFG1_COLMAX(v)          ((v) << 16)
  49 #define ISC_PFE_CFG1_COLMAX_MASK        GENMASK(31, 16)
  50
  51 /* ISC Parallel Front End Configuration 2 Register */
  52 #define ISC_PFE_CFG2    0x00000014
  53
  54 #define ISC_PFE_CFG2_ROWMIN(v)          ((v))
  55 #define ISC_PFE_CFG2_ROWMIN_MASK        GENMASK(15, 0)
  56 #define ISC_PFE_CFG2_ROWMAX(v)          ((v) << 16)
  57 #define ISC_PFE_CFG2_ROWMAX_MASK        GENMASK(31, 16)
  58
  59 /* ISC Clock Enable Register */
  60 #define ISC_CLKEN               0x00000018
  61
  62 /* ISC Clock Disable Register */
  63 #define ISC_CLKDIS              0x0000001c
  64
  65 /* ISC Clock Status Register */
  66 #define ISC_CLKSR               0x00000020
  67 #define ISC_CLKSR_SIP           BIT(31)
  68
  69 #define ISC_CLK(n)              BIT(n)
  70
  71 /* ISC Clock Configuration Register */
  72 #define ISC_CLKCFG              0x00000024
  73 #define ISC_CLKCFG_DIV_SHIFT(n) ((n)*16)
  74 #define ISC_CLKCFG_DIV_MASK(n)  GENMASK(((n)*16 + 7), (n)*16)
  75 #define ISC_CLKCFG_SEL_SHIFT(n) ((n)*16 + 8)
  76 #define ISC_CLKCFG_SEL_MASK(n)  GENMASK(((n)*17 + 8), ((n)*16 + 8))
  77
  78 /* ISC Interrupt Enable Register */
  79 #define ISC_INTEN       0x00000028
  80
  81 /* ISC Interrupt Disable Register */
  82 #define ISC_INTDIS      0x0000002c
  83
  84 /* ISC Interrupt Mask Register */
  85 #define ISC_INTMASK     0x00000030
  86
  87 /* ISC Interrupt Status Register */
  88 #define ISC_INTSR       0x00000034
  89
  90 #define ISC_INT_DDONE           BIT(8)
  91 #define ISC_INT_HISDONE         BIT(12)
  92
  93 /* ISC White Balance Control Register */
  94 #define ISC_WB_CTRL     0x00000058
  95
  96 /* ISC White Balance Configuration Register */
  97 #define ISC_WB_CFG      0x0000005c
  98
  99 /* ISC White Balance Offset for R, GR Register */
 100 #define ISC_WB_O_RGR    0x00000060
 101
 102 /* ISC White Balance Offset for B, GB Register */
 103 #define ISC_WB_O_BGB    0x00000064
 104
 105 /* ISC White Balance Gain for R, GR Register */
 106 #define ISC_WB_G_RGR    0x00000068
 107
 108 /* ISC White Balance Gain for B, GB Register */
 109 #define ISC_WB_G_BGB    0x0000006c
 110
 111 #define ISC_WB_O_ZERO_VAL       (1 << 13)
 112
 113 /* ISC Color Filter Array Control Register */
 114 #define ISC_CFA_CTRL    0x00000070
 115
 116 /* ISC Color Filter Array Configuration Register */
 117 #define ISC_CFA_CFG     0x00000074
 118 #define ISC_CFA_CFG_EITPOL      BIT(4)
 119
 120 #define ISC_BAY_CFG_GRGR        0x0
 121 #define ISC_BAY_CFG_RGRG        0x1
 122 #define ISC_BAY_CFG_GBGB        0x2
 123 #define ISC_BAY_CFG_BGBG        0x3
 124
 125 /* ISC Color Correction Control Register */
 126 #define ISC_CC_CTRL     0x00000078
 127
 128 /* ISC Color Correction RR RG Register */
 129 #define ISC_CC_RR_RG    0x0000007c
 130
 131 /* ISC Color Correction RB OR Register */
 132 #define ISC_CC_RB_OR    0x00000080
 133
 134 /* ISC Color Correction GR GG Register */
 135 #define ISC_CC_GR_GG    0x00000084
 136
 137 /* ISC Color Correction GB OG Register */
 138 #define ISC_CC_GB_OG    0x00000088
 139
 140 /* ISC Color Correction BR BG Register */
 141 #define ISC_CC_BR_BG    0x0000008c
 142
 143 /* ISC Color Correction BB OB Register */
 144 #define ISC_CC_BB_OB    0x00000090
 145
 146 /* ISC Gamma Correction Control Register */
 147 #define ISC_GAM_CTRL    0x00000094
 148
 149 /* ISC_Gamma Correction Blue Entry Register */
 150 #define ISC_GAM_BENTRY  0x00000098
 151
 152 /* ISC_Gamma Correction Green Entry Register */
 153 #define ISC_GAM_GENTRY  0x00000198
 154
 155 /* ISC_Gamma Correction Green Entry Register */
 156 #define ISC_GAM_RENTRY  0x00000298
 157
 158 /* Color Space Conversion Control Register */
 159 #define ISC_CSC_CTRL    0x00000398
 160
 161 /* Color Space Conversion YR YG Register */
 162 #define ISC_CSC_YR_YG   0x0000039c
 163
 164 /* Color Space Conversion YB OY Register */
 165 #define ISC_CSC_YB_OY   0x000003a0
 166
 167 /* Color Space Conversion CBR CBG Register */
 168 #define ISC_CSC_CBR_CBG 0x000003a4
 169
 170 /* Color Space Conversion CBB OCB Register */
 171 #define ISC_CSC_CBB_OCB 0x000003a8
 172
 173 /* Color Space Conversion CRR CRG Register */
 174 #define ISC_CSC_CRR_CRG 0x000003ac
 175
 176 /* Color Space Conversion CRB OCR Register */
 177 #define ISC_CSC_CRB_OCR 0x000003b0
 178
 179 /* Contrast And Brightness Control Register */
 180 #define ISC_CBC_CTRL    0x000003b4
 181
 182 /* Contrast And Brightness Configuration Register */
 183 #define ISC_CBC_CFG     0x000003b8
 184
 185 /* Brightness Register */
 186 #define ISC_CBC_BRIGHT  0x000003bc
 187 #define ISC_CBC_BRIGHT_MASK     GENMASK(10, 0)
 188
 189 /* Contrast Register */
 190 #define ISC_CBC_CONTRAST        0x000003c0
 191 #define ISC_CBC_CONTRAST_MASK   GENMASK(11, 0)
 192
 193 /* Subsampling 4:4:4 to 4:2:2 Control Register */
 194 #define ISC_SUB422_CTRL 0x000003c4
 195
 196 /* Subsampling 4:2:2 to 4:2:0 Control Register */
 197 #define ISC_SUB420_CTRL 0x000003cc
 198
 199 /* Rounding, Limiting and Packing Configuration Register */
 200 #define ISC_RLP_CFG     0x000003d0
 201
 202 #define ISC_RLP_CFG_MODE_DAT8           0x0
 203 #define ISC_RLP_CFG_MODE_DAT9           0x1
 204 #define ISC_RLP_CFG_MODE_DAT10          0x2
 205 #define ISC_RLP_CFG_MODE_DAT11          0x3
 206 #define ISC_RLP_CFG_MODE_DAT12          0x4
 207 #define ISC_RLP_CFG_MODE_DATY8          0x5
 208 #define ISC_RLP_CFG_MODE_DATY10         0x6
 209 #define ISC_RLP_CFG_MODE_ARGB444        0x7
 210 #define ISC_RLP_CFG_MODE_ARGB555        0x8
 211 #define ISC_RLP_CFG_MODE_RGB565         0x9
 212 #define ISC_RLP_CFG_MODE_ARGB32         0xa
 213 #define ISC_RLP_CFG_MODE_YYCC           0xb
 214 #define ISC_RLP_CFG_MODE_YYCC_LIMITED   0xc
 215 #define ISC_RLP_CFG_MODE_MASK           GENMASK(3, 0)
 216
 217 /* Histogram Control Register */
 218 #define ISC_HIS_CTRL    0x000003d4
 219
 220 #define ISC_HIS_CTRL_EN                 BIT(0)
 221 #define ISC_HIS_CTRL_DIS                0x0
 222
 223 /* Histogram Configuration Register */
 224 #define ISC_HIS_CFG     0x000003d8
 225
 226 #define ISC_HIS_CFG_MODE_GR             0x0
 227 #define ISC_HIS_CFG_MODE_R              0x1
 228 #define ISC_HIS_CFG_MODE_GB             0x2
 229 #define ISC_HIS_CFG_MODE_B              0x3
 230 #define ISC_HIS_CFG_MODE_Y              0x4
 231 #define ISC_HIS_CFG_MODE_RAW            0x5
 232 #define ISC_HIS_CFG_MODE_YCCIR656       0x6
 233
 234 #define ISC_HIS_CFG_BAYSEL_SHIFT        4
 235
 236 #define ISC_HIS_CFG_RAR                 BIT(8)
 237
 238 /* DMA Configuration Register */
 239 #define ISC_DCFG        0x000003e0
 240 #define ISC_DCFG_IMODE_PACKED8          0x0
 241 #define ISC_DCFG_IMODE_PACKED16         0x1
 242 #define ISC_DCFG_IMODE_PACKED32         0x2
 243 #define ISC_DCFG_IMODE_YC422SP          0x3
 244 #define ISC_DCFG_IMODE_YC422P           0x4
 245 #define ISC_DCFG_IMODE_YC420SP          0x5
 246 #define ISC_DCFG_IMODE_YC420P           0x6
 247 #define ISC_DCFG_IMODE_MASK             GENMASK(2, 0)
 248
 249 #define ISC_DCFG_YMBSIZE_SINGLE         (0x0 << 4)
 250 #define ISC_DCFG_YMBSIZE_BEATS4         (0x1 << 4)
 251 #define ISC_DCFG_YMBSIZE_BEATS8         (0x2 << 4)
 252 #define ISC_DCFG_YMBSIZE_BEATS16        (0x3 << 4)
 253 #define ISC_DCFG_YMBSIZE_MASK           GENMASK(5, 4)
 254
 255 #define ISC_DCFG_CMBSIZE_SINGLE         (0x0 << 8)
 256 #define ISC_DCFG_CMBSIZE_BEATS4         (0x1 << 8)
 257 #define ISC_DCFG_CMBSIZE_BEATS8         (0x2 << 8)
 258 #define ISC_DCFG_CMBSIZE_BEATS16        (0x3 << 8)
 259 #define ISC_DCFG_CMBSIZE_MASK           GENMASK(9, 8)
 260
 261 /* DMA Control Register */
 262 #define ISC_DCTRL       0x000003e4
 263
 264 #define ISC_DCTRL_DVIEW_PACKED          (0x0 << 1)
 265 #define ISC_DCTRL_DVIEW_SEMIPLANAR      (0x1 << 1)
 266 #define ISC_DCTRL_DVIEW_PLANAR          (0x2 << 1)
 267 #define ISC_DCTRL_DVIEW_MASK            GENMASK(2, 1)
 268
 269 #define ISC_DCTRL_IE_IS                 (0x0 << 4)
 270
 271 /* DMA Descriptor Address Register */
 272 #define ISC_DNDA        0x000003e8
 273
 274 /* DMA Address 0 Register */
 275 #define ISC_DAD0        0x000003ec
 276
 277 /* DMA Address 1 Register */
 278 #define ISC_DAD1        0x000003f4
 279
 280 /* DMA Address 2 Register */
 281 #define ISC_DAD2        0x000003fc
 282
 283 /* Histogram Entry */
 284 #define ISC_HIS_ENTRY   0x00000410
 285
 286 #endif