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treewide: remove redundant IS_ERR() before error code check
[linux/fpc-iii.git] / drivers / media / rc / winbond-cir.c
blob630e376d3688618b296b7440f55cfd952b76e521
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * winbond-cir.c - Driver for the Consumer IR functionality of Winbond
4 * SuperI/O chips.
5 *
6 * Currently supports the Winbond WPCD376i chip (PNP id WEC1022), but
7 * could probably support others (Winbond WEC102X, NatSemi, etc)
8 * with minor modifications.
9 *
10 * Original Author: David Härdeman <david@hardeman.nu>
11 * Copyright (C) 2012 Sean Young <sean@mess.org>
12 * Copyright (C) 2009 - 2011 David Härdeman <david@hardeman.nu>
13 *
14 * Dedicated to my daughter Matilda, without whose loving attention this
15 * driver would have been finished in half the time and with a fraction
16 * of the bugs.
17 *
18 * Written using:
19 * o Winbond WPCD376I datasheet helpfully provided by Jesse Barnes at Intel
20 * o NatSemi PC87338/PC97338 datasheet (for the serial port stuff)
21 * o DSDT dumps
22 *
23 * Supported features:
24 * o IR Receive
25 * o IR Transmit
26 * o Wake-On-CIR functionality
27 * o Carrier detection
28 */
29
30 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31
32 #include <linux/module.h>
33 #include <linux/pnp.h>
34 #include <linux/interrupt.h>
35 #include <linux/timer.h>
36 #include <linux/leds.h>
37 #include <linux/spinlock.h>
38 #include <linux/pci_ids.h>
39 #include <linux/io.h>
40 #include <linux/bitrev.h>
41 #include <linux/slab.h>
42 #include <linux/wait.h>
43 #include <linux/sched.h>
44 #include <media/rc-core.h>
45
46 #define DRVNAME "winbond-cir"
47
48 /* CEIR Wake-Up Registers, relative to data->wbase */
49 #define WBCIR_REG_WCEIR_CTL 0x03 /* CEIR Receiver Control */
50 #define WBCIR_REG_WCEIR_STS 0x04 /* CEIR Receiver Status */
51 #define WBCIR_REG_WCEIR_EV_EN 0x05 /* CEIR Receiver Event Enable */
52 #define WBCIR_REG_WCEIR_CNTL 0x06 /* CEIR Receiver Counter Low */
53 #define WBCIR_REG_WCEIR_CNTH 0x07 /* CEIR Receiver Counter High */
54 #define WBCIR_REG_WCEIR_INDEX 0x08 /* CEIR Receiver Index */
55 #define WBCIR_REG_WCEIR_DATA 0x09 /* CEIR Receiver Data */
56 #define WBCIR_REG_WCEIR_CSL 0x0A /* CEIR Re. Compare Strlen */
57 #define WBCIR_REG_WCEIR_CFG1 0x0B /* CEIR Re. Configuration 1 */
58 #define WBCIR_REG_WCEIR_CFG2 0x0C /* CEIR Re. Configuration 2 */
59
60 /* CEIR Enhanced Functionality Registers, relative to data->ebase */
61 #define WBCIR_REG_ECEIR_CTS 0x00 /* Enhanced IR Control Status */
62 #define WBCIR_REG_ECEIR_CCTL 0x01 /* Infrared Counter Control */
63 #define WBCIR_REG_ECEIR_CNT_LO 0x02 /* Infrared Counter LSB */
64 #define WBCIR_REG_ECEIR_CNT_HI 0x03 /* Infrared Counter MSB */
65 #define WBCIR_REG_ECEIR_IREM 0x04 /* Infrared Emitter Status */
66
67 /* SP3 Banked Registers, relative to data->sbase */
68 #define WBCIR_REG_SP3_BSR 0x03 /* Bank Select, all banks */
69 /* Bank 0 */
70 #define WBCIR_REG_SP3_RXDATA 0x00 /* FIFO RX data (r) */
71 #define WBCIR_REG_SP3_TXDATA 0x00 /* FIFO TX data (w) */
72 #define WBCIR_REG_SP3_IER 0x01 /* Interrupt Enable */
73 #define WBCIR_REG_SP3_EIR 0x02 /* Event Identification (r) */
74 #define WBCIR_REG_SP3_FCR 0x02 /* FIFO Control (w) */
75 #define WBCIR_REG_SP3_MCR 0x04 /* Mode Control */
76 #define WBCIR_REG_SP3_LSR 0x05 /* Link Status */
77 #define WBCIR_REG_SP3_MSR 0x06 /* Modem Status */
78 #define WBCIR_REG_SP3_ASCR 0x07 /* Aux Status and Control */
79 /* Bank 2 */
80 #define WBCIR_REG_SP3_BGDL 0x00 /* Baud Divisor LSB */
81 #define WBCIR_REG_SP3_BGDH 0x01 /* Baud Divisor MSB */
82 #define WBCIR_REG_SP3_EXCR1 0x02 /* Extended Control 1 */
83 #define WBCIR_REG_SP3_EXCR2 0x04 /* Extended Control 2 */
84 #define WBCIR_REG_SP3_TXFLV 0x06 /* TX FIFO Level */
85 #define WBCIR_REG_SP3_RXFLV 0x07 /* RX FIFO Level */
86 /* Bank 3 */
87 #define WBCIR_REG_SP3_MRID 0x00 /* Module Identification */
88 #define WBCIR_REG_SP3_SH_LCR 0x01 /* LCR Shadow */
89 #define WBCIR_REG_SP3_SH_FCR 0x02 /* FCR Shadow */
90 /* Bank 4 */
91 #define WBCIR_REG_SP3_IRCR1 0x02 /* Infrared Control 1 */
92 /* Bank 5 */
93 #define WBCIR_REG_SP3_IRCR2 0x04 /* Infrared Control 2 */
94 /* Bank 6 */
95 #define WBCIR_REG_SP3_IRCR3 0x00 /* Infrared Control 3 */
96 #define WBCIR_REG_SP3_SIR_PW 0x02 /* SIR Pulse Width */
97 /* Bank 7 */
98 #define WBCIR_REG_SP3_IRRXDC 0x00 /* IR RX Demod Control */
99 #define WBCIR_REG_SP3_IRTXMC 0x01 /* IR TX Mod Control */
100 #define WBCIR_REG_SP3_RCCFG 0x02 /* CEIR Config */
101 #define WBCIR_REG_SP3_IRCFG1 0x04 /* Infrared Config 1 */
102 #define WBCIR_REG_SP3_IRCFG4 0x07 /* Infrared Config 4 */
103
104 /*
105 * Magic values follow
106 */
107
108 /* No interrupts for WBCIR_REG_SP3_IER and WBCIR_REG_SP3_EIR */
109 #define WBCIR_IRQ_NONE 0x00
110 /* RX data bit for WBCIR_REG_SP3_IER and WBCIR_REG_SP3_EIR */
111 #define WBCIR_IRQ_RX 0x01
112 /* TX data low bit for WBCIR_REG_SP3_IER and WBCIR_REG_SP3_EIR */
113 #define WBCIR_IRQ_TX_LOW 0x02
114 /* Over/Under-flow bit for WBCIR_REG_SP3_IER and WBCIR_REG_SP3_EIR */
115 #define WBCIR_IRQ_ERR 0x04
116 /* TX data empty bit for WBCEIR_REG_SP3_IER and WBCIR_REG_SP3_EIR */
117 #define WBCIR_IRQ_TX_EMPTY 0x20
118 /* Led enable/disable bit for WBCIR_REG_ECEIR_CTS */
119 #define WBCIR_LED_ENABLE 0x80
120 /* RX data available bit for WBCIR_REG_SP3_LSR */
121 #define WBCIR_RX_AVAIL 0x01
122 /* RX data overrun error bit for WBCIR_REG_SP3_LSR */
123 #define WBCIR_RX_OVERRUN 0x02
124 /* TX End-Of-Transmission bit for WBCIR_REG_SP3_ASCR */
125 #define WBCIR_TX_EOT 0x04
126 /* RX disable bit for WBCIR_REG_SP3_ASCR */
127 #define WBCIR_RX_DISABLE 0x20
128 /* TX data underrun error bit for WBCIR_REG_SP3_ASCR */
129 #define WBCIR_TX_UNDERRUN 0x40
130 /* Extended mode enable bit for WBCIR_REG_SP3_EXCR1 */
131 #define WBCIR_EXT_ENABLE 0x01
132 /* Select compare register in WBCIR_REG_WCEIR_INDEX (bits 5 & 6) */
133 #define WBCIR_REGSEL_COMPARE 0x10
134 /* Select mask register in WBCIR_REG_WCEIR_INDEX (bits 5 & 6) */
135 #define WBCIR_REGSEL_MASK 0x20
136 /* Starting address of selected register in WBCIR_REG_WCEIR_INDEX */
137 #define WBCIR_REG_ADDR0 0x00
138 /* Enable carrier counter */
139 #define WBCIR_CNTR_EN 0x01
140 /* Reset carrier counter */
141 #define WBCIR_CNTR_R 0x02
142 /* Invert TX */
143 #define WBCIR_IRTX_INV 0x04
144 /* Receiver oversampling */
145 #define WBCIR_RX_T_OV 0x40
146
147 /* Valid banks for the SP3 UART */
148 enum wbcir_bank {
149 WBCIR_BANK_0 = 0x00,
150 WBCIR_BANK_1 = 0x80,
151 WBCIR_BANK_2 = 0xE0,
152 WBCIR_BANK_3 = 0xE4,
153 WBCIR_BANK_4 = 0xE8,
154 WBCIR_BANK_5 = 0xEC,
155 WBCIR_BANK_6 = 0xF0,
156 WBCIR_BANK_7 = 0xF4,
157 };
158
159 /* Supported power-on IR Protocols */
160 enum wbcir_protocol {
161 IR_PROTOCOL_RC5 = 0x0,
162 IR_PROTOCOL_NEC = 0x1,
163 IR_PROTOCOL_RC6 = 0x2,
164 };
165
166 /* Possible states for IR reception */
167 enum wbcir_rxstate {
168 WBCIR_RXSTATE_INACTIVE = 0,
169 WBCIR_RXSTATE_ACTIVE,
170 WBCIR_RXSTATE_ERROR
171 };
172
173 /* Possible states for IR transmission */
174 enum wbcir_txstate {
175 WBCIR_TXSTATE_INACTIVE = 0,
176 WBCIR_TXSTATE_ACTIVE,
177 WBCIR_TXSTATE_ERROR
178 };
179
180 /* Misc */
181 #define WBCIR_NAME "Winbond CIR"
182 #define WBCIR_ID_FAMILY 0xF1 /* Family ID for the WPCD376I */
183 #define WBCIR_ID_CHIP 0x04 /* Chip ID for the WPCD376I */
184 #define WAKEUP_IOMEM_LEN 0x10 /* Wake-Up I/O Reg Len */
185 #define EHFUNC_IOMEM_LEN 0x10 /* Enhanced Func I/O Reg Len */
186 #define SP_IOMEM_LEN 0x08 /* Serial Port 3 (IR) Reg Len */
187
188 /* Per-device data */
189 struct wbcir_data {
190 spinlock_t spinlock;
191 struct rc_dev *dev;
192 struct led_classdev led;
193
194 unsigned long wbase; /* Wake-Up Baseaddr */
195 unsigned long ebase; /* Enhanced Func. Baseaddr */
196 unsigned long sbase; /* Serial Port Baseaddr */
197 unsigned int irq; /* Serial Port IRQ */
198 u8 irqmask;
199
200 /* RX state */
201 enum wbcir_rxstate rxstate;
202 int carrier_report_enabled;
203 u32 pulse_duration;
204
205 /* TX state */
206 enum wbcir_txstate txstate;
207 u32 txlen;
208 u32 txoff;
209 u32 *txbuf;
210 u8 txmask;
211 u32 txcarrier;
212 };
213
214 static bool invert; /* default = 0 */
215 module_param(invert, bool, 0444);
216 MODULE_PARM_DESC(invert, "Invert the signal from the IR receiver");
217
218 static bool txandrx; /* default = 0 */
219 module_param(txandrx, bool, 0444);
220 MODULE_PARM_DESC(txandrx, "Allow simultaneous TX and RX");
221
222
223 /*****************************************************************************
224 *
225 * UTILITY FUNCTIONS
226 *
227 *****************************************************************************/
228
229 /* Caller needs to hold wbcir_lock */
230 static void
231 wbcir_set_bits(unsigned long addr, u8 bits, u8 mask)
232 {
233 u8 val;
234
235 val = inb(addr);
236 val = ((val & ~mask) | (bits & mask));
237 outb(val, addr);
238 }
239
240 /* Selects the register bank for the serial port */
241 static inline void
242 wbcir_select_bank(struct wbcir_data *data, enum wbcir_bank bank)
243 {
244 outb(bank, data->sbase + WBCIR_REG_SP3_BSR);
245 }
246
247 static inline void
248 wbcir_set_irqmask(struct wbcir_data *data, u8 irqmask)
249 {
250 if (data->irqmask == irqmask)
251 return;
252
253 wbcir_select_bank(data, WBCIR_BANK_0);
254 outb(irqmask, data->sbase + WBCIR_REG_SP3_IER);
255 data->irqmask = irqmask;
256 }
257
258 static enum led_brightness
259 wbcir_led_brightness_get(struct led_classdev *led_cdev)
260 {
261 struct wbcir_data *data = container_of(led_cdev,
262 struct wbcir_data,
263 led);
264
265 if (inb(data->ebase + WBCIR_REG_ECEIR_CTS) & WBCIR_LED_ENABLE)
266 return LED_FULL;
267 else
268 return LED_OFF;
269 }
270
271 static void
272 wbcir_led_brightness_set(struct led_classdev *led_cdev,
273 enum led_brightness brightness)
274 {
275 struct wbcir_data *data = container_of(led_cdev,
276 struct wbcir_data,
277 led);
278
279 wbcir_set_bits(data->ebase + WBCIR_REG_ECEIR_CTS,
280 brightness == LED_OFF ? 0x00 : WBCIR_LED_ENABLE,
281 WBCIR_LED_ENABLE);
282 }
283
284 /* Manchester encodes bits to RC6 message cells (see wbcir_shutdown) */
285 static u8
286 wbcir_to_rc6cells(u8 val)
287 {
288 u8 coded = 0x00;
289 int i;
290
291 val &= 0x0F;
292 for (i = 0; i < 4; i++) {
293 if (val & 0x01)
294 coded |= 0x02 << (i * 2);
295 else
296 coded |= 0x01 << (i * 2);
297 val >>= 1;
298 }
299
300 return coded;
301 }
302
303 /*****************************************************************************
304 *
305 * INTERRUPT FUNCTIONS
306 *
307 *****************************************************************************/
308
309 static void
310 wbcir_carrier_report(struct wbcir_data *data)
311 {
312 unsigned counter = inb(data->ebase + WBCIR_REG_ECEIR_CNT_LO) |
313 inb(data->ebase + WBCIR_REG_ECEIR_CNT_HI) << 8;
314
315 if (counter > 0 && counter < 0xffff) {
316 struct ir_raw_event ev = {
317 .carrier_report = 1,
318 .carrier = DIV_ROUND_CLOSEST(counter * 1000000u,
319 data->pulse_duration)
320 };
321
322 ir_raw_event_store(data->dev, &ev);
323 }
324
325 /* reset and restart the counter */
326 data->pulse_duration = 0;
327 wbcir_set_bits(data->ebase + WBCIR_REG_ECEIR_CCTL, WBCIR_CNTR_R,
328 WBCIR_CNTR_EN | WBCIR_CNTR_R);
329 wbcir_set_bits(data->ebase + WBCIR_REG_ECEIR_CCTL, WBCIR_CNTR_EN,
330 WBCIR_CNTR_EN | WBCIR_CNTR_R);
331 }
332
333 static void
334 wbcir_idle_rx(struct rc_dev *dev, bool idle)
335 {
336 struct wbcir_data *data = dev->priv;
337
338 if (!idle && data->rxstate == WBCIR_RXSTATE_INACTIVE)
339 data->rxstate = WBCIR_RXSTATE_ACTIVE;
340
341 if (idle && data->rxstate != WBCIR_RXSTATE_INACTIVE) {
342 data->rxstate = WBCIR_RXSTATE_INACTIVE;
343
344 if (data->carrier_report_enabled)
345 wbcir_carrier_report(data);
346
347 /* Tell hardware to go idle by setting RXINACTIVE */
348 outb(WBCIR_RX_DISABLE, data->sbase + WBCIR_REG_SP3_ASCR);
349 }
350 }
351
352 static void
353 wbcir_irq_rx(struct wbcir_data *data, struct pnp_dev *device)
354 {
355 u8 irdata;
356 struct ir_raw_event rawir = {};
357 unsigned duration;
358
359 /* Since RXHDLEV is set, at least 8 bytes are in the FIFO */
360 while (inb(data->sbase + WBCIR_REG_SP3_LSR) & WBCIR_RX_AVAIL) {
361 irdata = inb(data->sbase + WBCIR_REG_SP3_RXDATA);
362 if (data->rxstate == WBCIR_RXSTATE_ERROR)
363 continue;
364
365 duration = ((irdata & 0x7F) + 1) *
366 (data->carrier_report_enabled ? 2 : 10);
367 rawir.pulse = irdata & 0x80 ? false : true;
368 rawir.duration = US_TO_NS(duration);
369
370 if (rawir.pulse)
371 data->pulse_duration += duration;
372
373 ir_raw_event_store_with_filter(data->dev, &rawir);
374 }
375
376 ir_raw_event_handle(data->dev);
377 }
378
379 static void
380 wbcir_irq_tx(struct wbcir_data *data)
381 {
382 unsigned int space;
383 unsigned int used;
384 u8 bytes[16];
385 u8 byte;
386
387 if (!data->txbuf)
388 return;
389
390 switch (data->txstate) {
391 case WBCIR_TXSTATE_INACTIVE:
392 /* TX FIFO empty */
393 space = 16;
394 break;
395 case WBCIR_TXSTATE_ACTIVE:
396 /* TX FIFO low (3 bytes or less) */
397 space = 13;
398 break;
399 case WBCIR_TXSTATE_ERROR:
400 space = 0;
401 break;
402 default:
403 return;
404 }
405
406 /*
407 * TX data is run-length coded in bytes: YXXXXXXX
408 * Y = space (1) or pulse (0)
409 * X = duration, encoded as (X + 1) * 10us (i.e 10 to 1280 us)
410 */
411 for (used = 0; used < space && data->txoff != data->txlen; used++) {
412 if (data->txbuf[data->txoff] == 0) {
413 data->txoff++;
414 continue;
415 }
416 byte = min((u32)0x80, data->txbuf[data->txoff]);
417 data->txbuf[data->txoff] -= byte;
418 byte--;
419 byte |= (data->txoff % 2 ? 0x80 : 0x00); /* pulse/space */
420 bytes[used] = byte;
421 }
422
423 while (data->txoff != data->txlen && data->txbuf[data->txoff] == 0)
424 data->txoff++;
425
426 if (used == 0) {
427 /* Finished */
428 if (data->txstate == WBCIR_TXSTATE_ERROR)
429 /* Clear TX underrun bit */
430 outb(WBCIR_TX_UNDERRUN, data->sbase + WBCIR_REG_SP3_ASCR);
431 wbcir_set_irqmask(data, WBCIR_IRQ_RX | WBCIR_IRQ_ERR);
432 kfree(data->txbuf);
433 data->txbuf = NULL;
434 data->txstate = WBCIR_TXSTATE_INACTIVE;
435 } else if (data->txoff == data->txlen) {
436 /* At the end of transmission, tell the hw before last byte */
437 outsb(data->sbase + WBCIR_REG_SP3_TXDATA, bytes, used - 1);
438 outb(WBCIR_TX_EOT, data->sbase + WBCIR_REG_SP3_ASCR);
439 outb(bytes[used - 1], data->sbase + WBCIR_REG_SP3_TXDATA);
440 wbcir_set_irqmask(data, WBCIR_IRQ_RX | WBCIR_IRQ_ERR |
441 WBCIR_IRQ_TX_EMPTY);
442 } else {
443 /* More data to follow... */
444 outsb(data->sbase + WBCIR_REG_SP3_RXDATA, bytes, used);
445 if (data->txstate == WBCIR_TXSTATE_INACTIVE) {
446 wbcir_set_irqmask(data, WBCIR_IRQ_RX | WBCIR_IRQ_ERR |
447 WBCIR_IRQ_TX_LOW);
448 data->txstate = WBCIR_TXSTATE_ACTIVE;
449 }
450 }
451 }
452
453 static irqreturn_t
454 wbcir_irq_handler(int irqno, void *cookie)
455 {
456 struct pnp_dev *device = cookie;
457 struct wbcir_data *data = pnp_get_drvdata(device);
458 unsigned long flags;
459 u8 status;
460
461 spin_lock_irqsave(&data->spinlock, flags);
462 wbcir_select_bank(data, WBCIR_BANK_0);
463 status = inb(data->sbase + WBCIR_REG_SP3_EIR);
464 status &= data->irqmask;
465
466 if (!status) {
467 spin_unlock_irqrestore(&data->spinlock, flags);
468 return IRQ_NONE;
469 }
470
471 if (status & WBCIR_IRQ_ERR) {
472 /* RX overflow? (read clears bit) */
473 if (inb(data->sbase + WBCIR_REG_SP3_LSR) & WBCIR_RX_OVERRUN) {
474 data->rxstate = WBCIR_RXSTATE_ERROR;
475 ir_raw_event_reset(data->dev);
476 }
477
478 /* TX underflow? */
479 if (inb(data->sbase + WBCIR_REG_SP3_ASCR) & WBCIR_TX_UNDERRUN)
480 data->txstate = WBCIR_TXSTATE_ERROR;
481 }
482
483 if (status & WBCIR_IRQ_RX)
484 wbcir_irq_rx(data, device);
485
486 if (status & (WBCIR_IRQ_TX_LOW | WBCIR_IRQ_TX_EMPTY))
487 wbcir_irq_tx(data);
488
489 spin_unlock_irqrestore(&data->spinlock, flags);
490 return IRQ_HANDLED;
491 }
492
493 /*****************************************************************************
494 *
495 * RC-CORE INTERFACE FUNCTIONS
496 *
497 *****************************************************************************/
498
499 static int
500 wbcir_set_carrier_report(struct rc_dev *dev, int enable)
501 {
502 struct wbcir_data *data = dev->priv;
503 unsigned long flags;
504
505 spin_lock_irqsave(&data->spinlock, flags);
506
507 if (data->carrier_report_enabled == enable) {
508 spin_unlock_irqrestore(&data->spinlock, flags);
509 return 0;
510 }
511
512 data->pulse_duration = 0;
513 wbcir_set_bits(data->ebase + WBCIR_REG_ECEIR_CCTL, WBCIR_CNTR_R,
514 WBCIR_CNTR_EN | WBCIR_CNTR_R);
515
516 if (enable && data->dev->idle)
517 wbcir_set_bits(data->ebase + WBCIR_REG_ECEIR_CCTL,
518 WBCIR_CNTR_EN, WBCIR_CNTR_EN | WBCIR_CNTR_R);
519
520 /* Set a higher sampling resolution if carrier reports are enabled */
521 wbcir_select_bank(data, WBCIR_BANK_2);
522 data->dev->rx_resolution = US_TO_NS(enable ? 2 : 10);
523 outb(enable ? 0x03 : 0x0f, data->sbase + WBCIR_REG_SP3_BGDL);
524 outb(0x00, data->sbase + WBCIR_REG_SP3_BGDH);
525
526 /* Enable oversampling if carrier reports are enabled */
527 wbcir_select_bank(data, WBCIR_BANK_7);
528 wbcir_set_bits(data->sbase + WBCIR_REG_SP3_RCCFG,
529 enable ? WBCIR_RX_T_OV : 0, WBCIR_RX_T_OV);
530
531 data->carrier_report_enabled = enable;
532 spin_unlock_irqrestore(&data->spinlock, flags);
533
534 return 0;
535 }
536
537 static int
538 wbcir_txcarrier(struct rc_dev *dev, u32 carrier)
539 {
540 struct wbcir_data *data = dev->priv;
541 unsigned long flags;
542 u8 val;
543 u32 freq;
544
545 freq = DIV_ROUND_CLOSEST(carrier, 1000);
546 if (freq < 30 || freq > 60)
547 return -EINVAL;
548
549 switch (freq) {
550 case 58:
551 case 59:
552 case 60:
553 val = freq - 58;
554 freq *= 1000;
555 break;
556 case 57:
557 val = freq - 27;
558 freq = 56900;
559 break;
560 default:
561 val = freq - 27;
562 freq *= 1000;
563 break;
564 }
565
566 spin_lock_irqsave(&data->spinlock, flags);
567 if (data->txstate != WBCIR_TXSTATE_INACTIVE) {
568 spin_unlock_irqrestore(&data->spinlock, flags);
569 return -EBUSY;
570 }
571
572 if (data->txcarrier != freq) {
573 wbcir_select_bank(data, WBCIR_BANK_7);
574 wbcir_set_bits(data->sbase + WBCIR_REG_SP3_IRTXMC, val, 0x1F);
575 data->txcarrier = freq;
576 }
577
578 spin_unlock_irqrestore(&data->spinlock, flags);
579 return 0;
580 }
581
582 static int
583 wbcir_txmask(struct rc_dev *dev, u32 mask)
584 {
585 struct wbcir_data *data = dev->priv;
586 unsigned long flags;
587 u8 val;
588
589 /* return the number of transmitters */
590 if (mask > 15)
591 return 4;
592
593 /* Four outputs, only one output can be enabled at a time */
594 switch (mask) {
595 case 0x1:
596 val = 0x0;
597 break;
598 case 0x2:
599 val = 0x1;
600 break;
601 case 0x4:
602 val = 0x2;
603 break;
604 case 0x8:
605 val = 0x3;
606 break;
607 default:
608 return -EINVAL;
609 }
610
611 spin_lock_irqsave(&data->spinlock, flags);
612 if (data->txstate != WBCIR_TXSTATE_INACTIVE) {
613 spin_unlock_irqrestore(&data->spinlock, flags);
614 return -EBUSY;
615 }
616
617 if (data->txmask != mask) {
618 wbcir_set_bits(data->ebase + WBCIR_REG_ECEIR_CTS, val, 0x0c);
619 data->txmask = mask;
620 }
621
622 spin_unlock_irqrestore(&data->spinlock, flags);
623 return 0;
624 }
625
626 static int
627 wbcir_tx(struct rc_dev *dev, unsigned *b, unsigned count)
628 {
629 struct wbcir_data *data = dev->priv;
630 unsigned *buf;
631 unsigned i;
632 unsigned long flags;
633
634 buf = kmalloc_array(count, sizeof(*b), GFP_KERNEL);
635 if (!buf)
636 return -ENOMEM;
637
638 /* Convert values to multiples of 10us */
639 for (i = 0; i < count; i++)
640 buf[i] = DIV_ROUND_CLOSEST(b[i], 10);
641
642 /* Not sure if this is possible, but better safe than sorry */
643 spin_lock_irqsave(&data->spinlock, flags);
644 if (data->txstate != WBCIR_TXSTATE_INACTIVE) {
645 spin_unlock_irqrestore(&data->spinlock, flags);
646 kfree(buf);
647 return -EBUSY;
648 }
649
650 /* Fill the TX fifo once, the irq handler will do the rest */
651 data->txbuf = buf;
652 data->txlen = count;
653 data->txoff = 0;
654 wbcir_irq_tx(data);
655
656 /* We're done */
657 spin_unlock_irqrestore(&data->spinlock, flags);
658 return count;
659 }
660
661 /*****************************************************************************
662 *
663 * SETUP/INIT/SUSPEND/RESUME FUNCTIONS
664 *
665 *****************************************************************************/
666
667 static void
668 wbcir_shutdown(struct pnp_dev *device)
669 {
670 struct device *dev = &device->dev;
671 struct wbcir_data *data = pnp_get_drvdata(device);
672 struct rc_dev *rc = data->dev;
673 bool do_wake = true;
674 u8 match[11];
675 u8 mask[11];
676 u8 rc6_csl = 0;
677 u8 proto;
678 u32 wake_sc = rc->scancode_wakeup_filter.data;
679 u32 mask_sc = rc->scancode_wakeup_filter.mask;
680 int i;
681
682 memset(match, 0, sizeof(match));
683 memset(mask, 0, sizeof(mask));
684
685 if (!mask_sc || !device_may_wakeup(dev)) {
686 do_wake = false;
687 goto finish;
688 }
689
690 switch (rc->wakeup_protocol) {
691 case RC_PROTO_RC5:
692 /* Mask = 13 bits, ex toggle */
693 mask[0] = (mask_sc & 0x003f);
694 mask[0] |= (mask_sc & 0x0300) >> 2;
695 mask[1] = (mask_sc & 0x1c00) >> 10;
696 if (mask_sc & 0x0040) /* 2nd start bit */
697 match[1] |= 0x10;
698
699 match[0] = (wake_sc & 0x003F); /* 6 command bits */
700 match[0] |= (wake_sc & 0x0300) >> 2; /* 2 address bits */
701 match[1] = (wake_sc & 0x1c00) >> 10; /* 3 address bits */
702 if (!(wake_sc & 0x0040)) /* 2nd start bit */
703 match[1] |= 0x10;
704
705 proto = IR_PROTOCOL_RC5;
706 break;
707
708 case RC_PROTO_NEC:
709 mask[1] = bitrev8(mask_sc);
710 mask[0] = mask[1];
711 mask[3] = bitrev8(mask_sc >> 8);
712 mask[2] = mask[3];
713
714 match[1] = bitrev8(wake_sc);
715 match[0] = ~match[1];
716 match[3] = bitrev8(wake_sc >> 8);
717 match[2] = ~match[3];
718
719 proto = IR_PROTOCOL_NEC;
720 break;
721
722 case RC_PROTO_NECX:
723 mask[1] = bitrev8(mask_sc);
724 mask[0] = mask[1];
725 mask[2] = bitrev8(mask_sc >> 8);
726 mask[3] = bitrev8(mask_sc >> 16);
727
728 match[1] = bitrev8(wake_sc);
729 match[0] = ~match[1];
730 match[2] = bitrev8(wake_sc >> 8);
731 match[3] = bitrev8(wake_sc >> 16);
732
733 proto = IR_PROTOCOL_NEC;
734 break;
735
736 case RC_PROTO_NEC32:
737 mask[0] = bitrev8(mask_sc);
738 mask[1] = bitrev8(mask_sc >> 8);
739 mask[2] = bitrev8(mask_sc >> 16);
740 mask[3] = bitrev8(mask_sc >> 24);
741
742 match[0] = bitrev8(wake_sc);
743 match[1] = bitrev8(wake_sc >> 8);
744 match[2] = bitrev8(wake_sc >> 16);
745 match[3] = bitrev8(wake_sc >> 24);
746
747 proto = IR_PROTOCOL_NEC;
748 break;
749
750 case RC_PROTO_RC6_0:
751 /* Command */
752 match[0] = wbcir_to_rc6cells(wake_sc >> 0);
753 mask[0] = wbcir_to_rc6cells(mask_sc >> 0);
754 match[1] = wbcir_to_rc6cells(wake_sc >> 4);
755 mask[1] = wbcir_to_rc6cells(mask_sc >> 4);
756
757 /* Address */
758 match[2] = wbcir_to_rc6cells(wake_sc >> 8);
759 mask[2] = wbcir_to_rc6cells(mask_sc >> 8);
760 match[3] = wbcir_to_rc6cells(wake_sc >> 12);
761 mask[3] = wbcir_to_rc6cells(mask_sc >> 12);
762
763 /* Header */
764 match[4] = 0x50; /* mode1 = mode0 = 0, ignore toggle */
765 mask[4] = 0xF0;
766 match[5] = 0x09; /* start bit = 1, mode2 = 0 */
767 mask[5] = 0x0F;
768
769 rc6_csl = 44;
770 proto = IR_PROTOCOL_RC6;
771 break;
772
773 case RC_PROTO_RC6_6A_24:
774 case RC_PROTO_RC6_6A_32:
775 case RC_PROTO_RC6_MCE:
776 i = 0;
777
778 /* Command */
779 match[i] = wbcir_to_rc6cells(wake_sc >> 0);
780 mask[i++] = wbcir_to_rc6cells(mask_sc >> 0);
781 match[i] = wbcir_to_rc6cells(wake_sc >> 4);
782 mask[i++] = wbcir_to_rc6cells(mask_sc >> 4);
783
784 /* Address + Toggle */
785 match[i] = wbcir_to_rc6cells(wake_sc >> 8);
786 mask[i++] = wbcir_to_rc6cells(mask_sc >> 8);
787 match[i] = wbcir_to_rc6cells(wake_sc >> 12);
788 mask[i++] = wbcir_to_rc6cells(mask_sc >> 12);
789
790 /* Customer bits 7 - 0 */
791 match[i] = wbcir_to_rc6cells(wake_sc >> 16);
792 mask[i++] = wbcir_to_rc6cells(mask_sc >> 16);
793
794 if (rc->wakeup_protocol == RC_PROTO_RC6_6A_20) {
795 rc6_csl = 52;
796 } else {
797 match[i] = wbcir_to_rc6cells(wake_sc >> 20);
798 mask[i++] = wbcir_to_rc6cells(mask_sc >> 20);
799
800 if (rc->wakeup_protocol == RC_PROTO_RC6_6A_24) {
801 rc6_csl = 60;
802 } else {
803 /* Customer range bit and bits 15 - 8 */
804 match[i] = wbcir_to_rc6cells(wake_sc >> 24);
805 mask[i++] = wbcir_to_rc6cells(mask_sc >> 24);
806 match[i] = wbcir_to_rc6cells(wake_sc >> 28);
807 mask[i++] = wbcir_to_rc6cells(mask_sc >> 28);
808 rc6_csl = 76;
809 }
810 }
811
812 /* Header */
813 match[i] = 0x93; /* mode1 = mode0 = 1, submode = 0 */
814 mask[i++] = 0xFF;
815 match[i] = 0x0A; /* start bit = 1, mode2 = 1 */
816 mask[i++] = 0x0F;
817 proto = IR_PROTOCOL_RC6;
818 break;
819 default:
820 do_wake = false;
821 break;
822 }
823
824 finish:
825 if (do_wake) {
826 /* Set compare and compare mask */
827 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_INDEX,
828 WBCIR_REGSEL_COMPARE | WBCIR_REG_ADDR0,
829 0x3F);
830 outsb(data->wbase + WBCIR_REG_WCEIR_DATA, match, 11);
831 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_INDEX,
832 WBCIR_REGSEL_MASK | WBCIR_REG_ADDR0,
833 0x3F);
834 outsb(data->wbase + WBCIR_REG_WCEIR_DATA, mask, 11);
835
836 /* RC6 Compare String Len */
837 outb(rc6_csl, data->wbase + WBCIR_REG_WCEIR_CSL);
838
839 /* Clear status bits NEC_REP, BUFF, MSG_END, MATCH */
840 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_STS, 0x17, 0x17);
841
842 /* Clear BUFF_EN, Clear END_EN, Set MATCH_EN */
843 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_EV_EN, 0x01, 0x07);
844
845 /* Set CEIR_EN */
846 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_CTL,
847 (proto << 4) | 0x01, 0x31);
848
849 } else {
850 /* Clear BUFF_EN, Clear END_EN, Clear MATCH_EN */
851 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_EV_EN, 0x00, 0x07);
852
853 /* Clear CEIR_EN */
854 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_CTL, 0x00, 0x01);
855 }
856
857 /*
858 * ACPI will set the HW disable bit for SP3 which means that the
859 * output signals are left in an undefined state which may cause
860 * spurious interrupts which we need to ignore until the hardware
861 * is reinitialized.
862 */
863 wbcir_set_irqmask(data, WBCIR_IRQ_NONE);
864 disable_irq(data->irq);
865 }
866
867 /*
868 * Wakeup handling is done on shutdown.
869 */
870 static int
871 wbcir_set_wakeup_filter(struct rc_dev *rc, struct rc_scancode_filter *filter)
872 {
873 return 0;
874 }
875
876 static int
877 wbcir_suspend(struct pnp_dev *device, pm_message_t state)
878 {
879 struct wbcir_data *data = pnp_get_drvdata(device);
880 led_classdev_suspend(&data->led);
881 wbcir_shutdown(device);
882 return 0;
883 }
884
885 static void
886 wbcir_init_hw(struct wbcir_data *data)
887 {
888 /* Disable interrupts */
889 wbcir_set_irqmask(data, WBCIR_IRQ_NONE);
890
891 /* Set RX_INV, Clear CEIR_EN (needed for the led) */
892 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_CTL, invert ? 8 : 0, 0x09);
893
894 /* Clear status bits NEC_REP, BUFF, MSG_END, MATCH */
895 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_STS, 0x17, 0x17);
896
897 /* Clear BUFF_EN, Clear END_EN, Clear MATCH_EN */
898 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_EV_EN, 0x00, 0x07);
899
900 /* Set RC5 cell time to correspond to 36 kHz */
901 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_CFG1, 0x4A, 0x7F);
902
903 /* Set IRTX_INV */
904 if (invert)
905 outb(WBCIR_IRTX_INV, data->ebase + WBCIR_REG_ECEIR_CCTL);
906 else
907 outb(0x00, data->ebase + WBCIR_REG_ECEIR_CCTL);
908
909 /*
910 * Clear IR LED, set SP3 clock to 24Mhz, set TX mask to IRTX1,
911 * set SP3_IRRX_SW to binary 01, helpfully not documented
912 */
913 outb(0x10, data->ebase + WBCIR_REG_ECEIR_CTS);
914 data->txmask = 0x1;
915
916 /* Enable extended mode */
917 wbcir_select_bank(data, WBCIR_BANK_2);
918 outb(WBCIR_EXT_ENABLE, data->sbase + WBCIR_REG_SP3_EXCR1);
919
920 /*
921 * Configure baud generator, IR data will be sampled at
922 * a bitrate of: (24Mhz * prescaler) / (divisor * 16).
923 *
924 * The ECIR registers include a flag to change the
925 * 24Mhz clock freq to 48Mhz.
926 *
927 * It's not documented in the specs, but fifo levels
928 * other than 16 seems to be unsupported.
929 */
930
931 /* prescaler 1.0, tx/rx fifo lvl 16 */
932 outb(0x30, data->sbase + WBCIR_REG_SP3_EXCR2);
933
934 /* Set baud divisor to sample every 10 us */
935 outb(0x0f, data->sbase + WBCIR_REG_SP3_BGDL);
936 outb(0x00, data->sbase + WBCIR_REG_SP3_BGDH);
937
938 /* Set CEIR mode */
939 wbcir_select_bank(data, WBCIR_BANK_0);
940 outb(0xC0, data->sbase + WBCIR_REG_SP3_MCR);
941 inb(data->sbase + WBCIR_REG_SP3_LSR); /* Clear LSR */
942 inb(data->sbase + WBCIR_REG_SP3_MSR); /* Clear MSR */
943
944 /* Disable RX demod, enable run-length enc/dec, set freq span */
945 wbcir_select_bank(data, WBCIR_BANK_7);
946 outb(0x90, data->sbase + WBCIR_REG_SP3_RCCFG);
947
948 /* Disable timer */
949 wbcir_select_bank(data, WBCIR_BANK_4);
950 outb(0x00, data->sbase + WBCIR_REG_SP3_IRCR1);
951
952 /* Disable MSR interrupt, clear AUX_IRX, mask RX during TX? */
953 wbcir_select_bank(data, WBCIR_BANK_5);
954 outb(txandrx ? 0x03 : 0x02, data->sbase + WBCIR_REG_SP3_IRCR2);
955
956 /* Disable CRC */
957 wbcir_select_bank(data, WBCIR_BANK_6);
958 outb(0x20, data->sbase + WBCIR_REG_SP3_IRCR3);
959
960 /* Set RX demodulation freq, not really used */
961 wbcir_select_bank(data, WBCIR_BANK_7);
962 outb(0xF2, data->sbase + WBCIR_REG_SP3_IRRXDC);
963
964 /* Set TX modulation, 36kHz, 7us pulse width */
965 outb(0x69, data->sbase + WBCIR_REG_SP3_IRTXMC);
966 data->txcarrier = 36000;
967
968 /* Set invert and pin direction */
969 if (invert)
970 outb(0x10, data->sbase + WBCIR_REG_SP3_IRCFG4);
971 else
972 outb(0x00, data->sbase + WBCIR_REG_SP3_IRCFG4);
973
974 /* Set FIFO thresholds (RX = 8, TX = 3), reset RX/TX */
975 wbcir_select_bank(data, WBCIR_BANK_0);
976 outb(0x97, data->sbase + WBCIR_REG_SP3_FCR);
977
978 /* Clear AUX status bits */
979 outb(0xE0, data->sbase + WBCIR_REG_SP3_ASCR);
980
981 /* Clear RX state */
982 data->rxstate = WBCIR_RXSTATE_INACTIVE;
983 wbcir_idle_rx(data->dev, true);
984
985 /* Clear TX state */
986 if (data->txstate == WBCIR_TXSTATE_ACTIVE) {
987 kfree(data->txbuf);
988 data->txbuf = NULL;
989 data->txstate = WBCIR_TXSTATE_INACTIVE;
990 }
991
992 /* Enable interrupts */
993 wbcir_set_irqmask(data, WBCIR_IRQ_RX | WBCIR_IRQ_ERR);
994 }
995
996 static int
997 wbcir_resume(struct pnp_dev *device)
998 {
999 struct wbcir_data *data = pnp_get_drvdata(device);
1000
1001 wbcir_init_hw(data);
1002 ir_raw_event_reset(data->dev);
1003 enable_irq(data->irq);
1004 led_classdev_resume(&data->led);
1005
1006 return 0;
1007 }
1008
1009 static int
1010 wbcir_probe(struct pnp_dev *device, const struct pnp_device_id *dev_id)
1011 {
1012 struct device *dev = &device->dev;
1013 struct wbcir_data *data;
1014 int err;
1015
1016 if (!(pnp_port_len(device, 0) == EHFUNC_IOMEM_LEN &&
1017 pnp_port_len(device, 1) == WAKEUP_IOMEM_LEN &&
1018 pnp_port_len(device, 2) == SP_IOMEM_LEN)) {
1019 dev_err(dev, "Invalid resources\n");
1020 return -ENODEV;
1021 }
1022
1023 data = kzalloc(sizeof(*data), GFP_KERNEL);
1024 if (!data) {
1025 err = -ENOMEM;
1026 goto exit;
1027 }
1028
1029 pnp_set_drvdata(device, data);
1030
1031 spin_lock_init(&data->spinlock);
1032 data->ebase = pnp_port_start(device, 0);
1033 data->wbase = pnp_port_start(device, 1);
1034 data->sbase = pnp_port_start(device, 2);
1035 data->irq = pnp_irq(device, 0);
1036
1037 if (data->wbase == 0 || data->ebase == 0 ||
1038 data->sbase == 0 || data->irq == -1) {
1039 err = -ENODEV;
1040 dev_err(dev, "Invalid resources\n");
1041 goto exit_free_data;
1042 }
1043
1044 dev_dbg(&device->dev, "Found device (w: 0x%lX, e: 0x%lX, s: 0x%lX, i: %u)\n",
1045 data->wbase, data->ebase, data->sbase, data->irq);
1046
1047 data->led.name = "cir::activity";
1048 data->led.default_trigger = "rc-feedback";
1049 data->led.brightness_set = wbcir_led_brightness_set;
1050 data->led.brightness_get = wbcir_led_brightness_get;
1051 err = led_classdev_register(&device->dev, &data->led);
1052 if (err)
1053 goto exit_free_data;
1054
1055 data->dev = rc_allocate_device(RC_DRIVER_IR_RAW);
1056 if (!data->dev) {
1057 err = -ENOMEM;
1058 goto exit_unregister_led;
1059 }
1060
1061 data->dev->driver_name = DRVNAME;
1062 data->dev->device_name = WBCIR_NAME;
1063 data->dev->input_phys = "wbcir/cir0";
1064 data->dev->input_id.bustype = BUS_HOST;
1065 data->dev->input_id.vendor = PCI_VENDOR_ID_WINBOND;
1066 data->dev->input_id.product = WBCIR_ID_FAMILY;
1067 data->dev->input_id.version = WBCIR_ID_CHIP;
1068 data->dev->map_name = RC_MAP_RC6_MCE;
1069 data->dev->s_idle = wbcir_idle_rx;
1070 data->dev->s_carrier_report = wbcir_set_carrier_report;
1071 data->dev->s_tx_mask = wbcir_txmask;
1072 data->dev->s_tx_carrier = wbcir_txcarrier;
1073 data->dev->tx_ir = wbcir_tx;
1074 data->dev->priv = data;
1075 data->dev->dev.parent = &device->dev;
1076 data->dev->min_timeout = 1;
1077 data->dev->timeout = IR_DEFAULT_TIMEOUT;
1078 data->dev->max_timeout = 10 * IR_DEFAULT_TIMEOUT;
1079 data->dev->rx_resolution = US_TO_NS(2);
1080 data->dev->allowed_protocols = RC_PROTO_BIT_ALL_IR_DECODER;
1081 data->dev->allowed_wakeup_protocols = RC_PROTO_BIT_NEC |
1082 RC_PROTO_BIT_NECX | RC_PROTO_BIT_NEC32 | RC_PROTO_BIT_RC5 |
1083 RC_PROTO_BIT_RC6_0 | RC_PROTO_BIT_RC6_6A_20 |
1084 RC_PROTO_BIT_RC6_6A_24 | RC_PROTO_BIT_RC6_6A_32 |
1085 RC_PROTO_BIT_RC6_MCE;
1086 data->dev->wakeup_protocol = RC_PROTO_RC6_MCE;
1087 data->dev->scancode_wakeup_filter.data = 0x800f040c;
1088 data->dev->scancode_wakeup_filter.mask = 0xffff7fff;
1089 data->dev->s_wakeup_filter = wbcir_set_wakeup_filter;
1090
1091 err = rc_register_device(data->dev);
1092 if (err)
1093 goto exit_free_rc;
1094
1095 if (!request_region(data->wbase, WAKEUP_IOMEM_LEN, DRVNAME)) {
1096 dev_err(dev, "Region 0x%lx-0x%lx already in use!\n",
1097 data->wbase, data->wbase + WAKEUP_IOMEM_LEN - 1);
1098 err = -EBUSY;
1099 goto exit_unregister_device;
1100 }
1101
1102 if (!request_region(data->ebase, EHFUNC_IOMEM_LEN, DRVNAME)) {
1103 dev_err(dev, "Region 0x%lx-0x%lx already in use!\n",
1104 data->ebase, data->ebase + EHFUNC_IOMEM_LEN - 1);
1105 err = -EBUSY;
1106 goto exit_release_wbase;
1107 }
1108
1109 if (!request_region(data->sbase, SP_IOMEM_LEN, DRVNAME)) {
1110 dev_err(dev, "Region 0x%lx-0x%lx already in use!\n",
1111 data->sbase, data->sbase + SP_IOMEM_LEN - 1);
1112 err = -EBUSY;
1113 goto exit_release_ebase;
1114 }
1115
1116 err = request_irq(data->irq, wbcir_irq_handler,
1117 0, DRVNAME, device);
1118 if (err) {
1119 dev_err(dev, "Failed to claim IRQ %u\n", data->irq);
1120 err = -EBUSY;
1121 goto exit_release_sbase;
1122 }
1123
1124 device_init_wakeup(&device->dev, 1);
1125
1126 wbcir_init_hw(data);
1127
1128 return 0;
1129
1130 exit_release_sbase:
1131 release_region(data->sbase, SP_IOMEM_LEN);
1132 exit_release_ebase:
1133 release_region(data->ebase, EHFUNC_IOMEM_LEN);
1134 exit_release_wbase:
1135 release_region(data->wbase, WAKEUP_IOMEM_LEN);
1136 exit_unregister_device:
1137 rc_unregister_device(data->dev);
1138 data->dev = NULL;
1139 exit_free_rc:
1140 rc_free_device(data->dev);
1141 exit_unregister_led:
1142 led_classdev_unregister(&data->led);
1143 exit_free_data:
1144 kfree(data);
1145 pnp_set_drvdata(device, NULL);
1146 exit:
1147 return err;
1148 }
1149
1150 static void
1151 wbcir_remove(struct pnp_dev *device)
1152 {
1153 struct wbcir_data *data = pnp_get_drvdata(device);
1154
1155 /* Disable interrupts */
1156 wbcir_set_irqmask(data, WBCIR_IRQ_NONE);
1157 free_irq(data->irq, device);
1158
1159 /* Clear status bits NEC_REP, BUFF, MSG_END, MATCH */
1160 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_STS, 0x17, 0x17);
1161
1162 /* Clear CEIR_EN */
1163 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_CTL, 0x00, 0x01);
1164
1165 /* Clear BUFF_EN, END_EN, MATCH_EN */
1166 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_EV_EN, 0x00, 0x07);
1167
1168 rc_unregister_device(data->dev);
1169
1170 led_classdev_unregister(&data->led);
1171
1172 /* This is ok since &data->led isn't actually used */
1173 wbcir_led_brightness_set(&data->led, LED_OFF);
1174
1175 release_region(data->wbase, WAKEUP_IOMEM_LEN);
1176 release_region(data->ebase, EHFUNC_IOMEM_LEN);
1177 release_region(data->sbase, SP_IOMEM_LEN);
1178
1179 kfree(data);
1180
1181 pnp_set_drvdata(device, NULL);
1182 }
1183
1184 static const struct pnp_device_id wbcir_ids[] = {
1185 { "WEC1022", 0 },
1186 { "", 0 }
1187 };
1188 MODULE_DEVICE_TABLE(pnp, wbcir_ids);
1189
1190 static struct pnp_driver wbcir_driver = {
1191 .name = DRVNAME,
1192 .id_table = wbcir_ids,
1193 .probe = wbcir_probe,
1194 .remove = wbcir_remove,
1195 .suspend = wbcir_suspend,
1196 .resume = wbcir_resume,
1197 .shutdown = wbcir_shutdown
1198 };
1199
1200 static int __init
1201 wbcir_init(void)
1202 {
1203 int ret;
1204
1205 ret = pnp_register_driver(&wbcir_driver);
1206 if (ret)
1207 pr_err("Unable to register driver\n");
1208
1209 return ret;
1210 }
1211
1212 static void __exit
1213 wbcir_exit(void)
1214 {
1215 pnp_unregister_driver(&wbcir_driver);
1216 }
1217
1218 module_init(wbcir_init);
1219 module_exit(wbcir_exit);
1220
1221 MODULE_AUTHOR("David Härdeman <david@hardeman.nu>");
1222 MODULE_DESCRIPTION("Winbond SuperI/O Consumer IR Driver");
1223 MODULE_LICENSE("GPL");
Linux with added FPC-III support