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treewide: remove redundant IS_ERR() before error code check
[linux/fpc-iii.git] / drivers / misc / habanalabs / goya / goya_coresight.c
blobc1ee6e2b5dfff495da19e68cba5753adf3c81d72
1 // SPDX-License-Identifier: GPL-2.0
2
3 /*
4 * Copyright 2016-2019 HabanaLabs, Ltd.
5 * All Rights Reserved.
6 */
7
8 #include "goyaP.h"
9 #include "include/goya/goya_coresight.h"
10 #include "include/goya/asic_reg/goya_regs.h"
11 #include "include/goya/asic_reg/goya_masks.h"
12
13 #include <uapi/misc/habanalabs.h>
14
15 #include <linux/coresight.h>
16
17 #define GOYA_PLDM_CORESIGHT_TIMEOUT_USEC (CORESIGHT_TIMEOUT_USEC * 100)
18
19 #define SPMU_SECTION_SIZE DMA_CH_0_CS_SPMU_MAX_OFFSET
20 #define SPMU_EVENT_TYPES_OFFSET 0x400
21 #define SPMU_MAX_COUNTERS 6
22
23 static u64 debug_stm_regs[GOYA_STM_LAST + 1] = {
24 [GOYA_STM_CPU] = mmCPU_STM_BASE,
25 [GOYA_STM_DMA_CH_0_CS] = mmDMA_CH_0_CS_STM_BASE,
26 [GOYA_STM_DMA_CH_1_CS] = mmDMA_CH_1_CS_STM_BASE,
27 [GOYA_STM_DMA_CH_2_CS] = mmDMA_CH_2_CS_STM_BASE,
28 [GOYA_STM_DMA_CH_3_CS] = mmDMA_CH_3_CS_STM_BASE,
29 [GOYA_STM_DMA_CH_4_CS] = mmDMA_CH_4_CS_STM_BASE,
30 [GOYA_STM_DMA_MACRO_CS] = mmDMA_MACRO_CS_STM_BASE,
31 [GOYA_STM_MME1_SBA] = mmMME1_SBA_STM_BASE,
32 [GOYA_STM_MME3_SBB] = mmMME3_SBB_STM_BASE,
33 [GOYA_STM_MME4_WACS2] = mmMME4_WACS2_STM_BASE,
34 [GOYA_STM_MME4_WACS] = mmMME4_WACS_STM_BASE,
35 [GOYA_STM_MMU_CS] = mmMMU_CS_STM_BASE,
36 [GOYA_STM_PCIE] = mmPCIE_STM_BASE,
37 [GOYA_STM_PSOC] = mmPSOC_STM_BASE,
38 [GOYA_STM_TPC0_EML] = mmTPC0_EML_STM_BASE,
39 [GOYA_STM_TPC1_EML] = mmTPC1_EML_STM_BASE,
40 [GOYA_STM_TPC2_EML] = mmTPC2_EML_STM_BASE,
41 [GOYA_STM_TPC3_EML] = mmTPC3_EML_STM_BASE,
42 [GOYA_STM_TPC4_EML] = mmTPC4_EML_STM_BASE,
43 [GOYA_STM_TPC5_EML] = mmTPC5_EML_STM_BASE,
44 [GOYA_STM_TPC6_EML] = mmTPC6_EML_STM_BASE,
45 [GOYA_STM_TPC7_EML] = mmTPC7_EML_STM_BASE
46 };
47
48 static u64 debug_etf_regs[GOYA_ETF_LAST + 1] = {
49 [GOYA_ETF_CPU_0] = mmCPU_ETF_0_BASE,
50 [GOYA_ETF_CPU_1] = mmCPU_ETF_1_BASE,
51 [GOYA_ETF_CPU_TRACE] = mmCPU_ETF_TRACE_BASE,
52 [GOYA_ETF_DMA_CH_0_CS] = mmDMA_CH_0_CS_ETF_BASE,
53 [GOYA_ETF_DMA_CH_1_CS] = mmDMA_CH_1_CS_ETF_BASE,
54 [GOYA_ETF_DMA_CH_2_CS] = mmDMA_CH_2_CS_ETF_BASE,
55 [GOYA_ETF_DMA_CH_3_CS] = mmDMA_CH_3_CS_ETF_BASE,
56 [GOYA_ETF_DMA_CH_4_CS] = mmDMA_CH_4_CS_ETF_BASE,
57 [GOYA_ETF_DMA_MACRO_CS] = mmDMA_MACRO_CS_ETF_BASE,
58 [GOYA_ETF_MME1_SBA] = mmMME1_SBA_ETF_BASE,
59 [GOYA_ETF_MME3_SBB] = mmMME3_SBB_ETF_BASE,
60 [GOYA_ETF_MME4_WACS2] = mmMME4_WACS2_ETF_BASE,
61 [GOYA_ETF_MME4_WACS] = mmMME4_WACS_ETF_BASE,
62 [GOYA_ETF_MMU_CS] = mmMMU_CS_ETF_BASE,
63 [GOYA_ETF_PCIE] = mmPCIE_ETF_BASE,
64 [GOYA_ETF_PSOC] = mmPSOC_ETF_BASE,
65 [GOYA_ETF_TPC0_EML] = mmTPC0_EML_ETF_BASE,
66 [GOYA_ETF_TPC1_EML] = mmTPC1_EML_ETF_BASE,
67 [GOYA_ETF_TPC2_EML] = mmTPC2_EML_ETF_BASE,
68 [GOYA_ETF_TPC3_EML] = mmTPC3_EML_ETF_BASE,
69 [GOYA_ETF_TPC4_EML] = mmTPC4_EML_ETF_BASE,
70 [GOYA_ETF_TPC5_EML] = mmTPC5_EML_ETF_BASE,
71 [GOYA_ETF_TPC6_EML] = mmTPC6_EML_ETF_BASE,
72 [GOYA_ETF_TPC7_EML] = mmTPC7_EML_ETF_BASE
73 };
74
75 static u64 debug_funnel_regs[GOYA_FUNNEL_LAST + 1] = {
76 [GOYA_FUNNEL_CPU] = mmCPU_FUNNEL_BASE,
77 [GOYA_FUNNEL_DMA_CH_6_1] = mmDMA_CH_FUNNEL_6_1_BASE,
78 [GOYA_FUNNEL_DMA_MACRO_3_1] = mmDMA_MACRO_FUNNEL_3_1_BASE,
79 [GOYA_FUNNEL_MME0_RTR] = mmMME0_RTR_FUNNEL_BASE,
80 [GOYA_FUNNEL_MME1_RTR] = mmMME1_RTR_FUNNEL_BASE,
81 [GOYA_FUNNEL_MME2_RTR] = mmMME2_RTR_FUNNEL_BASE,
82 [GOYA_FUNNEL_MME3_RTR] = mmMME3_RTR_FUNNEL_BASE,
83 [GOYA_FUNNEL_MME4_RTR] = mmMME4_RTR_FUNNEL_BASE,
84 [GOYA_FUNNEL_MME5_RTR] = mmMME5_RTR_FUNNEL_BASE,
85 [GOYA_FUNNEL_PCIE] = mmPCIE_FUNNEL_BASE,
86 [GOYA_FUNNEL_PSOC] = mmPSOC_FUNNEL_BASE,
87 [GOYA_FUNNEL_TPC0_EML] = mmTPC0_EML_FUNNEL_BASE,
88 [GOYA_FUNNEL_TPC1_EML] = mmTPC1_EML_FUNNEL_BASE,
89 [GOYA_FUNNEL_TPC1_RTR] = mmTPC1_RTR_FUNNEL_BASE,
90 [GOYA_FUNNEL_TPC2_EML] = mmTPC2_EML_FUNNEL_BASE,
91 [GOYA_FUNNEL_TPC2_RTR] = mmTPC2_RTR_FUNNEL_BASE,
92 [GOYA_FUNNEL_TPC3_EML] = mmTPC3_EML_FUNNEL_BASE,
93 [GOYA_FUNNEL_TPC3_RTR] = mmTPC3_RTR_FUNNEL_BASE,
94 [GOYA_FUNNEL_TPC4_EML] = mmTPC4_EML_FUNNEL_BASE,
95 [GOYA_FUNNEL_TPC4_RTR] = mmTPC4_RTR_FUNNEL_BASE,
96 [GOYA_FUNNEL_TPC5_EML] = mmTPC5_EML_FUNNEL_BASE,
97 [GOYA_FUNNEL_TPC5_RTR] = mmTPC5_RTR_FUNNEL_BASE,
98 [GOYA_FUNNEL_TPC6_EML] = mmTPC6_EML_FUNNEL_BASE,
99 [GOYA_FUNNEL_TPC6_RTR] = mmTPC6_RTR_FUNNEL_BASE,
100 [GOYA_FUNNEL_TPC7_EML] = mmTPC7_EML_FUNNEL_BASE
101 };
102
103 static u64 debug_bmon_regs[GOYA_BMON_LAST + 1] = {
104 [GOYA_BMON_CPU_RD] = mmCPU_RD_BMON_BASE,
105 [GOYA_BMON_CPU_WR] = mmCPU_WR_BMON_BASE,
106 [GOYA_BMON_DMA_CH_0_0] = mmDMA_CH_0_BMON_0_BASE,
107 [GOYA_BMON_DMA_CH_0_1] = mmDMA_CH_0_BMON_1_BASE,
108 [GOYA_BMON_DMA_CH_1_0] = mmDMA_CH_1_BMON_0_BASE,
109 [GOYA_BMON_DMA_CH_1_1] = mmDMA_CH_1_BMON_1_BASE,
110 [GOYA_BMON_DMA_CH_2_0] = mmDMA_CH_2_BMON_0_BASE,
111 [GOYA_BMON_DMA_CH_2_1] = mmDMA_CH_2_BMON_1_BASE,
112 [GOYA_BMON_DMA_CH_3_0] = mmDMA_CH_3_BMON_0_BASE,
113 [GOYA_BMON_DMA_CH_3_1] = mmDMA_CH_3_BMON_1_BASE,
114 [GOYA_BMON_DMA_CH_4_0] = mmDMA_CH_4_BMON_0_BASE,
115 [GOYA_BMON_DMA_CH_4_1] = mmDMA_CH_4_BMON_1_BASE,
116 [GOYA_BMON_DMA_MACRO_0] = mmDMA_MACRO_BMON_0_BASE,
117 [GOYA_BMON_DMA_MACRO_1] = mmDMA_MACRO_BMON_1_BASE,
118 [GOYA_BMON_DMA_MACRO_2] = mmDMA_MACRO_BMON_2_BASE,
119 [GOYA_BMON_DMA_MACRO_3] = mmDMA_MACRO_BMON_3_BASE,
120 [GOYA_BMON_DMA_MACRO_4] = mmDMA_MACRO_BMON_4_BASE,
121 [GOYA_BMON_DMA_MACRO_5] = mmDMA_MACRO_BMON_5_BASE,
122 [GOYA_BMON_DMA_MACRO_6] = mmDMA_MACRO_BMON_6_BASE,
123 [GOYA_BMON_DMA_MACRO_7] = mmDMA_MACRO_BMON_7_BASE,
124 [GOYA_BMON_MME1_SBA_0] = mmMME1_SBA_BMON0_BASE,
125 [GOYA_BMON_MME1_SBA_1] = mmMME1_SBA_BMON1_BASE,
126 [GOYA_BMON_MME3_SBB_0] = mmMME3_SBB_BMON0_BASE,
127 [GOYA_BMON_MME3_SBB_1] = mmMME3_SBB_BMON1_BASE,
128 [GOYA_BMON_MME4_WACS2_0] = mmMME4_WACS2_BMON0_BASE,
129 [GOYA_BMON_MME4_WACS2_1] = mmMME4_WACS2_BMON1_BASE,
130 [GOYA_BMON_MME4_WACS2_2] = mmMME4_WACS2_BMON2_BASE,
131 [GOYA_BMON_MME4_WACS_0] = mmMME4_WACS_BMON0_BASE,
132 [GOYA_BMON_MME4_WACS_1] = mmMME4_WACS_BMON1_BASE,
133 [GOYA_BMON_MME4_WACS_2] = mmMME4_WACS_BMON2_BASE,
134 [GOYA_BMON_MME4_WACS_3] = mmMME4_WACS_BMON3_BASE,
135 [GOYA_BMON_MME4_WACS_4] = mmMME4_WACS_BMON4_BASE,
136 [GOYA_BMON_MME4_WACS_5] = mmMME4_WACS_BMON5_BASE,
137 [GOYA_BMON_MME4_WACS_6] = mmMME4_WACS_BMON6_BASE,
138 [GOYA_BMON_MMU_0] = mmMMU_BMON_0_BASE,
139 [GOYA_BMON_MMU_1] = mmMMU_BMON_1_BASE,
140 [GOYA_BMON_PCIE_MSTR_RD] = mmPCIE_BMON_MSTR_RD_BASE,
141 [GOYA_BMON_PCIE_MSTR_WR] = mmPCIE_BMON_MSTR_WR_BASE,
142 [GOYA_BMON_PCIE_SLV_RD] = mmPCIE_BMON_SLV_RD_BASE,
143 [GOYA_BMON_PCIE_SLV_WR] = mmPCIE_BMON_SLV_WR_BASE,
144 [GOYA_BMON_TPC0_EML_0] = mmTPC0_EML_BUSMON_0_BASE,
145 [GOYA_BMON_TPC0_EML_1] = mmTPC0_EML_BUSMON_1_BASE,
146 [GOYA_BMON_TPC0_EML_2] = mmTPC0_EML_BUSMON_2_BASE,
147 [GOYA_BMON_TPC0_EML_3] = mmTPC0_EML_BUSMON_3_BASE,
148 [GOYA_BMON_TPC1_EML_0] = mmTPC1_EML_BUSMON_0_BASE,
149 [GOYA_BMON_TPC1_EML_1] = mmTPC1_EML_BUSMON_1_BASE,
150 [GOYA_BMON_TPC1_EML_2] = mmTPC1_EML_BUSMON_2_BASE,
151 [GOYA_BMON_TPC1_EML_3] = mmTPC1_EML_BUSMON_3_BASE,
152 [GOYA_BMON_TPC2_EML_0] = mmTPC2_EML_BUSMON_0_BASE,
153 [GOYA_BMON_TPC2_EML_1] = mmTPC2_EML_BUSMON_1_BASE,
154 [GOYA_BMON_TPC2_EML_2] = mmTPC2_EML_BUSMON_2_BASE,
155 [GOYA_BMON_TPC2_EML_3] = mmTPC2_EML_BUSMON_3_BASE,
156 [GOYA_BMON_TPC3_EML_0] = mmTPC3_EML_BUSMON_0_BASE,
157 [GOYA_BMON_TPC3_EML_1] = mmTPC3_EML_BUSMON_1_BASE,
158 [GOYA_BMON_TPC3_EML_2] = mmTPC3_EML_BUSMON_2_BASE,
159 [GOYA_BMON_TPC3_EML_3] = mmTPC3_EML_BUSMON_3_BASE,
160 [GOYA_BMON_TPC4_EML_0] = mmTPC4_EML_BUSMON_0_BASE,
161 [GOYA_BMON_TPC4_EML_1] = mmTPC4_EML_BUSMON_1_BASE,
162 [GOYA_BMON_TPC4_EML_2] = mmTPC4_EML_BUSMON_2_BASE,
163 [GOYA_BMON_TPC4_EML_3] = mmTPC4_EML_BUSMON_3_BASE,
164 [GOYA_BMON_TPC5_EML_0] = mmTPC5_EML_BUSMON_0_BASE,
165 [GOYA_BMON_TPC5_EML_1] = mmTPC5_EML_BUSMON_1_BASE,
166 [GOYA_BMON_TPC5_EML_2] = mmTPC5_EML_BUSMON_2_BASE,
167 [GOYA_BMON_TPC5_EML_3] = mmTPC5_EML_BUSMON_3_BASE,
168 [GOYA_BMON_TPC6_EML_0] = mmTPC6_EML_BUSMON_0_BASE,
169 [GOYA_BMON_TPC6_EML_1] = mmTPC6_EML_BUSMON_1_BASE,
170 [GOYA_BMON_TPC6_EML_2] = mmTPC6_EML_BUSMON_2_BASE,
171 [GOYA_BMON_TPC6_EML_3] = mmTPC6_EML_BUSMON_3_BASE,
172 [GOYA_BMON_TPC7_EML_0] = mmTPC7_EML_BUSMON_0_BASE,
173 [GOYA_BMON_TPC7_EML_1] = mmTPC7_EML_BUSMON_1_BASE,
174 [GOYA_BMON_TPC7_EML_2] = mmTPC7_EML_BUSMON_2_BASE,
175 [GOYA_BMON_TPC7_EML_3] = mmTPC7_EML_BUSMON_3_BASE
176 };
177
178 static u64 debug_spmu_regs[GOYA_SPMU_LAST + 1] = {
179 [GOYA_SPMU_DMA_CH_0_CS] = mmDMA_CH_0_CS_SPMU_BASE,
180 [GOYA_SPMU_DMA_CH_1_CS] = mmDMA_CH_1_CS_SPMU_BASE,
181 [GOYA_SPMU_DMA_CH_2_CS] = mmDMA_CH_2_CS_SPMU_BASE,
182 [GOYA_SPMU_DMA_CH_3_CS] = mmDMA_CH_3_CS_SPMU_BASE,
183 [GOYA_SPMU_DMA_CH_4_CS] = mmDMA_CH_4_CS_SPMU_BASE,
184 [GOYA_SPMU_DMA_MACRO_CS] = mmDMA_MACRO_CS_SPMU_BASE,
185 [GOYA_SPMU_MME1_SBA] = mmMME1_SBA_SPMU_BASE,
186 [GOYA_SPMU_MME3_SBB] = mmMME3_SBB_SPMU_BASE,
187 [GOYA_SPMU_MME4_WACS2] = mmMME4_WACS2_SPMU_BASE,
188 [GOYA_SPMU_MME4_WACS] = mmMME4_WACS_SPMU_BASE,
189 [GOYA_SPMU_MMU_CS] = mmMMU_CS_SPMU_BASE,
190 [GOYA_SPMU_PCIE] = mmPCIE_SPMU_BASE,
191 [GOYA_SPMU_TPC0_EML] = mmTPC0_EML_SPMU_BASE,
192 [GOYA_SPMU_TPC1_EML] = mmTPC1_EML_SPMU_BASE,
193 [GOYA_SPMU_TPC2_EML] = mmTPC2_EML_SPMU_BASE,
194 [GOYA_SPMU_TPC3_EML] = mmTPC3_EML_SPMU_BASE,
195 [GOYA_SPMU_TPC4_EML] = mmTPC4_EML_SPMU_BASE,
196 [GOYA_SPMU_TPC5_EML] = mmTPC5_EML_SPMU_BASE,
197 [GOYA_SPMU_TPC6_EML] = mmTPC6_EML_SPMU_BASE,
198 [GOYA_SPMU_TPC7_EML] = mmTPC7_EML_SPMU_BASE
199 };
200
201 static int goya_coresight_timeout(struct hl_device *hdev, u64 addr,
202 int position, bool up)
203 {
204 int rc;
205 u32 val, timeout_usec;
206
207 if (hdev->pldm)
208 timeout_usec = GOYA_PLDM_CORESIGHT_TIMEOUT_USEC;
209 else
210 timeout_usec = CORESIGHT_TIMEOUT_USEC;
211
212 rc = hl_poll_timeout(
213 hdev,
214 addr,
215 val,
216 up ? val & BIT(position) : !(val & BIT(position)),
217 1000,
218 timeout_usec);
219
220 if (rc) {
221 dev_err(hdev->dev,
222 "Timeout while waiting for coresight, addr: 0x%llx, position: %d, up: %d\n",
223 addr, position, up);
224 return -EFAULT;
225 }
226
227 return 0;
228 }
229
230 static int goya_config_stm(struct hl_device *hdev,
231 struct hl_debug_params *params)
232 {
233 struct hl_debug_params_stm *input;
234 u64 base_reg;
235 int rc;
236
237 if (params->reg_idx >= ARRAY_SIZE(debug_stm_regs)) {
238 dev_err(hdev->dev, "Invalid register index in STM\n");
239 return -EINVAL;
240 }
241
242 base_reg = debug_stm_regs[params->reg_idx] - CFG_BASE;
243
244 WREG32(base_reg + 0xFB0, CORESIGHT_UNLOCK);
245
246 if (params->enable) {
247 input = params->input;
248
249 if (!input)
250 return -EINVAL;
251
252 WREG32(base_reg + 0xE80, 0x80004);
253 WREG32(base_reg + 0xD64, 7);
254 WREG32(base_reg + 0xD60, 0);
255 WREG32(base_reg + 0xD00, lower_32_bits(input->he_mask));
256 WREG32(base_reg + 0xD20, lower_32_bits(input->sp_mask));
257 WREG32(base_reg + 0xD60, 1);
258 WREG32(base_reg + 0xD00, upper_32_bits(input->he_mask));
259 WREG32(base_reg + 0xD20, upper_32_bits(input->sp_mask));
260 WREG32(base_reg + 0xE70, 0x10);
261 WREG32(base_reg + 0xE60, 0);
262 WREG32(base_reg + 0xE64, 0x420000);
263 WREG32(base_reg + 0xE00, 0xFFFFFFFF);
264 WREG32(base_reg + 0xE20, 0xFFFFFFFF);
265 WREG32(base_reg + 0xEF4, input->id);
266 WREG32(base_reg + 0xDF4, 0x80);
267 WREG32(base_reg + 0xE8C, input->frequency);
268 WREG32(base_reg + 0xE90, 0x7FF);
269 WREG32(base_reg + 0xE80, 0x7 | (input->id << 16));
270 } else {
271 WREG32(base_reg + 0xE80, 4);
272 WREG32(base_reg + 0xD64, 0);
273 WREG32(base_reg + 0xD60, 1);
274 WREG32(base_reg + 0xD00, 0);
275 WREG32(base_reg + 0xD20, 0);
276 WREG32(base_reg + 0xD60, 0);
277 WREG32(base_reg + 0xE20, 0);
278 WREG32(base_reg + 0xE00, 0);
279 WREG32(base_reg + 0xDF4, 0x80);
280 WREG32(base_reg + 0xE70, 0);
281 WREG32(base_reg + 0xE60, 0);
282 WREG32(base_reg + 0xE64, 0);
283 WREG32(base_reg + 0xE8C, 0);
284
285 rc = goya_coresight_timeout(hdev, base_reg + 0xE80, 23, false);
286 if (rc) {
287 dev_err(hdev->dev,
288 "Failed to disable STM on timeout, error %d\n",
289 rc);
290 return rc;
291 }
292
293 WREG32(base_reg + 0xE80, 4);
294 }
295
296 return 0;
297 }
298
299 static int goya_config_etf(struct hl_device *hdev,
300 struct hl_debug_params *params)
301 {
302 struct hl_debug_params_etf *input;
303 u64 base_reg;
304 u32 val;
305 int rc;
306
307 if (params->reg_idx >= ARRAY_SIZE(debug_etf_regs)) {
308 dev_err(hdev->dev, "Invalid register index in ETF\n");
309 return -EINVAL;
310 }
311
312 base_reg = debug_etf_regs[params->reg_idx] - CFG_BASE;
313
314 WREG32(base_reg + 0xFB0, CORESIGHT_UNLOCK);
315
316 val = RREG32(base_reg + 0x304);
317 val |= 0x1000;
318 WREG32(base_reg + 0x304, val);
319 val |= 0x40;
320 WREG32(base_reg + 0x304, val);
321
322 rc = goya_coresight_timeout(hdev, base_reg + 0x304, 6, false);
323 if (rc) {
324 dev_err(hdev->dev,
325 "Failed to %s ETF on timeout, error %d\n",
326 params->enable ? "enable" : "disable", rc);
327 return rc;
328 }
329
330 rc = goya_coresight_timeout(hdev, base_reg + 0xC, 2, true);
331 if (rc) {
332 dev_err(hdev->dev,
333 "Failed to %s ETF on timeout, error %d\n",
334 params->enable ? "enable" : "disable", rc);
335 return rc;
336 }
337
338 WREG32(base_reg + 0x20, 0);
339
340 if (params->enable) {
341 input = params->input;
342
343 if (!input)
344 return -EINVAL;
345
346 WREG32(base_reg + 0x34, 0x3FFC);
347 WREG32(base_reg + 0x28, input->sink_mode);
348 WREG32(base_reg + 0x304, 0x4001);
349 WREG32(base_reg + 0x308, 0xA);
350 WREG32(base_reg + 0x20, 1);
351 } else {
352 WREG32(base_reg + 0x34, 0);
353 WREG32(base_reg + 0x28, 0);
354 WREG32(base_reg + 0x304, 0);
355 }
356
357 return 0;
358 }
359
360 static int goya_etr_validate_address(struct hl_device *hdev, u64 addr,
361 u32 size)
362 {
363 struct asic_fixed_properties *prop = &hdev->asic_prop;
364 u64 range_start, range_end;
365
366 if (hdev->mmu_enable) {
367 range_start = prop->va_space_dram_start_address;
368 range_end = prop->va_space_dram_end_address;
369 } else {
370 range_start = prop->dram_user_base_address;
371 range_end = prop->dram_end_address;
372 }
373
374 return hl_mem_area_inside_range(addr, size, range_start, range_end);
375 }
376
377 static int goya_config_etr(struct hl_device *hdev,
378 struct hl_debug_params *params)
379 {
380 struct hl_debug_params_etr *input;
381 u32 val;
382 int rc;
383
384 WREG32(mmPSOC_ETR_LAR, CORESIGHT_UNLOCK);
385
386 val = RREG32(mmPSOC_ETR_FFCR);
387 val |= 0x1000;
388 WREG32(mmPSOC_ETR_FFCR, val);
389 val |= 0x40;
390 WREG32(mmPSOC_ETR_FFCR, val);
391
392 rc = goya_coresight_timeout(hdev, mmPSOC_ETR_FFCR, 6, false);
393 if (rc) {
394 dev_err(hdev->dev, "Failed to %s ETR on timeout, error %d\n",
395 params->enable ? "enable" : "disable", rc);
396 return rc;
397 }
398
399 rc = goya_coresight_timeout(hdev, mmPSOC_ETR_STS, 2, true);
400 if (rc) {
401 dev_err(hdev->dev, "Failed to %s ETR on timeout, error %d\n",
402 params->enable ? "enable" : "disable", rc);
403 return rc;
404 }
405
406 WREG32(mmPSOC_ETR_CTL, 0);
407
408 if (params->enable) {
409 input = params->input;
410
411 if (!input)
412 return -EINVAL;
413
414 if (input->buffer_size == 0) {
415 dev_err(hdev->dev,
416 "ETR buffer size should be bigger than 0\n");
417 return -EINVAL;
418 }
419
420 if (!goya_etr_validate_address(hdev,
421 input->buffer_address, input->buffer_size)) {
422 dev_err(hdev->dev, "buffer address is not valid\n");
423 return -EINVAL;
424 }
425
426 WREG32(mmPSOC_ETR_BUFWM, 0x3FFC);
427 WREG32(mmPSOC_ETR_RSZ, input->buffer_size);
428 WREG32(mmPSOC_ETR_MODE, input->sink_mode);
429 WREG32(mmPSOC_ETR_AXICTL,
430 0x700 | PSOC_ETR_AXICTL_PROTCTRLBIT1_SHIFT);
431 WREG32(mmPSOC_ETR_DBALO,
432 lower_32_bits(input->buffer_address));
433 WREG32(mmPSOC_ETR_DBAHI,
434 upper_32_bits(input->buffer_address));
435 WREG32(mmPSOC_ETR_FFCR, 3);
436 WREG32(mmPSOC_ETR_PSCR, 0xA);
437 WREG32(mmPSOC_ETR_CTL, 1);
438 } else {
439 WREG32(mmPSOC_ETR_BUFWM, 0);
440 WREG32(mmPSOC_ETR_RSZ, 0x400);
441 WREG32(mmPSOC_ETR_DBALO, 0);
442 WREG32(mmPSOC_ETR_DBAHI, 0);
443 WREG32(mmPSOC_ETR_PSCR, 0);
444 WREG32(mmPSOC_ETR_MODE, 0);
445 WREG32(mmPSOC_ETR_FFCR, 0);
446
447 if (params->output_size >= sizeof(u64)) {
448 u32 rwp, rwphi;
449
450 /*
451 * The trace buffer address is 40 bits wide. The end of
452 * the buffer is set in the RWP register (lower 32
453 * bits), and in the RWPHI register (upper 8 bits).
454 */
455 rwp = RREG32(mmPSOC_ETR_RWP);
456 rwphi = RREG32(mmPSOC_ETR_RWPHI) & 0xff;
457 *(u64 *) params->output = ((u64) rwphi << 32) | rwp;
458 }
459 }
460
461 return 0;
462 }
463
464 static int goya_config_funnel(struct hl_device *hdev,
465 struct hl_debug_params *params)
466 {
467 u64 base_reg;
468
469 if (params->reg_idx >= ARRAY_SIZE(debug_funnel_regs)) {
470 dev_err(hdev->dev, "Invalid register index in FUNNEL\n");
471 return -EINVAL;
472 }
473
474 base_reg = debug_funnel_regs[params->reg_idx] - CFG_BASE;
475
476 WREG32(base_reg + 0xFB0, CORESIGHT_UNLOCK);
477
478 WREG32(base_reg, params->enable ? 0x33F : 0);
479
480 return 0;
481 }
482
483 static int goya_config_bmon(struct hl_device *hdev,
484 struct hl_debug_params *params)
485 {
486 struct hl_debug_params_bmon *input;
487 u64 base_reg;
488 u32 pcie_base = 0;
489
490 if (params->reg_idx >= ARRAY_SIZE(debug_bmon_regs)) {
491 dev_err(hdev->dev, "Invalid register index in BMON\n");
492 return -EINVAL;
493 }
494
495 base_reg = debug_bmon_regs[params->reg_idx] - CFG_BASE;
496
497 WREG32(base_reg + 0x104, 1);
498
499 if (params->enable) {
500 input = params->input;
501
502 if (!input)
503 return -EINVAL;
504
505 WREG32(base_reg + 0x200, lower_32_bits(input->start_addr0));
506 WREG32(base_reg + 0x204, upper_32_bits(input->start_addr0));
507 WREG32(base_reg + 0x208, lower_32_bits(input->addr_mask0));
508 WREG32(base_reg + 0x20C, upper_32_bits(input->addr_mask0));
509 WREG32(base_reg + 0x240, lower_32_bits(input->start_addr1));
510 WREG32(base_reg + 0x244, upper_32_bits(input->start_addr1));
511 WREG32(base_reg + 0x248, lower_32_bits(input->addr_mask1));
512 WREG32(base_reg + 0x24C, upper_32_bits(input->addr_mask1));
513 WREG32(base_reg + 0x224, 0);
514 WREG32(base_reg + 0x234, 0);
515 WREG32(base_reg + 0x30C, input->bw_win);
516 WREG32(base_reg + 0x308, input->win_capture);
517
518 /* PCIE IF BMON bug WA */
519 if (params->reg_idx != GOYA_BMON_PCIE_MSTR_RD &&
520 params->reg_idx != GOYA_BMON_PCIE_MSTR_WR &&
521 params->reg_idx != GOYA_BMON_PCIE_SLV_RD &&
522 params->reg_idx != GOYA_BMON_PCIE_SLV_WR)
523 pcie_base = 0xA000000;
524
525 WREG32(base_reg + 0x700, pcie_base | 0xB00 | (input->id << 12));
526 WREG32(base_reg + 0x708, pcie_base | 0xA00 | (input->id << 12));
527 WREG32(base_reg + 0x70C, pcie_base | 0xC00 | (input->id << 12));
528
529 WREG32(base_reg + 0x100, 0x11);
530 WREG32(base_reg + 0x304, 0x1);
531 } else {
532 WREG32(base_reg + 0x200, 0);
533 WREG32(base_reg + 0x204, 0);
534 WREG32(base_reg + 0x208, 0xFFFFFFFF);
535 WREG32(base_reg + 0x20C, 0xFFFFFFFF);
536 WREG32(base_reg + 0x240, 0);
537 WREG32(base_reg + 0x244, 0);
538 WREG32(base_reg + 0x248, 0xFFFFFFFF);
539 WREG32(base_reg + 0x24C, 0xFFFFFFFF);
540 WREG32(base_reg + 0x224, 0xFFFFFFFF);
541 WREG32(base_reg + 0x234, 0x1070F);
542 WREG32(base_reg + 0x30C, 0);
543 WREG32(base_reg + 0x308, 0xFFFF);
544 WREG32(base_reg + 0x700, 0xA000B00);
545 WREG32(base_reg + 0x708, 0xA000A00);
546 WREG32(base_reg + 0x70C, 0xA000C00);
547 WREG32(base_reg + 0x100, 1);
548 WREG32(base_reg + 0x304, 0);
549 WREG32(base_reg + 0x104, 0);
550 }
551
552 return 0;
553 }
554
555 static int goya_config_spmu(struct hl_device *hdev,
556 struct hl_debug_params *params)
557 {
558 u64 base_reg;
559 struct hl_debug_params_spmu *input = params->input;
560 u64 *output;
561 u32 output_arr_len;
562 u32 events_num;
563 u32 overflow_idx;
564 u32 cycle_cnt_idx;
565 int i;
566
567 if (params->reg_idx >= ARRAY_SIZE(debug_spmu_regs)) {
568 dev_err(hdev->dev, "Invalid register index in SPMU\n");
569 return -EINVAL;
570 }
571
572 base_reg = debug_spmu_regs[params->reg_idx] - CFG_BASE;
573
574 if (params->enable) {
575 input = params->input;
576
577 if (!input)
578 return -EINVAL;
579
580 if (input->event_types_num < 3) {
581 dev_err(hdev->dev,
582 "not enough event types values for SPMU enable\n");
583 return -EINVAL;
584 }
585
586 if (input->event_types_num > SPMU_MAX_COUNTERS) {
587 dev_err(hdev->dev,
588 "too many event types values for SPMU enable\n");
589 return -EINVAL;
590 }
591
592 WREG32(base_reg + 0xE04, 0x41013046);
593 WREG32(base_reg + 0xE04, 0x41013040);
594
595 for (i = 0 ; i < input->event_types_num ; i++)
596 WREG32(base_reg + SPMU_EVENT_TYPES_OFFSET + i * 4,
597 input->event_types[i]);
598
599 WREG32(base_reg + 0xE04, 0x41013041);
600 WREG32(base_reg + 0xC00, 0x8000003F);
601 } else {
602 output = params->output;
603 output_arr_len = params->output_size / 8;
604 events_num = output_arr_len - 2;
605 overflow_idx = output_arr_len - 2;
606 cycle_cnt_idx = output_arr_len - 1;
607
608 if (!output)
609 return -EINVAL;
610
611 if (output_arr_len < 3) {
612 dev_err(hdev->dev,
613 "not enough values for SPMU disable\n");
614 return -EINVAL;
615 }
616
617 if (events_num > SPMU_MAX_COUNTERS) {
618 dev_err(hdev->dev,
619 "too many events values for SPMU disable\n");
620 return -EINVAL;
621 }
622
623 WREG32(base_reg + 0xE04, 0x41013040);
624
625 for (i = 0 ; i < events_num ; i++)
626 output[i] = RREG32(base_reg + i * 8);
627
628 output[overflow_idx] = RREG32(base_reg + 0xCC0);
629
630 output[cycle_cnt_idx] = RREG32(base_reg + 0xFC);
631 output[cycle_cnt_idx] <<= 32;
632 output[cycle_cnt_idx] |= RREG32(base_reg + 0xF8);
633
634 WREG32(base_reg + 0xCC0, 0);
635 }
636
637 return 0;
638 }
639
640 int goya_debug_coresight(struct hl_device *hdev, void *data)
641 {
642 struct hl_debug_params *params = data;
643 u32 val;
644 int rc = 0;
645
646 switch (params->op) {
647 case HL_DEBUG_OP_STM:
648 rc = goya_config_stm(hdev, params);
649 break;
650 case HL_DEBUG_OP_ETF:
651 rc = goya_config_etf(hdev, params);
652 break;
653 case HL_DEBUG_OP_ETR:
654 rc = goya_config_etr(hdev, params);
655 break;
656 case HL_DEBUG_OP_FUNNEL:
657 rc = goya_config_funnel(hdev, params);
658 break;
659 case HL_DEBUG_OP_BMON:
660 rc = goya_config_bmon(hdev, params);
661 break;
662 case HL_DEBUG_OP_SPMU:
663 rc = goya_config_spmu(hdev, params);
664 break;
665 case HL_DEBUG_OP_TIMESTAMP:
666 /* Do nothing as this opcode is deprecated */
667 break;
668
669 default:
670 dev_err(hdev->dev, "Unknown coresight id %d\n", params->op);
671 return -EINVAL;
672 }
673
674 /* Perform read from the device to flush all configuration */
675 val = RREG32(mmPCIE_DBI_DEVICE_ID_VENDOR_ID_REG);
676
677 return rc;
678 }
679
680 void goya_halt_coresight(struct hl_device *hdev)
681 {
682 struct hl_debug_params params = {};
683 int i, rc;
684
685 for (i = GOYA_ETF_FIRST ; i <= GOYA_ETF_LAST ; i++) {
686 params.reg_idx = i;
687 rc = goya_config_etf(hdev, &params);
688 if (rc)
689 dev_err(hdev->dev, "halt ETF failed, %d/%d\n", rc, i);
690 }
691
692 rc = goya_config_etr(hdev, &params);
693 if (rc)
694 dev_err(hdev->dev, "halt ETR failed, %d\n", rc);
695 }
Linux with added FPC-III support