drivers/misc/mei/pci-me.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2003-2019, Intel Corporation. All rights reserved.
   4  * Intel Management Engine Interface (Intel MEI) Linux driver
   5  */
   6
   7 #include <linux/module.h>
   8 #include <linux/moduleparam.h>
   9 #include <linux/kernel.h>
  10 #include <linux/device.h>
  11 #include <linux/fs.h>
  12 #include <linux/errno.h>
  13 #include <linux/types.h>
  14 #include <linux/fcntl.h>
  15 #include <linux/pci.h>
  16 #include <linux/poll.h>
  17 #include <linux/ioctl.h>
  18 #include <linux/cdev.h>
  19 #include <linux/sched.h>
  20 #include <linux/uuid.h>
  21 #include <linux/compat.h>
  22 #include <linux/jiffies.h>
  23 #include <linux/interrupt.h>
  24
  25 #include <linux/pm_domain.h>
  26 #include <linux/pm_runtime.h>
  27
  28 #include <linux/mei.h>
  29
  30 #include "mei_dev.h"
  31 #include "client.h"
  32 #include "hw-me-regs.h"
  33 #include "hw-me.h"
  34
  35 /* mei_pci_tbl - PCI Device ID Table */
  36 static const struct pci_device_id mei_me_pci_tbl[] = {
  37         {MEI_PCI_DEVICE(MEI_DEV_ID_82946GZ, MEI_ME_ICH_CFG)},
  38         {MEI_PCI_DEVICE(MEI_DEV_ID_82G35, MEI_ME_ICH_CFG)},
  39         {MEI_PCI_DEVICE(MEI_DEV_ID_82Q965, MEI_ME_ICH_CFG)},
  40         {MEI_PCI_DEVICE(MEI_DEV_ID_82G965, MEI_ME_ICH_CFG)},
  41         {MEI_PCI_DEVICE(MEI_DEV_ID_82GM965, MEI_ME_ICH_CFG)},
  42         {MEI_PCI_DEVICE(MEI_DEV_ID_82GME965, MEI_ME_ICH_CFG)},
  43         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82Q35, MEI_ME_ICH_CFG)},
  44         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82G33, MEI_ME_ICH_CFG)},
  45         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82Q33, MEI_ME_ICH_CFG)},
  46         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82X38, MEI_ME_ICH_CFG)},
  47         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_3200, MEI_ME_ICH_CFG)},
  48
  49         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_6, MEI_ME_ICH_CFG)},
  50         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_7, MEI_ME_ICH_CFG)},
  51         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_8, MEI_ME_ICH_CFG)},
  52         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_9, MEI_ME_ICH_CFG)},
  53         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_10, MEI_ME_ICH_CFG)},
  54         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_1, MEI_ME_ICH_CFG)},
  55         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_2, MEI_ME_ICH_CFG)},
  56         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_3, MEI_ME_ICH_CFG)},
  57         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_4, MEI_ME_ICH_CFG)},
  58
  59         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_1, MEI_ME_ICH10_CFG)},
  60         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_2, MEI_ME_ICH10_CFG)},
  61         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_3, MEI_ME_ICH10_CFG)},
  62         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_4, MEI_ME_ICH10_CFG)},
  63
  64         {MEI_PCI_DEVICE(MEI_DEV_ID_IBXPK_1, MEI_ME_PCH6_CFG)},
  65         {MEI_PCI_DEVICE(MEI_DEV_ID_IBXPK_2, MEI_ME_PCH6_CFG)},
  66         {MEI_PCI_DEVICE(MEI_DEV_ID_CPT_1, MEI_ME_PCH_CPT_PBG_CFG)},
  67         {MEI_PCI_DEVICE(MEI_DEV_ID_PBG_1, MEI_ME_PCH_CPT_PBG_CFG)},
  68         {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_1, MEI_ME_PCH7_CFG)},
  69         {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_2, MEI_ME_PCH7_CFG)},
  70         {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_3, MEI_ME_PCH7_CFG)},
  71         {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_H, MEI_ME_PCH8_SPS_CFG)},
  72         {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_W, MEI_ME_PCH8_SPS_CFG)},
  73         {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_LP, MEI_ME_PCH8_CFG)},
  74         {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_HR, MEI_ME_PCH8_SPS_CFG)},
  75         {MEI_PCI_DEVICE(MEI_DEV_ID_WPT_LP, MEI_ME_PCH8_CFG)},
  76         {MEI_PCI_DEVICE(MEI_DEV_ID_WPT_LP_2, MEI_ME_PCH8_CFG)},
  77
  78         {MEI_PCI_DEVICE(MEI_DEV_ID_SPT, MEI_ME_PCH8_CFG)},
  79         {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_2, MEI_ME_PCH8_CFG)},
  80         {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H, MEI_ME_PCH8_SPS_CFG)},
  81         {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H_2, MEI_ME_PCH8_SPS_CFG)},
  82         {MEI_PCI_DEVICE(MEI_DEV_ID_LBG, MEI_ME_PCH12_CFG)},
  83
  84         {MEI_PCI_DEVICE(MEI_DEV_ID_BXT_M, MEI_ME_PCH8_CFG)},
  85         {MEI_PCI_DEVICE(MEI_DEV_ID_APL_I, MEI_ME_PCH8_CFG)},
  86
  87         {MEI_PCI_DEVICE(MEI_DEV_ID_DNV_IE, MEI_ME_PCH8_CFG)},
  88
  89         {MEI_PCI_DEVICE(MEI_DEV_ID_GLK, MEI_ME_PCH8_CFG)},
  90
  91         {MEI_PCI_DEVICE(MEI_DEV_ID_KBP, MEI_ME_PCH8_CFG)},
  92         {MEI_PCI_DEVICE(MEI_DEV_ID_KBP_2, MEI_ME_PCH8_CFG)},
  93
  94         {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_LP, MEI_ME_PCH12_CFG)},
  95         {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_LP_4, MEI_ME_PCH8_CFG)},
  96         {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_H, MEI_ME_PCH12_CFG)},
  97         {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_H_4, MEI_ME_PCH8_CFG)},
  98
  99         {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_LP, MEI_ME_PCH12_CFG)},
 100         {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_LP_3, MEI_ME_PCH8_CFG)},
 101         {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_V, MEI_ME_PCH12_CFG)},
 102         {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_H, MEI_ME_PCH12_CFG)},
 103         {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_H_3, MEI_ME_PCH8_CFG)},
 104
 105         {MEI_PCI_DEVICE(MEI_DEV_ID_ICP_LP, MEI_ME_PCH12_CFG)},
 106
 107         {MEI_PCI_DEVICE(MEI_DEV_ID_TGP_LP, MEI_ME_PCH15_CFG)},
 108
 109         {MEI_PCI_DEVICE(MEI_DEV_ID_JSP_N, MEI_ME_PCH15_CFG)},
 110
 111         {MEI_PCI_DEVICE(MEI_DEV_ID_MCC, MEI_ME_PCH15_CFG)},
 112         {MEI_PCI_DEVICE(MEI_DEV_ID_MCC_4, MEI_ME_PCH8_CFG)},
 113
 114         /* required last entry */
 115         {0, }
 116 };
 117
 118 MODULE_DEVICE_TABLE(pci, mei_me_pci_tbl);
 119
 120 #ifdef CONFIG_PM
 121 static inline void mei_me_set_pm_domain(struct mei_device *dev);
 122 static inline void mei_me_unset_pm_domain(struct mei_device *dev);
 123 #else
 124 static inline void mei_me_set_pm_domain(struct mei_device *dev) {}
 125 static inline void mei_me_unset_pm_domain(struct mei_device *dev) {}
 126 #endif /* CONFIG_PM */
 127
 128 static int mei_me_read_fws(const struct mei_device *dev, int where, u32 *val)
 129 {
 130         struct pci_dev *pdev = to_pci_dev(dev->dev);
 131
 132         return pci_read_config_dword(pdev, where, val);
 133 }
 134
 135 /**
 136  * mei_me_quirk_probe - probe for devices that doesn't valid ME interface
 137  *
 138  * @pdev: PCI device structure
 139  * @cfg: per generation config
 140  *
 141  * Return: true if ME Interface is valid, false otherwise
 142  */
 143 static bool mei_me_quirk_probe(struct pci_dev *pdev,
 144                                 const struct mei_cfg *cfg)
 145 {
 146         if (cfg->quirk_probe && cfg->quirk_probe(pdev)) {
 147                 dev_info(&pdev->dev, "Device doesn't have valid ME Interface\n");
 148                 return false;
 149         }
 150
 151         return true;
 152 }
 153
 154 /**
 155  * mei_me_probe - Device Initialization Routine
 156  *
 157  * @pdev: PCI device structure
 158  * @ent: entry in kcs_pci_tbl
 159  *
 160  * Return: 0 on success, <0 on failure.
 161  */
 162 static int mei_me_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 163 {
 164         const struct mei_cfg *cfg;
 165         struct mei_device *dev;
 166         struct mei_me_hw *hw;
 167         unsigned int irqflags;
 168         int err;
 169
 170         cfg = mei_me_get_cfg(ent->driver_data);
 171         if (!cfg)
 172                 return -ENODEV;
 173
 174         if (!mei_me_quirk_probe(pdev, cfg))
 175                 return -ENODEV;
 176
 177         /* enable pci dev */
 178         err = pcim_enable_device(pdev);
 179         if (err) {
 180                 dev_err(&pdev->dev, "failed to enable pci device.\n");
 181                 goto end;
 182         }
 183         /* set PCI host mastering  */
 184         pci_set_master(pdev);
 185         /* pci request regions and mapping IO device memory for mei driver */
 186         err = pcim_iomap_regions(pdev, BIT(0), KBUILD_MODNAME);
 187         if (err) {
 188                 dev_err(&pdev->dev, "failed to get pci regions.\n");
 189                 goto end;
 190         }
 191
 192         if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) ||
 193             dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
 194
 195                 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
 196                 if (err)
 197                         err = dma_set_coherent_mask(&pdev->dev,
 198                                                     DMA_BIT_MASK(32));
 199         }
 200         if (err) {
 201                 dev_err(&pdev->dev, "No usable DMA configuration, aborting\n");
 202                 goto end;
 203         }
 204
 205         /* allocates and initializes the mei dev structure */
 206         dev = mei_me_dev_init(&pdev->dev, cfg);
 207         if (!dev) {
 208                 err = -ENOMEM;
 209                 goto end;
 210         }
 211         hw = to_me_hw(dev);
 212         hw->mem_addr = pcim_iomap_table(pdev)[0];
 213         hw->irq = pdev->irq;
 214         hw->read_fws = mei_me_read_fws;
 215
 216         pci_enable_msi(pdev);
 217
 218          /* request and enable interrupt */
 219         irqflags = pci_dev_msi_enabled(pdev) ? IRQF_ONESHOT : IRQF_SHARED;
 220
 221         err = request_threaded_irq(pdev->irq,
 222                         mei_me_irq_quick_handler,
 223                         mei_me_irq_thread_handler,
 224                         irqflags, KBUILD_MODNAME, dev);
 225         if (err) {
 226                 dev_err(&pdev->dev, "request_threaded_irq failure. irq = %d\n",
 227                        pdev->irq);
 228                 goto end;
 229         }
 230
 231         if (mei_start(dev)) {
 232                 dev_err(&pdev->dev, "init hw failure.\n");
 233                 err = -ENODEV;
 234                 goto release_irq;
 235         }
 236
 237         pm_runtime_set_autosuspend_delay(&pdev->dev, MEI_ME_RPM_TIMEOUT);
 238         pm_runtime_use_autosuspend(&pdev->dev);
 239
 240         err = mei_register(dev, &pdev->dev);
 241         if (err)
 242                 goto stop;
 243
 244         pci_set_drvdata(pdev, dev);
 245
 246         /*
 247          * MEI requires to resume from runtime suspend mode
 248          * in order to perform link reset flow upon system suspend.
 249          */
 250         dev_pm_set_driver_flags(&pdev->dev, DPM_FLAG_NEVER_SKIP);
 251
 252         /*
 253          * ME maps runtime suspend/resume to D0i states,
 254          * hence we need to go around native PCI runtime service which
 255          * eventually brings the device into D3cold/hot state,
 256          * but the mei device cannot wake up from D3 unlike from D0i3.
 257          * To get around the PCI device native runtime pm,
 258          * ME uses runtime pm domain handlers which take precedence
 259          * over the driver's pm handlers.
 260          */
 261         mei_me_set_pm_domain(dev);
 262
 263         if (mei_pg_is_enabled(dev)) {
 264                 pm_runtime_put_noidle(&pdev->dev);
 265                 if (hw->d0i3_supported)
 266                         pm_runtime_allow(&pdev->dev);
 267         }
 268
 269         dev_dbg(&pdev->dev, "initialization successful.\n");
 270
 271         return 0;
 272
 273 stop:
 274         mei_stop(dev);
 275 release_irq:
 276         mei_cancel_work(dev);
 277         mei_disable_interrupts(dev);
 278         free_irq(pdev->irq, dev);
 279 end:
 280         dev_err(&pdev->dev, "initialization failed.\n");
 281         return err;
 282 }
 283
 284 /**
 285  * mei_me_shutdown - Device Removal Routine
 286  *
 287  * @pdev: PCI device structure
 288  *
 289  * mei_me_shutdown is called from the reboot notifier
 290  * it's a simplified version of remove so we go down
 291  * faster.
 292  */
 293 static void mei_me_shutdown(struct pci_dev *pdev)
 294 {
 295         struct mei_device *dev;
 296
 297         dev = pci_get_drvdata(pdev);
 298         if (!dev)
 299                 return;
 300
 301         dev_dbg(&pdev->dev, "shutdown\n");
 302         mei_stop(dev);
 303
 304         mei_me_unset_pm_domain(dev);
 305
 306         mei_disable_interrupts(dev);
 307         free_irq(pdev->irq, dev);
 308 }
 309
 310 /**
 311  * mei_me_remove - Device Removal Routine
 312  *
 313  * @pdev: PCI device structure
 314  *
 315  * mei_me_remove is called by the PCI subsystem to alert the driver
 316  * that it should release a PCI device.
 317  */
 318 static void mei_me_remove(struct pci_dev *pdev)
 319 {
 320         struct mei_device *dev;
 321
 322         dev = pci_get_drvdata(pdev);
 323         if (!dev)
 324                 return;
 325
 326         if (mei_pg_is_enabled(dev))
 327                 pm_runtime_get_noresume(&pdev->dev);
 328
 329         dev_dbg(&pdev->dev, "stop\n");
 330         mei_stop(dev);
 331
 332         mei_me_unset_pm_domain(dev);
 333
 334         mei_disable_interrupts(dev);
 335
 336         free_irq(pdev->irq, dev);
 337
 338         mei_deregister(dev);
 339 }
 340
 341 #ifdef CONFIG_PM_SLEEP
 342 static int mei_me_pci_suspend(struct device *device)
 343 {
 344         struct pci_dev *pdev = to_pci_dev(device);
 345         struct mei_device *dev = pci_get_drvdata(pdev);
 346
 347         if (!dev)
 348                 return -ENODEV;
 349
 350         dev_dbg(&pdev->dev, "suspend\n");
 351
 352         mei_stop(dev);
 353
 354         mei_disable_interrupts(dev);
 355
 356         free_irq(pdev->irq, dev);
 357         pci_disable_msi(pdev);
 358
 359         return 0;
 360 }
 361
 362 static int mei_me_pci_resume(struct device *device)
 363 {
 364         struct pci_dev *pdev = to_pci_dev(device);
 365         struct mei_device *dev;
 366         unsigned int irqflags;
 367         int err;
 368
 369         dev = pci_get_drvdata(pdev);
 370         if (!dev)
 371                 return -ENODEV;
 372
 373         pci_enable_msi(pdev);
 374
 375         irqflags = pci_dev_msi_enabled(pdev) ? IRQF_ONESHOT : IRQF_SHARED;
 376
 377         /* request and enable interrupt */
 378         err = request_threaded_irq(pdev->irq,
 379                         mei_me_irq_quick_handler,
 380                         mei_me_irq_thread_handler,
 381                         irqflags, KBUILD_MODNAME, dev);
 382
 383         if (err) {
 384                 dev_err(&pdev->dev, "request_threaded_irq failed: irq = %d.\n",
 385                                 pdev->irq);
 386                 return err;
 387         }
 388
 389         err = mei_restart(dev);
 390         if (err)
 391                 return err;
 392
 393         /* Start timer if stopped in suspend */
 394         schedule_delayed_work(&dev->timer_work, HZ);
 395
 396         return 0;
 397 }
 398 #endif /* CONFIG_PM_SLEEP */
 399
 400 #ifdef CONFIG_PM
 401 static int mei_me_pm_runtime_idle(struct device *device)
 402 {
 403         struct mei_device *dev;
 404
 405         dev_dbg(device, "rpm: me: runtime_idle\n");
 406
 407         dev = dev_get_drvdata(device);
 408         if (!dev)
 409                 return -ENODEV;
 410         if (mei_write_is_idle(dev))
 411                 pm_runtime_autosuspend(device);
 412
 413         return -EBUSY;
 414 }
 415
 416 static int mei_me_pm_runtime_suspend(struct device *device)
 417 {
 418         struct mei_device *dev;
 419         int ret;
 420
 421         dev_dbg(device, "rpm: me: runtime suspend\n");
 422
 423         dev = dev_get_drvdata(device);
 424         if (!dev)
 425                 return -ENODEV;
 426
 427         mutex_lock(&dev->device_lock);
 428
 429         if (mei_write_is_idle(dev))
 430                 ret = mei_me_pg_enter_sync(dev);
 431         else
 432                 ret = -EAGAIN;
 433
 434         mutex_unlock(&dev->device_lock);
 435
 436         dev_dbg(device, "rpm: me: runtime suspend ret=%d\n", ret);
 437
 438         if (ret && ret != -EAGAIN)
 439                 schedule_work(&dev->reset_work);
 440
 441         return ret;
 442 }
 443
 444 static int mei_me_pm_runtime_resume(struct device *device)
 445 {
 446         struct mei_device *dev;
 447         int ret;
 448
 449         dev_dbg(device, "rpm: me: runtime resume\n");
 450
 451         dev = dev_get_drvdata(device);
 452         if (!dev)
 453                 return -ENODEV;
 454
 455         mutex_lock(&dev->device_lock);
 456
 457         ret = mei_me_pg_exit_sync(dev);
 458
 459         mutex_unlock(&dev->device_lock);
 460
 461         dev_dbg(device, "rpm: me: runtime resume ret = %d\n", ret);
 462
 463         if (ret)
 464                 schedule_work(&dev->reset_work);
 465
 466         return ret;
 467 }
 468
 469 /**
 470  * mei_me_set_pm_domain - fill and set pm domain structure for device
 471  *
 472  * @dev: mei_device
 473  */
 474 static inline void mei_me_set_pm_domain(struct mei_device *dev)
 475 {
 476         struct pci_dev *pdev  = to_pci_dev(dev->dev);
 477
 478         if (pdev->dev.bus && pdev->dev.bus->pm) {
 479                 dev->pg_domain.ops = *pdev->dev.bus->pm;
 480
 481                 dev->pg_domain.ops.runtime_suspend = mei_me_pm_runtime_suspend;
 482                 dev->pg_domain.ops.runtime_resume = mei_me_pm_runtime_resume;
 483                 dev->pg_domain.ops.runtime_idle = mei_me_pm_runtime_idle;
 484
 485                 dev_pm_domain_set(&pdev->dev, &dev->pg_domain);
 486         }
 487 }
 488
 489 /**
 490  * mei_me_unset_pm_domain - clean pm domain structure for device
 491  *
 492  * @dev: mei_device
 493  */
 494 static inline void mei_me_unset_pm_domain(struct mei_device *dev)
 495 {
 496         /* stop using pm callbacks if any */
 497         dev_pm_domain_set(dev->dev, NULL);
 498 }
 499
 500 static const struct dev_pm_ops mei_me_pm_ops = {
 501         SET_SYSTEM_SLEEP_PM_OPS(mei_me_pci_suspend,
 502                                 mei_me_pci_resume)
 503         SET_RUNTIME_PM_OPS(
 504                 mei_me_pm_runtime_suspend,
 505                 mei_me_pm_runtime_resume,
 506                 mei_me_pm_runtime_idle)
 507 };
 508
 509 #define MEI_ME_PM_OPS   (&mei_me_pm_ops)
 510 #else
 511 #define MEI_ME_PM_OPS   NULL
 512 #endif /* CONFIG_PM */
 513 /*
 514  *  PCI driver structure
 515  */
 516 static struct pci_driver mei_me_driver = {
 517         .name = KBUILD_MODNAME,
 518         .id_table = mei_me_pci_tbl,
 519         .probe = mei_me_probe,
 520         .remove = mei_me_remove,
 521         .shutdown = mei_me_shutdown,
 522         .driver.pm = MEI_ME_PM_OPS,
 523         .driver.probe_type = PROBE_PREFER_ASYNCHRONOUS,
 524 };
 525
 526 module_pci_driver(mei_me_driver);
 527
 528 MODULE_AUTHOR("Intel Corporation");
 529 MODULE_DESCRIPTION("Intel(R) Management Engine Interface");
 530 MODULE_LICENSE("GPL v2");