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treewide: remove redundant IS_ERR() before error code check
[linux/fpc-iii.git] / drivers / mmc / host / atmel-mci.c
blobaeaaa5314924947f8eb714171cd5ff75af5b445d
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Atmel MultiMedia Card Interface driver
4 *
5 * Copyright (C) 2004-2008 Atmel Corporation
6 */
7 #include <linux/blkdev.h>
8 #include <linux/clk.h>
9 #include <linux/debugfs.h>
10 #include <linux/device.h>
11 #include <linux/dmaengine.h>
12 #include <linux/dma-mapping.h>
13 #include <linux/err.h>
14 #include <linux/gpio.h>
15 #include <linux/init.h>
16 #include <linux/interrupt.h>
17 #include <linux/io.h>
18 #include <linux/ioport.h>
19 #include <linux/module.h>
20 #include <linux/of.h>
21 #include <linux/of_device.h>
22 #include <linux/of_gpio.h>
23 #include <linux/platform_device.h>
24 #include <linux/scatterlist.h>
25 #include <linux/seq_file.h>
26 #include <linux/slab.h>
27 #include <linux/stat.h>
28 #include <linux/types.h>
29
30 #include <linux/mmc/host.h>
31 #include <linux/mmc/sdio.h>
32
33 #include <linux/atmel-mci.h>
34 #include <linux/atmel_pdc.h>
35 #include <linux/pm.h>
36 #include <linux/pm_runtime.h>
37 #include <linux/pinctrl/consumer.h>
38
39 #include <asm/cacheflush.h>
40 #include <asm/io.h>
41 #include <asm/unaligned.h>
42
43 /*
44 * Superset of MCI IP registers integrated in Atmel AT91 Processor
45 * Registers and bitfields marked with [2] are only available in MCI2
46 */
47
48 /* MCI Register Definitions */
49 #define ATMCI_CR 0x0000 /* Control */
50 #define ATMCI_CR_MCIEN BIT(0) /* MCI Enable */
51 #define ATMCI_CR_MCIDIS BIT(1) /* MCI Disable */
52 #define ATMCI_CR_PWSEN BIT(2) /* Power Save Enable */
53 #define ATMCI_CR_PWSDIS BIT(3) /* Power Save Disable */
54 #define ATMCI_CR_SWRST BIT(7) /* Software Reset */
55 #define ATMCI_MR 0x0004 /* Mode */
56 #define ATMCI_MR_CLKDIV(x) ((x) << 0) /* Clock Divider */
57 #define ATMCI_MR_PWSDIV(x) ((x) << 8) /* Power Saving Divider */
58 #define ATMCI_MR_RDPROOF BIT(11) /* Read Proof */
59 #define ATMCI_MR_WRPROOF BIT(12) /* Write Proof */
60 #define ATMCI_MR_PDCFBYTE BIT(13) /* Force Byte Transfer */
61 #define ATMCI_MR_PDCPADV BIT(14) /* Padding Value */
62 #define ATMCI_MR_PDCMODE BIT(15) /* PDC-oriented Mode */
63 #define ATMCI_MR_CLKODD(x) ((x) << 16) /* LSB of Clock Divider */
64 #define ATMCI_DTOR 0x0008 /* Data Timeout */
65 #define ATMCI_DTOCYC(x) ((x) << 0) /* Data Timeout Cycles */
66 #define ATMCI_DTOMUL(x) ((x) << 4) /* Data Timeout Multiplier */
67 #define ATMCI_SDCR 0x000c /* SD Card / SDIO */
68 #define ATMCI_SDCSEL_SLOT_A (0 << 0) /* Select SD slot A */
69 #define ATMCI_SDCSEL_SLOT_B (1 << 0) /* Select SD slot A */
70 #define ATMCI_SDCSEL_MASK (3 << 0)
71 #define ATMCI_SDCBUS_1BIT (0 << 6) /* 1-bit data bus */
72 #define ATMCI_SDCBUS_4BIT (2 << 6) /* 4-bit data bus */
73 #define ATMCI_SDCBUS_8BIT (3 << 6) /* 8-bit data bus[2] */
74 #define ATMCI_SDCBUS_MASK (3 << 6)
75 #define ATMCI_ARGR 0x0010 /* Command Argument */
76 #define ATMCI_CMDR 0x0014 /* Command */
77 #define ATMCI_CMDR_CMDNB(x) ((x) << 0) /* Command Opcode */
78 #define ATMCI_CMDR_RSPTYP_NONE (0 << 6) /* No response */
79 #define ATMCI_CMDR_RSPTYP_48BIT (1 << 6) /* 48-bit response */
80 #define ATMCI_CMDR_RSPTYP_136BIT (2 << 6) /* 136-bit response */
81 #define ATMCI_CMDR_SPCMD_INIT (1 << 8) /* Initialization command */
82 #define ATMCI_CMDR_SPCMD_SYNC (2 << 8) /* Synchronized command */
83 #define ATMCI_CMDR_SPCMD_INT (4 << 8) /* Interrupt command */
84 #define ATMCI_CMDR_SPCMD_INTRESP (5 << 8) /* Interrupt response */
85 #define ATMCI_CMDR_OPDCMD (1 << 11) /* Open Drain */
86 #define ATMCI_CMDR_MAXLAT_5CYC (0 << 12) /* Max latency 5 cycles */
87 #define ATMCI_CMDR_MAXLAT_64CYC (1 << 12) /* Max latency 64 cycles */
88 #define ATMCI_CMDR_START_XFER (1 << 16) /* Start data transfer */
89 #define ATMCI_CMDR_STOP_XFER (2 << 16) /* Stop data transfer */
90 #define ATMCI_CMDR_TRDIR_WRITE (0 << 18) /* Write data */
91 #define ATMCI_CMDR_TRDIR_READ (1 << 18) /* Read data */
92 #define ATMCI_CMDR_BLOCK (0 << 19) /* Single-block transfer */
93 #define ATMCI_CMDR_MULTI_BLOCK (1 << 19) /* Multi-block transfer */
94 #define ATMCI_CMDR_STREAM (2 << 19) /* MMC Stream transfer */
95 #define ATMCI_CMDR_SDIO_BYTE (4 << 19) /* SDIO Byte transfer */
96 #define ATMCI_CMDR_SDIO_BLOCK (5 << 19) /* SDIO Block transfer */
97 #define ATMCI_CMDR_SDIO_SUSPEND (1 << 24) /* SDIO Suspend Command */
98 #define ATMCI_CMDR_SDIO_RESUME (2 << 24) /* SDIO Resume Command */
99 #define ATMCI_BLKR 0x0018 /* Block */
100 #define ATMCI_BCNT(x) ((x) << 0) /* Data Block Count */
101 #define ATMCI_BLKLEN(x) ((x) << 16) /* Data Block Length */
102 #define ATMCI_CSTOR 0x001c /* Completion Signal Timeout[2] */
103 #define ATMCI_CSTOCYC(x) ((x) << 0) /* CST cycles */
104 #define ATMCI_CSTOMUL(x) ((x) << 4) /* CST multiplier */
105 #define ATMCI_RSPR 0x0020 /* Response 0 */
106 #define ATMCI_RSPR1 0x0024 /* Response 1 */
107 #define ATMCI_RSPR2 0x0028 /* Response 2 */
108 #define ATMCI_RSPR3 0x002c /* Response 3 */
109 #define ATMCI_RDR 0x0030 /* Receive Data */
110 #define ATMCI_TDR 0x0034 /* Transmit Data */
111 #define ATMCI_SR 0x0040 /* Status */
112 #define ATMCI_IER 0x0044 /* Interrupt Enable */
113 #define ATMCI_IDR 0x0048 /* Interrupt Disable */
114 #define ATMCI_IMR 0x004c /* Interrupt Mask */
115 #define ATMCI_CMDRDY BIT(0) /* Command Ready */
116 #define ATMCI_RXRDY BIT(1) /* Receiver Ready */
117 #define ATMCI_TXRDY BIT(2) /* Transmitter Ready */
118 #define ATMCI_BLKE BIT(3) /* Data Block Ended */
119 #define ATMCI_DTIP BIT(4) /* Data Transfer In Progress */
120 #define ATMCI_NOTBUSY BIT(5) /* Data Not Busy */
121 #define ATMCI_ENDRX BIT(6) /* End of RX Buffer */
122 #define ATMCI_ENDTX BIT(7) /* End of TX Buffer */
123 #define ATMCI_SDIOIRQA BIT(8) /* SDIO IRQ in slot A */
124 #define ATMCI_SDIOIRQB BIT(9) /* SDIO IRQ in slot B */
125 #define ATMCI_SDIOWAIT BIT(12) /* SDIO Read Wait Operation Status */
126 #define ATMCI_CSRCV BIT(13) /* CE-ATA Completion Signal Received */
127 #define ATMCI_RXBUFF BIT(14) /* RX Buffer Full */
128 #define ATMCI_TXBUFE BIT(15) /* TX Buffer Empty */
129 #define ATMCI_RINDE BIT(16) /* Response Index Error */
130 #define ATMCI_RDIRE BIT(17) /* Response Direction Error */
131 #define ATMCI_RCRCE BIT(18) /* Response CRC Error */
132 #define ATMCI_RENDE BIT(19) /* Response End Bit Error */
133 #define ATMCI_RTOE BIT(20) /* Response Time-Out Error */
134 #define ATMCI_DCRCE BIT(21) /* Data CRC Error */
135 #define ATMCI_DTOE BIT(22) /* Data Time-Out Error */
136 #define ATMCI_CSTOE BIT(23) /* Completion Signal Time-out Error */
137 #define ATMCI_BLKOVRE BIT(24) /* DMA Block Overrun Error */
138 #define ATMCI_DMADONE BIT(25) /* DMA Transfer Done */
139 #define ATMCI_FIFOEMPTY BIT(26) /* FIFO Empty Flag */
140 #define ATMCI_XFRDONE BIT(27) /* Transfer Done Flag */
141 #define ATMCI_ACKRCV BIT(28) /* Boot Operation Acknowledge Received */
142 #define ATMCI_ACKRCVE BIT(29) /* Boot Operation Acknowledge Error */
143 #define ATMCI_OVRE BIT(30) /* RX Overrun Error */
144 #define ATMCI_UNRE BIT(31) /* TX Underrun Error */
145 #define ATMCI_DMA 0x0050 /* DMA Configuration[2] */
146 #define ATMCI_DMA_OFFSET(x) ((x) << 0) /* DMA Write Buffer Offset */
147 #define ATMCI_DMA_CHKSIZE(x) ((x) << 4) /* DMA Channel Read and Write Chunk Size */
148 #define ATMCI_DMAEN BIT(8) /* DMA Hardware Handshaking Enable */
149 #define ATMCI_CFG 0x0054 /* Configuration[2] */
150 #define ATMCI_CFG_FIFOMODE_1DATA BIT(0) /* MCI Internal FIFO control mode */
151 #define ATMCI_CFG_FERRCTRL_COR BIT(4) /* Flow Error flag reset control mode */
152 #define ATMCI_CFG_HSMODE BIT(8) /* High Speed Mode */
153 #define ATMCI_CFG_LSYNC BIT(12) /* Synchronize on the last block */
154 #define ATMCI_WPMR 0x00e4 /* Write Protection Mode[2] */
155 #define ATMCI_WP_EN BIT(0) /* WP Enable */
156 #define ATMCI_WP_KEY (0x4d4349 << 8) /* WP Key */
157 #define ATMCI_WPSR 0x00e8 /* Write Protection Status[2] */
158 #define ATMCI_GET_WP_VS(x) ((x) & 0x0f)
159 #define ATMCI_GET_WP_VSRC(x) (((x) >> 8) & 0xffff)
160 #define ATMCI_VERSION 0x00FC /* Version */
161 #define ATMCI_FIFO_APERTURE 0x0200 /* FIFO Aperture[2] */
162
163 /* This is not including the FIFO Aperture on MCI2 */
164 #define ATMCI_REGS_SIZE 0x100
165
166 /* Register access macros */
167 #define atmci_readl(port, reg) \
168 __raw_readl((port)->regs + reg)
169 #define atmci_writel(port, reg, value) \
170 __raw_writel((value), (port)->regs + reg)
171
172 #define AUTOSUSPEND_DELAY 50
173
174 #define ATMCI_DATA_ERROR_FLAGS (ATMCI_DCRCE | ATMCI_DTOE | ATMCI_OVRE | ATMCI_UNRE)
175 #define ATMCI_DMA_THRESHOLD 16
176
177 enum {
178 EVENT_CMD_RDY = 0,
179 EVENT_XFER_COMPLETE,
180 EVENT_NOTBUSY,
181 EVENT_DATA_ERROR,
182 };
183
184 enum atmel_mci_state {
185 STATE_IDLE = 0,
186 STATE_SENDING_CMD,
187 STATE_DATA_XFER,
188 STATE_WAITING_NOTBUSY,
189 STATE_SENDING_STOP,
190 STATE_END_REQUEST,
191 };
192
193 enum atmci_xfer_dir {
194 XFER_RECEIVE = 0,
195 XFER_TRANSMIT,
196 };
197
198 enum atmci_pdc_buf {
199 PDC_FIRST_BUF = 0,
200 PDC_SECOND_BUF,
201 };
202
203 struct atmel_mci_caps {
204 bool has_dma_conf_reg;
205 bool has_pdc;
206 bool has_cfg_reg;
207 bool has_cstor_reg;
208 bool has_highspeed;
209 bool has_rwproof;
210 bool has_odd_clk_div;
211 bool has_bad_data_ordering;
212 bool need_reset_after_xfer;
213 bool need_blksz_mul_4;
214 bool need_notbusy_for_read_ops;
215 };
216
217 struct atmel_mci_dma {
218 struct dma_chan *chan;
219 struct dma_async_tx_descriptor *data_desc;
220 };
221
222 /**
223 * struct atmel_mci - MMC controller state shared between all slots
224 * @lock: Spinlock protecting the queue and associated data.
225 * @regs: Pointer to MMIO registers.
226 * @sg: Scatterlist entry currently being processed by PIO or PDC code.
227 * @pio_offset: Offset into the current scatterlist entry.
228 * @buffer: Buffer used if we don't have the r/w proof capability. We
229 * don't have the time to switch pdc buffers so we have to use only
230 * one buffer for the full transaction.
231 * @buf_size: size of the buffer.
232 * @phys_buf_addr: buffer address needed for pdc.
233 * @cur_slot: The slot which is currently using the controller.
234 * @mrq: The request currently being processed on @cur_slot,
235 * or NULL if the controller is idle.
236 * @cmd: The command currently being sent to the card, or NULL.
237 * @data: The data currently being transferred, or NULL if no data
238 * transfer is in progress.
239 * @data_size: just data->blocks * data->blksz.
240 * @dma: DMA client state.
241 * @data_chan: DMA channel being used for the current data transfer.
242 * @cmd_status: Snapshot of SR taken upon completion of the current
243 * command. Only valid when EVENT_CMD_COMPLETE is pending.
244 * @data_status: Snapshot of SR taken upon completion of the current
245 * data transfer. Only valid when EVENT_DATA_COMPLETE or
246 * EVENT_DATA_ERROR is pending.
247 * @stop_cmdr: Value to be loaded into CMDR when the stop command is
248 * to be sent.
249 * @tasklet: Tasklet running the request state machine.
250 * @pending_events: Bitmask of events flagged by the interrupt handler
251 * to be processed by the tasklet.
252 * @completed_events: Bitmask of events which the state machine has
253 * processed.
254 * @state: Tasklet state.
255 * @queue: List of slots waiting for access to the controller.
256 * @need_clock_update: Update the clock rate before the next request.
257 * @need_reset: Reset controller before next request.
258 * @timer: Timer to balance the data timeout error flag which cannot rise.
259 * @mode_reg: Value of the MR register.
260 * @cfg_reg: Value of the CFG register.
261 * @bus_hz: The rate of @mck in Hz. This forms the basis for MMC bus
262 * rate and timeout calculations.
263 * @mapbase: Physical address of the MMIO registers.
264 * @mck: The peripheral bus clock hooked up to the MMC controller.
265 * @pdev: Platform device associated with the MMC controller.
266 * @slot: Slots sharing this MMC controller.
267 * @caps: MCI capabilities depending on MCI version.
268 * @prepare_data: function to setup MCI before data transfer which
269 * depends on MCI capabilities.
270 * @submit_data: function to start data transfer which depends on MCI
271 * capabilities.
272 * @stop_transfer: function to stop data transfer which depends on MCI
273 * capabilities.
274 *
275 * Locking
276 * =======
277 *
278 * @lock is a softirq-safe spinlock protecting @queue as well as
279 * @cur_slot, @mrq and @state. These must always be updated
280 * at the same time while holding @lock.
281 *
282 * @lock also protects mode_reg and need_clock_update since these are
283 * used to synchronize mode register updates with the queue
284 * processing.
285 *
286 * The @mrq field of struct atmel_mci_slot is also protected by @lock,
287 * and must always be written at the same time as the slot is added to
288 * @queue.
289 *
290 * @pending_events and @completed_events are accessed using atomic bit
291 * operations, so they don't need any locking.
292 *
293 * None of the fields touched by the interrupt handler need any
294 * locking. However, ordering is important: Before EVENT_DATA_ERROR or
295 * EVENT_DATA_COMPLETE is set in @pending_events, all data-related
296 * interrupts must be disabled and @data_status updated with a
297 * snapshot of SR. Similarly, before EVENT_CMD_COMPLETE is set, the
298 * CMDRDY interrupt must be disabled and @cmd_status updated with a
299 * snapshot of SR, and before EVENT_XFER_COMPLETE can be set, the
300 * bytes_xfered field of @data must be written. This is ensured by
301 * using barriers.
302 */
303 struct atmel_mci {
304 spinlock_t lock;
305 void __iomem *regs;
306
307 struct scatterlist *sg;
308 unsigned int sg_len;
309 unsigned int pio_offset;
310 unsigned int *buffer;
311 unsigned int buf_size;
312 dma_addr_t buf_phys_addr;
313
314 struct atmel_mci_slot *cur_slot;
315 struct mmc_request *mrq;
316 struct mmc_command *cmd;
317 struct mmc_data *data;
318 unsigned int data_size;
319
320 struct atmel_mci_dma dma;
321 struct dma_chan *data_chan;
322 struct dma_slave_config dma_conf;
323
324 u32 cmd_status;
325 u32 data_status;
326 u32 stop_cmdr;
327
328 struct tasklet_struct tasklet;
329 unsigned long pending_events;
330 unsigned long completed_events;
331 enum atmel_mci_state state;
332 struct list_head queue;
333
334 bool need_clock_update;
335 bool need_reset;
336 struct timer_list timer;
337 u32 mode_reg;
338 u32 cfg_reg;
339 unsigned long bus_hz;
340 unsigned long mapbase;
341 struct clk *mck;
342 struct platform_device *pdev;
343
344 struct atmel_mci_slot *slot[ATMCI_MAX_NR_SLOTS];
345
346 struct atmel_mci_caps caps;
347
348 u32 (*prepare_data)(struct atmel_mci *host, struct mmc_data *data);
349 void (*submit_data)(struct atmel_mci *host, struct mmc_data *data);
350 void (*stop_transfer)(struct atmel_mci *host);
351 };
352
353 /**
354 * struct atmel_mci_slot - MMC slot state
355 * @mmc: The mmc_host representing this slot.
356 * @host: The MMC controller this slot is using.
357 * @sdc_reg: Value of SDCR to be written before using this slot.
358 * @sdio_irq: SDIO irq mask for this slot.
359 * @mrq: mmc_request currently being processed or waiting to be
360 * processed, or NULL when the slot is idle.
361 * @queue_node: List node for placing this node in the @queue list of
362 * &struct atmel_mci.
363 * @clock: Clock rate configured by set_ios(). Protected by host->lock.
364 * @flags: Random state bits associated with the slot.
365 * @detect_pin: GPIO pin used for card detection, or negative if not
366 * available.
367 * @wp_pin: GPIO pin used for card write protect sending, or negative
368 * if not available.
369 * @detect_is_active_high: The state of the detect pin when it is active.
370 * @detect_timer: Timer used for debouncing @detect_pin interrupts.
371 */
372 struct atmel_mci_slot {
373 struct mmc_host *mmc;
374 struct atmel_mci *host;
375
376 u32 sdc_reg;
377 u32 sdio_irq;
378
379 struct mmc_request *mrq;
380 struct list_head queue_node;
381
382 unsigned int clock;
383 unsigned long flags;
384 #define ATMCI_CARD_PRESENT 0
385 #define ATMCI_CARD_NEED_INIT 1
386 #define ATMCI_SHUTDOWN 2
387
388 int detect_pin;
389 int wp_pin;
390 bool detect_is_active_high;
391
392 struct timer_list detect_timer;
393 };
394
395 #define atmci_test_and_clear_pending(host, event) \
396 test_and_clear_bit(event, &host->pending_events)
397 #define atmci_set_completed(host, event) \
398 set_bit(event, &host->completed_events)
399 #define atmci_set_pending(host, event) \
400 set_bit(event, &host->pending_events)
401
402 /*
403 * The debugfs stuff below is mostly optimized away when
404 * CONFIG_DEBUG_FS is not set.
405 */
406 static int atmci_req_show(struct seq_file *s, void *v)
407 {
408 struct atmel_mci_slot *slot = s->private;
409 struct mmc_request *mrq;
410 struct mmc_command *cmd;
411 struct mmc_command *stop;
412 struct mmc_data *data;
413
414 /* Make sure we get a consistent snapshot */
415 spin_lock_bh(&slot->host->lock);
416 mrq = slot->mrq;
417
418 if (mrq) {
419 cmd = mrq->cmd;
420 data = mrq->data;
421 stop = mrq->stop;
422
423 if (cmd)
424 seq_printf(s,
425 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
426 cmd->opcode, cmd->arg, cmd->flags,
427 cmd->resp[0], cmd->resp[1], cmd->resp[2],
428 cmd->resp[3], cmd->error);
429 if (data)
430 seq_printf(s, "DATA %u / %u * %u flg %x err %d\n",
431 data->bytes_xfered, data->blocks,
432 data->blksz, data->flags, data->error);
433 if (stop)
434 seq_printf(s,
435 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
436 stop->opcode, stop->arg, stop->flags,
437 stop->resp[0], stop->resp[1], stop->resp[2],
438 stop->resp[3], stop->error);
439 }
440
441 spin_unlock_bh(&slot->host->lock);
442
443 return 0;
444 }
445
446 DEFINE_SHOW_ATTRIBUTE(atmci_req);
447
448 static void atmci_show_status_reg(struct seq_file *s,
449 const char *regname, u32 value)
450 {
451 static const char *sr_bit[] = {
452 [0] = "CMDRDY",
453 [1] = "RXRDY",
454 [2] = "TXRDY",
455 [3] = "BLKE",
456 [4] = "DTIP",
457 [5] = "NOTBUSY",
458 [6] = "ENDRX",
459 [7] = "ENDTX",
460 [8] = "SDIOIRQA",
461 [9] = "SDIOIRQB",
462 [12] = "SDIOWAIT",
463 [14] = "RXBUFF",
464 [15] = "TXBUFE",
465 [16] = "RINDE",
466 [17] = "RDIRE",
467 [18] = "RCRCE",
468 [19] = "RENDE",
469 [20] = "RTOE",
470 [21] = "DCRCE",
471 [22] = "DTOE",
472 [23] = "CSTOE",
473 [24] = "BLKOVRE",
474 [25] = "DMADONE",
475 [26] = "FIFOEMPTY",
476 [27] = "XFRDONE",
477 [30] = "OVRE",
478 [31] = "UNRE",
479 };
480 unsigned int i;
481
482 seq_printf(s, "%s:\t0x%08x", regname, value);
483 for (i = 0; i < ARRAY_SIZE(sr_bit); i++) {
484 if (value & (1 << i)) {
485 if (sr_bit[i])
486 seq_printf(s, " %s", sr_bit[i]);
487 else
488 seq_puts(s, " UNKNOWN");
489 }
490 }
491 seq_putc(s, '\n');
492 }
493
494 static int atmci_regs_show(struct seq_file *s, void *v)
495 {
496 struct atmel_mci *host = s->private;
497 u32 *buf;
498 int ret = 0;
499
500
501 buf = kmalloc(ATMCI_REGS_SIZE, GFP_KERNEL);
502 if (!buf)
503 return -ENOMEM;
504
505 pm_runtime_get_sync(&host->pdev->dev);
506
507 /*
508 * Grab a more or less consistent snapshot. Note that we're
509 * not disabling interrupts, so IMR and SR may not be
510 * consistent.
511 */
512 spin_lock_bh(&host->lock);
513 memcpy_fromio(buf, host->regs, ATMCI_REGS_SIZE);
514 spin_unlock_bh(&host->lock);
515
516 pm_runtime_mark_last_busy(&host->pdev->dev);
517 pm_runtime_put_autosuspend(&host->pdev->dev);
518
519 seq_printf(s, "MR:\t0x%08x%s%s ",
520 buf[ATMCI_MR / 4],
521 buf[ATMCI_MR / 4] & ATMCI_MR_RDPROOF ? " RDPROOF" : "",
522 buf[ATMCI_MR / 4] & ATMCI_MR_WRPROOF ? " WRPROOF" : "");
523 if (host->caps.has_odd_clk_div)
524 seq_printf(s, "{CLKDIV,CLKODD}=%u\n",
525 ((buf[ATMCI_MR / 4] & 0xff) << 1)
526 | ((buf[ATMCI_MR / 4] >> 16) & 1));
527 else
528 seq_printf(s, "CLKDIV=%u\n",
529 (buf[ATMCI_MR / 4] & 0xff));
530 seq_printf(s, "DTOR:\t0x%08x\n", buf[ATMCI_DTOR / 4]);
531 seq_printf(s, "SDCR:\t0x%08x\n", buf[ATMCI_SDCR / 4]);
532 seq_printf(s, "ARGR:\t0x%08x\n", buf[ATMCI_ARGR / 4]);
533 seq_printf(s, "BLKR:\t0x%08x BCNT=%u BLKLEN=%u\n",
534 buf[ATMCI_BLKR / 4],
535 buf[ATMCI_BLKR / 4] & 0xffff,
536 (buf[ATMCI_BLKR / 4] >> 16) & 0xffff);
537 if (host->caps.has_cstor_reg)
538 seq_printf(s, "CSTOR:\t0x%08x\n", buf[ATMCI_CSTOR / 4]);
539
540 /* Don't read RSPR and RDR; it will consume the data there */
541
542 atmci_show_status_reg(s, "SR", buf[ATMCI_SR / 4]);
543 atmci_show_status_reg(s, "IMR", buf[ATMCI_IMR / 4]);
544
545 if (host->caps.has_dma_conf_reg) {
546 u32 val;
547
548 val = buf[ATMCI_DMA / 4];
549 seq_printf(s, "DMA:\t0x%08x OFFSET=%u CHKSIZE=%u%s\n",
550 val, val & 3,
551 ((val >> 4) & 3) ?
552 1 << (((val >> 4) & 3) + 1) : 1,
553 val & ATMCI_DMAEN ? " DMAEN" : "");
554 }
555 if (host->caps.has_cfg_reg) {
556 u32 val;
557
558 val = buf[ATMCI_CFG / 4];
559 seq_printf(s, "CFG:\t0x%08x%s%s%s%s\n",
560 val,
561 val & ATMCI_CFG_FIFOMODE_1DATA ? " FIFOMODE_ONE_DATA" : "",
562 val & ATMCI_CFG_FERRCTRL_COR ? " FERRCTRL_CLEAR_ON_READ" : "",
563 val & ATMCI_CFG_HSMODE ? " HSMODE" : "",
564 val & ATMCI_CFG_LSYNC ? " LSYNC" : "");
565 }
566
567 kfree(buf);
568
569 return ret;
570 }
571
572 DEFINE_SHOW_ATTRIBUTE(atmci_regs);
573
574 static void atmci_init_debugfs(struct atmel_mci_slot *slot)
575 {
576 struct mmc_host *mmc = slot->mmc;
577 struct atmel_mci *host = slot->host;
578 struct dentry *root;
579
580 root = mmc->debugfs_root;
581 if (!root)
582 return;
583
584 debugfs_create_file("regs", S_IRUSR, root, host, &atmci_regs_fops);
585 debugfs_create_file("req", S_IRUSR, root, slot, &atmci_req_fops);
586 debugfs_create_u32("state", S_IRUSR, root, &host->state);
587 debugfs_create_xul("pending_events", S_IRUSR, root,
588 &host->pending_events);
589 debugfs_create_xul("completed_events", S_IRUSR, root,
590 &host->completed_events);
591 }
592
593 #if defined(CONFIG_OF)
594 static const struct of_device_id atmci_dt_ids[] = {
595 { .compatible = "atmel,hsmci" },
596 { /* sentinel */ }
597 };
598
599 MODULE_DEVICE_TABLE(of, atmci_dt_ids);
600
601 static struct mci_platform_data*
602 atmci_of_init(struct platform_device *pdev)
603 {
604 struct device_node *np = pdev->dev.of_node;
605 struct device_node *cnp;
606 struct mci_platform_data *pdata;
607 u32 slot_id;
608
609 if (!np) {
610 dev_err(&pdev->dev, "device node not found\n");
611 return ERR_PTR(-EINVAL);
612 }
613
614 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
615 if (!pdata)
616 return ERR_PTR(-ENOMEM);
617
618 for_each_child_of_node(np, cnp) {
619 if (of_property_read_u32(cnp, "reg", &slot_id)) {
620 dev_warn(&pdev->dev, "reg property is missing for %pOF\n",
621 cnp);
622 continue;
623 }
624
625 if (slot_id >= ATMCI_MAX_NR_SLOTS) {
626 dev_warn(&pdev->dev, "can't have more than %d slots\n",
627 ATMCI_MAX_NR_SLOTS);
628 of_node_put(cnp);
629 break;
630 }
631
632 if (of_property_read_u32(cnp, "bus-width",
633 &pdata->slot[slot_id].bus_width))
634 pdata->slot[slot_id].bus_width = 1;
635
636 pdata->slot[slot_id].detect_pin =
637 of_get_named_gpio(cnp, "cd-gpios", 0);
638
639 pdata->slot[slot_id].detect_is_active_high =
640 of_property_read_bool(cnp, "cd-inverted");
641
642 pdata->slot[slot_id].non_removable =
643 of_property_read_bool(cnp, "non-removable");
644
645 pdata->slot[slot_id].wp_pin =
646 of_get_named_gpio(cnp, "wp-gpios", 0);
647 }
648
649 return pdata;
650 }
651 #else /* CONFIG_OF */
652 static inline struct mci_platform_data*
653 atmci_of_init(struct platform_device *dev)
654 {
655 return ERR_PTR(-EINVAL);
656 }
657 #endif
658
659 static inline unsigned int atmci_get_version(struct atmel_mci *host)
660 {
661 return atmci_readl(host, ATMCI_VERSION) & 0x00000fff;
662 }
663
664 /*
665 * Fix sconfig's burst size according to atmel MCI. We need to convert them as:
666 * 1 -> 0, 4 -> 1, 8 -> 2, 16 -> 3.
667 * With version 0x600, we need to convert them as: 1 -> 0, 2 -> 1, 4 -> 2,
668 * 8 -> 3, 16 -> 4.
669 *
670 * This can be done by finding most significant bit set.
671 */
672 static inline unsigned int atmci_convert_chksize(struct atmel_mci *host,
673 unsigned int maxburst)
674 {
675 unsigned int version = atmci_get_version(host);
676 unsigned int offset = 2;
677
678 if (version >= 0x600)
679 offset = 1;
680
681 if (maxburst > 1)
682 return fls(maxburst) - offset;
683 else
684 return 0;
685 }
686
687 static void atmci_timeout_timer(struct timer_list *t)
688 {
689 struct atmel_mci *host;
690
691 host = from_timer(host, t, timer);
692
693 dev_dbg(&host->pdev->dev, "software timeout\n");
694
695 if (host->mrq->cmd->data) {
696 host->mrq->cmd->data->error = -ETIMEDOUT;
697 host->data = NULL;
698 /*
699 * With some SDIO modules, sometimes DMA transfer hangs. If
700 * stop_transfer() is not called then the DMA request is not
701 * removed, following ones are queued and never computed.
702 */
703 if (host->state == STATE_DATA_XFER)
704 host->stop_transfer(host);
705 } else {
706 host->mrq->cmd->error = -ETIMEDOUT;
707 host->cmd = NULL;
708 }
709 host->need_reset = 1;
710 host->state = STATE_END_REQUEST;
711 smp_wmb();
712 tasklet_schedule(&host->tasklet);
713 }
714
715 static inline unsigned int atmci_ns_to_clocks(struct atmel_mci *host,
716 unsigned int ns)
717 {
718 /*
719 * It is easier here to use us instead of ns for the timeout,
720 * it prevents from overflows during calculation.
721 */
722 unsigned int us = DIV_ROUND_UP(ns, 1000);
723
724 /* Maximum clock frequency is host->bus_hz/2 */
725 return us * (DIV_ROUND_UP(host->bus_hz, 2000000));
726 }
727
728 static void atmci_set_timeout(struct atmel_mci *host,
729 struct atmel_mci_slot *slot, struct mmc_data *data)
730 {
731 static unsigned dtomul_to_shift[] = {
732 0, 4, 7, 8, 10, 12, 16, 20
733 };
734 unsigned timeout;
735 unsigned dtocyc;
736 unsigned dtomul;
737
738 timeout = atmci_ns_to_clocks(host, data->timeout_ns)
739 + data->timeout_clks;
740
741 for (dtomul = 0; dtomul < 8; dtomul++) {
742 unsigned shift = dtomul_to_shift[dtomul];
743 dtocyc = (timeout + (1 << shift) - 1) >> shift;
744 if (dtocyc < 15)
745 break;
746 }
747
748 if (dtomul >= 8) {
749 dtomul = 7;
750 dtocyc = 15;
751 }
752
753 dev_vdbg(&slot->mmc->class_dev, "setting timeout to %u cycles\n",
754 dtocyc << dtomul_to_shift[dtomul]);
755 atmci_writel(host, ATMCI_DTOR, (ATMCI_DTOMUL(dtomul) | ATMCI_DTOCYC(dtocyc)));
756 }
757
758 /*
759 * Return mask with command flags to be enabled for this command.
760 */
761 static u32 atmci_prepare_command(struct mmc_host *mmc,
762 struct mmc_command *cmd)
763 {
764 struct mmc_data *data;
765 u32 cmdr;
766
767 cmd->error = -EINPROGRESS;
768
769 cmdr = ATMCI_CMDR_CMDNB(cmd->opcode);
770
771 if (cmd->flags & MMC_RSP_PRESENT) {
772 if (cmd->flags & MMC_RSP_136)
773 cmdr |= ATMCI_CMDR_RSPTYP_136BIT;
774 else
775 cmdr |= ATMCI_CMDR_RSPTYP_48BIT;
776 }
777
778 /*
779 * This should really be MAXLAT_5 for CMD2 and ACMD41, but
780 * it's too difficult to determine whether this is an ACMD or
781 * not. Better make it 64.
782 */
783 cmdr |= ATMCI_CMDR_MAXLAT_64CYC;
784
785 if (mmc->ios.bus_mode == MMC_BUSMODE_OPENDRAIN)
786 cmdr |= ATMCI_CMDR_OPDCMD;
787
788 data = cmd->data;
789 if (data) {
790 cmdr |= ATMCI_CMDR_START_XFER;
791
792 if (cmd->opcode == SD_IO_RW_EXTENDED) {
793 cmdr |= ATMCI_CMDR_SDIO_BLOCK;
794 } else {
795 if (data->blocks > 1)
796 cmdr |= ATMCI_CMDR_MULTI_BLOCK;
797 else
798 cmdr |= ATMCI_CMDR_BLOCK;
799 }
800
801 if (data->flags & MMC_DATA_READ)
802 cmdr |= ATMCI_CMDR_TRDIR_READ;
803 }
804
805 return cmdr;
806 }
807
808 static void atmci_send_command(struct atmel_mci *host,
809 struct mmc_command *cmd, u32 cmd_flags)
810 {
811 WARN_ON(host->cmd);
812 host->cmd = cmd;
813
814 dev_vdbg(&host->pdev->dev,
815 "start command: ARGR=0x%08x CMDR=0x%08x\n",
816 cmd->arg, cmd_flags);
817
818 atmci_writel(host, ATMCI_ARGR, cmd->arg);
819 atmci_writel(host, ATMCI_CMDR, cmd_flags);
820 }
821
822 static void atmci_send_stop_cmd(struct atmel_mci *host, struct mmc_data *data)
823 {
824 dev_dbg(&host->pdev->dev, "send stop command\n");
825 atmci_send_command(host, data->stop, host->stop_cmdr);
826 atmci_writel(host, ATMCI_IER, ATMCI_CMDRDY);
827 }
828
829 /*
830 * Configure given PDC buffer taking care of alignement issues.
831 * Update host->data_size and host->sg.
832 */
833 static void atmci_pdc_set_single_buf(struct atmel_mci *host,
834 enum atmci_xfer_dir dir, enum atmci_pdc_buf buf_nb)
835 {
836 u32 pointer_reg, counter_reg;
837 unsigned int buf_size;
838
839 if (dir == XFER_RECEIVE) {
840 pointer_reg = ATMEL_PDC_RPR;
841 counter_reg = ATMEL_PDC_RCR;
842 } else {
843 pointer_reg = ATMEL_PDC_TPR;
844 counter_reg = ATMEL_PDC_TCR;
845 }
846
847 if (buf_nb == PDC_SECOND_BUF) {
848 pointer_reg += ATMEL_PDC_SCND_BUF_OFF;
849 counter_reg += ATMEL_PDC_SCND_BUF_OFF;
850 }
851
852 if (!host->caps.has_rwproof) {
853 buf_size = host->buf_size;
854 atmci_writel(host, pointer_reg, host->buf_phys_addr);
855 } else {
856 buf_size = sg_dma_len(host->sg);
857 atmci_writel(host, pointer_reg, sg_dma_address(host->sg));
858 }
859
860 if (host->data_size <= buf_size) {
861 if (host->data_size & 0x3) {
862 /* If size is different from modulo 4, transfer bytes */
863 atmci_writel(host, counter_reg, host->data_size);
864 atmci_writel(host, ATMCI_MR, host->mode_reg | ATMCI_MR_PDCFBYTE);
865 } else {
866 /* Else transfer 32-bits words */
867 atmci_writel(host, counter_reg, host->data_size / 4);
868 }
869 host->data_size = 0;
870 } else {
871 /* We assume the size of a page is 32-bits aligned */
872 atmci_writel(host, counter_reg, sg_dma_len(host->sg) / 4);
873 host->data_size -= sg_dma_len(host->sg);
874 if (host->data_size)
875 host->sg = sg_next(host->sg);
876 }
877 }
878
879 /*
880 * Configure PDC buffer according to the data size ie configuring one or two
881 * buffers. Don't use this function if you want to configure only the second
882 * buffer. In this case, use atmci_pdc_set_single_buf.
883 */
884 static void atmci_pdc_set_both_buf(struct atmel_mci *host, int dir)
885 {
886 atmci_pdc_set_single_buf(host, dir, PDC_FIRST_BUF);
887 if (host->data_size)
888 atmci_pdc_set_single_buf(host, dir, PDC_SECOND_BUF);
889 }
890
891 /*
892 * Unmap sg lists, called when transfer is finished.
893 */
894 static void atmci_pdc_cleanup(struct atmel_mci *host)
895 {
896 struct mmc_data *data = host->data;
897
898 if (data)
899 dma_unmap_sg(&host->pdev->dev,
900 data->sg, data->sg_len,
901 mmc_get_dma_dir(data));
902 }
903
904 /*
905 * Disable PDC transfers. Update pending flags to EVENT_XFER_COMPLETE after
906 * having received ATMCI_TXBUFE or ATMCI_RXBUFF interrupt. Enable ATMCI_NOTBUSY
907 * interrupt needed for both transfer directions.
908 */
909 static void atmci_pdc_complete(struct atmel_mci *host)
910 {
911 int transfer_size = host->data->blocks * host->data->blksz;
912 int i;
913
914 atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS);
915
916 if ((!host->caps.has_rwproof)
917 && (host->data->flags & MMC_DATA_READ)) {
918 if (host->caps.has_bad_data_ordering)
919 for (i = 0; i < transfer_size; i++)
920 host->buffer[i] = swab32(host->buffer[i]);
921 sg_copy_from_buffer(host->data->sg, host->data->sg_len,
922 host->buffer, transfer_size);
923 }
924
925 atmci_pdc_cleanup(host);
926
927 dev_dbg(&host->pdev->dev, "(%s) set pending xfer complete\n", __func__);
928 atmci_set_pending(host, EVENT_XFER_COMPLETE);
929 tasklet_schedule(&host->tasklet);
930 }
931
932 static void atmci_dma_cleanup(struct atmel_mci *host)
933 {
934 struct mmc_data *data = host->data;
935
936 if (data)
937 dma_unmap_sg(host->dma.chan->device->dev,
938 data->sg, data->sg_len,
939 mmc_get_dma_dir(data));
940 }
941
942 /*
943 * This function is called by the DMA driver from tasklet context.
944 */
945 static void atmci_dma_complete(void *arg)
946 {
947 struct atmel_mci *host = arg;
948 struct mmc_data *data = host->data;
949
950 dev_vdbg(&host->pdev->dev, "DMA complete\n");
951
952 if (host->caps.has_dma_conf_reg)
953 /* Disable DMA hardware handshaking on MCI */
954 atmci_writel(host, ATMCI_DMA, atmci_readl(host, ATMCI_DMA) & ~ATMCI_DMAEN);
955
956 atmci_dma_cleanup(host);
957
958 /*
959 * If the card was removed, data will be NULL. No point trying
960 * to send the stop command or waiting for NBUSY in this case.
961 */
962 if (data) {
963 dev_dbg(&host->pdev->dev,
964 "(%s) set pending xfer complete\n", __func__);
965 atmci_set_pending(host, EVENT_XFER_COMPLETE);
966 tasklet_schedule(&host->tasklet);
967
968 /*
969 * Regardless of what the documentation says, we have
970 * to wait for NOTBUSY even after block read
971 * operations.
972 *
973 * When the DMA transfer is complete, the controller
974 * may still be reading the CRC from the card, i.e.
975 * the data transfer is still in progress and we
976 * haven't seen all the potential error bits yet.
977 *
978 * The interrupt handler will schedule a different
979 * tasklet to finish things up when the data transfer
980 * is completely done.
981 *
982 * We may not complete the mmc request here anyway
983 * because the mmc layer may call back and cause us to
984 * violate the "don't submit new operations from the
985 * completion callback" rule of the dma engine
986 * framework.
987 */
988 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
989 }
990 }
991
992 /*
993 * Returns a mask of interrupt flags to be enabled after the whole
994 * request has been prepared.
995 */
996 static u32 atmci_prepare_data(struct atmel_mci *host, struct mmc_data *data)
997 {
998 u32 iflags;
999
1000 data->error = -EINPROGRESS;
1001
1002 host->sg = data->sg;
1003 host->sg_len = data->sg_len;
1004 host->data = data;
1005 host->data_chan = NULL;
1006
1007 iflags = ATMCI_DATA_ERROR_FLAGS;
1008
1009 /*
1010 * Errata: MMC data write operation with less than 12
1011 * bytes is impossible.
1012 *
1013 * Errata: MCI Transmit Data Register (TDR) FIFO
1014 * corruption when length is not multiple of 4.
1015 */
1016 if (data->blocks * data->blksz < 12
1017 || (data->blocks * data->blksz) & 3)
1018 host->need_reset = true;
1019
1020 host->pio_offset = 0;
1021 if (data->flags & MMC_DATA_READ)
1022 iflags |= ATMCI_RXRDY;
1023 else
1024 iflags |= ATMCI_TXRDY;
1025
1026 return iflags;
1027 }
1028
1029 /*
1030 * Set interrupt flags and set block length into the MCI mode register even
1031 * if this value is also accessible in the MCI block register. It seems to be
1032 * necessary before the High Speed MCI version. It also map sg and configure
1033 * PDC registers.
1034 */
1035 static u32
1036 atmci_prepare_data_pdc(struct atmel_mci *host, struct mmc_data *data)
1037 {
1038 u32 iflags, tmp;
1039 int i;
1040
1041 data->error = -EINPROGRESS;
1042
1043 host->data = data;
1044 host->sg = data->sg;
1045 iflags = ATMCI_DATA_ERROR_FLAGS;
1046
1047 /* Enable pdc mode */
1048 atmci_writel(host, ATMCI_MR, host->mode_reg | ATMCI_MR_PDCMODE);
1049
1050 if (data->flags & MMC_DATA_READ)
1051 iflags |= ATMCI_ENDRX | ATMCI_RXBUFF;
1052 else
1053 iflags |= ATMCI_ENDTX | ATMCI_TXBUFE | ATMCI_BLKE;
1054
1055 /* Set BLKLEN */
1056 tmp = atmci_readl(host, ATMCI_MR);
1057 tmp &= 0x0000ffff;
1058 tmp |= ATMCI_BLKLEN(data->blksz);
1059 atmci_writel(host, ATMCI_MR, tmp);
1060
1061 /* Configure PDC */
1062 host->data_size = data->blocks * data->blksz;
1063 dma_map_sg(&host->pdev->dev, data->sg, data->sg_len,
1064 mmc_get_dma_dir(data));
1065
1066 if ((!host->caps.has_rwproof)
1067 && (host->data->flags & MMC_DATA_WRITE)) {
1068 sg_copy_to_buffer(host->data->sg, host->data->sg_len,
1069 host->buffer, host->data_size);
1070 if (host->caps.has_bad_data_ordering)
1071 for (i = 0; i < host->data_size; i++)
1072 host->buffer[i] = swab32(host->buffer[i]);
1073 }
1074
1075 if (host->data_size)
1076 atmci_pdc_set_both_buf(host, data->flags & MMC_DATA_READ ?
1077 XFER_RECEIVE : XFER_TRANSMIT);
1078 return iflags;
1079 }
1080
1081 static u32
1082 atmci_prepare_data_dma(struct atmel_mci *host, struct mmc_data *data)
1083 {
1084 struct dma_chan *chan;
1085 struct dma_async_tx_descriptor *desc;
1086 struct scatterlist *sg;
1087 unsigned int i;
1088 enum dma_transfer_direction slave_dirn;
1089 unsigned int sglen;
1090 u32 maxburst;
1091 u32 iflags;
1092
1093 data->error = -EINPROGRESS;
1094
1095 WARN_ON(host->data);
1096 host->sg = NULL;
1097 host->data = data;
1098
1099 iflags = ATMCI_DATA_ERROR_FLAGS;
1100
1101 /*
1102 * We don't do DMA on "complex" transfers, i.e. with
1103 * non-word-aligned buffers or lengths. Also, we don't bother
1104 * with all the DMA setup overhead for short transfers.
1105 */
1106 if (data->blocks * data->blksz < ATMCI_DMA_THRESHOLD)
1107 return atmci_prepare_data(host, data);
1108 if (data->blksz & 3)
1109 return atmci_prepare_data(host, data);
1110
1111 for_each_sg(data->sg, sg, data->sg_len, i) {
1112 if (sg->offset & 3 || sg->length & 3)
1113 return atmci_prepare_data(host, data);
1114 }
1115
1116 /* If we don't have a channel, we can't do DMA */
1117 chan = host->dma.chan;
1118 if (chan)
1119 host->data_chan = chan;
1120
1121 if (!chan)
1122 return -ENODEV;
1123
1124 if (data->flags & MMC_DATA_READ) {
1125 host->dma_conf.direction = slave_dirn = DMA_DEV_TO_MEM;
1126 maxburst = atmci_convert_chksize(host,
1127 host->dma_conf.src_maxburst);
1128 } else {
1129 host->dma_conf.direction = slave_dirn = DMA_MEM_TO_DEV;
1130 maxburst = atmci_convert_chksize(host,
1131 host->dma_conf.dst_maxburst);
1132 }
1133
1134 if (host->caps.has_dma_conf_reg)
1135 atmci_writel(host, ATMCI_DMA, ATMCI_DMA_CHKSIZE(maxburst) |
1136 ATMCI_DMAEN);
1137
1138 sglen = dma_map_sg(chan->device->dev, data->sg,
1139 data->sg_len, mmc_get_dma_dir(data));
1140
1141 dmaengine_slave_config(chan, &host->dma_conf);
1142 desc = dmaengine_prep_slave_sg(chan,
1143 data->sg, sglen, slave_dirn,
1144 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1145 if (!desc)
1146 goto unmap_exit;
1147
1148 host->dma.data_desc = desc;
1149 desc->callback = atmci_dma_complete;
1150 desc->callback_param = host;
1151
1152 return iflags;
1153 unmap_exit:
1154 dma_unmap_sg(chan->device->dev, data->sg, data->sg_len,
1155 mmc_get_dma_dir(data));
1156 return -ENOMEM;
1157 }
1158
1159 static void
1160 atmci_submit_data(struct atmel_mci *host, struct mmc_data *data)
1161 {
1162 return;
1163 }
1164
1165 /*
1166 * Start PDC according to transfer direction.
1167 */
1168 static void
1169 atmci_submit_data_pdc(struct atmel_mci *host, struct mmc_data *data)
1170 {
1171 if (data->flags & MMC_DATA_READ)
1172 atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN);
1173 else
1174 atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
1175 }
1176
1177 static void
1178 atmci_submit_data_dma(struct atmel_mci *host, struct mmc_data *data)
1179 {
1180 struct dma_chan *chan = host->data_chan;
1181 struct dma_async_tx_descriptor *desc = host->dma.data_desc;
1182
1183 if (chan) {
1184 dmaengine_submit(desc);
1185 dma_async_issue_pending(chan);
1186 }
1187 }
1188
1189 static void atmci_stop_transfer(struct atmel_mci *host)
1190 {
1191 dev_dbg(&host->pdev->dev,
1192 "(%s) set pending xfer complete\n", __func__);
1193 atmci_set_pending(host, EVENT_XFER_COMPLETE);
1194 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1195 }
1196
1197 /*
1198 * Stop data transfer because error(s) occurred.
1199 */
1200 static void atmci_stop_transfer_pdc(struct atmel_mci *host)
1201 {
1202 atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS);
1203 }
1204
1205 static void atmci_stop_transfer_dma(struct atmel_mci *host)
1206 {
1207 struct dma_chan *chan = host->data_chan;
1208
1209 if (chan) {
1210 dmaengine_terminate_all(chan);
1211 atmci_dma_cleanup(host);
1212 } else {
1213 /* Data transfer was stopped by the interrupt handler */
1214 dev_dbg(&host->pdev->dev,
1215 "(%s) set pending xfer complete\n", __func__);
1216 atmci_set_pending(host, EVENT_XFER_COMPLETE);
1217 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1218 }
1219 }
1220
1221 /*
1222 * Start a request: prepare data if needed, prepare the command and activate
1223 * interrupts.
1224 */
1225 static void atmci_start_request(struct atmel_mci *host,
1226 struct atmel_mci_slot *slot)
1227 {
1228 struct mmc_request *mrq;
1229 struct mmc_command *cmd;
1230 struct mmc_data *data;
1231 u32 iflags;
1232 u32 cmdflags;
1233
1234 mrq = slot->mrq;
1235 host->cur_slot = slot;
1236 host->mrq = mrq;
1237
1238 host->pending_events = 0;
1239 host->completed_events = 0;
1240 host->cmd_status = 0;
1241 host->data_status = 0;
1242
1243 dev_dbg(&host->pdev->dev, "start request: cmd %u\n", mrq->cmd->opcode);
1244
1245 if (host->need_reset || host->caps.need_reset_after_xfer) {
1246 iflags = atmci_readl(host, ATMCI_IMR);
1247 iflags &= (ATMCI_SDIOIRQA | ATMCI_SDIOIRQB);
1248 atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
1249 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIEN);
1250 atmci_writel(host, ATMCI_MR, host->mode_reg);
1251 if (host->caps.has_cfg_reg)
1252 atmci_writel(host, ATMCI_CFG, host->cfg_reg);
1253 atmci_writel(host, ATMCI_IER, iflags);
1254 host->need_reset = false;
1255 }
1256 atmci_writel(host, ATMCI_SDCR, slot->sdc_reg);
1257
1258 iflags = atmci_readl(host, ATMCI_IMR);
1259 if (iflags & ~(ATMCI_SDIOIRQA | ATMCI_SDIOIRQB))
1260 dev_dbg(&slot->mmc->class_dev, "WARNING: IMR=0x%08x\n",
1261 iflags);
1262
1263 if (unlikely(test_and_clear_bit(ATMCI_CARD_NEED_INIT, &slot->flags))) {
1264 /* Send init sequence (74 clock cycles) */
1265 atmci_writel(host, ATMCI_CMDR, ATMCI_CMDR_SPCMD_INIT);
1266 while (!(atmci_readl(host, ATMCI_SR) & ATMCI_CMDRDY))
1267 cpu_relax();
1268 }
1269 iflags = 0;
1270 data = mrq->data;
1271 if (data) {
1272 atmci_set_timeout(host, slot, data);
1273
1274 /* Must set block count/size before sending command */
1275 atmci_writel(host, ATMCI_BLKR, ATMCI_BCNT(data->blocks)
1276 | ATMCI_BLKLEN(data->blksz));
1277 dev_vdbg(&slot->mmc->class_dev, "BLKR=0x%08x\n",
1278 ATMCI_BCNT(data->blocks) | ATMCI_BLKLEN(data->blksz));
1279
1280 iflags |= host->prepare_data(host, data);
1281 }
1282
1283 iflags |= ATMCI_CMDRDY;
1284 cmd = mrq->cmd;
1285 cmdflags = atmci_prepare_command(slot->mmc, cmd);
1286
1287 /*
1288 * DMA transfer should be started before sending the command to avoid
1289 * unexpected errors especially for read operations in SDIO mode.
1290 * Unfortunately, in PDC mode, command has to be sent before starting
1291 * the transfer.
1292 */
1293 if (host->submit_data != &atmci_submit_data_dma)
1294 atmci_send_command(host, cmd, cmdflags);
1295
1296 if (data)
1297 host->submit_data(host, data);
1298
1299 if (host->submit_data == &atmci_submit_data_dma)
1300 atmci_send_command(host, cmd, cmdflags);
1301
1302 if (mrq->stop) {
1303 host->stop_cmdr = atmci_prepare_command(slot->mmc, mrq->stop);
1304 host->stop_cmdr |= ATMCI_CMDR_STOP_XFER;
1305 if (!(data->flags & MMC_DATA_WRITE))
1306 host->stop_cmdr |= ATMCI_CMDR_TRDIR_READ;
1307 host->stop_cmdr |= ATMCI_CMDR_MULTI_BLOCK;
1308 }
1309
1310 /*
1311 * We could have enabled interrupts earlier, but I suspect
1312 * that would open up a nice can of interesting race
1313 * conditions (e.g. command and data complete, but stop not
1314 * prepared yet.)
1315 */
1316 atmci_writel(host, ATMCI_IER, iflags);
1317
1318 mod_timer(&host->timer, jiffies + msecs_to_jiffies(2000));
1319 }
1320
1321 static void atmci_queue_request(struct atmel_mci *host,
1322 struct atmel_mci_slot *slot, struct mmc_request *mrq)
1323 {
1324 dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n",
1325 host->state);
1326
1327 spin_lock_bh(&host->lock);
1328 slot->mrq = mrq;
1329 if (host->state == STATE_IDLE) {
1330 host->state = STATE_SENDING_CMD;
1331 atmci_start_request(host, slot);
1332 } else {
1333 dev_dbg(&host->pdev->dev, "queue request\n");
1334 list_add_tail(&slot->queue_node, &host->queue);
1335 }
1336 spin_unlock_bh(&host->lock);
1337 }
1338
1339 static void atmci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1340 {
1341 struct atmel_mci_slot *slot = mmc_priv(mmc);
1342 struct atmel_mci *host = slot->host;
1343 struct mmc_data *data;
1344
1345 WARN_ON(slot->mrq);
1346 dev_dbg(&host->pdev->dev, "MRQ: cmd %u\n", mrq->cmd->opcode);
1347
1348 /*
1349 * We may "know" the card is gone even though there's still an
1350 * electrical connection. If so, we really need to communicate
1351 * this to the MMC core since there won't be any more
1352 * interrupts as the card is completely removed. Otherwise,
1353 * the MMC core might believe the card is still there even
1354 * though the card was just removed very slowly.
1355 */
1356 if (!test_bit(ATMCI_CARD_PRESENT, &slot->flags)) {
1357 mrq->cmd->error = -ENOMEDIUM;
1358 mmc_request_done(mmc, mrq);
1359 return;
1360 }
1361
1362 /* We don't support multiple blocks of weird lengths. */
1363 data = mrq->data;
1364 if (data && data->blocks > 1 && data->blksz & 3) {
1365 mrq->cmd->error = -EINVAL;
1366 mmc_request_done(mmc, mrq);
1367 }
1368
1369 atmci_queue_request(host, slot, mrq);
1370 }
1371
1372 static void atmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1373 {
1374 struct atmel_mci_slot *slot = mmc_priv(mmc);
1375 struct atmel_mci *host = slot->host;
1376 unsigned int i;
1377
1378 slot->sdc_reg &= ~ATMCI_SDCBUS_MASK;
1379 switch (ios->bus_width) {
1380 case MMC_BUS_WIDTH_1:
1381 slot->sdc_reg |= ATMCI_SDCBUS_1BIT;
1382 break;
1383 case MMC_BUS_WIDTH_4:
1384 slot->sdc_reg |= ATMCI_SDCBUS_4BIT;
1385 break;
1386 case MMC_BUS_WIDTH_8:
1387 slot->sdc_reg |= ATMCI_SDCBUS_8BIT;
1388 break;
1389 }
1390
1391 if (ios->clock) {
1392 unsigned int clock_min = ~0U;
1393 int clkdiv;
1394
1395 spin_lock_bh(&host->lock);
1396 if (!host->mode_reg) {
1397 atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
1398 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIEN);
1399 if (host->caps.has_cfg_reg)
1400 atmci_writel(host, ATMCI_CFG, host->cfg_reg);
1401 }
1402
1403 /*
1404 * Use mirror of ios->clock to prevent race with mmc
1405 * core ios update when finding the minimum.
1406 */
1407 slot->clock = ios->clock;
1408 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
1409 if (host->slot[i] && host->slot[i]->clock
1410 && host->slot[i]->clock < clock_min)
1411 clock_min = host->slot[i]->clock;
1412 }
1413
1414 /* Calculate clock divider */
1415 if (host->caps.has_odd_clk_div) {
1416 clkdiv = DIV_ROUND_UP(host->bus_hz, clock_min) - 2;
1417 if (clkdiv < 0) {
1418 dev_warn(&mmc->class_dev,
1419 "clock %u too fast; using %lu\n",
1420 clock_min, host->bus_hz / 2);
1421 clkdiv = 0;
1422 } else if (clkdiv > 511) {
1423 dev_warn(&mmc->class_dev,
1424 "clock %u too slow; using %lu\n",
1425 clock_min, host->bus_hz / (511 + 2));
1426 clkdiv = 511;
1427 }
1428 host->mode_reg = ATMCI_MR_CLKDIV(clkdiv >> 1)
1429 | ATMCI_MR_CLKODD(clkdiv & 1);
1430 } else {
1431 clkdiv = DIV_ROUND_UP(host->bus_hz, 2 * clock_min) - 1;
1432 if (clkdiv > 255) {
1433 dev_warn(&mmc->class_dev,
1434 "clock %u too slow; using %lu\n",
1435 clock_min, host->bus_hz / (2 * 256));
1436 clkdiv = 255;
1437 }
1438 host->mode_reg = ATMCI_MR_CLKDIV(clkdiv);
1439 }
1440
1441 /*
1442 * WRPROOF and RDPROOF prevent overruns/underruns by
1443 * stopping the clock when the FIFO is full/empty.
1444 * This state is not expected to last for long.
1445 */
1446 if (host->caps.has_rwproof)
1447 host->mode_reg |= (ATMCI_MR_WRPROOF | ATMCI_MR_RDPROOF);
1448
1449 if (host->caps.has_cfg_reg) {
1450 /* setup High Speed mode in relation with card capacity */
1451 if (ios->timing == MMC_TIMING_SD_HS)
1452 host->cfg_reg |= ATMCI_CFG_HSMODE;
1453 else
1454 host->cfg_reg &= ~ATMCI_CFG_HSMODE;
1455 }
1456
1457 if (list_empty(&host->queue)) {
1458 atmci_writel(host, ATMCI_MR, host->mode_reg);
1459 if (host->caps.has_cfg_reg)
1460 atmci_writel(host, ATMCI_CFG, host->cfg_reg);
1461 } else {
1462 host->need_clock_update = true;
1463 }
1464
1465 spin_unlock_bh(&host->lock);
1466 } else {
1467 bool any_slot_active = false;
1468
1469 spin_lock_bh(&host->lock);
1470 slot->clock = 0;
1471 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
1472 if (host->slot[i] && host->slot[i]->clock) {
1473 any_slot_active = true;
1474 break;
1475 }
1476 }
1477 if (!any_slot_active) {
1478 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIDIS);
1479 if (host->mode_reg) {
1480 atmci_readl(host, ATMCI_MR);
1481 }
1482 host->mode_reg = 0;
1483 }
1484 spin_unlock_bh(&host->lock);
1485 }
1486
1487 switch (ios->power_mode) {
1488 case MMC_POWER_OFF:
1489 if (!IS_ERR(mmc->supply.vmmc))
1490 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1491 break;
1492 case MMC_POWER_UP:
1493 set_bit(ATMCI_CARD_NEED_INIT, &slot->flags);
1494 if (!IS_ERR(mmc->supply.vmmc))
1495 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd);
1496 break;
1497 default:
1498 break;
1499 }
1500 }
1501
1502 static int atmci_get_ro(struct mmc_host *mmc)
1503 {
1504 int read_only = -ENOSYS;
1505 struct atmel_mci_slot *slot = mmc_priv(mmc);
1506
1507 if (gpio_is_valid(slot->wp_pin)) {
1508 read_only = gpio_get_value(slot->wp_pin);
1509 dev_dbg(&mmc->class_dev, "card is %s\n",
1510 read_only ? "read-only" : "read-write");
1511 }
1512
1513 return read_only;
1514 }
1515
1516 static int atmci_get_cd(struct mmc_host *mmc)
1517 {
1518 int present = -ENOSYS;
1519 struct atmel_mci_slot *slot = mmc_priv(mmc);
1520
1521 if (gpio_is_valid(slot->detect_pin)) {
1522 present = !(gpio_get_value(slot->detect_pin) ^
1523 slot->detect_is_active_high);
1524 dev_dbg(&mmc->class_dev, "card is %spresent\n",
1525 present ? "" : "not ");
1526 }
1527
1528 return present;
1529 }
1530
1531 static void atmci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1532 {
1533 struct atmel_mci_slot *slot = mmc_priv(mmc);
1534 struct atmel_mci *host = slot->host;
1535
1536 if (enable)
1537 atmci_writel(host, ATMCI_IER, slot->sdio_irq);
1538 else
1539 atmci_writel(host, ATMCI_IDR, slot->sdio_irq);
1540 }
1541
1542 static const struct mmc_host_ops atmci_ops = {
1543 .request = atmci_request,
1544 .set_ios = atmci_set_ios,
1545 .get_ro = atmci_get_ro,
1546 .get_cd = atmci_get_cd,
1547 .enable_sdio_irq = atmci_enable_sdio_irq,
1548 };
1549
1550 /* Called with host->lock held */
1551 static void atmci_request_end(struct atmel_mci *host, struct mmc_request *mrq)
1552 __releases(&host->lock)
1553 __acquires(&host->lock)
1554 {
1555 struct atmel_mci_slot *slot = NULL;
1556 struct mmc_host *prev_mmc = host->cur_slot->mmc;
1557
1558 WARN_ON(host->cmd || host->data);
1559
1560 /*
1561 * Update the MMC clock rate if necessary. This may be
1562 * necessary if set_ios() is called when a different slot is
1563 * busy transferring data.
1564 */
1565 if (host->need_clock_update) {
1566 atmci_writel(host, ATMCI_MR, host->mode_reg);
1567 if (host->caps.has_cfg_reg)
1568 atmci_writel(host, ATMCI_CFG, host->cfg_reg);
1569 }
1570
1571 host->cur_slot->mrq = NULL;
1572 host->mrq = NULL;
1573 if (!list_empty(&host->queue)) {
1574 slot = list_entry(host->queue.next,
1575 struct atmel_mci_slot, queue_node);
1576 list_del(&slot->queue_node);
1577 dev_vdbg(&host->pdev->dev, "list not empty: %s is next\n",
1578 mmc_hostname(slot->mmc));
1579 host->state = STATE_SENDING_CMD;
1580 atmci_start_request(host, slot);
1581 } else {
1582 dev_vdbg(&host->pdev->dev, "list empty\n");
1583 host->state = STATE_IDLE;
1584 }
1585
1586 del_timer(&host->timer);
1587
1588 spin_unlock(&host->lock);
1589 mmc_request_done(prev_mmc, mrq);
1590 spin_lock(&host->lock);
1591 }
1592
1593 static void atmci_command_complete(struct atmel_mci *host,
1594 struct mmc_command *cmd)
1595 {
1596 u32 status = host->cmd_status;
1597
1598 /* Read the response from the card (up to 16 bytes) */
1599 cmd->resp[0] = atmci_readl(host, ATMCI_RSPR);
1600 cmd->resp[1] = atmci_readl(host, ATMCI_RSPR);
1601 cmd->resp[2] = atmci_readl(host, ATMCI_RSPR);
1602 cmd->resp[3] = atmci_readl(host, ATMCI_RSPR);
1603
1604 if (status & ATMCI_RTOE)
1605 cmd->error = -ETIMEDOUT;
1606 else if ((cmd->flags & MMC_RSP_CRC) && (status & ATMCI_RCRCE))
1607 cmd->error = -EILSEQ;
1608 else if (status & (ATMCI_RINDE | ATMCI_RDIRE | ATMCI_RENDE))
1609 cmd->error = -EIO;
1610 else if (host->mrq->data && (host->mrq->data->blksz & 3)) {
1611 if (host->caps.need_blksz_mul_4) {
1612 cmd->error = -EINVAL;
1613 host->need_reset = 1;
1614 }
1615 } else
1616 cmd->error = 0;
1617 }
1618
1619 static void atmci_detect_change(struct timer_list *t)
1620 {
1621 struct atmel_mci_slot *slot = from_timer(slot, t, detect_timer);
1622 bool present;
1623 bool present_old;
1624
1625 /*
1626 * atmci_cleanup_slot() sets the ATMCI_SHUTDOWN flag before
1627 * freeing the interrupt. We must not re-enable the interrupt
1628 * if it has been freed, and if we're shutting down, it
1629 * doesn't really matter whether the card is present or not.
1630 */
1631 smp_rmb();
1632 if (test_bit(ATMCI_SHUTDOWN, &slot->flags))
1633 return;
1634
1635 enable_irq(gpio_to_irq(slot->detect_pin));
1636 present = !(gpio_get_value(slot->detect_pin) ^
1637 slot->detect_is_active_high);
1638 present_old = test_bit(ATMCI_CARD_PRESENT, &slot->flags);
1639
1640 dev_vdbg(&slot->mmc->class_dev, "detect change: %d (was %d)\n",
1641 present, present_old);
1642
1643 if (present != present_old) {
1644 struct atmel_mci *host = slot->host;
1645 struct mmc_request *mrq;
1646
1647 dev_dbg(&slot->mmc->class_dev, "card %s\n",
1648 present ? "inserted" : "removed");
1649
1650 spin_lock(&host->lock);
1651
1652 if (!present)
1653 clear_bit(ATMCI_CARD_PRESENT, &slot->flags);
1654 else
1655 set_bit(ATMCI_CARD_PRESENT, &slot->flags);
1656
1657 /* Clean up queue if present */
1658 mrq = slot->mrq;
1659 if (mrq) {
1660 if (mrq == host->mrq) {
1661 /*
1662 * Reset controller to terminate any ongoing
1663 * commands or data transfers.
1664 */
1665 atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
1666 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIEN);
1667 atmci_writel(host, ATMCI_MR, host->mode_reg);
1668 if (host->caps.has_cfg_reg)
1669 atmci_writel(host, ATMCI_CFG, host->cfg_reg);
1670
1671 host->data = NULL;
1672 host->cmd = NULL;
1673
1674 switch (host->state) {
1675 case STATE_IDLE:
1676 break;
1677 case STATE_SENDING_CMD:
1678 mrq->cmd->error = -ENOMEDIUM;
1679 if (mrq->data)
1680 host->stop_transfer(host);
1681 break;
1682 case STATE_DATA_XFER:
1683 mrq->data->error = -ENOMEDIUM;
1684 host->stop_transfer(host);
1685 break;
1686 case STATE_WAITING_NOTBUSY:
1687 mrq->data->error = -ENOMEDIUM;
1688 break;
1689 case STATE_SENDING_STOP:
1690 mrq->stop->error = -ENOMEDIUM;
1691 break;
1692 case STATE_END_REQUEST:
1693 break;
1694 }
1695
1696 atmci_request_end(host, mrq);
1697 } else {
1698 list_del(&slot->queue_node);
1699 mrq->cmd->error = -ENOMEDIUM;
1700 if (mrq->data)
1701 mrq->data->error = -ENOMEDIUM;
1702 if (mrq->stop)
1703 mrq->stop->error = -ENOMEDIUM;
1704
1705 spin_unlock(&host->lock);
1706 mmc_request_done(slot->mmc, mrq);
1707 spin_lock(&host->lock);
1708 }
1709 }
1710 spin_unlock(&host->lock);
1711
1712 mmc_detect_change(slot->mmc, 0);
1713 }
1714 }
1715
1716 static void atmci_tasklet_func(unsigned long priv)
1717 {
1718 struct atmel_mci *host = (struct atmel_mci *)priv;
1719 struct mmc_request *mrq = host->mrq;
1720 struct mmc_data *data = host->data;
1721 enum atmel_mci_state state = host->state;
1722 enum atmel_mci_state prev_state;
1723 u32 status;
1724
1725 spin_lock(&host->lock);
1726
1727 state = host->state;
1728
1729 dev_vdbg(&host->pdev->dev,
1730 "tasklet: state %u pending/completed/mask %lx/%lx/%x\n",
1731 state, host->pending_events, host->completed_events,
1732 atmci_readl(host, ATMCI_IMR));
1733
1734 do {
1735 prev_state = state;
1736 dev_dbg(&host->pdev->dev, "FSM: state=%d\n", state);
1737
1738 switch (state) {
1739 case STATE_IDLE:
1740 break;
1741
1742 case STATE_SENDING_CMD:
1743 /*
1744 * Command has been sent, we are waiting for command
1745 * ready. Then we have three next states possible:
1746 * END_REQUEST by default, WAITING_NOTBUSY if it's a
1747 * command needing it or DATA_XFER if there is data.
1748 */
1749 dev_dbg(&host->pdev->dev, "FSM: cmd ready?\n");
1750 if (!atmci_test_and_clear_pending(host,
1751 EVENT_CMD_RDY))
1752 break;
1753
1754 dev_dbg(&host->pdev->dev, "set completed cmd ready\n");
1755 host->cmd = NULL;
1756 atmci_set_completed(host, EVENT_CMD_RDY);
1757 atmci_command_complete(host, mrq->cmd);
1758 if (mrq->data) {
1759 dev_dbg(&host->pdev->dev,
1760 "command with data transfer");
1761 /*
1762 * If there is a command error don't start
1763 * data transfer.
1764 */
1765 if (mrq->cmd->error) {
1766 host->stop_transfer(host);
1767 host->data = NULL;
1768 atmci_writel(host, ATMCI_IDR,
1769 ATMCI_TXRDY | ATMCI_RXRDY
1770 | ATMCI_DATA_ERROR_FLAGS);
1771 state = STATE_END_REQUEST;
1772 } else
1773 state = STATE_DATA_XFER;
1774 } else if ((!mrq->data) && (mrq->cmd->flags & MMC_RSP_BUSY)) {
1775 dev_dbg(&host->pdev->dev,
1776 "command response need waiting notbusy");
1777 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1778 state = STATE_WAITING_NOTBUSY;
1779 } else
1780 state = STATE_END_REQUEST;
1781
1782 break;
1783
1784 case STATE_DATA_XFER:
1785 if (atmci_test_and_clear_pending(host,
1786 EVENT_DATA_ERROR)) {
1787 dev_dbg(&host->pdev->dev, "set completed data error\n");
1788 atmci_set_completed(host, EVENT_DATA_ERROR);
1789 state = STATE_END_REQUEST;
1790 break;
1791 }
1792
1793 /*
1794 * A data transfer is in progress. The event expected
1795 * to move to the next state depends of data transfer
1796 * type (PDC or DMA). Once transfer done we can move
1797 * to the next step which is WAITING_NOTBUSY in write
1798 * case and directly SENDING_STOP in read case.
1799 */
1800 dev_dbg(&host->pdev->dev, "FSM: xfer complete?\n");
1801 if (!atmci_test_and_clear_pending(host,
1802 EVENT_XFER_COMPLETE))
1803 break;
1804
1805 dev_dbg(&host->pdev->dev,
1806 "(%s) set completed xfer complete\n",
1807 __func__);
1808 atmci_set_completed(host, EVENT_XFER_COMPLETE);
1809
1810 if (host->caps.need_notbusy_for_read_ops ||
1811 (host->data->flags & MMC_DATA_WRITE)) {
1812 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1813 state = STATE_WAITING_NOTBUSY;
1814 } else if (host->mrq->stop) {
1815 atmci_writel(host, ATMCI_IER, ATMCI_CMDRDY);
1816 atmci_send_stop_cmd(host, data);
1817 state = STATE_SENDING_STOP;
1818 } else {
1819 host->data = NULL;
1820 data->bytes_xfered = data->blocks * data->blksz;
1821 data->error = 0;
1822 state = STATE_END_REQUEST;
1823 }
1824 break;
1825
1826 case STATE_WAITING_NOTBUSY:
1827 /*
1828 * We can be in the state for two reasons: a command
1829 * requiring waiting not busy signal (stop command
1830 * included) or a write operation. In the latest case,
1831 * we need to send a stop command.
1832 */
1833 dev_dbg(&host->pdev->dev, "FSM: not busy?\n");
1834 if (!atmci_test_and_clear_pending(host,
1835 EVENT_NOTBUSY))
1836 break;
1837
1838 dev_dbg(&host->pdev->dev, "set completed not busy\n");
1839 atmci_set_completed(host, EVENT_NOTBUSY);
1840
1841 if (host->data) {
1842 /*
1843 * For some commands such as CMD53, even if
1844 * there is data transfer, there is no stop
1845 * command to send.
1846 */
1847 if (host->mrq->stop) {
1848 atmci_writel(host, ATMCI_IER,
1849 ATMCI_CMDRDY);
1850 atmci_send_stop_cmd(host, data);
1851 state = STATE_SENDING_STOP;
1852 } else {
1853 host->data = NULL;
1854 data->bytes_xfered = data->blocks
1855 * data->blksz;
1856 data->error = 0;
1857 state = STATE_END_REQUEST;
1858 }
1859 } else
1860 state = STATE_END_REQUEST;
1861 break;
1862
1863 case STATE_SENDING_STOP:
1864 /*
1865 * In this state, it is important to set host->data to
1866 * NULL (which is tested in the waiting notbusy state)
1867 * in order to go to the end request state instead of
1868 * sending stop again.
1869 */
1870 dev_dbg(&host->pdev->dev, "FSM: cmd ready?\n");
1871 if (!atmci_test_and_clear_pending(host,
1872 EVENT_CMD_RDY))
1873 break;
1874
1875 dev_dbg(&host->pdev->dev, "FSM: cmd ready\n");
1876 host->cmd = NULL;
1877 data->bytes_xfered = data->blocks * data->blksz;
1878 data->error = 0;
1879 atmci_command_complete(host, mrq->stop);
1880 if (mrq->stop->error) {
1881 host->stop_transfer(host);
1882 atmci_writel(host, ATMCI_IDR,
1883 ATMCI_TXRDY | ATMCI_RXRDY
1884 | ATMCI_DATA_ERROR_FLAGS);
1885 state = STATE_END_REQUEST;
1886 } else {
1887 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1888 state = STATE_WAITING_NOTBUSY;
1889 }
1890 host->data = NULL;
1891 break;
1892
1893 case STATE_END_REQUEST:
1894 atmci_writel(host, ATMCI_IDR, ATMCI_TXRDY | ATMCI_RXRDY
1895 | ATMCI_DATA_ERROR_FLAGS);
1896 status = host->data_status;
1897 if (unlikely(status)) {
1898 host->stop_transfer(host);
1899 host->data = NULL;
1900 if (data) {
1901 if (status & ATMCI_DTOE) {
1902 data->error = -ETIMEDOUT;
1903 } else if (status & ATMCI_DCRCE) {
1904 data->error = -EILSEQ;
1905 } else {
1906 data->error = -EIO;
1907 }
1908 }
1909 }
1910
1911 atmci_request_end(host, host->mrq);
1912 goto unlock; /* atmci_request_end() sets host->state */
1913 break;
1914 }
1915 } while (state != prev_state);
1916
1917 host->state = state;
1918
1919 unlock:
1920 spin_unlock(&host->lock);
1921 }
1922
1923 static void atmci_read_data_pio(struct atmel_mci *host)
1924 {
1925 struct scatterlist *sg = host->sg;
1926 unsigned int offset = host->pio_offset;
1927 struct mmc_data *data = host->data;
1928 u32 value;
1929 u32 status;
1930 unsigned int nbytes = 0;
1931
1932 do {
1933 value = atmci_readl(host, ATMCI_RDR);
1934 if (likely(offset + 4 <= sg->length)) {
1935 sg_pcopy_from_buffer(sg, 1, &value, sizeof(u32), offset);
1936
1937 offset += 4;
1938 nbytes += 4;
1939
1940 if (offset == sg->length) {
1941 flush_dcache_page(sg_page(sg));
1942 host->sg = sg = sg_next(sg);
1943 host->sg_len--;
1944 if (!sg || !host->sg_len)
1945 goto done;
1946
1947 offset = 0;
1948 }
1949 } else {
1950 unsigned int remaining = sg->length - offset;
1951
1952 sg_pcopy_from_buffer(sg, 1, &value, remaining, offset);
1953 nbytes += remaining;
1954
1955 flush_dcache_page(sg_page(sg));
1956 host->sg = sg = sg_next(sg);
1957 host->sg_len--;
1958 if (!sg || !host->sg_len)
1959 goto done;
1960
1961 offset = 4 - remaining;
1962 sg_pcopy_from_buffer(sg, 1, (u8 *)&value + remaining,
1963 offset, 0);
1964 nbytes += offset;
1965 }
1966
1967 status = atmci_readl(host, ATMCI_SR);
1968 if (status & ATMCI_DATA_ERROR_FLAGS) {
1969 atmci_writel(host, ATMCI_IDR, (ATMCI_NOTBUSY | ATMCI_RXRDY
1970 | ATMCI_DATA_ERROR_FLAGS));
1971 host->data_status = status;
1972 data->bytes_xfered += nbytes;
1973 return;
1974 }
1975 } while (status & ATMCI_RXRDY);
1976
1977 host->pio_offset = offset;
1978 data->bytes_xfered += nbytes;
1979
1980 return;
1981
1982 done:
1983 atmci_writel(host, ATMCI_IDR, ATMCI_RXRDY);
1984 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1985 data->bytes_xfered += nbytes;
1986 smp_wmb();
1987 atmci_set_pending(host, EVENT_XFER_COMPLETE);
1988 }
1989
1990 static void atmci_write_data_pio(struct atmel_mci *host)
1991 {
1992 struct scatterlist *sg = host->sg;
1993 unsigned int offset = host->pio_offset;
1994 struct mmc_data *data = host->data;
1995 u32 value;
1996 u32 status;
1997 unsigned int nbytes = 0;
1998
1999 do {
2000 if (likely(offset + 4 <= sg->length)) {
2001 sg_pcopy_to_buffer(sg, 1, &value, sizeof(u32), offset);
2002 atmci_writel(host, ATMCI_TDR, value);
2003
2004 offset += 4;
2005 nbytes += 4;
2006 if (offset == sg->length) {
2007 host->sg = sg = sg_next(sg);
2008 host->sg_len--;
2009 if (!sg || !host->sg_len)
2010 goto done;
2011
2012 offset = 0;
2013 }
2014 } else {
2015 unsigned int remaining = sg->length - offset;
2016
2017 value = 0;
2018 sg_pcopy_to_buffer(sg, 1, &value, remaining, offset);
2019 nbytes += remaining;
2020
2021 host->sg = sg = sg_next(sg);
2022 host->sg_len--;
2023 if (!sg || !host->sg_len) {
2024 atmci_writel(host, ATMCI_TDR, value);
2025 goto done;
2026 }
2027
2028 offset = 4 - remaining;
2029 sg_pcopy_to_buffer(sg, 1, (u8 *)&value + remaining,
2030 offset, 0);
2031 atmci_writel(host, ATMCI_TDR, value);
2032 nbytes += offset;
2033 }
2034
2035 status = atmci_readl(host, ATMCI_SR);
2036 if (status & ATMCI_DATA_ERROR_FLAGS) {
2037 atmci_writel(host, ATMCI_IDR, (ATMCI_NOTBUSY | ATMCI_TXRDY
2038 | ATMCI_DATA_ERROR_FLAGS));
2039 host->data_status = status;
2040 data->bytes_xfered += nbytes;
2041 return;
2042 }
2043 } while (status & ATMCI_TXRDY);
2044
2045 host->pio_offset = offset;
2046 data->bytes_xfered += nbytes;
2047
2048 return;
2049
2050 done:
2051 atmci_writel(host, ATMCI_IDR, ATMCI_TXRDY);
2052 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
2053 data->bytes_xfered += nbytes;
2054 smp_wmb();
2055 atmci_set_pending(host, EVENT_XFER_COMPLETE);
2056 }
2057
2058 static void atmci_sdio_interrupt(struct atmel_mci *host, u32 status)
2059 {
2060 int i;
2061
2062 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
2063 struct atmel_mci_slot *slot = host->slot[i];
2064 if (slot && (status & slot->sdio_irq)) {
2065 mmc_signal_sdio_irq(slot->mmc);
2066 }
2067 }
2068 }
2069
2070
2071 static irqreturn_t atmci_interrupt(int irq, void *dev_id)
2072 {
2073 struct atmel_mci *host = dev_id;
2074 u32 status, mask, pending;
2075 unsigned int pass_count = 0;
2076
2077 do {
2078 status = atmci_readl(host, ATMCI_SR);
2079 mask = atmci_readl(host, ATMCI_IMR);
2080 pending = status & mask;
2081 if (!pending)
2082 break;
2083
2084 if (pending & ATMCI_DATA_ERROR_FLAGS) {
2085 dev_dbg(&host->pdev->dev, "IRQ: data error\n");
2086 atmci_writel(host, ATMCI_IDR, ATMCI_DATA_ERROR_FLAGS
2087 | ATMCI_RXRDY | ATMCI_TXRDY
2088 | ATMCI_ENDRX | ATMCI_ENDTX
2089 | ATMCI_RXBUFF | ATMCI_TXBUFE);
2090
2091 host->data_status = status;
2092 dev_dbg(&host->pdev->dev, "set pending data error\n");
2093 smp_wmb();
2094 atmci_set_pending(host, EVENT_DATA_ERROR);
2095 tasklet_schedule(&host->tasklet);
2096 }
2097
2098 if (pending & ATMCI_TXBUFE) {
2099 dev_dbg(&host->pdev->dev, "IRQ: tx buffer empty\n");
2100 atmci_writel(host, ATMCI_IDR, ATMCI_TXBUFE);
2101 atmci_writel(host, ATMCI_IDR, ATMCI_ENDTX);
2102 /*
2103 * We can receive this interruption before having configured
2104 * the second pdc buffer, so we need to reconfigure first and
2105 * second buffers again
2106 */
2107 if (host->data_size) {
2108 atmci_pdc_set_both_buf(host, XFER_TRANSMIT);
2109 atmci_writel(host, ATMCI_IER, ATMCI_ENDTX);
2110 atmci_writel(host, ATMCI_IER, ATMCI_TXBUFE);
2111 } else {
2112 atmci_pdc_complete(host);
2113 }
2114 } else if (pending & ATMCI_ENDTX) {
2115 dev_dbg(&host->pdev->dev, "IRQ: end of tx buffer\n");
2116 atmci_writel(host, ATMCI_IDR, ATMCI_ENDTX);
2117
2118 if (host->data_size) {
2119 atmci_pdc_set_single_buf(host,
2120 XFER_TRANSMIT, PDC_SECOND_BUF);
2121 atmci_writel(host, ATMCI_IER, ATMCI_ENDTX);
2122 }
2123 }
2124
2125 if (pending & ATMCI_RXBUFF) {
2126 dev_dbg(&host->pdev->dev, "IRQ: rx buffer full\n");
2127 atmci_writel(host, ATMCI_IDR, ATMCI_RXBUFF);
2128 atmci_writel(host, ATMCI_IDR, ATMCI_ENDRX);
2129 /*
2130 * We can receive this interruption before having configured
2131 * the second pdc buffer, so we need to reconfigure first and
2132 * second buffers again
2133 */
2134 if (host->data_size) {
2135 atmci_pdc_set_both_buf(host, XFER_RECEIVE);
2136 atmci_writel(host, ATMCI_IER, ATMCI_ENDRX);
2137 atmci_writel(host, ATMCI_IER, ATMCI_RXBUFF);
2138 } else {
2139 atmci_pdc_complete(host);
2140 }
2141 } else if (pending & ATMCI_ENDRX) {
2142 dev_dbg(&host->pdev->dev, "IRQ: end of rx buffer\n");
2143 atmci_writel(host, ATMCI_IDR, ATMCI_ENDRX);
2144
2145 if (host->data_size) {
2146 atmci_pdc_set_single_buf(host,
2147 XFER_RECEIVE, PDC_SECOND_BUF);
2148 atmci_writel(host, ATMCI_IER, ATMCI_ENDRX);
2149 }
2150 }
2151
2152 /*
2153 * First mci IPs, so mainly the ones having pdc, have some
2154 * issues with the notbusy signal. You can't get it after
2155 * data transmission if you have not sent a stop command.
2156 * The appropriate workaround is to use the BLKE signal.
2157 */
2158 if (pending & ATMCI_BLKE) {
2159 dev_dbg(&host->pdev->dev, "IRQ: blke\n");
2160 atmci_writel(host, ATMCI_IDR, ATMCI_BLKE);
2161 smp_wmb();
2162 dev_dbg(&host->pdev->dev, "set pending notbusy\n");
2163 atmci_set_pending(host, EVENT_NOTBUSY);
2164 tasklet_schedule(&host->tasklet);
2165 }
2166
2167 if (pending & ATMCI_NOTBUSY) {
2168 dev_dbg(&host->pdev->dev, "IRQ: not_busy\n");
2169 atmci_writel(host, ATMCI_IDR, ATMCI_NOTBUSY);
2170 smp_wmb();
2171 dev_dbg(&host->pdev->dev, "set pending notbusy\n");
2172 atmci_set_pending(host, EVENT_NOTBUSY);
2173 tasklet_schedule(&host->tasklet);
2174 }
2175
2176 if (pending & ATMCI_RXRDY)
2177 atmci_read_data_pio(host);
2178 if (pending & ATMCI_TXRDY)
2179 atmci_write_data_pio(host);
2180
2181 if (pending & ATMCI_CMDRDY) {
2182 dev_dbg(&host->pdev->dev, "IRQ: cmd ready\n");
2183 atmci_writel(host, ATMCI_IDR, ATMCI_CMDRDY);
2184 host->cmd_status = status;
2185 smp_wmb();
2186 dev_dbg(&host->pdev->dev, "set pending cmd rdy\n");
2187 atmci_set_pending(host, EVENT_CMD_RDY);
2188 tasklet_schedule(&host->tasklet);
2189 }
2190
2191 if (pending & (ATMCI_SDIOIRQA | ATMCI_SDIOIRQB))
2192 atmci_sdio_interrupt(host, status);
2193
2194 } while (pass_count++ < 5);
2195
2196 return pass_count ? IRQ_HANDLED : IRQ_NONE;
2197 }
2198
2199 static irqreturn_t atmci_detect_interrupt(int irq, void *dev_id)
2200 {
2201 struct atmel_mci_slot *slot = dev_id;
2202
2203 /*
2204 * Disable interrupts until the pin has stabilized and check
2205 * the state then. Use mod_timer() since we may be in the
2206 * middle of the timer routine when this interrupt triggers.
2207 */
2208 disable_irq_nosync(irq);
2209 mod_timer(&slot->detect_timer, jiffies + msecs_to_jiffies(20));
2210
2211 return IRQ_HANDLED;
2212 }
2213
2214 static int atmci_init_slot(struct atmel_mci *host,
2215 struct mci_slot_pdata *slot_data, unsigned int id,
2216 u32 sdc_reg, u32 sdio_irq)
2217 {
2218 struct mmc_host *mmc;
2219 struct atmel_mci_slot *slot;
2220
2221 mmc = mmc_alloc_host(sizeof(struct atmel_mci_slot), &host->pdev->dev);
2222 if (!mmc)
2223 return -ENOMEM;
2224
2225 slot = mmc_priv(mmc);
2226 slot->mmc = mmc;
2227 slot->host = host;
2228 slot->detect_pin = slot_data->detect_pin;
2229 slot->wp_pin = slot_data->wp_pin;
2230 slot->detect_is_active_high = slot_data->detect_is_active_high;
2231 slot->sdc_reg = sdc_reg;
2232 slot->sdio_irq = sdio_irq;
2233
2234 dev_dbg(&mmc->class_dev,
2235 "slot[%u]: bus_width=%u, detect_pin=%d, "
2236 "detect_is_active_high=%s, wp_pin=%d\n",
2237 id, slot_data->bus_width, slot_data->detect_pin,
2238 slot_data->detect_is_active_high ? "true" : "false",
2239 slot_data->wp_pin);
2240
2241 mmc->ops = &atmci_ops;
2242 mmc->f_min = DIV_ROUND_UP(host->bus_hz, 512);
2243 mmc->f_max = host->bus_hz / 2;
2244 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
2245 if (sdio_irq)
2246 mmc->caps |= MMC_CAP_SDIO_IRQ;
2247 if (host->caps.has_highspeed)
2248 mmc->caps |= MMC_CAP_SD_HIGHSPEED;
2249 /*
2250 * Without the read/write proof capability, it is strongly suggested to
2251 * use only one bit for data to prevent fifo underruns and overruns
2252 * which will corrupt data.
2253 */
2254 if ((slot_data->bus_width >= 4) && host->caps.has_rwproof) {
2255 mmc->caps |= MMC_CAP_4_BIT_DATA;
2256 if (slot_data->bus_width >= 8)
2257 mmc->caps |= MMC_CAP_8_BIT_DATA;
2258 }
2259
2260 if (atmci_get_version(host) < 0x200) {
2261 mmc->max_segs = 256;
2262 mmc->max_blk_size = 4095;
2263 mmc->max_blk_count = 256;
2264 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
2265 mmc->max_seg_size = mmc->max_blk_size * mmc->max_segs;
2266 } else {
2267 mmc->max_segs = 64;
2268 mmc->max_req_size = 32768 * 512;
2269 mmc->max_blk_size = 32768;
2270 mmc->max_blk_count = 512;
2271 }
2272
2273 /* Assume card is present initially */
2274 set_bit(ATMCI_CARD_PRESENT, &slot->flags);
2275 if (gpio_is_valid(slot->detect_pin)) {
2276 if (devm_gpio_request(&host->pdev->dev, slot->detect_pin,
2277 "mmc_detect")) {
2278 dev_dbg(&mmc->class_dev, "no detect pin available\n");
2279 slot->detect_pin = -EBUSY;
2280 } else if (gpio_get_value(slot->detect_pin) ^
2281 slot->detect_is_active_high) {
2282 clear_bit(ATMCI_CARD_PRESENT, &slot->flags);
2283 }
2284 }
2285
2286 if (!gpio_is_valid(slot->detect_pin)) {
2287 if (slot_data->non_removable)
2288 mmc->caps |= MMC_CAP_NONREMOVABLE;
2289 else
2290 mmc->caps |= MMC_CAP_NEEDS_POLL;
2291 }
2292
2293 if (gpio_is_valid(slot->wp_pin)) {
2294 if (devm_gpio_request(&host->pdev->dev, slot->wp_pin,
2295 "mmc_wp")) {
2296 dev_dbg(&mmc->class_dev, "no WP pin available\n");
2297 slot->wp_pin = -EBUSY;
2298 }
2299 }
2300
2301 host->slot[id] = slot;
2302 mmc_regulator_get_supply(mmc);
2303 mmc_add_host(mmc);
2304
2305 if (gpio_is_valid(slot->detect_pin)) {
2306 int ret;
2307
2308 timer_setup(&slot->detect_timer, atmci_detect_change, 0);
2309
2310 ret = request_irq(gpio_to_irq(slot->detect_pin),
2311 atmci_detect_interrupt,
2312 IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
2313 "mmc-detect", slot);
2314 if (ret) {
2315 dev_dbg(&mmc->class_dev,
2316 "could not request IRQ %d for detect pin\n",
2317 gpio_to_irq(slot->detect_pin));
2318 slot->detect_pin = -EBUSY;
2319 }
2320 }
2321
2322 atmci_init_debugfs(slot);
2323
2324 return 0;
2325 }
2326
2327 static void atmci_cleanup_slot(struct atmel_mci_slot *slot,
2328 unsigned int id)
2329 {
2330 /* Debugfs stuff is cleaned up by mmc core */
2331
2332 set_bit(ATMCI_SHUTDOWN, &slot->flags);
2333 smp_wmb();
2334
2335 mmc_remove_host(slot->mmc);
2336
2337 if (gpio_is_valid(slot->detect_pin)) {
2338 int pin = slot->detect_pin;
2339
2340 free_irq(gpio_to_irq(pin), slot);
2341 del_timer_sync(&slot->detect_timer);
2342 }
2343
2344 slot->host->slot[id] = NULL;
2345 mmc_free_host(slot->mmc);
2346 }
2347
2348 static int atmci_configure_dma(struct atmel_mci *host)
2349 {
2350 host->dma.chan = dma_request_chan(&host->pdev->dev, "rxtx");
2351
2352 if (PTR_ERR(host->dma.chan) == -ENODEV) {
2353 struct mci_platform_data *pdata = host->pdev->dev.platform_data;
2354 dma_cap_mask_t mask;
2355
2356 if (!pdata || !pdata->dma_filter)
2357 return -ENODEV;
2358
2359 dma_cap_zero(mask);
2360 dma_cap_set(DMA_SLAVE, mask);
2361
2362 host->dma.chan = dma_request_channel(mask, pdata->dma_filter,
2363 pdata->dma_slave);
2364 if (!host->dma.chan)
2365 host->dma.chan = ERR_PTR(-ENODEV);
2366 }
2367
2368 if (IS_ERR(host->dma.chan))
2369 return PTR_ERR(host->dma.chan);
2370
2371 dev_info(&host->pdev->dev, "using %s for DMA transfers\n",
2372 dma_chan_name(host->dma.chan));
2373
2374 host->dma_conf.src_addr = host->mapbase + ATMCI_RDR;
2375 host->dma_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
2376 host->dma_conf.src_maxburst = 1;
2377 host->dma_conf.dst_addr = host->mapbase + ATMCI_TDR;
2378 host->dma_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
2379 host->dma_conf.dst_maxburst = 1;
2380 host->dma_conf.device_fc = false;
2381
2382 return 0;
2383 }
2384
2385 /*
2386 * HSMCI (High Speed MCI) module is not fully compatible with MCI module.
2387 * HSMCI provides DMA support and a new config register but no more supports
2388 * PDC.
2389 */
2390 static void atmci_get_cap(struct atmel_mci *host)
2391 {
2392 unsigned int version;
2393
2394 version = atmci_get_version(host);
2395 dev_info(&host->pdev->dev,
2396 "version: 0x%x\n", version);
2397
2398 host->caps.has_dma_conf_reg = 0;
2399 host->caps.has_pdc = 1;
2400 host->caps.has_cfg_reg = 0;
2401 host->caps.has_cstor_reg = 0;
2402 host->caps.has_highspeed = 0;
2403 host->caps.has_rwproof = 0;
2404 host->caps.has_odd_clk_div = 0;
2405 host->caps.has_bad_data_ordering = 1;
2406 host->caps.need_reset_after_xfer = 1;
2407 host->caps.need_blksz_mul_4 = 1;
2408 host->caps.need_notbusy_for_read_ops = 0;
2409
2410 /* keep only major version number */
2411 switch (version & 0xf00) {
2412 case 0x600:
2413 case 0x500:
2414 host->caps.has_odd_clk_div = 1;
2415 /* Fall through */
2416 case 0x400:
2417 case 0x300:
2418 host->caps.has_dma_conf_reg = 1;
2419 host->caps.has_pdc = 0;
2420 host->caps.has_cfg_reg = 1;
2421 host->caps.has_cstor_reg = 1;
2422 host->caps.has_highspeed = 1;
2423 /* Fall through */
2424 case 0x200:
2425 host->caps.has_rwproof = 1;
2426 host->caps.need_blksz_mul_4 = 0;
2427 host->caps.need_notbusy_for_read_ops = 1;
2428 /* Fall through */
2429 case 0x100:
2430 host->caps.has_bad_data_ordering = 0;
2431 host->caps.need_reset_after_xfer = 0;
2432 /* Fall through */
2433 case 0x0:
2434 break;
2435 default:
2436 host->caps.has_pdc = 0;
2437 dev_warn(&host->pdev->dev,
2438 "Unmanaged mci version, set minimum capabilities\n");
2439 break;
2440 }
2441 }
2442
2443 static int atmci_probe(struct platform_device *pdev)
2444 {
2445 struct mci_platform_data *pdata;
2446 struct atmel_mci *host;
2447 struct resource *regs;
2448 unsigned int nr_slots;
2449 int irq;
2450 int ret, i;
2451
2452 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2453 if (!regs)
2454 return -ENXIO;
2455 pdata = pdev->dev.platform_data;
2456 if (!pdata) {
2457 pdata = atmci_of_init(pdev);
2458 if (IS_ERR(pdata)) {
2459 dev_err(&pdev->dev, "platform data not available\n");
2460 return PTR_ERR(pdata);
2461 }
2462 }
2463
2464 irq = platform_get_irq(pdev, 0);
2465 if (irq < 0)
2466 return irq;
2467
2468 host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
2469 if (!host)
2470 return -ENOMEM;
2471
2472 host->pdev = pdev;
2473 spin_lock_init(&host->lock);
2474 INIT_LIST_HEAD(&host->queue);
2475
2476 host->mck = devm_clk_get(&pdev->dev, "mci_clk");
2477 if (IS_ERR(host->mck))
2478 return PTR_ERR(host->mck);
2479
2480 host->regs = devm_ioremap(&pdev->dev, regs->start, resource_size(regs));
2481 if (!host->regs)
2482 return -ENOMEM;
2483
2484 ret = clk_prepare_enable(host->mck);
2485 if (ret)
2486 return ret;
2487
2488 atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
2489 host->bus_hz = clk_get_rate(host->mck);
2490
2491 host->mapbase = regs->start;
2492
2493 tasklet_init(&host->tasklet, atmci_tasklet_func, (unsigned long)host);
2494
2495 ret = request_irq(irq, atmci_interrupt, 0, dev_name(&pdev->dev), host);
2496 if (ret) {
2497 clk_disable_unprepare(host->mck);
2498 return ret;
2499 }
2500
2501 /* Get MCI capabilities and set operations according to it */
2502 atmci_get_cap(host);
2503 ret = atmci_configure_dma(host);
2504 if (ret == -EPROBE_DEFER)
2505 goto err_dma_probe_defer;
2506 if (ret == 0) {
2507 host->prepare_data = &atmci_prepare_data_dma;
2508 host->submit_data = &atmci_submit_data_dma;
2509 host->stop_transfer = &atmci_stop_transfer_dma;
2510 } else if (host->caps.has_pdc) {
2511 dev_info(&pdev->dev, "using PDC\n");
2512 host->prepare_data = &atmci_prepare_data_pdc;
2513 host->submit_data = &atmci_submit_data_pdc;
2514 host->stop_transfer = &atmci_stop_transfer_pdc;
2515 } else {
2516 dev_info(&pdev->dev, "using PIO\n");
2517 host->prepare_data = &atmci_prepare_data;
2518 host->submit_data = &atmci_submit_data;
2519 host->stop_transfer = &atmci_stop_transfer;
2520 }
2521
2522 platform_set_drvdata(pdev, host);
2523
2524 timer_setup(&host->timer, atmci_timeout_timer, 0);
2525
2526 pm_runtime_get_noresume(&pdev->dev);
2527 pm_runtime_set_active(&pdev->dev);
2528 pm_runtime_set_autosuspend_delay(&pdev->dev, AUTOSUSPEND_DELAY);
2529 pm_runtime_use_autosuspend(&pdev->dev);
2530 pm_runtime_enable(&pdev->dev);
2531
2532 /* We need at least one slot to succeed */
2533 nr_slots = 0;
2534 ret = -ENODEV;
2535 if (pdata->slot[0].bus_width) {
2536 ret = atmci_init_slot(host, &pdata->slot[0],
2537 0, ATMCI_SDCSEL_SLOT_A, ATMCI_SDIOIRQA);
2538 if (!ret) {
2539 nr_slots++;
2540 host->buf_size = host->slot[0]->mmc->max_req_size;
2541 }
2542 }
2543 if (pdata->slot[1].bus_width) {
2544 ret = atmci_init_slot(host, &pdata->slot[1],
2545 1, ATMCI_SDCSEL_SLOT_B, ATMCI_SDIOIRQB);
2546 if (!ret) {
2547 nr_slots++;
2548 if (host->slot[1]->mmc->max_req_size > host->buf_size)
2549 host->buf_size =
2550 host->slot[1]->mmc->max_req_size;
2551 }
2552 }
2553
2554 if (!nr_slots) {
2555 dev_err(&pdev->dev, "init failed: no slot defined\n");
2556 goto err_init_slot;
2557 }
2558
2559 if (!host->caps.has_rwproof) {
2560 host->buffer = dma_alloc_coherent(&pdev->dev, host->buf_size,
2561 &host->buf_phys_addr,
2562 GFP_KERNEL);
2563 if (!host->buffer) {
2564 ret = -ENOMEM;
2565 dev_err(&pdev->dev, "buffer allocation failed\n");
2566 goto err_dma_alloc;
2567 }
2568 }
2569
2570 dev_info(&pdev->dev,
2571 "Atmel MCI controller at 0x%08lx irq %d, %u slots\n",
2572 host->mapbase, irq, nr_slots);
2573
2574 pm_runtime_mark_last_busy(&host->pdev->dev);
2575 pm_runtime_put_autosuspend(&pdev->dev);
2576
2577 return 0;
2578
2579 err_dma_alloc:
2580 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
2581 if (host->slot[i])
2582 atmci_cleanup_slot(host->slot[i], i);
2583 }
2584 err_init_slot:
2585 clk_disable_unprepare(host->mck);
2586
2587 pm_runtime_disable(&pdev->dev);
2588 pm_runtime_put_noidle(&pdev->dev);
2589
2590 del_timer_sync(&host->timer);
2591 if (!IS_ERR(host->dma.chan))
2592 dma_release_channel(host->dma.chan);
2593 err_dma_probe_defer:
2594 free_irq(irq, host);
2595 return ret;
2596 }
2597
2598 static int atmci_remove(struct platform_device *pdev)
2599 {
2600 struct atmel_mci *host = platform_get_drvdata(pdev);
2601 unsigned int i;
2602
2603 pm_runtime_get_sync(&pdev->dev);
2604
2605 if (host->buffer)
2606 dma_free_coherent(&pdev->dev, host->buf_size,
2607 host->buffer, host->buf_phys_addr);
2608
2609 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
2610 if (host->slot[i])
2611 atmci_cleanup_slot(host->slot[i], i);
2612 }
2613
2614 atmci_writel(host, ATMCI_IDR, ~0UL);
2615 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIDIS);
2616 atmci_readl(host, ATMCI_SR);
2617
2618 del_timer_sync(&host->timer);
2619 if (!IS_ERR(host->dma.chan))
2620 dma_release_channel(host->dma.chan);
2621
2622 free_irq(platform_get_irq(pdev, 0), host);
2623
2624 clk_disable_unprepare(host->mck);
2625
2626 pm_runtime_disable(&pdev->dev);
2627 pm_runtime_put_noidle(&pdev->dev);
2628
2629 return 0;
2630 }
2631
2632 #ifdef CONFIG_PM
2633 static int atmci_runtime_suspend(struct device *dev)
2634 {
2635 struct atmel_mci *host = dev_get_drvdata(dev);
2636
2637 clk_disable_unprepare(host->mck);
2638
2639 pinctrl_pm_select_sleep_state(dev);
2640
2641 return 0;
2642 }
2643
2644 static int atmci_runtime_resume(struct device *dev)
2645 {
2646 struct atmel_mci *host = dev_get_drvdata(dev);
2647
2648 pinctrl_select_default_state(dev);
2649
2650 return clk_prepare_enable(host->mck);
2651 }
2652 #endif
2653
2654 static const struct dev_pm_ops atmci_dev_pm_ops = {
2655 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
2656 pm_runtime_force_resume)
2657 SET_RUNTIME_PM_OPS(atmci_runtime_suspend, atmci_runtime_resume, NULL)
2658 };
2659
2660 static struct platform_driver atmci_driver = {
2661 .probe = atmci_probe,
2662 .remove = atmci_remove,
2663 .driver = {
2664 .name = "atmel_mci",
2665 .of_match_table = of_match_ptr(atmci_dt_ids),
2666 .pm = &atmci_dev_pm_ops,
2667 },
2668 };
2669 module_platform_driver(atmci_driver);
2670
2671 MODULE_DESCRIPTION("Atmel Multimedia Card Interface driver");
2672 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
2673 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support