drivers/mmc/host/mvsdio.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  *  Copyright (C) 2008 Marvell Semiconductors, All Rights Reserved.
   4  */
   5
   6 #ifndef __MVSDIO_H
   7 #define __MVSDIO_H
   8
   9 /*
  10  * Clock rates
  11  */
  12
  13 #define MVSD_CLOCKRATE_MAX                      50000000
  14 #define MVSD_BASE_DIV_MAX                       0x7ff
  15
  16
  17 /*
  18  * Register offsets
  19  */
  20
  21 #define MVSD_SYS_ADDR_LOW                       0x000
  22 #define MVSD_SYS_ADDR_HI                        0x004
  23 #define MVSD_BLK_SIZE                           0x008
  24 #define MVSD_BLK_COUNT                          0x00c
  25 #define MVSD_ARG_LOW                            0x010
  26 #define MVSD_ARG_HI                             0x014
  27 #define MVSD_XFER_MODE                          0x018
  28 #define MVSD_CMD                                0x01c
  29 #define MVSD_RSP(i)                             (0x020 + ((i)<<2))
  30 #define MVSD_RSP0                               0x020
  31 #define MVSD_RSP1                               0x024
  32 #define MVSD_RSP2                               0x028
  33 #define MVSD_RSP3                               0x02c
  34 #define MVSD_RSP4                               0x030
  35 #define MVSD_RSP5                               0x034
  36 #define MVSD_RSP6                               0x038
  37 #define MVSD_RSP7                               0x03c
  38 #define MVSD_FIFO                               0x040
  39 #define MVSD_RSP_CRC7                           0x044
  40 #define MVSD_HW_STATE                           0x048
  41 #define MVSD_HOST_CTRL                          0x050
  42 #define MVSD_BLK_GAP_CTRL                       0x054
  43 #define MVSD_CLK_CTRL                           0x058
  44 #define MVSD_SW_RESET                           0x05c
  45 #define MVSD_NOR_INTR_STATUS                    0x060
  46 #define MVSD_ERR_INTR_STATUS                    0x064
  47 #define MVSD_NOR_STATUS_EN                      0x068
  48 #define MVSD_ERR_STATUS_EN                      0x06c
  49 #define MVSD_NOR_INTR_EN                        0x070
  50 #define MVSD_ERR_INTR_EN                        0x074
  51 #define MVSD_AUTOCMD12_ERR_STATUS               0x078
  52 #define MVSD_CURR_BYTE_LEFT                     0x07c
  53 #define MVSD_CURR_BLK_LEFT                      0x080
  54 #define MVSD_AUTOCMD12_ARG_LOW                  0x084
  55 #define MVSD_AUTOCMD12_ARG_HI                   0x088
  56 #define MVSD_AUTOCMD12_CMD                      0x08c
  57 #define MVSD_AUTO_RSP(i)                        (0x090 + ((i)<<2))
  58 #define MVSD_AUTO_RSP0                          0x090
  59 #define MVSD_AUTO_RSP1                          0x094
  60 #define MVSD_AUTO_RSP2                          0x098
  61 #define MVSD_CLK_DIV                            0x128
  62
  63 #define MVSD_WINDOW_CTRL(i)                     (0x108 + ((i) << 3))
  64 #define MVSD_WINDOW_BASE(i)                     (0x10c + ((i) << 3))
  65
  66
  67 /*
  68  * MVSD_CMD
  69  */
  70
  71 #define MVSD_CMD_RSP_NONE                       (0 << 0)
  72 #define MVSD_CMD_RSP_136                        (1 << 0)
  73 #define MVSD_CMD_RSP_48                         (2 << 0)
  74 #define MVSD_CMD_RSP_48BUSY                     (3 << 0)
  75
  76 #define MVSD_CMD_CHECK_DATACRC16                (1 << 2)
  77 #define MVSD_CMD_CHECK_CMDCRC                   (1 << 3)
  78 #define MVSD_CMD_INDX_CHECK                     (1 << 4)
  79 #define MVSD_CMD_DATA_PRESENT                   (1 << 5)
  80 #define MVSD_UNEXPECTED_RESP                    (1 << 7)
  81 #define MVSD_CMD_INDEX(x)                       ((x) << 8)
  82
  83
  84 /*
  85  * MVSD_AUTOCMD12_CMD
  86  */
  87
  88 #define MVSD_AUTOCMD12_BUSY                     (1 << 0)
  89 #define MVSD_AUTOCMD12_INDX_CHECK               (1 << 1)
  90 #define MVSD_AUTOCMD12_INDEX(x)                 ((x) << 8)
  91
  92 /*
  93  * MVSD_XFER_MODE
  94  */
  95
  96 #define MVSD_XFER_MODE_WR_DATA_START            (1 << 0)
  97 #define MVSD_XFER_MODE_HW_WR_DATA_EN            (1 << 1)
  98 #define MVSD_XFER_MODE_AUTO_CMD12               (1 << 2)
  99 #define MVSD_XFER_MODE_INT_CHK_EN               (1 << 3)
 100 #define MVSD_XFER_MODE_TO_HOST                  (1 << 4)
 101 #define MVSD_XFER_MODE_STOP_CLK                 (1 << 5)
 102 #define MVSD_XFER_MODE_PIO                      (1 << 6)
 103
 104
 105 /*
 106  * MVSD_HOST_CTRL
 107  */
 108
 109 #define MVSD_HOST_CTRL_PUSH_PULL_EN             (1 << 0)
 110
 111 #define MVSD_HOST_CTRL_CARD_TYPE_MEM_ONLY       (0 << 1)
 112 #define MVSD_HOST_CTRL_CARD_TYPE_IO_ONLY        (1 << 1)
 113 #define MVSD_HOST_CTRL_CARD_TYPE_IO_MEM_COMBO   (2 << 1)
 114 #define MVSD_HOST_CTRL_CARD_TYPE_IO_MMC         (3 << 1)
 115 #define MVSD_HOST_CTRL_CARD_TYPE_MASK           (3 << 1)
 116
 117 #define MVSD_HOST_CTRL_BIG_ENDIAN               (1 << 3)
 118 #define MVSD_HOST_CTRL_LSB_FIRST                (1 << 4)
 119 #define MVSD_HOST_CTRL_DATA_WIDTH_4_BITS        (1 << 9)
 120 #define MVSD_HOST_CTRL_HI_SPEED_EN              (1 << 10)
 121
 122 #define MVSD_HOST_CTRL_TMOUT_MAX                0xf
 123 #define MVSD_HOST_CTRL_TMOUT_MASK               (0xf << 11)
 124 #define MVSD_HOST_CTRL_TMOUT(x)                 ((x) << 11)
 125 #define MVSD_HOST_CTRL_TMOUT_EN                 (1 << 15)
 126
 127
 128 /*
 129  * MVSD_SW_RESET
 130  */
 131
 132 #define MVSD_SW_RESET_NOW                       (1 << 8)
 133
 134
 135 /*
 136  * Normal interrupt status bits
 137  */
 138
 139 #define MVSD_NOR_CMD_DONE                       (1 << 0)
 140 #define MVSD_NOR_XFER_DONE                      (1 << 1)
 141 #define MVSD_NOR_BLK_GAP_EVT                    (1 << 2)
 142 #define MVSD_NOR_DMA_DONE                       (1 << 3)
 143 #define MVSD_NOR_TX_AVAIL                       (1 << 4)
 144 #define MVSD_NOR_RX_READY                       (1 << 5)
 145 #define MVSD_NOR_CARD_INT                       (1 << 8)
 146 #define MVSD_NOR_READ_WAIT_ON                   (1 << 9)
 147 #define MVSD_NOR_RX_FIFO_8W                     (1 << 10)
 148 #define MVSD_NOR_TX_FIFO_8W                     (1 << 11)
 149 #define MVSD_NOR_SUSPEND_ON                     (1 << 12)
 150 #define MVSD_NOR_AUTOCMD12_DONE                 (1 << 13)
 151 #define MVSD_NOR_UNEXP_RSP                      (1 << 14)
 152 #define MVSD_NOR_ERROR                          (1 << 15)
 153
 154
 155 /*
 156  * Error status bits
 157  */
 158
 159 #define MVSD_ERR_CMD_TIMEOUT                    (1 << 0)
 160 #define MVSD_ERR_CMD_CRC                        (1 << 1)
 161 #define MVSD_ERR_CMD_ENDBIT                     (1 << 2)
 162 #define MVSD_ERR_CMD_INDEX                      (1 << 3)
 163 #define MVSD_ERR_DATA_TIMEOUT                   (1 << 4)
 164 #define MVSD_ERR_DATA_CRC                       (1 << 5)
 165 #define MVSD_ERR_DATA_ENDBIT                    (1 << 6)
 166 #define MVSD_ERR_AUTOCMD12                      (1 << 8)
 167 #define MVSD_ERR_CMD_STARTBIT                   (1 << 9)
 168 #define MVSD_ERR_XFER_SIZE                      (1 << 10)
 169 #define MVSD_ERR_RESP_T_BIT                     (1 << 11)
 170 #define MVSD_ERR_CRC_ENDBIT                     (1 << 12)
 171 #define MVSD_ERR_CRC_STARTBIT                   (1 << 13)
 172 #define MVSD_ERR_CRC_STATUS                     (1 << 14)
 173
 174
 175 /*
 176  * CMD12 error status bits
 177  */
 178
 179 #define MVSD_AUTOCMD12_ERR_NOTEXE               (1 << 0)
 180 #define MVSD_AUTOCMD12_ERR_TIMEOUT              (1 << 1)
 181 #define MVSD_AUTOCMD12_ERR_CRC                  (1 << 2)
 182 #define MVSD_AUTOCMD12_ERR_ENDBIT               (1 << 3)
 183 #define MVSD_AUTOCMD12_ERR_INDEX                (1 << 4)
 184 #define MVSD_AUTOCMD12_ERR_RESP_T_BIT           (1 << 5)
 185 #define MVSD_AUTOCMD12_ERR_RESP_STARTBIT        (1 << 6)
 186
 187 #endif