?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
treewide: remove redundant IS_ERR() before error code check
[linux/fpc-iii.git] / drivers / mmc / host / mxcmmc.c
blobb3d654c688e52769b50745eb6f7db574535f86dc
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * linux/drivers/mmc/host/mxcmmc.c - Freescale i.MX MMCI driver
4 *
5 * This is a driver for the SDHC controller found in Freescale MX2/MX3
6 * SoCs. It is basically the same hardware as found on MX1 (imxmmc.c).
7 * Unlike the hardware found on MX1, this hardware just works and does
8 * not need all the quirks found in imxmmc.c, hence the separate driver.
9 *
10 * Copyright (C) 2008 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
11 * Copyright (C) 2006 Pavel Pisa, PiKRON <ppisa@pikron.com>
12 *
13 * derived from pxamci.c by Russell King
14 */
15
16 #include <linux/module.h>
17 #include <linux/init.h>
18 #include <linux/ioport.h>
19 #include <linux/platform_device.h>
20 #include <linux/highmem.h>
21 #include <linux/interrupt.h>
22 #include <linux/irq.h>
23 #include <linux/blkdev.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/mmc/host.h>
26 #include <linux/mmc/card.h>
27 #include <linux/delay.h>
28 #include <linux/clk.h>
29 #include <linux/io.h>
30 #include <linux/regulator/consumer.h>
31 #include <linux/dmaengine.h>
32 #include <linux/types.h>
33 #include <linux/of.h>
34 #include <linux/of_device.h>
35 #include <linux/of_dma.h>
36 #include <linux/mmc/slot-gpio.h>
37
38 #include <asm/dma.h>
39 #include <asm/irq.h>
40 #include <linux/platform_data/mmc-mxcmmc.h>
41
42 #include <linux/platform_data/dma-imx.h>
43
44 #define DRIVER_NAME "mxc-mmc"
45 #define MXCMCI_TIMEOUT_MS 10000
46
47 #define MMC_REG_STR_STP_CLK 0x00
48 #define MMC_REG_STATUS 0x04
49 #define MMC_REG_CLK_RATE 0x08
50 #define MMC_REG_CMD_DAT_CONT 0x0C
51 #define MMC_REG_RES_TO 0x10
52 #define MMC_REG_READ_TO 0x14
53 #define MMC_REG_BLK_LEN 0x18
54 #define MMC_REG_NOB 0x1C
55 #define MMC_REG_REV_NO 0x20
56 #define MMC_REG_INT_CNTR 0x24
57 #define MMC_REG_CMD 0x28
58 #define MMC_REG_ARG 0x2C
59 #define MMC_REG_RES_FIFO 0x34
60 #define MMC_REG_BUFFER_ACCESS 0x38
61
62 #define STR_STP_CLK_RESET (1 << 3)
63 #define STR_STP_CLK_START_CLK (1 << 1)
64 #define STR_STP_CLK_STOP_CLK (1 << 0)
65
66 #define STATUS_CARD_INSERTION (1 << 31)
67 #define STATUS_CARD_REMOVAL (1 << 30)
68 #define STATUS_YBUF_EMPTY (1 << 29)
69 #define STATUS_XBUF_EMPTY (1 << 28)
70 #define STATUS_YBUF_FULL (1 << 27)
71 #define STATUS_XBUF_FULL (1 << 26)
72 #define STATUS_BUF_UND_RUN (1 << 25)
73 #define STATUS_BUF_OVFL (1 << 24)
74 #define STATUS_SDIO_INT_ACTIVE (1 << 14)
75 #define STATUS_END_CMD_RESP (1 << 13)
76 #define STATUS_WRITE_OP_DONE (1 << 12)
77 #define STATUS_DATA_TRANS_DONE (1 << 11)
78 #define STATUS_READ_OP_DONE (1 << 11)
79 #define STATUS_WR_CRC_ERROR_CODE_MASK (3 << 10)
80 #define STATUS_CARD_BUS_CLK_RUN (1 << 8)
81 #define STATUS_BUF_READ_RDY (1 << 7)
82 #define STATUS_BUF_WRITE_RDY (1 << 6)
83 #define STATUS_RESP_CRC_ERR (1 << 5)
84 #define STATUS_CRC_READ_ERR (1 << 3)
85 #define STATUS_CRC_WRITE_ERR (1 << 2)
86 #define STATUS_TIME_OUT_RESP (1 << 1)
87 #define STATUS_TIME_OUT_READ (1 << 0)
88 #define STATUS_ERR_MASK 0x2f
89
90 #define CMD_DAT_CONT_CMD_RESP_LONG_OFF (1 << 12)
91 #define CMD_DAT_CONT_STOP_READWAIT (1 << 11)
92 #define CMD_DAT_CONT_START_READWAIT (1 << 10)
93 #define CMD_DAT_CONT_BUS_WIDTH_4 (2 << 8)
94 #define CMD_DAT_CONT_INIT (1 << 7)
95 #define CMD_DAT_CONT_WRITE (1 << 4)
96 #define CMD_DAT_CONT_DATA_ENABLE (1 << 3)
97 #define CMD_DAT_CONT_RESPONSE_48BIT_CRC (1 << 0)
98 #define CMD_DAT_CONT_RESPONSE_136BIT (2 << 0)
99 #define CMD_DAT_CONT_RESPONSE_48BIT (3 << 0)
100
101 #define INT_SDIO_INT_WKP_EN (1 << 18)
102 #define INT_CARD_INSERTION_WKP_EN (1 << 17)
103 #define INT_CARD_REMOVAL_WKP_EN (1 << 16)
104 #define INT_CARD_INSERTION_EN (1 << 15)
105 #define INT_CARD_REMOVAL_EN (1 << 14)
106 #define INT_SDIO_IRQ_EN (1 << 13)
107 #define INT_DAT0_EN (1 << 12)
108 #define INT_BUF_READ_EN (1 << 4)
109 #define INT_BUF_WRITE_EN (1 << 3)
110 #define INT_END_CMD_RES_EN (1 << 2)
111 #define INT_WRITE_OP_DONE_EN (1 << 1)
112 #define INT_READ_OP_EN (1 << 0)
113
114 enum mxcmci_type {
115 IMX21_MMC,
116 IMX31_MMC,
117 MPC512X_MMC,
118 };
119
120 struct mxcmci_host {
121 struct mmc_host *mmc;
122 void __iomem *base;
123 dma_addr_t phys_base;
124 int detect_irq;
125 struct dma_chan *dma;
126 struct dma_async_tx_descriptor *desc;
127 int do_dma;
128 int default_irq_mask;
129 int use_sdio;
130 unsigned int power_mode;
131 struct imxmmc_platform_data *pdata;
132
133 struct mmc_request *req;
134 struct mmc_command *cmd;
135 struct mmc_data *data;
136
137 unsigned int datasize;
138 unsigned int dma_dir;
139
140 u16 rev_no;
141 unsigned int cmdat;
142
143 struct clk *clk_ipg;
144 struct clk *clk_per;
145
146 int clock;
147
148 struct work_struct datawork;
149 spinlock_t lock;
150
151 int burstlen;
152 int dmareq;
153 struct dma_slave_config dma_slave_config;
154 struct imx_dma_data dma_data;
155
156 struct timer_list watchdog;
157 enum mxcmci_type devtype;
158 };
159
160 static const struct platform_device_id mxcmci_devtype[] = {
161 {
162 .name = "imx21-mmc",
163 .driver_data = IMX21_MMC,
164 }, {
165 .name = "imx31-mmc",
166 .driver_data = IMX31_MMC,
167 }, {
168 .name = "mpc512x-sdhc",
169 .driver_data = MPC512X_MMC,
170 }, {
171 /* sentinel */
172 }
173 };
174 MODULE_DEVICE_TABLE(platform, mxcmci_devtype);
175
176 static const struct of_device_id mxcmci_of_match[] = {
177 {
178 .compatible = "fsl,imx21-mmc",
179 .data = &mxcmci_devtype[IMX21_MMC],
180 }, {
181 .compatible = "fsl,imx31-mmc",
182 .data = &mxcmci_devtype[IMX31_MMC],
183 }, {
184 .compatible = "fsl,mpc5121-sdhc",
185 .data = &mxcmci_devtype[MPC512X_MMC],
186 }, {
187 /* sentinel */
188 }
189 };
190 MODULE_DEVICE_TABLE(of, mxcmci_of_match);
191
192 static inline int is_imx31_mmc(struct mxcmci_host *host)
193 {
194 return host->devtype == IMX31_MMC;
195 }
196
197 static inline int is_mpc512x_mmc(struct mxcmci_host *host)
198 {
199 return host->devtype == MPC512X_MMC;
200 }
201
202 static inline u32 mxcmci_readl(struct mxcmci_host *host, int reg)
203 {
204 if (IS_ENABLED(CONFIG_PPC_MPC512x))
205 return ioread32be(host->base + reg);
206 else
207 return readl(host->base + reg);
208 }
209
210 static inline void mxcmci_writel(struct mxcmci_host *host, u32 val, int reg)
211 {
212 if (IS_ENABLED(CONFIG_PPC_MPC512x))
213 iowrite32be(val, host->base + reg);
214 else
215 writel(val, host->base + reg);
216 }
217
218 static inline u16 mxcmci_readw(struct mxcmci_host *host, int reg)
219 {
220 if (IS_ENABLED(CONFIG_PPC_MPC512x))
221 return ioread32be(host->base + reg);
222 else
223 return readw(host->base + reg);
224 }
225
226 static inline void mxcmci_writew(struct mxcmci_host *host, u16 val, int reg)
227 {
228 if (IS_ENABLED(CONFIG_PPC_MPC512x))
229 iowrite32be(val, host->base + reg);
230 else
231 writew(val, host->base + reg);
232 }
233
234 static void mxcmci_set_clk_rate(struct mxcmci_host *host, unsigned int clk_ios);
235
236 static void mxcmci_set_power(struct mxcmci_host *host, unsigned int vdd)
237 {
238 if (!IS_ERR(host->mmc->supply.vmmc)) {
239 if (host->power_mode == MMC_POWER_UP)
240 mmc_regulator_set_ocr(host->mmc,
241 host->mmc->supply.vmmc, vdd);
242 else if (host->power_mode == MMC_POWER_OFF)
243 mmc_regulator_set_ocr(host->mmc,
244 host->mmc->supply.vmmc, 0);
245 }
246
247 if (host->pdata && host->pdata->setpower)
248 host->pdata->setpower(mmc_dev(host->mmc), vdd);
249 }
250
251 static inline int mxcmci_use_dma(struct mxcmci_host *host)
252 {
253 return host->do_dma;
254 }
255
256 static void mxcmci_softreset(struct mxcmci_host *host)
257 {
258 int i;
259
260 dev_dbg(mmc_dev(host->mmc), "mxcmci_softreset\n");
261
262 /* reset sequence */
263 mxcmci_writew(host, STR_STP_CLK_RESET, MMC_REG_STR_STP_CLK);
264 mxcmci_writew(host, STR_STP_CLK_RESET | STR_STP_CLK_START_CLK,
265 MMC_REG_STR_STP_CLK);
266
267 for (i = 0; i < 8; i++)
268 mxcmci_writew(host, STR_STP_CLK_START_CLK, MMC_REG_STR_STP_CLK);
269
270 mxcmci_writew(host, 0xff, MMC_REG_RES_TO);
271 }
272
273 #if IS_ENABLED(CONFIG_PPC_MPC512x)
274 static inline void buffer_swap32(u32 *buf, int len)
275 {
276 int i;
277
278 for (i = 0; i < ((len + 3) / 4); i++) {
279 *buf = swab32(*buf);
280 buf++;
281 }
282 }
283
284 static void mxcmci_swap_buffers(struct mmc_data *data)
285 {
286 struct scatterlist *sg;
287 int i;
288
289 for_each_sg(data->sg, sg, data->sg_len, i)
290 buffer_swap32(sg_virt(sg), sg->length);
291 }
292 #else
293 static inline void mxcmci_swap_buffers(struct mmc_data *data) {}
294 #endif
295
296 static int mxcmci_setup_data(struct mxcmci_host *host, struct mmc_data *data)
297 {
298 unsigned int nob = data->blocks;
299 unsigned int blksz = data->blksz;
300 unsigned int datasize = nob * blksz;
301 struct scatterlist *sg;
302 enum dma_transfer_direction slave_dirn;
303 int i, nents;
304
305 host->data = data;
306 data->bytes_xfered = 0;
307
308 mxcmci_writew(host, nob, MMC_REG_NOB);
309 mxcmci_writew(host, blksz, MMC_REG_BLK_LEN);
310 host->datasize = datasize;
311
312 if (!mxcmci_use_dma(host))
313 return 0;
314
315 for_each_sg(data->sg, sg, data->sg_len, i) {
316 if (sg->offset & 3 || sg->length & 3 || sg->length < 512) {
317 host->do_dma = 0;
318 return 0;
319 }
320 }
321
322 if (data->flags & MMC_DATA_READ) {
323 host->dma_dir = DMA_FROM_DEVICE;
324 slave_dirn = DMA_DEV_TO_MEM;
325 } else {
326 host->dma_dir = DMA_TO_DEVICE;
327 slave_dirn = DMA_MEM_TO_DEV;
328
329 mxcmci_swap_buffers(data);
330 }
331
332 nents = dma_map_sg(host->dma->device->dev, data->sg,
333 data->sg_len, host->dma_dir);
334 if (nents != data->sg_len)
335 return -EINVAL;
336
337 host->desc = dmaengine_prep_slave_sg(host->dma,
338 data->sg, data->sg_len, slave_dirn,
339 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
340
341 if (!host->desc) {
342 dma_unmap_sg(host->dma->device->dev, data->sg, data->sg_len,
343 host->dma_dir);
344 host->do_dma = 0;
345 return 0; /* Fall back to PIO */
346 }
347 wmb();
348
349 dmaengine_submit(host->desc);
350 dma_async_issue_pending(host->dma);
351
352 mod_timer(&host->watchdog, jiffies + msecs_to_jiffies(MXCMCI_TIMEOUT_MS));
353
354 return 0;
355 }
356
357 static void mxcmci_cmd_done(struct mxcmci_host *host, unsigned int stat);
358 static void mxcmci_data_done(struct mxcmci_host *host, unsigned int stat);
359
360 static void mxcmci_dma_callback(void *data)
361 {
362 struct mxcmci_host *host = data;
363 u32 stat;
364
365 del_timer(&host->watchdog);
366
367 stat = mxcmci_readl(host, MMC_REG_STATUS);
368
369 dev_dbg(mmc_dev(host->mmc), "%s: 0x%08x\n", __func__, stat);
370
371 mxcmci_data_done(host, stat);
372 }
373
374 static int mxcmci_start_cmd(struct mxcmci_host *host, struct mmc_command *cmd,
375 unsigned int cmdat)
376 {
377 u32 int_cntr = host->default_irq_mask;
378 unsigned long flags;
379
380 WARN_ON(host->cmd != NULL);
381 host->cmd = cmd;
382
383 switch (mmc_resp_type(cmd)) {
384 case MMC_RSP_R1: /* short CRC, OPCODE */
385 case MMC_RSP_R1B:/* short CRC, OPCODE, BUSY */
386 cmdat |= CMD_DAT_CONT_RESPONSE_48BIT_CRC;
387 break;
388 case MMC_RSP_R2: /* long 136 bit + CRC */
389 cmdat |= CMD_DAT_CONT_RESPONSE_136BIT;
390 break;
391 case MMC_RSP_R3: /* short */
392 cmdat |= CMD_DAT_CONT_RESPONSE_48BIT;
393 break;
394 case MMC_RSP_NONE:
395 break;
396 default:
397 dev_err(mmc_dev(host->mmc), "unhandled response type 0x%x\n",
398 mmc_resp_type(cmd));
399 cmd->error = -EINVAL;
400 return -EINVAL;
401 }
402
403 int_cntr = INT_END_CMD_RES_EN;
404
405 if (mxcmci_use_dma(host)) {
406 if (host->dma_dir == DMA_FROM_DEVICE) {
407 host->desc->callback = mxcmci_dma_callback;
408 host->desc->callback_param = host;
409 } else {
410 int_cntr |= INT_WRITE_OP_DONE_EN;
411 }
412 }
413
414 spin_lock_irqsave(&host->lock, flags);
415 if (host->use_sdio)
416 int_cntr |= INT_SDIO_IRQ_EN;
417 mxcmci_writel(host, int_cntr, MMC_REG_INT_CNTR);
418 spin_unlock_irqrestore(&host->lock, flags);
419
420 mxcmci_writew(host, cmd->opcode, MMC_REG_CMD);
421 mxcmci_writel(host, cmd->arg, MMC_REG_ARG);
422 mxcmci_writew(host, cmdat, MMC_REG_CMD_DAT_CONT);
423
424 return 0;
425 }
426
427 static void mxcmci_finish_request(struct mxcmci_host *host,
428 struct mmc_request *req)
429 {
430 u32 int_cntr = host->default_irq_mask;
431 unsigned long flags;
432
433 spin_lock_irqsave(&host->lock, flags);
434 if (host->use_sdio)
435 int_cntr |= INT_SDIO_IRQ_EN;
436 mxcmci_writel(host, int_cntr, MMC_REG_INT_CNTR);
437 spin_unlock_irqrestore(&host->lock, flags);
438
439 host->req = NULL;
440 host->cmd = NULL;
441 host->data = NULL;
442
443 mmc_request_done(host->mmc, req);
444 }
445
446 static int mxcmci_finish_data(struct mxcmci_host *host, unsigned int stat)
447 {
448 struct mmc_data *data = host->data;
449 int data_error;
450
451 if (mxcmci_use_dma(host)) {
452 dma_unmap_sg(host->dma->device->dev, data->sg, data->sg_len,
453 host->dma_dir);
454 mxcmci_swap_buffers(data);
455 }
456
457 if (stat & STATUS_ERR_MASK) {
458 dev_dbg(mmc_dev(host->mmc), "request failed. status: 0x%08x\n",
459 stat);
460 if (stat & STATUS_CRC_READ_ERR) {
461 dev_err(mmc_dev(host->mmc), "%s: -EILSEQ\n", __func__);
462 data->error = -EILSEQ;
463 } else if (stat & STATUS_CRC_WRITE_ERR) {
464 u32 err_code = (stat >> 9) & 0x3;
465 if (err_code == 2) { /* No CRC response */
466 dev_err(mmc_dev(host->mmc),
467 "%s: No CRC -ETIMEDOUT\n", __func__);
468 data->error = -ETIMEDOUT;
469 } else {
470 dev_err(mmc_dev(host->mmc),
471 "%s: -EILSEQ\n", __func__);
472 data->error = -EILSEQ;
473 }
474 } else if (stat & STATUS_TIME_OUT_READ) {
475 dev_err(mmc_dev(host->mmc),
476 "%s: read -ETIMEDOUT\n", __func__);
477 data->error = -ETIMEDOUT;
478 } else {
479 dev_err(mmc_dev(host->mmc), "%s: -EIO\n", __func__);
480 data->error = -EIO;
481 }
482 } else {
483 data->bytes_xfered = host->datasize;
484 }
485
486 data_error = data->error;
487
488 host->data = NULL;
489
490 return data_error;
491 }
492
493 static void mxcmci_read_response(struct mxcmci_host *host, unsigned int stat)
494 {
495 struct mmc_command *cmd = host->cmd;
496 int i;
497 u32 a, b, c;
498
499 if (!cmd)
500 return;
501
502 if (stat & STATUS_TIME_OUT_RESP) {
503 dev_dbg(mmc_dev(host->mmc), "CMD TIMEOUT\n");
504 cmd->error = -ETIMEDOUT;
505 } else if (stat & STATUS_RESP_CRC_ERR && cmd->flags & MMC_RSP_CRC) {
506 dev_dbg(mmc_dev(host->mmc), "cmd crc error\n");
507 cmd->error = -EILSEQ;
508 }
509
510 if (cmd->flags & MMC_RSP_PRESENT) {
511 if (cmd->flags & MMC_RSP_136) {
512 for (i = 0; i < 4; i++) {
513 a = mxcmci_readw(host, MMC_REG_RES_FIFO);
514 b = mxcmci_readw(host, MMC_REG_RES_FIFO);
515 cmd->resp[i] = a << 16 | b;
516 }
517 } else {
518 a = mxcmci_readw(host, MMC_REG_RES_FIFO);
519 b = mxcmci_readw(host, MMC_REG_RES_FIFO);
520 c = mxcmci_readw(host, MMC_REG_RES_FIFO);
521 cmd->resp[0] = a << 24 | b << 8 | c >> 8;
522 }
523 }
524 }
525
526 static int mxcmci_poll_status(struct mxcmci_host *host, u32 mask)
527 {
528 u32 stat;
529 unsigned long timeout = jiffies + HZ;
530
531 do {
532 stat = mxcmci_readl(host, MMC_REG_STATUS);
533 if (stat & STATUS_ERR_MASK)
534 return stat;
535 if (time_after(jiffies, timeout)) {
536 mxcmci_softreset(host);
537 mxcmci_set_clk_rate(host, host->clock);
538 return STATUS_TIME_OUT_READ;
539 }
540 if (stat & mask)
541 return 0;
542 cpu_relax();
543 } while (1);
544 }
545
546 static int mxcmci_pull(struct mxcmci_host *host, void *_buf, int bytes)
547 {
548 unsigned int stat;
549 u32 *buf = _buf;
550
551 while (bytes > 3) {
552 stat = mxcmci_poll_status(host,
553 STATUS_BUF_READ_RDY | STATUS_READ_OP_DONE);
554 if (stat)
555 return stat;
556 *buf++ = cpu_to_le32(mxcmci_readl(host, MMC_REG_BUFFER_ACCESS));
557 bytes -= 4;
558 }
559
560 if (bytes) {
561 u8 *b = (u8 *)buf;
562 u32 tmp;
563
564 stat = mxcmci_poll_status(host,
565 STATUS_BUF_READ_RDY | STATUS_READ_OP_DONE);
566 if (stat)
567 return stat;
568 tmp = cpu_to_le32(mxcmci_readl(host, MMC_REG_BUFFER_ACCESS));
569 memcpy(b, &tmp, bytes);
570 }
571
572 return 0;
573 }
574
575 static int mxcmci_push(struct mxcmci_host *host, void *_buf, int bytes)
576 {
577 unsigned int stat;
578 u32 *buf = _buf;
579
580 while (bytes > 3) {
581 stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY);
582 if (stat)
583 return stat;
584 mxcmci_writel(host, cpu_to_le32(*buf++), MMC_REG_BUFFER_ACCESS);
585 bytes -= 4;
586 }
587
588 if (bytes) {
589 u8 *b = (u8 *)buf;
590 u32 tmp;
591
592 stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY);
593 if (stat)
594 return stat;
595
596 memcpy(&tmp, b, bytes);
597 mxcmci_writel(host, cpu_to_le32(tmp), MMC_REG_BUFFER_ACCESS);
598 }
599
600 return mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY);
601 }
602
603 static int mxcmci_transfer_data(struct mxcmci_host *host)
604 {
605 struct mmc_data *data = host->req->data;
606 struct scatterlist *sg;
607 int stat, i;
608
609 host->data = data;
610 host->datasize = 0;
611
612 if (data->flags & MMC_DATA_READ) {
613 for_each_sg(data->sg, sg, data->sg_len, i) {
614 stat = mxcmci_pull(host, sg_virt(sg), sg->length);
615 if (stat)
616 return stat;
617 host->datasize += sg->length;
618 }
619 } else {
620 for_each_sg(data->sg, sg, data->sg_len, i) {
621 stat = mxcmci_push(host, sg_virt(sg), sg->length);
622 if (stat)
623 return stat;
624 host->datasize += sg->length;
625 }
626 stat = mxcmci_poll_status(host, STATUS_WRITE_OP_DONE);
627 if (stat)
628 return stat;
629 }
630 return 0;
631 }
632
633 static void mxcmci_datawork(struct work_struct *work)
634 {
635 struct mxcmci_host *host = container_of(work, struct mxcmci_host,
636 datawork);
637 int datastat = mxcmci_transfer_data(host);
638
639 mxcmci_writel(host, STATUS_READ_OP_DONE | STATUS_WRITE_OP_DONE,
640 MMC_REG_STATUS);
641 mxcmci_finish_data(host, datastat);
642
643 if (host->req->stop) {
644 if (mxcmci_start_cmd(host, host->req->stop, 0)) {
645 mxcmci_finish_request(host, host->req);
646 return;
647 }
648 } else {
649 mxcmci_finish_request(host, host->req);
650 }
651 }
652
653 static void mxcmci_data_done(struct mxcmci_host *host, unsigned int stat)
654 {
655 struct mmc_request *req;
656 int data_error;
657 unsigned long flags;
658
659 spin_lock_irqsave(&host->lock, flags);
660
661 if (!host->data) {
662 spin_unlock_irqrestore(&host->lock, flags);
663 return;
664 }
665
666 if (!host->req) {
667 spin_unlock_irqrestore(&host->lock, flags);
668 return;
669 }
670
671 req = host->req;
672 if (!req->stop)
673 host->req = NULL; /* we will handle finish req below */
674
675 data_error = mxcmci_finish_data(host, stat);
676
677 spin_unlock_irqrestore(&host->lock, flags);
678
679 if (data_error)
680 return;
681
682 mxcmci_read_response(host, stat);
683 host->cmd = NULL;
684
685 if (req->stop) {
686 if (mxcmci_start_cmd(host, req->stop, 0)) {
687 mxcmci_finish_request(host, req);
688 return;
689 }
690 } else {
691 mxcmci_finish_request(host, req);
692 }
693 }
694
695 static void mxcmci_cmd_done(struct mxcmci_host *host, unsigned int stat)
696 {
697 mxcmci_read_response(host, stat);
698 host->cmd = NULL;
699
700 if (!host->data && host->req) {
701 mxcmci_finish_request(host, host->req);
702 return;
703 }
704
705 /* For the DMA case the DMA engine handles the data transfer
706 * automatically. For non DMA we have to do it ourselves.
707 * Don't do it in interrupt context though.
708 */
709 if (!mxcmci_use_dma(host) && host->data)
710 schedule_work(&host->datawork);
711
712 }
713
714 static irqreturn_t mxcmci_irq(int irq, void *devid)
715 {
716 struct mxcmci_host *host = devid;
717 bool sdio_irq;
718 u32 stat;
719
720 stat = mxcmci_readl(host, MMC_REG_STATUS);
721 mxcmci_writel(host,
722 stat & ~(STATUS_SDIO_INT_ACTIVE | STATUS_DATA_TRANS_DONE |
723 STATUS_WRITE_OP_DONE),
724 MMC_REG_STATUS);
725
726 dev_dbg(mmc_dev(host->mmc), "%s: 0x%08x\n", __func__, stat);
727
728 spin_lock(&host->lock);
729 sdio_irq = (stat & STATUS_SDIO_INT_ACTIVE) && host->use_sdio;
730 spin_unlock(&host->lock);
731
732 if (mxcmci_use_dma(host) && (stat & (STATUS_WRITE_OP_DONE)))
733 mxcmci_writel(host, STATUS_WRITE_OP_DONE, MMC_REG_STATUS);
734
735 if (sdio_irq) {
736 mxcmci_writel(host, STATUS_SDIO_INT_ACTIVE, MMC_REG_STATUS);
737 mmc_signal_sdio_irq(host->mmc);
738 }
739
740 if (stat & STATUS_END_CMD_RESP)
741 mxcmci_cmd_done(host, stat);
742
743 if (mxcmci_use_dma(host) && (stat & STATUS_WRITE_OP_DONE)) {
744 del_timer(&host->watchdog);
745 mxcmci_data_done(host, stat);
746 }
747
748 if (host->default_irq_mask &&
749 (stat & (STATUS_CARD_INSERTION | STATUS_CARD_REMOVAL)))
750 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
751
752 return IRQ_HANDLED;
753 }
754
755 static void mxcmci_request(struct mmc_host *mmc, struct mmc_request *req)
756 {
757 struct mxcmci_host *host = mmc_priv(mmc);
758 unsigned int cmdat = host->cmdat;
759 int error;
760
761 WARN_ON(host->req != NULL);
762
763 host->req = req;
764 host->cmdat &= ~CMD_DAT_CONT_INIT;
765
766 if (host->dma)
767 host->do_dma = 1;
768
769 if (req->data) {
770 error = mxcmci_setup_data(host, req->data);
771 if (error) {
772 req->cmd->error = error;
773 goto out;
774 }
775
776
777 cmdat |= CMD_DAT_CONT_DATA_ENABLE;
778
779 if (req->data->flags & MMC_DATA_WRITE)
780 cmdat |= CMD_DAT_CONT_WRITE;
781 }
782
783 error = mxcmci_start_cmd(host, req->cmd, cmdat);
784
785 out:
786 if (error)
787 mxcmci_finish_request(host, req);
788 }
789
790 static void mxcmci_set_clk_rate(struct mxcmci_host *host, unsigned int clk_ios)
791 {
792 unsigned int divider;
793 int prescaler = 0;
794 unsigned int clk_in = clk_get_rate(host->clk_per);
795
796 while (prescaler <= 0x800) {
797 for (divider = 1; divider <= 0xF; divider++) {
798 int x;
799
800 x = (clk_in / (divider + 1));
801
802 if (prescaler)
803 x /= (prescaler * 2);
804
805 if (x <= clk_ios)
806 break;
807 }
808 if (divider < 0x10)
809 break;
810
811 if (prescaler == 0)
812 prescaler = 1;
813 else
814 prescaler <<= 1;
815 }
816
817 mxcmci_writew(host, (prescaler << 4) | divider, MMC_REG_CLK_RATE);
818
819 dev_dbg(mmc_dev(host->mmc), "scaler: %d divider: %d in: %d out: %d\n",
820 prescaler, divider, clk_in, clk_ios);
821 }
822
823 static int mxcmci_setup_dma(struct mmc_host *mmc)
824 {
825 struct mxcmci_host *host = mmc_priv(mmc);
826 struct dma_slave_config *config = &host->dma_slave_config;
827
828 config->dst_addr = host->phys_base + MMC_REG_BUFFER_ACCESS;
829 config->src_addr = host->phys_base + MMC_REG_BUFFER_ACCESS;
830 config->dst_addr_width = 4;
831 config->src_addr_width = 4;
832 config->dst_maxburst = host->burstlen;
833 config->src_maxburst = host->burstlen;
834 config->device_fc = false;
835
836 return dmaengine_slave_config(host->dma, config);
837 }
838
839 static void mxcmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
840 {
841 struct mxcmci_host *host = mmc_priv(mmc);
842 int burstlen, ret;
843
844 /*
845 * use burstlen of 64 (16 words) in 4 bit mode (--> reg value 0)
846 * use burstlen of 16 (4 words) in 1 bit mode (--> reg value 16)
847 */
848 if (ios->bus_width == MMC_BUS_WIDTH_4)
849 burstlen = 16;
850 else
851 burstlen = 4;
852
853 if (mxcmci_use_dma(host) && burstlen != host->burstlen) {
854 host->burstlen = burstlen;
855 ret = mxcmci_setup_dma(mmc);
856 if (ret) {
857 dev_err(mmc_dev(host->mmc),
858 "failed to config DMA channel. Falling back to PIO\n");
859 dma_release_channel(host->dma);
860 host->do_dma = 0;
861 host->dma = NULL;
862 }
863 }
864
865 if (ios->bus_width == MMC_BUS_WIDTH_4)
866 host->cmdat |= CMD_DAT_CONT_BUS_WIDTH_4;
867 else
868 host->cmdat &= ~CMD_DAT_CONT_BUS_WIDTH_4;
869
870 if (host->power_mode != ios->power_mode) {
871 host->power_mode = ios->power_mode;
872 mxcmci_set_power(host, ios->vdd);
873
874 if (ios->power_mode == MMC_POWER_ON)
875 host->cmdat |= CMD_DAT_CONT_INIT;
876 }
877
878 if (ios->clock) {
879 mxcmci_set_clk_rate(host, ios->clock);
880 mxcmci_writew(host, STR_STP_CLK_START_CLK, MMC_REG_STR_STP_CLK);
881 } else {
882 mxcmci_writew(host, STR_STP_CLK_STOP_CLK, MMC_REG_STR_STP_CLK);
883 }
884
885 host->clock = ios->clock;
886 }
887
888 static irqreturn_t mxcmci_detect_irq(int irq, void *data)
889 {
890 struct mmc_host *mmc = data;
891
892 dev_dbg(mmc_dev(mmc), "%s\n", __func__);
893
894 mmc_detect_change(mmc, msecs_to_jiffies(250));
895 return IRQ_HANDLED;
896 }
897
898 static int mxcmci_get_ro(struct mmc_host *mmc)
899 {
900 struct mxcmci_host *host = mmc_priv(mmc);
901
902 if (host->pdata && host->pdata->get_ro)
903 return !!host->pdata->get_ro(mmc_dev(mmc));
904 /*
905 * If board doesn't support read only detection (no mmc_gpio
906 * context or gpio is invalid), then let the mmc core decide
907 * what to do.
908 */
909 return mmc_gpio_get_ro(mmc);
910 }
911
912 static void mxcmci_enable_sdio_irq(struct mmc_host *mmc, int enable)
913 {
914 struct mxcmci_host *host = mmc_priv(mmc);
915 unsigned long flags;
916 u32 int_cntr;
917
918 spin_lock_irqsave(&host->lock, flags);
919 host->use_sdio = enable;
920 int_cntr = mxcmci_readl(host, MMC_REG_INT_CNTR);
921
922 if (enable)
923 int_cntr |= INT_SDIO_IRQ_EN;
924 else
925 int_cntr &= ~INT_SDIO_IRQ_EN;
926
927 mxcmci_writel(host, int_cntr, MMC_REG_INT_CNTR);
928 spin_unlock_irqrestore(&host->lock, flags);
929 }
930
931 static void mxcmci_init_card(struct mmc_host *host, struct mmc_card *card)
932 {
933 struct mxcmci_host *mxcmci = mmc_priv(host);
934
935 /*
936 * MX3 SoCs have a silicon bug which corrupts CRC calculation of
937 * multi-block transfers when connected SDIO peripheral doesn't
938 * drive the BUSY line as required by the specs.
939 * One way to prevent this is to only allow 1-bit transfers.
940 */
941
942 if (is_imx31_mmc(mxcmci) && card->type == MMC_TYPE_SDIO)
943 host->caps &= ~MMC_CAP_4_BIT_DATA;
944 else
945 host->caps |= MMC_CAP_4_BIT_DATA;
946 }
947
948 static bool filter(struct dma_chan *chan, void *param)
949 {
950 struct mxcmci_host *host = param;
951
952 if (!imx_dma_is_general_purpose(chan))
953 return false;
954
955 chan->private = &host->dma_data;
956
957 return true;
958 }
959
960 static void mxcmci_watchdog(struct timer_list *t)
961 {
962 struct mxcmci_host *host = from_timer(host, t, watchdog);
963 struct mmc_request *req = host->req;
964 unsigned int stat = mxcmci_readl(host, MMC_REG_STATUS);
965
966 if (host->dma_dir == DMA_FROM_DEVICE) {
967 dmaengine_terminate_all(host->dma);
968 dev_err(mmc_dev(host->mmc),
969 "%s: read time out (status = 0x%08x)\n",
970 __func__, stat);
971 } else {
972 dev_err(mmc_dev(host->mmc),
973 "%s: write time out (status = 0x%08x)\n",
974 __func__, stat);
975 mxcmci_softreset(host);
976 }
977
978 /* Mark transfer as erroneus and inform the upper layers */
979
980 if (host->data)
981 host->data->error = -ETIMEDOUT;
982 host->req = NULL;
983 host->cmd = NULL;
984 host->data = NULL;
985 mmc_request_done(host->mmc, req);
986 }
987
988 static const struct mmc_host_ops mxcmci_ops = {
989 .request = mxcmci_request,
990 .set_ios = mxcmci_set_ios,
991 .get_ro = mxcmci_get_ro,
992 .enable_sdio_irq = mxcmci_enable_sdio_irq,
993 .init_card = mxcmci_init_card,
994 };
995
996 static int mxcmci_probe(struct platform_device *pdev)
997 {
998 struct mmc_host *mmc;
999 struct mxcmci_host *host;
1000 struct resource *res;
1001 int ret = 0, irq;
1002 bool dat3_card_detect = false;
1003 dma_cap_mask_t mask;
1004 const struct of_device_id *of_id;
1005 struct imxmmc_platform_data *pdata = pdev->dev.platform_data;
1006
1007 pr_info("i.MX/MPC512x SDHC driver\n");
1008
1009 of_id = of_match_device(mxcmci_of_match, &pdev->dev);
1010
1011 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1012 irq = platform_get_irq(pdev, 0);
1013 if (irq < 0)
1014 return irq;
1015
1016 mmc = mmc_alloc_host(sizeof(*host), &pdev->dev);
1017 if (!mmc)
1018 return -ENOMEM;
1019
1020 host = mmc_priv(mmc);
1021
1022 host->base = devm_ioremap_resource(&pdev->dev, res);
1023 if (IS_ERR(host->base)) {
1024 ret = PTR_ERR(host->base);
1025 goto out_free;
1026 }
1027
1028 host->phys_base = res->start;
1029
1030 ret = mmc_of_parse(mmc);
1031 if (ret)
1032 goto out_free;
1033 mmc->ops = &mxcmci_ops;
1034
1035 /* For devicetree parsing, the bus width is read from devicetree */
1036 if (pdata)
1037 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ;
1038 else
1039 mmc->caps |= MMC_CAP_SDIO_IRQ;
1040
1041 /* MMC core transfer sizes tunable parameters */
1042 mmc->max_blk_size = 2048;
1043 mmc->max_blk_count = 65535;
1044 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1045 mmc->max_seg_size = mmc->max_req_size;
1046
1047 if (of_id) {
1048 const struct platform_device_id *id_entry = of_id->data;
1049 host->devtype = id_entry->driver_data;
1050 } else {
1051 host->devtype = pdev->id_entry->driver_data;
1052 }
1053
1054 /* adjust max_segs after devtype detection */
1055 if (!is_mpc512x_mmc(host))
1056 mmc->max_segs = 64;
1057
1058 host->mmc = mmc;
1059 host->pdata = pdata;
1060 spin_lock_init(&host->lock);
1061
1062 if (pdata)
1063 dat3_card_detect = pdata->dat3_card_detect;
1064 else if (mmc_card_is_removable(mmc)
1065 && !of_property_read_bool(pdev->dev.of_node, "cd-gpios"))
1066 dat3_card_detect = true;
1067
1068 ret = mmc_regulator_get_supply(mmc);
1069 if (ret)
1070 goto out_free;
1071
1072 if (!mmc->ocr_avail) {
1073 if (pdata && pdata->ocr_avail)
1074 mmc->ocr_avail = pdata->ocr_avail;
1075 else
1076 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
1077 }
1078
1079 if (dat3_card_detect)
1080 host->default_irq_mask =
1081 INT_CARD_INSERTION_EN | INT_CARD_REMOVAL_EN;
1082 else
1083 host->default_irq_mask = 0;
1084
1085 host->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1086 if (IS_ERR(host->clk_ipg)) {
1087 ret = PTR_ERR(host->clk_ipg);
1088 goto out_free;
1089 }
1090
1091 host->clk_per = devm_clk_get(&pdev->dev, "per");
1092 if (IS_ERR(host->clk_per)) {
1093 ret = PTR_ERR(host->clk_per);
1094 goto out_free;
1095 }
1096
1097 ret = clk_prepare_enable(host->clk_per);
1098 if (ret)
1099 goto out_free;
1100
1101 ret = clk_prepare_enable(host->clk_ipg);
1102 if (ret)
1103 goto out_clk_per_put;
1104
1105 mxcmci_softreset(host);
1106
1107 host->rev_no = mxcmci_readw(host, MMC_REG_REV_NO);
1108 if (host->rev_no != 0x400) {
1109 ret = -ENODEV;
1110 dev_err(mmc_dev(host->mmc), "wrong rev.no. 0x%08x. aborting.\n",
1111 host->rev_no);
1112 goto out_clk_put;
1113 }
1114
1115 mmc->f_min = clk_get_rate(host->clk_per) >> 16;
1116 mmc->f_max = clk_get_rate(host->clk_per) >> 1;
1117
1118 /* recommended in data sheet */
1119 mxcmci_writew(host, 0x2db4, MMC_REG_READ_TO);
1120
1121 mxcmci_writel(host, host->default_irq_mask, MMC_REG_INT_CNTR);
1122
1123 if (!host->pdata) {
1124 host->dma = dma_request_chan(&pdev->dev, "rx-tx");
1125 if (IS_ERR(host->dma)) {
1126 if (PTR_ERR(host->dma) == -EPROBE_DEFER) {
1127 ret = -EPROBE_DEFER;
1128 goto out_clk_put;
1129 }
1130
1131 /* Ignore errors to fall back to PIO mode */
1132 host->dma = NULL;
1133 }
1134 } else {
1135 res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1136 if (res) {
1137 host->dmareq = res->start;
1138 host->dma_data.peripheral_type = IMX_DMATYPE_SDHC;
1139 host->dma_data.priority = DMA_PRIO_LOW;
1140 host->dma_data.dma_request = host->dmareq;
1141 dma_cap_zero(mask);
1142 dma_cap_set(DMA_SLAVE, mask);
1143 host->dma = dma_request_channel(mask, filter, host);
1144 }
1145 }
1146 if (host->dma)
1147 mmc->max_seg_size = dma_get_max_seg_size(
1148 host->dma->device->dev);
1149 else
1150 dev_info(mmc_dev(host->mmc), "dma not available. Using PIO\n");
1151
1152 INIT_WORK(&host->datawork, mxcmci_datawork);
1153
1154 ret = devm_request_irq(&pdev->dev, irq, mxcmci_irq, 0,
1155 dev_name(&pdev->dev), host);
1156 if (ret)
1157 goto out_free_dma;
1158
1159 platform_set_drvdata(pdev, mmc);
1160
1161 if (host->pdata && host->pdata->init) {
1162 ret = host->pdata->init(&pdev->dev, mxcmci_detect_irq,
1163 host->mmc);
1164 if (ret)
1165 goto out_free_dma;
1166 }
1167
1168 timer_setup(&host->watchdog, mxcmci_watchdog, 0);
1169
1170 mmc_add_host(mmc);
1171
1172 return 0;
1173
1174 out_free_dma:
1175 if (host->dma)
1176 dma_release_channel(host->dma);
1177
1178 out_clk_put:
1179 clk_disable_unprepare(host->clk_ipg);
1180 out_clk_per_put:
1181 clk_disable_unprepare(host->clk_per);
1182
1183 out_free:
1184 mmc_free_host(mmc);
1185
1186 return ret;
1187 }
1188
1189 static int mxcmci_remove(struct platform_device *pdev)
1190 {
1191 struct mmc_host *mmc = platform_get_drvdata(pdev);
1192 struct mxcmci_host *host = mmc_priv(mmc);
1193
1194 mmc_remove_host(mmc);
1195
1196 if (host->pdata && host->pdata->exit)
1197 host->pdata->exit(&pdev->dev, mmc);
1198
1199 if (host->dma)
1200 dma_release_channel(host->dma);
1201
1202 clk_disable_unprepare(host->clk_per);
1203 clk_disable_unprepare(host->clk_ipg);
1204
1205 mmc_free_host(mmc);
1206
1207 return 0;
1208 }
1209
1210 #ifdef CONFIG_PM_SLEEP
1211 static int mxcmci_suspend(struct device *dev)
1212 {
1213 struct mmc_host *mmc = dev_get_drvdata(dev);
1214 struct mxcmci_host *host = mmc_priv(mmc);
1215
1216 clk_disable_unprepare(host->clk_per);
1217 clk_disable_unprepare(host->clk_ipg);
1218 return 0;
1219 }
1220
1221 static int mxcmci_resume(struct device *dev)
1222 {
1223 struct mmc_host *mmc = dev_get_drvdata(dev);
1224 struct mxcmci_host *host = mmc_priv(mmc);
1225 int ret;
1226
1227 ret = clk_prepare_enable(host->clk_per);
1228 if (ret)
1229 return ret;
1230
1231 ret = clk_prepare_enable(host->clk_ipg);
1232 if (ret)
1233 clk_disable_unprepare(host->clk_per);
1234
1235 return ret;
1236 }
1237 #endif
1238
1239 static SIMPLE_DEV_PM_OPS(mxcmci_pm_ops, mxcmci_suspend, mxcmci_resume);
1240
1241 static struct platform_driver mxcmci_driver = {
1242 .probe = mxcmci_probe,
1243 .remove = mxcmci_remove,
1244 .id_table = mxcmci_devtype,
1245 .driver = {
1246 .name = DRIVER_NAME,
1247 .pm = &mxcmci_pm_ops,
1248 .of_match_table = mxcmci_of_match,
1249 }
1250 };
1251
1252 module_platform_driver(mxcmci_driver);
1253
1254 MODULE_DESCRIPTION("i.MX Multimedia Card Interface Driver");
1255 MODULE_AUTHOR("Sascha Hauer, Pengutronix");
1256 MODULE_LICENSE("GPL");
1257 MODULE_ALIAS("platform:mxc-mmc");
Linux with added FPC-III support