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treewide: remove redundant IS_ERR() before error code check
[linux/fpc-iii.git] / drivers / mmc / host / owl-mmc.c
blob01ffe51f413df8556a1731ab02ec3a9ce1721007
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Actions Semi Owl SoCs SD/MMC driver
4 *
5 * Copyright (c) 2014 Actions Semi Inc.
6 * Copyright (c) 2019 Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
7 *
8 * TODO: SDIO support
9 */
10
11 #include <linux/clk.h>
12 #include <linux/delay.h>
13 #include <linux/dmaengine.h>
14 #include <linux/dma-direction.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/interrupt.h>
17 #include <linux/mmc/host.h>
18 #include <linux/mmc/slot-gpio.h>
19 #include <linux/module.h>
20 #include <linux/of_platform.h>
21 #include <linux/reset.h>
22 #include <linux/spinlock.h>
23
24 /*
25 * SDC registers
26 */
27 #define OWL_REG_SD_EN 0x0000
28 #define OWL_REG_SD_CTL 0x0004
29 #define OWL_REG_SD_STATE 0x0008
30 #define OWL_REG_SD_CMD 0x000c
31 #define OWL_REG_SD_ARG 0x0010
32 #define OWL_REG_SD_RSPBUF0 0x0014
33 #define OWL_REG_SD_RSPBUF1 0x0018
34 #define OWL_REG_SD_RSPBUF2 0x001c
35 #define OWL_REG_SD_RSPBUF3 0x0020
36 #define OWL_REG_SD_RSPBUF4 0x0024
37 #define OWL_REG_SD_DAT 0x0028
38 #define OWL_REG_SD_BLK_SIZE 0x002c
39 #define OWL_REG_SD_BLK_NUM 0x0030
40 #define OWL_REG_SD_BUF_SIZE 0x0034
41
42 /* SD_EN Bits */
43 #define OWL_SD_EN_RANE BIT(31)
44 #define OWL_SD_EN_RAN_SEED(x) (((x) & 0x3f) << 24)
45 #define OWL_SD_EN_S18EN BIT(12)
46 #define OWL_SD_EN_RESE BIT(10)
47 #define OWL_SD_EN_DAT1_S BIT(9)
48 #define OWL_SD_EN_CLK_S BIT(8)
49 #define OWL_SD_ENABLE BIT(7)
50 #define OWL_SD_EN_BSEL BIT(6)
51 #define OWL_SD_EN_SDIOEN BIT(3)
52 #define OWL_SD_EN_DDREN BIT(2)
53 #define OWL_SD_EN_DATAWID(x) (((x) & 0x3) << 0)
54
55 /* SD_CTL Bits */
56 #define OWL_SD_CTL_TOUTEN BIT(31)
57 #define OWL_SD_CTL_TOUTCNT(x) (((x) & 0x7f) << 24)
58 #define OWL_SD_CTL_DELAY_MSK GENMASK(23, 16)
59 #define OWL_SD_CTL_RDELAY(x) (((x) & 0xf) << 20)
60 #define OWL_SD_CTL_WDELAY(x) (((x) & 0xf) << 16)
61 #define OWL_SD_CTL_CMDLEN BIT(13)
62 #define OWL_SD_CTL_SCC BIT(12)
63 #define OWL_SD_CTL_TCN(x) (((x) & 0xf) << 8)
64 #define OWL_SD_CTL_TS BIT(7)
65 #define OWL_SD_CTL_LBE BIT(6)
66 #define OWL_SD_CTL_C7EN BIT(5)
67 #define OWL_SD_CTL_TM(x) (((x) & 0xf) << 0)
68
69 #define OWL_SD_DELAY_LOW_CLK 0x0f
70 #define OWL_SD_DELAY_MID_CLK 0x0a
71 #define OWL_SD_DELAY_HIGH_CLK 0x09
72 #define OWL_SD_RDELAY_DDR50 0x0a
73 #define OWL_SD_WDELAY_DDR50 0x08
74
75 /* SD_STATE Bits */
76 #define OWL_SD_STATE_DAT1BS BIT(18)
77 #define OWL_SD_STATE_SDIOB_P BIT(17)
78 #define OWL_SD_STATE_SDIOB_EN BIT(16)
79 #define OWL_SD_STATE_TOUTE BIT(15)
80 #define OWL_SD_STATE_BAEP BIT(14)
81 #define OWL_SD_STATE_MEMRDY BIT(12)
82 #define OWL_SD_STATE_CMDS BIT(11)
83 #define OWL_SD_STATE_DAT1AS BIT(10)
84 #define OWL_SD_STATE_SDIOA_P BIT(9)
85 #define OWL_SD_STATE_SDIOA_EN BIT(8)
86 #define OWL_SD_STATE_DAT0S BIT(7)
87 #define OWL_SD_STATE_TEIE BIT(6)
88 #define OWL_SD_STATE_TEI BIT(5)
89 #define OWL_SD_STATE_CLNR BIT(4)
90 #define OWL_SD_STATE_CLC BIT(3)
91 #define OWL_SD_STATE_WC16ER BIT(2)
92 #define OWL_SD_STATE_RC16ER BIT(1)
93 #define OWL_SD_STATE_CRC7ER BIT(0)
94
95 struct owl_mmc_host {
96 struct device *dev;
97 struct reset_control *reset;
98 void __iomem *base;
99 struct clk *clk;
100 struct completion sdc_complete;
101 spinlock_t lock;
102 int irq;
103 u32 clock;
104 bool ddr_50;
105
106 enum dma_data_direction dma_dir;
107 struct dma_chan *dma;
108 struct dma_async_tx_descriptor *desc;
109 struct dma_slave_config dma_cfg;
110 struct completion dma_complete;
111
112 struct mmc_host *mmc;
113 struct mmc_request *mrq;
114 struct mmc_command *cmd;
115 struct mmc_data *data;
116 };
117
118 static void owl_mmc_update_reg(void __iomem *reg, unsigned int val, bool state)
119 {
120 unsigned int regval;
121
122 regval = readl(reg);
123
124 if (state)
125 regval |= val;
126 else
127 regval &= ~val;
128
129 writel(regval, reg);
130 }
131
132 static irqreturn_t owl_irq_handler(int irq, void *devid)
133 {
134 struct owl_mmc_host *owl_host = devid;
135 unsigned long flags;
136 u32 state;
137
138 spin_lock_irqsave(&owl_host->lock, flags);
139
140 state = readl(owl_host->base + OWL_REG_SD_STATE);
141 if (state & OWL_SD_STATE_TEI) {
142 state = readl(owl_host->base + OWL_REG_SD_STATE);
143 state |= OWL_SD_STATE_TEI;
144 writel(state, owl_host->base + OWL_REG_SD_STATE);
145 complete(&owl_host->sdc_complete);
146 }
147
148 spin_unlock_irqrestore(&owl_host->lock, flags);
149
150 return IRQ_HANDLED;
151 }
152
153 static void owl_mmc_finish_request(struct owl_mmc_host *owl_host)
154 {
155 struct mmc_request *mrq = owl_host->mrq;
156 struct mmc_data *data = mrq->data;
157
158 /* Should never be NULL */
159 WARN_ON(!mrq);
160
161 owl_host->mrq = NULL;
162
163 if (data)
164 dma_unmap_sg(owl_host->dma->device->dev, data->sg, data->sg_len,
165 owl_host->dma_dir);
166
167 /* Finally finish request */
168 mmc_request_done(owl_host->mmc, mrq);
169 }
170
171 static void owl_mmc_send_cmd(struct owl_mmc_host *owl_host,
172 struct mmc_command *cmd,
173 struct mmc_data *data)
174 {
175 u32 mode, state, resp[2];
176 u32 cmd_rsp_mask = 0;
177
178 init_completion(&owl_host->sdc_complete);
179
180 switch (mmc_resp_type(cmd)) {
181 case MMC_RSP_NONE:
182 mode = OWL_SD_CTL_TM(0);
183 break;
184
185 case MMC_RSP_R1:
186 if (data) {
187 if (data->flags & MMC_DATA_READ)
188 mode = OWL_SD_CTL_TM(4);
189 else
190 mode = OWL_SD_CTL_TM(5);
191 } else {
192 mode = OWL_SD_CTL_TM(1);
193 }
194 cmd_rsp_mask = OWL_SD_STATE_CLNR | OWL_SD_STATE_CRC7ER;
195
196 break;
197
198 case MMC_RSP_R1B:
199 mode = OWL_SD_CTL_TM(3);
200 cmd_rsp_mask = OWL_SD_STATE_CLNR | OWL_SD_STATE_CRC7ER;
201 break;
202
203 case MMC_RSP_R2:
204 mode = OWL_SD_CTL_TM(2);
205 cmd_rsp_mask = OWL_SD_STATE_CLNR | OWL_SD_STATE_CRC7ER;
206 break;
207
208 case MMC_RSP_R3:
209 mode = OWL_SD_CTL_TM(1);
210 cmd_rsp_mask = OWL_SD_STATE_CLNR;
211 break;
212
213 default:
214 dev_warn(owl_host->dev, "Unknown MMC command\n");
215 cmd->error = -EINVAL;
216 return;
217 }
218
219 /* Keep current WDELAY and RDELAY */
220 mode |= (readl(owl_host->base + OWL_REG_SD_CTL) & (0xff << 16));
221
222 /* Start to send corresponding command type */
223 writel(cmd->arg, owl_host->base + OWL_REG_SD_ARG);
224 writel(cmd->opcode, owl_host->base + OWL_REG_SD_CMD);
225
226 /* Set LBE to send clk at the end of last read block */
227 if (data) {
228 mode |= (OWL_SD_CTL_TS | OWL_SD_CTL_LBE | 0x64000000);
229 } else {
230 mode &= ~(OWL_SD_CTL_TOUTEN | OWL_SD_CTL_LBE);
231 mode |= OWL_SD_CTL_TS;
232 }
233
234 owl_host->cmd = cmd;
235
236 /* Start transfer */
237 writel(mode, owl_host->base + OWL_REG_SD_CTL);
238
239 if (data)
240 return;
241
242 if (!wait_for_completion_timeout(&owl_host->sdc_complete, 30 * HZ)) {
243 dev_err(owl_host->dev, "CMD interrupt timeout\n");
244 cmd->error = -ETIMEDOUT;
245 return;
246 }
247
248 state = readl(owl_host->base + OWL_REG_SD_STATE);
249 if (mmc_resp_type(cmd) & MMC_RSP_PRESENT) {
250 if (cmd_rsp_mask & state) {
251 if (state & OWL_SD_STATE_CLNR) {
252 dev_err(owl_host->dev, "Error CMD_NO_RSP\n");
253 cmd->error = -EILSEQ;
254 return;
255 }
256
257 if (state & OWL_SD_STATE_CRC7ER) {
258 dev_err(owl_host->dev, "Error CMD_RSP_CRC\n");
259 cmd->error = -EILSEQ;
260 return;
261 }
262 }
263
264 if (mmc_resp_type(cmd) & MMC_RSP_136) {
265 cmd->resp[3] = readl(owl_host->base + OWL_REG_SD_RSPBUF0);
266 cmd->resp[2] = readl(owl_host->base + OWL_REG_SD_RSPBUF1);
267 cmd->resp[1] = readl(owl_host->base + OWL_REG_SD_RSPBUF2);
268 cmd->resp[0] = readl(owl_host->base + OWL_REG_SD_RSPBUF3);
269 } else {
270 resp[0] = readl(owl_host->base + OWL_REG_SD_RSPBUF0);
271 resp[1] = readl(owl_host->base + OWL_REG_SD_RSPBUF1);
272 cmd->resp[0] = resp[1] << 24 | resp[0] >> 8;
273 cmd->resp[1] = resp[1] >> 8;
274 }
275 }
276 }
277
278 static void owl_mmc_dma_complete(void *param)
279 {
280 struct owl_mmc_host *owl_host = param;
281 struct mmc_data *data = owl_host->data;
282
283 if (data)
284 complete(&owl_host->dma_complete);
285 }
286
287 static int owl_mmc_prepare_data(struct owl_mmc_host *owl_host,
288 struct mmc_data *data)
289 {
290 u32 total;
291
292 owl_mmc_update_reg(owl_host->base + OWL_REG_SD_EN, OWL_SD_EN_BSEL,
293 true);
294 writel(data->blocks, owl_host->base + OWL_REG_SD_BLK_NUM);
295 writel(data->blksz, owl_host->base + OWL_REG_SD_BLK_SIZE);
296 total = data->blksz * data->blocks;
297
298 if (total < 512)
299 writel(total, owl_host->base + OWL_REG_SD_BUF_SIZE);
300 else
301 writel(512, owl_host->base + OWL_REG_SD_BUF_SIZE);
302
303 if (data->flags & MMC_DATA_WRITE) {
304 owl_host->dma_dir = DMA_TO_DEVICE;
305 owl_host->dma_cfg.direction = DMA_MEM_TO_DEV;
306 } else {
307 owl_host->dma_dir = DMA_FROM_DEVICE;
308 owl_host->dma_cfg.direction = DMA_DEV_TO_MEM;
309 }
310
311 dma_map_sg(owl_host->dma->device->dev, data->sg,
312 data->sg_len, owl_host->dma_dir);
313
314 dmaengine_slave_config(owl_host->dma, &owl_host->dma_cfg);
315 owl_host->desc = dmaengine_prep_slave_sg(owl_host->dma, data->sg,
316 data->sg_len,
317 owl_host->dma_cfg.direction,
318 DMA_PREP_INTERRUPT |
319 DMA_CTRL_ACK);
320 if (!owl_host->desc) {
321 dev_err(owl_host->dev, "Can't prepare slave sg\n");
322 return -EBUSY;
323 }
324
325 owl_host->data = data;
326
327 owl_host->desc->callback = owl_mmc_dma_complete;
328 owl_host->desc->callback_param = (void *)owl_host;
329 data->error = 0;
330
331 return 0;
332 }
333
334 static void owl_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
335 {
336 struct owl_mmc_host *owl_host = mmc_priv(mmc);
337 struct mmc_data *data = mrq->data;
338 int ret;
339
340 owl_host->mrq = mrq;
341 if (mrq->data) {
342 ret = owl_mmc_prepare_data(owl_host, data);
343 if (ret < 0) {
344 data->error = ret;
345 goto err_out;
346 }
347
348 init_completion(&owl_host->dma_complete);
349 dmaengine_submit(owl_host->desc);
350 dma_async_issue_pending(owl_host->dma);
351 }
352
353 owl_mmc_send_cmd(owl_host, mrq->cmd, data);
354
355 if (data) {
356 if (!wait_for_completion_timeout(&owl_host->sdc_complete,
357 10 * HZ)) {
358 dev_err(owl_host->dev, "CMD interrupt timeout\n");
359 mrq->cmd->error = -ETIMEDOUT;
360 dmaengine_terminate_all(owl_host->dma);
361 goto err_out;
362 }
363
364 if (!wait_for_completion_timeout(&owl_host->dma_complete,
365 5 * HZ)) {
366 dev_err(owl_host->dev, "DMA interrupt timeout\n");
367 mrq->cmd->error = -ETIMEDOUT;
368 dmaengine_terminate_all(owl_host->dma);
369 goto err_out;
370 }
371
372 if (data->stop)
373 owl_mmc_send_cmd(owl_host, data->stop, NULL);
374
375 data->bytes_xfered = data->blocks * data->blksz;
376 }
377
378 err_out:
379 owl_mmc_finish_request(owl_host);
380 }
381
382 static int owl_mmc_set_clk_rate(struct owl_mmc_host *owl_host,
383 unsigned int rate)
384 {
385 unsigned long clk_rate;
386 int ret;
387 u32 reg;
388
389 reg = readl(owl_host->base + OWL_REG_SD_CTL);
390 reg &= ~OWL_SD_CTL_DELAY_MSK;
391
392 /* Set RDELAY and WDELAY based on the clock */
393 if (rate <= 1000000) {
394 writel(reg | OWL_SD_CTL_RDELAY(OWL_SD_DELAY_LOW_CLK) |
395 OWL_SD_CTL_WDELAY(OWL_SD_DELAY_LOW_CLK),
396 owl_host->base + OWL_REG_SD_CTL);
397 } else if ((rate > 1000000) && (rate <= 26000000)) {
398 writel(reg | OWL_SD_CTL_RDELAY(OWL_SD_DELAY_MID_CLK) |
399 OWL_SD_CTL_WDELAY(OWL_SD_DELAY_MID_CLK),
400 owl_host->base + OWL_REG_SD_CTL);
401 } else if ((rate > 26000000) && (rate <= 52000000) && !owl_host->ddr_50) {
402 writel(reg | OWL_SD_CTL_RDELAY(OWL_SD_DELAY_HIGH_CLK) |
403 OWL_SD_CTL_WDELAY(OWL_SD_DELAY_HIGH_CLK),
404 owl_host->base + OWL_REG_SD_CTL);
405 /* DDR50 mode has special delay chain */
406 } else if ((rate > 26000000) && (rate <= 52000000) && owl_host->ddr_50) {
407 writel(reg | OWL_SD_CTL_RDELAY(OWL_SD_RDELAY_DDR50) |
408 OWL_SD_CTL_WDELAY(OWL_SD_WDELAY_DDR50),
409 owl_host->base + OWL_REG_SD_CTL);
410 } else {
411 dev_err(owl_host->dev, "SD clock rate not supported\n");
412 return -EINVAL;
413 }
414
415 clk_rate = clk_round_rate(owl_host->clk, rate << 1);
416 ret = clk_set_rate(owl_host->clk, clk_rate);
417
418 return ret;
419 }
420
421 static void owl_mmc_set_clk(struct owl_mmc_host *owl_host, struct mmc_ios *ios)
422 {
423 if (!ios->clock)
424 return;
425
426 owl_host->clock = ios->clock;
427 owl_mmc_set_clk_rate(owl_host, ios->clock);
428 }
429
430 static void owl_mmc_set_bus_width(struct owl_mmc_host *owl_host,
431 struct mmc_ios *ios)
432 {
433 u32 reg;
434
435 reg = readl(owl_host->base + OWL_REG_SD_EN);
436 reg &= ~0x03;
437 switch (ios->bus_width) {
438 case MMC_BUS_WIDTH_1:
439 break;
440 case MMC_BUS_WIDTH_4:
441 reg |= OWL_SD_EN_DATAWID(1);
442 break;
443 case MMC_BUS_WIDTH_8:
444 reg |= OWL_SD_EN_DATAWID(2);
445 break;
446 }
447
448 writel(reg, owl_host->base + OWL_REG_SD_EN);
449 }
450
451 static void owl_mmc_ctr_reset(struct owl_mmc_host *owl_host)
452 {
453 reset_control_assert(owl_host->reset);
454 udelay(20);
455 reset_control_deassert(owl_host->reset);
456 }
457
458 static void owl_mmc_power_on(struct owl_mmc_host *owl_host)
459 {
460 u32 mode;
461
462 init_completion(&owl_host->sdc_complete);
463
464 /* Enable transfer end IRQ */
465 owl_mmc_update_reg(owl_host->base + OWL_REG_SD_STATE,
466 OWL_SD_STATE_TEIE, true);
467
468 /* Send init clk */
469 mode = (readl(owl_host->base + OWL_REG_SD_CTL) & (0xff << 16));
470 mode |= OWL_SD_CTL_TS | OWL_SD_CTL_TCN(5) | OWL_SD_CTL_TM(8);
471 writel(mode, owl_host->base + OWL_REG_SD_CTL);
472
473 if (!wait_for_completion_timeout(&owl_host->sdc_complete, HZ)) {
474 dev_err(owl_host->dev, "CMD interrupt timeout\n");
475 return;
476 }
477 }
478
479 static void owl_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
480 {
481 struct owl_mmc_host *owl_host = mmc_priv(mmc);
482
483 switch (ios->power_mode) {
484 case MMC_POWER_UP:
485 dev_dbg(owl_host->dev, "Powering card up\n");
486
487 /* Reset the SDC controller to clear all previous states */
488 owl_mmc_ctr_reset(owl_host);
489 clk_prepare_enable(owl_host->clk);
490 writel(OWL_SD_ENABLE | OWL_SD_EN_RESE,
491 owl_host->base + OWL_REG_SD_EN);
492
493 break;
494
495 case MMC_POWER_ON:
496 dev_dbg(owl_host->dev, "Powering card on\n");
497 owl_mmc_power_on(owl_host);
498
499 break;
500
501 case MMC_POWER_OFF:
502 dev_dbg(owl_host->dev, "Powering card off\n");
503 clk_disable_unprepare(owl_host->clk);
504
505 return;
506
507 default:
508 dev_dbg(owl_host->dev, "Ignoring unknown card power state\n");
509 break;
510 }
511
512 if (ios->clock != owl_host->clock)
513 owl_mmc_set_clk(owl_host, ios);
514
515 owl_mmc_set_bus_width(owl_host, ios);
516
517 /* Enable DDR mode if requested */
518 if (ios->timing == MMC_TIMING_UHS_DDR50) {
519 owl_host->ddr_50 = 1;
520 owl_mmc_update_reg(owl_host->base + OWL_REG_SD_EN,
521 OWL_SD_EN_DDREN, true);
522 } else {
523 owl_host->ddr_50 = 0;
524 }
525 }
526
527 static int owl_mmc_start_signal_voltage_switch(struct mmc_host *mmc,
528 struct mmc_ios *ios)
529 {
530 struct owl_mmc_host *owl_host = mmc_priv(mmc);
531
532 /* It is enough to change the pad ctrl bit for voltage switch */
533 switch (ios->signal_voltage) {
534 case MMC_SIGNAL_VOLTAGE_330:
535 owl_mmc_update_reg(owl_host->base + OWL_REG_SD_EN,
536 OWL_SD_EN_S18EN, false);
537 break;
538 case MMC_SIGNAL_VOLTAGE_180:
539 owl_mmc_update_reg(owl_host->base + OWL_REG_SD_EN,
540 OWL_SD_EN_S18EN, true);
541 break;
542 default:
543 return -ENOTSUPP;
544 }
545
546 return 0;
547 }
548
549 static const struct mmc_host_ops owl_mmc_ops = {
550 .request = owl_mmc_request,
551 .set_ios = owl_mmc_set_ios,
552 .get_ro = mmc_gpio_get_ro,
553 .get_cd = mmc_gpio_get_cd,
554 .start_signal_voltage_switch = owl_mmc_start_signal_voltage_switch,
555 };
556
557 static int owl_mmc_probe(struct platform_device *pdev)
558 {
559 struct owl_mmc_host *owl_host;
560 struct mmc_host *mmc;
561 struct resource *res;
562 int ret;
563
564 mmc = mmc_alloc_host(sizeof(struct owl_mmc_host), &pdev->dev);
565 if (!mmc) {
566 dev_err(&pdev->dev, "mmc alloc host failed\n");
567 return -ENOMEM;
568 }
569 platform_set_drvdata(pdev, mmc);
570
571 owl_host = mmc_priv(mmc);
572 owl_host->dev = &pdev->dev;
573 owl_host->mmc = mmc;
574 spin_lock_init(&owl_host->lock);
575
576 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
577 owl_host->base = devm_ioremap_resource(&pdev->dev, res);
578 if (IS_ERR(owl_host->base)) {
579 dev_err(&pdev->dev, "Failed to remap registers\n");
580 ret = PTR_ERR(owl_host->base);
581 goto err_free_host;
582 }
583
584 owl_host->clk = devm_clk_get(&pdev->dev, NULL);
585 if (IS_ERR(owl_host->clk)) {
586 dev_err(&pdev->dev, "No clock defined\n");
587 ret = PTR_ERR(owl_host->clk);
588 goto err_free_host;
589 }
590
591 owl_host->reset = devm_reset_control_get_exclusive(&pdev->dev, NULL);
592 if (IS_ERR(owl_host->reset)) {
593 dev_err(&pdev->dev, "Could not get reset control\n");
594 ret = PTR_ERR(owl_host->reset);
595 goto err_free_host;
596 }
597
598 mmc->ops = &owl_mmc_ops;
599 mmc->max_blk_count = 512;
600 mmc->max_blk_size = 512;
601 mmc->max_segs = 256;
602 mmc->max_seg_size = 262144;
603 mmc->max_req_size = 262144;
604 /* 100kHz ~ 52MHz */
605 mmc->f_min = 100000;
606 mmc->f_max = 52000000;
607 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
608 MMC_CAP_4_BIT_DATA;
609 mmc->caps2 = (MMC_CAP2_BOOTPART_NOACC | MMC_CAP2_NO_SDIO);
610 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34 |
611 MMC_VDD_165_195;
612
613 ret = mmc_of_parse(mmc);
614 if (ret)
615 goto err_free_host;
616
617 pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
618 pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask;
619 owl_host->dma = dma_request_chan(&pdev->dev, "mmc");
620 if (IS_ERR(owl_host->dma)) {
621 dev_err(owl_host->dev, "Failed to get external DMA channel.\n");
622 ret = PTR_ERR(owl_host->dma);
623 goto err_free_host;
624 }
625
626 dev_info(&pdev->dev, "Using %s for DMA transfers\n",
627 dma_chan_name(owl_host->dma));
628
629 owl_host->dma_cfg.src_addr = res->start + OWL_REG_SD_DAT;
630 owl_host->dma_cfg.dst_addr = res->start + OWL_REG_SD_DAT;
631 owl_host->dma_cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
632 owl_host->dma_cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
633 owl_host->dma_cfg.device_fc = false;
634
635 owl_host->irq = platform_get_irq(pdev, 0);
636 if (owl_host->irq < 0) {
637 ret = -EINVAL;
638 goto err_free_host;
639 }
640
641 ret = devm_request_irq(&pdev->dev, owl_host->irq, owl_irq_handler,
642 0, dev_name(&pdev->dev), owl_host);
643 if (ret) {
644 dev_err(&pdev->dev, "Failed to request irq %d\n",
645 owl_host->irq);
646 goto err_free_host;
647 }
648
649 ret = mmc_add_host(mmc);
650 if (ret) {
651 dev_err(&pdev->dev, "Failed to add host\n");
652 goto err_free_host;
653 }
654
655 dev_dbg(&pdev->dev, "Owl MMC Controller Initialized\n");
656
657 return 0;
658
659 err_free_host:
660 mmc_free_host(mmc);
661
662 return ret;
663 }
664
665 static int owl_mmc_remove(struct platform_device *pdev)
666 {
667 struct mmc_host *mmc = platform_get_drvdata(pdev);
668 struct owl_mmc_host *owl_host = mmc_priv(mmc);
669
670 mmc_remove_host(mmc);
671 disable_irq(owl_host->irq);
672 mmc_free_host(mmc);
673
674 return 0;
675 }
676
677 static const struct of_device_id owl_mmc_of_match[] = {
678 {.compatible = "actions,owl-mmc",},
679 { /* sentinel */ }
680 };
681 MODULE_DEVICE_TABLE(of, owl_mmc_of_match);
682
683 static struct platform_driver owl_mmc_driver = {
684 .driver = {
685 .name = "owl_mmc",
686 .of_match_table = of_match_ptr(owl_mmc_of_match),
687 },
688 .probe = owl_mmc_probe,
689 .remove = owl_mmc_remove,
690 };
691 module_platform_driver(owl_mmc_driver);
692
693 MODULE_DESCRIPTION("Actions Semi Owl SoCs SD/MMC Driver");
694 MODULE_AUTHOR("Actions Semi");
695 MODULE_AUTHOR("Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>");
696 MODULE_LICENSE("GPL");
Linux with added FPC-III support