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treewide: remove redundant IS_ERR() before error code check
[linux/fpc-iii.git] / drivers / mmc / host / renesas_sdhi_core.c
blob35cb24cd45b40b9b91b67403697eb181f3c59ae3
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Renesas SDHI
4 *
5 * Copyright (C) 2015-19 Renesas Electronics Corporation
6 * Copyright (C) 2016-19 Sang Engineering, Wolfram Sang
7 * Copyright (C) 2016-17 Horms Solutions, Simon Horman
8 * Copyright (C) 2009 Magnus Damm
9 *
10 * Based on "Compaq ASIC3 support":
11 *
12 * Copyright 2001 Compaq Computer Corporation.
13 * Copyright 2004-2005 Phil Blundell
14 * Copyright 2007-2008 OpenedHand Ltd.
15 *
16 * Authors: Phil Blundell <pb@handhelds.org>,
17 * Samuel Ortiz <sameo@openedhand.com>
18 *
19 */
20
21 #include <linux/kernel.h>
22 #include <linux/clk.h>
23 #include <linux/slab.h>
24 #include <linux/module.h>
25 #include <linux/of_device.h>
26 #include <linux/platform_device.h>
27 #include <linux/mmc/host.h>
28 #include <linux/mmc/slot-gpio.h>
29 #include <linux/mfd/tmio.h>
30 #include <linux/sh_dma.h>
31 #include <linux/delay.h>
32 #include <linux/pinctrl/consumer.h>
33 #include <linux/pinctrl/pinctrl-state.h>
34 #include <linux/regulator/consumer.h>
35 #include <linux/sys_soc.h>
36
37 #include "renesas_sdhi.h"
38 #include "tmio_mmc.h"
39
40 #define HOST_MODE 0xe4
41
42 #define SDHI_VER_GEN2_SDR50 0x490c
43 #define SDHI_VER_RZ_A1 0x820b
44 /* very old datasheets said 0x490c for SDR104, too. They are wrong! */
45 #define SDHI_VER_GEN2_SDR104 0xcb0d
46 #define SDHI_VER_GEN3_SD 0xcc10
47 #define SDHI_VER_GEN3_SDMMC 0xcd10
48
49 static void renesas_sdhi_sdbuf_width(struct tmio_mmc_host *host, int width)
50 {
51 u32 val;
52
53 /*
54 * see also
55 * renesas_sdhi_of_data :: dma_buswidth
56 */
57 switch (sd_ctrl_read16(host, CTL_VERSION)) {
58 case SDHI_VER_GEN2_SDR50:
59 val = (width == 32) ? 0x0001 : 0x0000;
60 break;
61 case SDHI_VER_GEN2_SDR104:
62 val = (width == 32) ? 0x0000 : 0x0001;
63 break;
64 case SDHI_VER_GEN3_SD:
65 case SDHI_VER_GEN3_SDMMC:
66 if (width == 64)
67 val = 0x0000;
68 else if (width == 32)
69 val = 0x0101;
70 else
71 val = 0x0001;
72 break;
73 default:
74 /* nothing to do */
75 return;
76 }
77
78 sd_ctrl_write16(host, HOST_MODE, val);
79 }
80
81 static int renesas_sdhi_clk_enable(struct tmio_mmc_host *host)
82 {
83 struct mmc_host *mmc = host->mmc;
84 struct renesas_sdhi *priv = host_to_priv(host);
85 int ret = clk_prepare_enable(priv->clk);
86
87 if (ret < 0)
88 return ret;
89
90 ret = clk_prepare_enable(priv->clk_cd);
91 if (ret < 0) {
92 clk_disable_unprepare(priv->clk);
93 return ret;
94 }
95
96 /*
97 * The clock driver may not know what maximum frequency
98 * actually works, so it should be set with the max-frequency
99 * property which will already have been read to f_max. If it
100 * was missing, assume the current frequency is the maximum.
101 */
102 if (!mmc->f_max)
103 mmc->f_max = clk_get_rate(priv->clk);
104
105 /*
106 * Minimum frequency is the minimum input clock frequency
107 * divided by our maximum divider.
108 */
109 mmc->f_min = max(clk_round_rate(priv->clk, 1) / 512, 1L);
110
111 /* enable 16bit data access on SDBUF as default */
112 renesas_sdhi_sdbuf_width(host, 16);
113
114 return 0;
115 }
116
117 static unsigned int renesas_sdhi_clk_update(struct tmio_mmc_host *host,
118 unsigned int new_clock)
119 {
120 struct renesas_sdhi *priv = host_to_priv(host);
121 unsigned int freq, diff, best_freq = 0, diff_min = ~0;
122 int i;
123
124 /* tested only on R-Car Gen2+ currently; may work for others */
125 if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2))
126 return clk_get_rate(priv->clk);
127
128 /*
129 * We want the bus clock to be as close as possible to, but no
130 * greater than, new_clock. As we can divide by 1 << i for
131 * any i in [0, 9] we want the input clock to be as close as
132 * possible, but no greater than, new_clock << i.
133 */
134 for (i = min(9, ilog2(UINT_MAX / new_clock)); i >= 0; i--) {
135 freq = clk_round_rate(priv->clk, new_clock << i);
136 if (freq > (new_clock << i)) {
137 /* Too fast; look for a slightly slower option */
138 freq = clk_round_rate(priv->clk,
139 (new_clock << i) / 4 * 3);
140 if (freq > (new_clock << i))
141 continue;
142 }
143
144 diff = new_clock - (freq >> i);
145 if (diff <= diff_min) {
146 best_freq = freq;
147 diff_min = diff;
148 }
149 }
150
151 clk_set_rate(priv->clk, best_freq);
152
153 return clk_get_rate(priv->clk);
154 }
155
156 static void renesas_sdhi_set_clock(struct tmio_mmc_host *host,
157 unsigned int new_clock)
158 {
159 u32 clk = 0, clock;
160
161 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
162 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
163
164 if (new_clock == 0) {
165 host->mmc->actual_clock = 0;
166 goto out;
167 }
168
169 host->mmc->actual_clock = renesas_sdhi_clk_update(host, new_clock);
170 clock = host->mmc->actual_clock / 512;
171
172 for (clk = 0x80000080; new_clock >= (clock << 1); clk >>= 1)
173 clock <<= 1;
174
175 /* 1/1 clock is option */
176 if ((host->pdata->flags & TMIO_MMC_CLK_ACTUAL) && ((clk >> 22) & 0x1)) {
177 if (!(host->mmc->ios.timing == MMC_TIMING_MMC_HS400))
178 clk |= 0xff;
179 else
180 clk &= ~0xff;
181 }
182
183 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, clk & CLK_CTL_DIV_MASK);
184 if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2))
185 usleep_range(10000, 11000);
186
187 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
188 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
189
190 out:
191 /* HW engineers overrode docs: no sleep needed on R-Car2+ */
192 if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2))
193 usleep_range(10000, 11000);
194 }
195
196 static void renesas_sdhi_clk_disable(struct tmio_mmc_host *host)
197 {
198 struct renesas_sdhi *priv = host_to_priv(host);
199
200 clk_disable_unprepare(priv->clk);
201 clk_disable_unprepare(priv->clk_cd);
202 }
203
204 static int renesas_sdhi_card_busy(struct mmc_host *mmc)
205 {
206 struct tmio_mmc_host *host = mmc_priv(mmc);
207
208 return !(sd_ctrl_read16_and_16_as_32(host, CTL_STATUS) &
209 TMIO_STAT_DAT0);
210 }
211
212 static int renesas_sdhi_start_signal_voltage_switch(struct mmc_host *mmc,
213 struct mmc_ios *ios)
214 {
215 struct tmio_mmc_host *host = mmc_priv(mmc);
216 struct renesas_sdhi *priv = host_to_priv(host);
217 struct pinctrl_state *pin_state;
218 int ret;
219
220 switch (ios->signal_voltage) {
221 case MMC_SIGNAL_VOLTAGE_330:
222 pin_state = priv->pins_default;
223 break;
224 case MMC_SIGNAL_VOLTAGE_180:
225 pin_state = priv->pins_uhs;
226 break;
227 default:
228 return -EINVAL;
229 }
230
231 /*
232 * If anything is missing, assume signal voltage is fixed at
233 * 3.3V and succeed/fail accordingly.
234 */
235 if (IS_ERR(priv->pinctrl) || IS_ERR(pin_state))
236 return ios->signal_voltage ==
237 MMC_SIGNAL_VOLTAGE_330 ? 0 : -EINVAL;
238
239 ret = mmc_regulator_set_vqmmc(host->mmc, ios);
240 if (ret)
241 return ret;
242
243 return pinctrl_select_state(priv->pinctrl, pin_state);
244 }
245
246 /* SCC registers */
247 #define SH_MOBILE_SDHI_SCC_DTCNTL 0x000
248 #define SH_MOBILE_SDHI_SCC_TAPSET 0x002
249 #define SH_MOBILE_SDHI_SCC_DT2FF 0x004
250 #define SH_MOBILE_SDHI_SCC_CKSEL 0x006
251 #define SH_MOBILE_SDHI_SCC_RVSCNTL 0x008
252 #define SH_MOBILE_SDHI_SCC_RVSREQ 0x00A
253 #define SH_MOBILE_SDHI_SCC_TMPPORT2 0x00E
254
255 /* Definitions for values the SH_MOBILE_SDHI_SCC_DTCNTL register */
256 #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN BIT(0)
257 #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT 16
258 #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_MASK 0xff
259
260 /* Definitions for values the SH_MOBILE_SDHI_SCC_CKSEL register */
261 #define SH_MOBILE_SDHI_SCC_CKSEL_DTSEL BIT(0)
262 /* Definitions for values the SH_MOBILE_SDHI_SCC_RVSCNTL register */
263 #define SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN BIT(0)
264 /* Definitions for values the SH_MOBILE_SDHI_SCC_RVSREQ register */
265 #define SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR BIT(2)
266 /* Definitions for values the SH_MOBILE_SDHI_SCC_TMPPORT2 register */
267 #define SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL BIT(4)
268 #define SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN BIT(31)
269
270 static inline u32 sd_scc_read32(struct tmio_mmc_host *host,
271 struct renesas_sdhi *priv, int addr)
272 {
273 return readl(priv->scc_ctl + (addr << host->bus_shift));
274 }
275
276 static inline void sd_scc_write32(struct tmio_mmc_host *host,
277 struct renesas_sdhi *priv,
278 int addr, u32 val)
279 {
280 writel(val, priv->scc_ctl + (addr << host->bus_shift));
281 }
282
283 static unsigned int renesas_sdhi_init_tuning(struct tmio_mmc_host *host)
284 {
285 struct renesas_sdhi *priv;
286
287 priv = host_to_priv(host);
288
289 /* Initialize SCC */
290 sd_ctrl_write32_as_16_and_16(host, CTL_STATUS, 0x0);
291
292 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
293 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
294
295 /* set sampling clock selection range */
296 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL,
297 SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN |
298 0x8 << SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT);
299
300 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL,
301 SH_MOBILE_SDHI_SCC_CKSEL_DTSEL |
302 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL));
303
304 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL,
305 ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN &
306 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL));
307
308 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF, priv->scc_tappos);
309
310 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
311 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
312
313 /* Read TAPNUM */
314 return (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL) >>
315 SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) &
316 SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_MASK;
317 }
318
319 static void renesas_sdhi_prepare_tuning(struct tmio_mmc_host *host,
320 unsigned long tap)
321 {
322 struct renesas_sdhi *priv = host_to_priv(host);
323
324 /* Set sampling clock position */
325 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, tap);
326 }
327
328 static void renesas_sdhi_hs400_complete(struct tmio_mmc_host *host)
329 {
330 struct renesas_sdhi *priv = host_to_priv(host);
331
332 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
333 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
334
335 /* Set HS400 mode */
336 sd_ctrl_write16(host, CTL_SDIF_MODE, 0x0001 |
337 sd_ctrl_read16(host, CTL_SDIF_MODE));
338
339 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF,
340 priv->scc_tappos_hs400);
341
342 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2,
343 (SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN |
344 SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL) |
345 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2));
346
347 /* Set the sampling clock selection range of HS400 mode */
348 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL,
349 SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN |
350 0x4 << SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT);
351
352
353 if (priv->quirks && priv->quirks->hs400_4taps)
354 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET,
355 host->tap_set / 2);
356
357 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL,
358 SH_MOBILE_SDHI_SCC_CKSEL_DTSEL |
359 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL));
360
361 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
362 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
363 }
364
365 static void renesas_sdhi_reset_scc(struct tmio_mmc_host *host,
366 struct renesas_sdhi *priv)
367 {
368 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
369 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
370
371 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL,
372 ~SH_MOBILE_SDHI_SCC_CKSEL_DTSEL &
373 sd_scc_read32(host, priv,
374 SH_MOBILE_SDHI_SCC_CKSEL));
375 }
376
377 static void renesas_sdhi_disable_scc(struct tmio_mmc_host *host)
378 {
379 struct renesas_sdhi *priv = host_to_priv(host);
380
381 renesas_sdhi_reset_scc(host, priv);
382
383 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL,
384 ~SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN &
385 sd_scc_read32(host, priv,
386 SH_MOBILE_SDHI_SCC_DTCNTL));
387
388 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
389 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
390 }
391
392 static void renesas_sdhi_reset_hs400_mode(struct tmio_mmc_host *host,
393 struct renesas_sdhi *priv)
394 {
395 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
396 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
397
398 /* Reset HS400 mode */
399 sd_ctrl_write16(host, CTL_SDIF_MODE, ~0x0001 &
400 sd_ctrl_read16(host, CTL_SDIF_MODE));
401
402 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF, priv->scc_tappos);
403
404 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2,
405 ~(SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN |
406 SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL) &
407 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2));
408
409 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
410 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
411 }
412
413 static void renesas_sdhi_prepare_hs400_tuning(struct tmio_mmc_host *host)
414 {
415 renesas_sdhi_reset_hs400_mode(host, host_to_priv(host));
416 }
417
418 #define SH_MOBILE_SDHI_MAX_TAP 3
419
420 static int renesas_sdhi_select_tuning(struct tmio_mmc_host *host)
421 {
422 struct renesas_sdhi *priv = host_to_priv(host);
423 unsigned long tap_cnt; /* counter of tuning success */
424 unsigned long tap_start;/* start position of tuning success */
425 unsigned long tap_end; /* end position of tuning success */
426 unsigned long ntap; /* temporary counter of tuning success */
427 unsigned long i;
428
429 /* Clear SCC_RVSREQ */
430 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0);
431
432 /*
433 * When tuning CMD19 is issued twice for each tap, merge the
434 * result requiring the tap to be good in both runs before
435 * considering it for tuning selection.
436 */
437 for (i = 0; i < host->tap_num * 2; i++) {
438 int offset = host->tap_num * (i < host->tap_num ? 1 : -1);
439
440 if (!test_bit(i, host->taps))
441 clear_bit(i + offset, host->taps);
442 }
443
444 /*
445 * Find the longest consecutive run of successful probes. If that
446 * is more than SH_MOBILE_SDHI_MAX_TAP probes long then use the
447 * center index as the tap.
448 */
449 tap_cnt = 0;
450 ntap = 0;
451 tap_start = 0;
452 tap_end = 0;
453 for (i = 0; i < host->tap_num * 2; i++) {
454 if (test_bit(i, host->taps)) {
455 ntap++;
456 } else {
457 if (ntap > tap_cnt) {
458 tap_start = i - ntap;
459 tap_end = i - 1;
460 tap_cnt = ntap;
461 }
462 ntap = 0;
463 }
464 }
465
466 if (ntap > tap_cnt) {
467 tap_start = i - ntap;
468 tap_end = i - 1;
469 tap_cnt = ntap;
470 }
471
472 if (tap_cnt >= SH_MOBILE_SDHI_MAX_TAP)
473 host->tap_set = (tap_start + tap_end) / 2 % host->tap_num;
474 else
475 return -EIO;
476
477 /* Set SCC */
478 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, host->tap_set);
479
480 /* Enable auto re-tuning */
481 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL,
482 SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN |
483 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL));
484
485 return 0;
486 }
487
488 static bool renesas_sdhi_check_scc_error(struct tmio_mmc_host *host)
489 {
490 struct renesas_sdhi *priv = host_to_priv(host);
491 bool use_4tap = priv->quirks && priv->quirks->hs400_4taps;
492
493 /*
494 * Skip checking SCC errors when running on 4 taps in HS400 mode as
495 * any retuning would still result in the same 4 taps being used.
496 */
497 if (!(host->mmc->ios.timing == MMC_TIMING_UHS_SDR104) &&
498 !(host->mmc->ios.timing == MMC_TIMING_MMC_HS200) &&
499 !(host->mmc->ios.timing == MMC_TIMING_MMC_HS400 && !use_4tap))
500 return false;
501
502 if (mmc_doing_retune(host->mmc))
503 return false;
504
505 /* Check SCC error */
506 if (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL) &
507 SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN &&
508 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ) &
509 SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR) {
510 /* Clear SCC error */
511 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0);
512 return true;
513 }
514
515 return false;
516 }
517
518 static void renesas_sdhi_hw_reset(struct tmio_mmc_host *host)
519 {
520 struct renesas_sdhi *priv;
521
522 priv = host_to_priv(host);
523
524 renesas_sdhi_reset_scc(host, priv);
525 renesas_sdhi_reset_hs400_mode(host, priv);
526
527 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
528 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
529
530 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL,
531 ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN &
532 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL));
533
534 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL,
535 ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN &
536 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL));
537
538 if (host->pdata->flags & TMIO_MMC_MIN_RCAR2)
539 sd_ctrl_write32_as_16_and_16(host, CTL_IRQ_MASK,
540 TMIO_MASK_INIT_RCAR2);
541 }
542
543 static int renesas_sdhi_wait_idle(struct tmio_mmc_host *host, u32 bit)
544 {
545 int timeout = 1000;
546 /* CBSY is set when busy, SCLKDIVEN is cleared when busy */
547 u32 wait_state = (bit == TMIO_STAT_CMD_BUSY ? TMIO_STAT_CMD_BUSY : 0);
548
549 while (--timeout && (sd_ctrl_read16_and_16_as_32(host, CTL_STATUS)
550 & bit) == wait_state)
551 udelay(1);
552
553 if (!timeout) {
554 dev_warn(&host->pdev->dev, "timeout waiting for SD bus idle\n");
555 return -EBUSY;
556 }
557
558 return 0;
559 }
560
561 static int renesas_sdhi_write16_hook(struct tmio_mmc_host *host, int addr)
562 {
563 u32 bit = TMIO_STAT_SCLKDIVEN;
564
565 switch (addr) {
566 case CTL_SD_CMD:
567 case CTL_STOP_INTERNAL_ACTION:
568 case CTL_XFER_BLK_COUNT:
569 case CTL_SD_XFER_LEN:
570 case CTL_SD_MEM_CARD_OPT:
571 case CTL_TRANSACTION_CTL:
572 case CTL_DMA_ENABLE:
573 case HOST_MODE:
574 if (host->pdata->flags & TMIO_MMC_HAVE_CBSY)
575 bit = TMIO_STAT_CMD_BUSY;
576 /* fallthrough */
577 case CTL_SD_CARD_CLK_CTL:
578 return renesas_sdhi_wait_idle(host, bit);
579 }
580
581 return 0;
582 }
583
584 static int renesas_sdhi_multi_io_quirk(struct mmc_card *card,
585 unsigned int direction, int blk_size)
586 {
587 /*
588 * In Renesas controllers, when performing a
589 * multiple block read of one or two blocks,
590 * depending on the timing with which the
591 * response register is read, the response
592 * value may not be read properly.
593 * Use single block read for this HW bug
594 */
595 if ((direction == MMC_DATA_READ) &&
596 blk_size == 2)
597 return 1;
598
599 return blk_size;
600 }
601
602 static void renesas_sdhi_enable_dma(struct tmio_mmc_host *host, bool enable)
603 {
604 /* Iff regs are 8 byte apart, sdbuf is 64 bit. Otherwise always 32. */
605 int width = (host->bus_shift == 2) ? 64 : 32;
606
607 sd_ctrl_write16(host, CTL_DMA_ENABLE, enable ? DMA_ENABLE_DMASDRW : 0);
608 renesas_sdhi_sdbuf_width(host, enable ? width : 16);
609 }
610
611 static const struct renesas_sdhi_quirks sdhi_quirks_4tap_nohs400 = {
612 .hs400_disabled = true,
613 .hs400_4taps = true,
614 };
615
616 static const struct renesas_sdhi_quirks sdhi_quirks_4tap = {
617 .hs400_4taps = true,
618 };
619
620 static const struct renesas_sdhi_quirks sdhi_quirks_nohs400 = {
621 .hs400_disabled = true,
622 };
623
624 static const struct soc_device_attribute sdhi_quirks_match[] = {
625 { .soc_id = "r8a774a1", .revision = "ES1.[012]", .data = &sdhi_quirks_4tap_nohs400 },
626 { .soc_id = "r8a7795", .revision = "ES1.*", .data = &sdhi_quirks_4tap_nohs400 },
627 { .soc_id = "r8a7795", .revision = "ES2.0", .data = &sdhi_quirks_4tap },
628 { .soc_id = "r8a7796", .revision = "ES1.[012]", .data = &sdhi_quirks_4tap_nohs400 },
629 { .soc_id = "r8a77980", .data = &sdhi_quirks_nohs400 },
630 { /* Sentinel. */ },
631 };
632
633 int renesas_sdhi_probe(struct platform_device *pdev,
634 const struct tmio_mmc_dma_ops *dma_ops)
635 {
636 struct tmio_mmc_data *mmd = pdev->dev.platform_data;
637 const struct renesas_sdhi_quirks *quirks = NULL;
638 const struct renesas_sdhi_of_data *of_data;
639 const struct soc_device_attribute *attr;
640 struct tmio_mmc_data *mmc_data;
641 struct tmio_mmc_dma *dma_priv;
642 struct tmio_mmc_host *host;
643 struct renesas_sdhi *priv;
644 int num_irqs, irq, ret, i;
645 struct resource *res;
646 u16 ver;
647
648 of_data = of_device_get_match_data(&pdev->dev);
649
650 attr = soc_device_match(sdhi_quirks_match);
651 if (attr)
652 quirks = attr->data;
653
654 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
655 if (!res)
656 return -EINVAL;
657
658 priv = devm_kzalloc(&pdev->dev, sizeof(struct renesas_sdhi),
659 GFP_KERNEL);
660 if (!priv)
661 return -ENOMEM;
662
663 priv->quirks = quirks;
664 mmc_data = &priv->mmc_data;
665 dma_priv = &priv->dma_priv;
666
667 priv->clk = devm_clk_get(&pdev->dev, NULL);
668 if (IS_ERR(priv->clk)) {
669 ret = PTR_ERR(priv->clk);
670 dev_err(&pdev->dev, "cannot get clock: %d\n", ret);
671 return ret;
672 }
673
674 /*
675 * Some controllers provide a 2nd clock just to run the internal card
676 * detection logic. Unfortunately, the existing driver architecture does
677 * not support a separation of clocks for runtime PM usage. When
678 * native hotplug is used, the tmio driver assumes that the core
679 * must continue to run for card detect to stay active, so we cannot
680 * disable it.
681 * Additionally, it is prohibited to supply a clock to the core but not
682 * to the card detect circuit. That leaves us with if separate clocks
683 * are presented, we must treat them both as virtually 1 clock.
684 */
685 priv->clk_cd = devm_clk_get(&pdev->dev, "cd");
686 if (IS_ERR(priv->clk_cd))
687 priv->clk_cd = NULL;
688
689 priv->pinctrl = devm_pinctrl_get(&pdev->dev);
690 if (!IS_ERR(priv->pinctrl)) {
691 priv->pins_default = pinctrl_lookup_state(priv->pinctrl,
692 PINCTRL_STATE_DEFAULT);
693 priv->pins_uhs = pinctrl_lookup_state(priv->pinctrl,
694 "state_uhs");
695 }
696
697 host = tmio_mmc_host_alloc(pdev, mmc_data);
698 if (IS_ERR(host))
699 return PTR_ERR(host);
700
701 if (of_data) {
702 mmc_data->flags |= of_data->tmio_flags;
703 mmc_data->ocr_mask = of_data->tmio_ocr_mask;
704 mmc_data->capabilities |= of_data->capabilities;
705 mmc_data->capabilities2 |= of_data->capabilities2;
706 mmc_data->dma_rx_offset = of_data->dma_rx_offset;
707 mmc_data->max_blk_count = of_data->max_blk_count;
708 mmc_data->max_segs = of_data->max_segs;
709 dma_priv->dma_buswidth = of_data->dma_buswidth;
710 host->bus_shift = of_data->bus_shift;
711 }
712
713 host->write16_hook = renesas_sdhi_write16_hook;
714 host->clk_enable = renesas_sdhi_clk_enable;
715 host->clk_disable = renesas_sdhi_clk_disable;
716 host->set_clock = renesas_sdhi_set_clock;
717 host->multi_io_quirk = renesas_sdhi_multi_io_quirk;
718 host->dma_ops = dma_ops;
719
720 if (quirks && quirks->hs400_disabled)
721 host->mmc->caps2 &= ~(MMC_CAP2_HS400 | MMC_CAP2_HS400_ES);
722
723 /* For some SoC, we disable internal WP. GPIO may override this */
724 if (mmc_can_gpio_ro(host->mmc))
725 mmc_data->capabilities2 &= ~MMC_CAP2_NO_WRITE_PROTECT;
726
727 /* SDR speeds are only available on Gen2+ */
728 if (mmc_data->flags & TMIO_MMC_MIN_RCAR2) {
729 /* card_busy caused issues on r8a73a4 (pre-Gen2) CD-less SDHI */
730 host->ops.card_busy = renesas_sdhi_card_busy;
731 host->ops.start_signal_voltage_switch =
732 renesas_sdhi_start_signal_voltage_switch;
733 host->sdcard_irq_setbit_mask = TMIO_STAT_ALWAYS_SET_27;
734
735 /* SDR and HS200/400 registers requires HW reset */
736 if (of_data && of_data->scc_offset) {
737 priv->scc_ctl = host->ctl + of_data->scc_offset;
738 host->mmc->caps |= MMC_CAP_HW_RESET;
739 host->hw_reset = renesas_sdhi_hw_reset;
740 }
741 }
742
743 /* Orginally registers were 16 bit apart, could be 32 or 64 nowadays */
744 if (!host->bus_shift && resource_size(res) > 0x100) /* old way to determine the shift */
745 host->bus_shift = 1;
746
747 if (mmd)
748 *mmc_data = *mmd;
749
750 dma_priv->filter = shdma_chan_filter;
751 dma_priv->enable = renesas_sdhi_enable_dma;
752
753 mmc_data->alignment_shift = 1; /* 2-byte alignment */
754 mmc_data->capabilities |= MMC_CAP_MMC_HIGHSPEED;
755
756 /*
757 * All SDHI blocks support 2-byte and larger block sizes in 4-bit
758 * bus width mode.
759 */
760 mmc_data->flags |= TMIO_MMC_BLKSZ_2BYTES;
761
762 /*
763 * All SDHI blocks support SDIO IRQ signalling.
764 */
765 mmc_data->flags |= TMIO_MMC_SDIO_IRQ;
766
767 /* All SDHI have CMD12 control bit */
768 mmc_data->flags |= TMIO_MMC_HAVE_CMD12_CTRL;
769
770 /* All SDHI have SDIO status bits which must be 1 */
771 mmc_data->flags |= TMIO_MMC_SDIO_STATUS_SETBITS;
772
773 ret = renesas_sdhi_clk_enable(host);
774 if (ret)
775 goto efree;
776
777 ver = sd_ctrl_read16(host, CTL_VERSION);
778 /* GEN2_SDR104 is first known SDHI to use 32bit block count */
779 if (ver < SDHI_VER_GEN2_SDR104 && mmc_data->max_blk_count > U16_MAX)
780 mmc_data->max_blk_count = U16_MAX;
781
782 /* One Gen2 SDHI incarnation does NOT have a CBSY bit */
783 if (ver == SDHI_VER_GEN2_SDR50)
784 mmc_data->flags &= ~TMIO_MMC_HAVE_CBSY;
785
786 ret = tmio_mmc_host_probe(host);
787 if (ret < 0)
788 goto edisclk;
789
790 /* Enable tuning iff we have an SCC and a supported mode */
791 if (of_data && of_data->scc_offset &&
792 (host->mmc->caps & MMC_CAP_UHS_SDR104 ||
793 host->mmc->caps2 & (MMC_CAP2_HS200_1_8V_SDR |
794 MMC_CAP2_HS400_1_8V))) {
795 const struct renesas_sdhi_scc *taps = of_data->taps;
796 bool use_4tap = priv->quirks && priv->quirks->hs400_4taps;
797 bool hit = false;
798
799 for (i = 0; i < of_data->taps_num; i++) {
800 if (taps[i].clk_rate == 0 ||
801 taps[i].clk_rate == host->mmc->f_max) {
802 priv->scc_tappos = taps->tap;
803 priv->scc_tappos_hs400 = use_4tap ?
804 taps->tap_hs400_4tap :
805 taps->tap;
806 hit = true;
807 break;
808 }
809 }
810
811 if (!hit)
812 dev_warn(&host->pdev->dev, "Unknown clock rate for tuning\n");
813
814 host->init_tuning = renesas_sdhi_init_tuning;
815 host->prepare_tuning = renesas_sdhi_prepare_tuning;
816 host->select_tuning = renesas_sdhi_select_tuning;
817 host->check_scc_error = renesas_sdhi_check_scc_error;
818 host->prepare_hs400_tuning =
819 renesas_sdhi_prepare_hs400_tuning;
820 host->hs400_downgrade = renesas_sdhi_disable_scc;
821 host->hs400_complete = renesas_sdhi_hs400_complete;
822 }
823
824 num_irqs = platform_irq_count(pdev);
825 if (num_irqs < 0) {
826 ret = num_irqs;
827 goto eirq;
828 }
829
830 /* There must be at least one IRQ source */
831 if (!num_irqs) {
832 ret = -ENXIO;
833 goto eirq;
834 }
835
836 for (i = 0; i < num_irqs; i++) {
837 irq = platform_get_irq(pdev, i);
838 if (irq < 0) {
839 ret = irq;
840 goto eirq;
841 }
842
843 ret = devm_request_irq(&pdev->dev, irq, tmio_mmc_irq, 0,
844 dev_name(&pdev->dev), host);
845 if (ret)
846 goto eirq;
847 }
848
849 dev_info(&pdev->dev, "%s base at 0x%08lx max clock rate %u MHz\n",
850 mmc_hostname(host->mmc), (unsigned long)
851 (platform_get_resource(pdev, IORESOURCE_MEM, 0)->start),
852 host->mmc->f_max / 1000000);
853
854 return ret;
855
856 eirq:
857 tmio_mmc_host_remove(host);
858 edisclk:
859 renesas_sdhi_clk_disable(host);
860 efree:
861 tmio_mmc_host_free(host);
862
863 return ret;
864 }
865 EXPORT_SYMBOL_GPL(renesas_sdhi_probe);
866
867 int renesas_sdhi_remove(struct platform_device *pdev)
868 {
869 struct tmio_mmc_host *host = platform_get_drvdata(pdev);
870
871 tmio_mmc_host_remove(host);
872 renesas_sdhi_clk_disable(host);
873
874 return 0;
875 }
876 EXPORT_SYMBOL_GPL(renesas_sdhi_remove);
877
878 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support