treewide: remove redundant IS_ERR() before error code check
[linux/fpc-iii.git] / drivers / mmc / host / renesas_sdhi_internal_dmac.c
blob47ac53e912411ee08fe1e56bdde58138c177c3b0
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * DMA support for Internal DMAC with SDHI SD/SDIO controller
5 * Copyright (C) 2016-19 Renesas Electronics Corporation
6 * Copyright (C) 2016-17 Horms Solutions, Simon Horman
7 * Copyright (C) 2018-19 Sang Engineering, Wolfram Sang
8 */
10 #include <linux/bitops.h>
11 #include <linux/device.h>
12 #include <linux/dma-mapping.h>
13 #include <linux/io-64-nonatomic-hi-lo.h>
14 #include <linux/mfd/tmio.h>
15 #include <linux/mmc/host.h>
16 #include <linux/mod_devicetable.h>
17 #include <linux/module.h>
18 #include <linux/pagemap.h>
19 #include <linux/scatterlist.h>
20 #include <linux/sys_soc.h>
22 #include "renesas_sdhi.h"
23 #include "tmio_mmc.h"
25 #define DM_CM_DTRAN_MODE 0x820
26 #define DM_CM_DTRAN_CTRL 0x828
27 #define DM_CM_RST 0x830
28 #define DM_CM_INFO1 0x840
29 #define DM_CM_INFO1_MASK 0x848
30 #define DM_CM_INFO2 0x850
31 #define DM_CM_INFO2_MASK 0x858
32 #define DM_DTRAN_ADDR 0x880
34 /* DM_CM_DTRAN_MODE */
35 #define DTRAN_MODE_CH_NUM_CH0 0 /* "downstream" = for write commands */
36 #define DTRAN_MODE_CH_NUM_CH1 BIT(16) /* "upstream" = for read commands */
37 #define DTRAN_MODE_BUS_WIDTH (BIT(5) | BIT(4))
38 #define DTRAN_MODE_ADDR_MODE BIT(0) /* 1 = Increment address, 0 = Fixed */
40 /* DM_CM_DTRAN_CTRL */
41 #define DTRAN_CTRL_DM_START BIT(0)
43 /* DM_CM_RST */
44 #define RST_DTRANRST1 BIT(9)
45 #define RST_DTRANRST0 BIT(8)
46 #define RST_RESERVED_BITS GENMASK_ULL(31, 0)
48 /* DM_CM_INFO1 and DM_CM_INFO1_MASK */
49 #define INFO1_CLEAR 0
50 #define INFO1_MASK_CLEAR GENMASK_ULL(31, 0)
51 #define INFO1_DTRANEND1 BIT(17)
52 #define INFO1_DTRANEND0 BIT(16)
54 /* DM_CM_INFO2 and DM_CM_INFO2_MASK */
55 #define INFO2_MASK_CLEAR GENMASK_ULL(31, 0)
56 #define INFO2_DTRANERR1 BIT(17)
57 #define INFO2_DTRANERR0 BIT(16)
60 * Specification of this driver:
61 * - host->chan_{rx,tx} will be used as a flag of enabling/disabling the dma
62 * - Since this SDHI DMAC register set has 16 but 32-bit width, we
63 * need a custom accessor.
66 static unsigned long global_flags;
68 * Workaround for avoiding to use RX DMAC by multiple channels.
69 * On R-Car H3 ES1.* and M3-W ES1.0, when multiple SDHI channels use
70 * RX DMAC simultaneously, sometimes hundreds of bytes data are not
71 * stored into the system memory even if the DMAC interrupt happened.
72 * So, this driver then uses one RX DMAC channel only.
74 #define SDHI_INTERNAL_DMAC_ONE_RX_ONLY 0
75 #define SDHI_INTERNAL_DMAC_RX_IN_USE 1
77 /* RZ/A2 does not have the ADRR_MODE bit */
78 #define SDHI_INTERNAL_DMAC_ADDR_MODE_FIXED_ONLY 2
80 /* Definitions for sampling clocks */
81 static struct renesas_sdhi_scc rcar_gen3_scc_taps[] = {
83 .clk_rate = 0,
84 .tap = 0x00000300,
85 .tap_hs400_4tap = 0x00000100,
89 static const struct renesas_sdhi_of_data of_rza2_compatible = {
90 .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_CLK_ACTUAL |
91 TMIO_MMC_HAVE_CBSY,
92 .tmio_ocr_mask = MMC_VDD_32_33,
93 .capabilities = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
94 MMC_CAP_CMD23,
95 .bus_shift = 2,
96 .scc_offset = 0 - 0x1000,
97 .taps = rcar_gen3_scc_taps,
98 .taps_num = ARRAY_SIZE(rcar_gen3_scc_taps),
99 /* DMAC can handle 32bit blk count but only 1 segment */
100 .max_blk_count = UINT_MAX / TMIO_MAX_BLK_SIZE,
101 .max_segs = 1,
104 static const struct renesas_sdhi_of_data of_rcar_gen3_compatible = {
105 .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_CLK_ACTUAL |
106 TMIO_MMC_HAVE_CBSY | TMIO_MMC_MIN_RCAR2,
107 .capabilities = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
108 MMC_CAP_CMD23,
109 .capabilities2 = MMC_CAP2_NO_WRITE_PROTECT | MMC_CAP2_MERGE_CAPABLE,
110 .bus_shift = 2,
111 .scc_offset = 0x1000,
112 .taps = rcar_gen3_scc_taps,
113 .taps_num = ARRAY_SIZE(rcar_gen3_scc_taps),
114 /* DMAC can handle 32bit blk count but only 1 segment */
115 .max_blk_count = UINT_MAX / TMIO_MAX_BLK_SIZE,
116 .max_segs = 1,
119 static const struct of_device_id renesas_sdhi_internal_dmac_of_match[] = {
120 { .compatible = "renesas,sdhi-r7s9210", .data = &of_rza2_compatible, },
121 { .compatible = "renesas,sdhi-mmc-r8a77470", .data = &of_rcar_gen3_compatible, },
122 { .compatible = "renesas,sdhi-r8a7795", .data = &of_rcar_gen3_compatible, },
123 { .compatible = "renesas,sdhi-r8a7796", .data = &of_rcar_gen3_compatible, },
124 { .compatible = "renesas,rcar-gen3-sdhi", .data = &of_rcar_gen3_compatible, },
127 MODULE_DEVICE_TABLE(of, renesas_sdhi_internal_dmac_of_match);
129 static void
130 renesas_sdhi_internal_dmac_dm_write(struct tmio_mmc_host *host,
131 int addr, u64 val)
133 writeq(val, host->ctl + addr);
136 static void
137 renesas_sdhi_internal_dmac_enable_dma(struct tmio_mmc_host *host, bool enable)
139 struct renesas_sdhi *priv = host_to_priv(host);
141 if (!host->chan_tx || !host->chan_rx)
142 return;
144 if (!enable)
145 renesas_sdhi_internal_dmac_dm_write(host, DM_CM_INFO1,
146 INFO1_CLEAR);
148 if (priv->dma_priv.enable)
149 priv->dma_priv.enable(host, enable);
152 static void
153 renesas_sdhi_internal_dmac_abort_dma(struct tmio_mmc_host *host) {
154 u64 val = RST_DTRANRST1 | RST_DTRANRST0;
156 renesas_sdhi_internal_dmac_enable_dma(host, false);
158 renesas_sdhi_internal_dmac_dm_write(host, DM_CM_RST,
159 RST_RESERVED_BITS & ~val);
160 renesas_sdhi_internal_dmac_dm_write(host, DM_CM_RST,
161 RST_RESERVED_BITS | val);
163 clear_bit(SDHI_INTERNAL_DMAC_RX_IN_USE, &global_flags);
165 renesas_sdhi_internal_dmac_enable_dma(host, true);
168 static void
169 renesas_sdhi_internal_dmac_dataend_dma(struct tmio_mmc_host *host) {
170 struct renesas_sdhi *priv = host_to_priv(host);
172 tasklet_schedule(&priv->dma_priv.dma_complete);
175 static void
176 renesas_sdhi_internal_dmac_start_dma(struct tmio_mmc_host *host,
177 struct mmc_data *data)
179 struct scatterlist *sg = host->sg_ptr;
180 u32 dtran_mode = DTRAN_MODE_BUS_WIDTH;
182 if (!test_bit(SDHI_INTERNAL_DMAC_ADDR_MODE_FIXED_ONLY, &global_flags))
183 dtran_mode |= DTRAN_MODE_ADDR_MODE;
185 if (!dma_map_sg(&host->pdev->dev, sg, host->sg_len,
186 mmc_get_dma_dir(data)))
187 goto force_pio;
189 /* This DMAC cannot handle if buffer is not 8-bytes alignment */
190 if (!IS_ALIGNED(sg_dma_address(sg), 8))
191 goto force_pio_with_unmap;
193 if (data->flags & MMC_DATA_READ) {
194 dtran_mode |= DTRAN_MODE_CH_NUM_CH1;
195 if (test_bit(SDHI_INTERNAL_DMAC_ONE_RX_ONLY, &global_flags) &&
196 test_and_set_bit(SDHI_INTERNAL_DMAC_RX_IN_USE, &global_flags))
197 goto force_pio_with_unmap;
198 } else {
199 dtran_mode |= DTRAN_MODE_CH_NUM_CH0;
202 renesas_sdhi_internal_dmac_enable_dma(host, true);
204 /* set dma parameters */
205 renesas_sdhi_internal_dmac_dm_write(host, DM_CM_DTRAN_MODE,
206 dtran_mode);
207 renesas_sdhi_internal_dmac_dm_write(host, DM_DTRAN_ADDR,
208 sg_dma_address(sg));
210 host->dma_on = true;
212 return;
214 force_pio_with_unmap:
215 dma_unmap_sg(&host->pdev->dev, sg, host->sg_len, mmc_get_dma_dir(data));
217 force_pio:
218 renesas_sdhi_internal_dmac_enable_dma(host, false);
221 static void renesas_sdhi_internal_dmac_issue_tasklet_fn(unsigned long arg)
223 struct tmio_mmc_host *host = (struct tmio_mmc_host *)arg;
225 tmio_mmc_enable_mmc_irqs(host, TMIO_STAT_DATAEND);
227 /* start the DMAC */
228 renesas_sdhi_internal_dmac_dm_write(host, DM_CM_DTRAN_CTRL,
229 DTRAN_CTRL_DM_START);
232 static void renesas_sdhi_internal_dmac_complete_tasklet_fn(unsigned long arg)
234 struct tmio_mmc_host *host = (struct tmio_mmc_host *)arg;
235 enum dma_data_direction dir;
237 spin_lock_irq(&host->lock);
239 if (!host->data)
240 goto out;
242 if (host->data->flags & MMC_DATA_READ)
243 dir = DMA_FROM_DEVICE;
244 else
245 dir = DMA_TO_DEVICE;
247 renesas_sdhi_internal_dmac_enable_dma(host, false);
248 dma_unmap_sg(&host->pdev->dev, host->sg_ptr, host->sg_len, dir);
250 if (dir == DMA_FROM_DEVICE)
251 clear_bit(SDHI_INTERNAL_DMAC_RX_IN_USE, &global_flags);
253 tmio_mmc_do_data_irq(host);
254 out:
255 spin_unlock_irq(&host->lock);
258 static void
259 renesas_sdhi_internal_dmac_request_dma(struct tmio_mmc_host *host,
260 struct tmio_mmc_data *pdata)
262 struct renesas_sdhi *priv = host_to_priv(host);
264 /* Disable DMAC interrupts, we don't use them */
265 renesas_sdhi_internal_dmac_dm_write(host, DM_CM_INFO1_MASK,
266 INFO1_MASK_CLEAR);
267 renesas_sdhi_internal_dmac_dm_write(host, DM_CM_INFO2_MASK,
268 INFO2_MASK_CLEAR);
270 /* Each value is set to non-zero to assume "enabling" each DMA */
271 host->chan_rx = host->chan_tx = (void *)0xdeadbeaf;
273 tasklet_init(&priv->dma_priv.dma_complete,
274 renesas_sdhi_internal_dmac_complete_tasklet_fn,
275 (unsigned long)host);
276 tasklet_init(&host->dma_issue,
277 renesas_sdhi_internal_dmac_issue_tasklet_fn,
278 (unsigned long)host);
281 static void
282 renesas_sdhi_internal_dmac_release_dma(struct tmio_mmc_host *host)
284 /* Each value is set to zero to assume "disabling" each DMA */
285 host->chan_rx = host->chan_tx = NULL;
288 static const struct tmio_mmc_dma_ops renesas_sdhi_internal_dmac_dma_ops = {
289 .start = renesas_sdhi_internal_dmac_start_dma,
290 .enable = renesas_sdhi_internal_dmac_enable_dma,
291 .request = renesas_sdhi_internal_dmac_request_dma,
292 .release = renesas_sdhi_internal_dmac_release_dma,
293 .abort = renesas_sdhi_internal_dmac_abort_dma,
294 .dataend = renesas_sdhi_internal_dmac_dataend_dma,
298 * Whitelist of specific R-Car Gen3 SoC ES versions to use this DMAC
299 * implementation as others may use a different implementation.
301 static const struct soc_device_attribute soc_dma_quirks[] = {
302 { .soc_id = "r7s9210",
303 .data = (void *)BIT(SDHI_INTERNAL_DMAC_ADDR_MODE_FIXED_ONLY) },
304 { .soc_id = "r8a7795", .revision = "ES1.*",
305 .data = (void *)BIT(SDHI_INTERNAL_DMAC_ONE_RX_ONLY) },
306 { .soc_id = "r8a7796", .revision = "ES1.0",
307 .data = (void *)BIT(SDHI_INTERNAL_DMAC_ONE_RX_ONLY) },
308 { /* sentinel */ }
311 static int renesas_sdhi_internal_dmac_probe(struct platform_device *pdev)
313 const struct soc_device_attribute *soc = soc_device_match(soc_dma_quirks);
314 struct device *dev = &pdev->dev;
316 if (soc)
317 global_flags |= (unsigned long)soc->data;
319 dev->dma_parms = devm_kzalloc(dev, sizeof(*dev->dma_parms), GFP_KERNEL);
320 if (!dev->dma_parms)
321 return -ENOMEM;
323 /* value is max of SD_SECCNT. Confirmed by HW engineers */
324 dma_set_max_seg_size(dev, 0xffffffff);
326 return renesas_sdhi_probe(pdev, &renesas_sdhi_internal_dmac_dma_ops);
329 static const struct dev_pm_ops renesas_sdhi_internal_dmac_dev_pm_ops = {
330 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
331 pm_runtime_force_resume)
332 SET_RUNTIME_PM_OPS(tmio_mmc_host_runtime_suspend,
333 tmio_mmc_host_runtime_resume,
334 NULL)
337 static struct platform_driver renesas_internal_dmac_sdhi_driver = {
338 .driver = {
339 .name = "renesas_sdhi_internal_dmac",
340 .pm = &renesas_sdhi_internal_dmac_dev_pm_ops,
341 .of_match_table = renesas_sdhi_internal_dmac_of_match,
343 .probe = renesas_sdhi_internal_dmac_probe,
344 .remove = renesas_sdhi_remove,
347 module_platform_driver(renesas_internal_dmac_sdhi_driver);
349 MODULE_DESCRIPTION("Renesas SDHI driver for internal DMAC");
350 MODULE_AUTHOR("Yoshihiro Shimoda");
351 MODULE_LICENSE("GPL v2");