?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
treewide: remove redundant IS_ERR() before error code check
[linux/fpc-iii.git] / drivers / mmc / host / sdhci-esdhc-imx.c
blob382f25b2fa458da7667dc158226059344c9828c3
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Freescale eSDHC i.MX controller driver for the platform bus.
4 *
5 * derived from the OF-version.
6 *
7 * Copyright (c) 2010 Pengutronix e.K.
8 * Author: Wolfram Sang <kernel@pengutronix.de>
9 */
10
11 #include <linux/io.h>
12 #include <linux/delay.h>
13 #include <linux/err.h>
14 #include <linux/clk.h>
15 #include <linux/module.h>
16 #include <linux/slab.h>
17 #include <linux/pm_qos.h>
18 #include <linux/mmc/host.h>
19 #include <linux/mmc/mmc.h>
20 #include <linux/mmc/sdio.h>
21 #include <linux/mmc/slot-gpio.h>
22 #include <linux/of.h>
23 #include <linux/of_device.h>
24 #include <linux/pinctrl/consumer.h>
25 #include <linux/platform_data/mmc-esdhc-imx.h>
26 #include <linux/pm_runtime.h>
27 #include "sdhci-pltfm.h"
28 #include "sdhci-esdhc.h"
29 #include "cqhci.h"
30
31 #define ESDHC_SYS_CTRL_DTOCV_MASK 0x0f
32 #define ESDHC_CTRL_D3CD 0x08
33 #define ESDHC_BURST_LEN_EN_INCR (1 << 27)
34 /* VENDOR SPEC register */
35 #define ESDHC_VENDOR_SPEC 0xc0
36 #define ESDHC_VENDOR_SPEC_SDIO_QUIRK (1 << 1)
37 #define ESDHC_VENDOR_SPEC_VSELECT (1 << 1)
38 #define ESDHC_VENDOR_SPEC_FRC_SDCLK_ON (1 << 8)
39 #define ESDHC_WTMK_LVL 0x44
40 #define ESDHC_WTMK_DEFAULT_VAL 0x10401040
41 #define ESDHC_WTMK_LVL_RD_WML_MASK 0x000000FF
42 #define ESDHC_WTMK_LVL_RD_WML_SHIFT 0
43 #define ESDHC_WTMK_LVL_WR_WML_MASK 0x00FF0000
44 #define ESDHC_WTMK_LVL_WR_WML_SHIFT 16
45 #define ESDHC_WTMK_LVL_WML_VAL_DEF 64
46 #define ESDHC_WTMK_LVL_WML_VAL_MAX 128
47 #define ESDHC_MIX_CTRL 0x48
48 #define ESDHC_MIX_CTRL_DDREN (1 << 3)
49 #define ESDHC_MIX_CTRL_AC23EN (1 << 7)
50 #define ESDHC_MIX_CTRL_EXE_TUNE (1 << 22)
51 #define ESDHC_MIX_CTRL_SMPCLK_SEL (1 << 23)
52 #define ESDHC_MIX_CTRL_AUTO_TUNE_EN (1 << 24)
53 #define ESDHC_MIX_CTRL_FBCLK_SEL (1 << 25)
54 #define ESDHC_MIX_CTRL_HS400_EN (1 << 26)
55 #define ESDHC_MIX_CTRL_HS400_ES_EN (1 << 27)
56 /* Bits 3 and 6 are not SDHCI standard definitions */
57 #define ESDHC_MIX_CTRL_SDHCI_MASK 0xb7
58 /* Tuning bits */
59 #define ESDHC_MIX_CTRL_TUNING_MASK 0x03c00000
60
61 /* dll control register */
62 #define ESDHC_DLL_CTRL 0x60
63 #define ESDHC_DLL_OVERRIDE_VAL_SHIFT 9
64 #define ESDHC_DLL_OVERRIDE_EN_SHIFT 8
65
66 /* tune control register */
67 #define ESDHC_TUNE_CTRL_STATUS 0x68
68 #define ESDHC_TUNE_CTRL_STEP 1
69 #define ESDHC_TUNE_CTRL_MIN 0
70 #define ESDHC_TUNE_CTRL_MAX ((1 << 7) - 1)
71
72 /* strobe dll register */
73 #define ESDHC_STROBE_DLL_CTRL 0x70
74 #define ESDHC_STROBE_DLL_CTRL_ENABLE (1 << 0)
75 #define ESDHC_STROBE_DLL_CTRL_RESET (1 << 1)
76 #define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT 3
77 #define ESDHC_STROBE_DLL_CTRL_SLV_UPDATE_INT_DEFAULT (4 << 20)
78
79 #define ESDHC_STROBE_DLL_STATUS 0x74
80 #define ESDHC_STROBE_DLL_STS_REF_LOCK (1 << 1)
81 #define ESDHC_STROBE_DLL_STS_SLV_LOCK 0x1
82
83 #define ESDHC_VEND_SPEC2 0xc8
84 #define ESDHC_VEND_SPEC2_EN_BUSY_IRQ (1 << 8)
85
86 #define ESDHC_TUNING_CTRL 0xcc
87 #define ESDHC_STD_TUNING_EN (1 << 24)
88 /* NOTE: the minimum valid tuning start tap for mx6sl is 1 */
89 #define ESDHC_TUNING_START_TAP_DEFAULT 0x1
90 #define ESDHC_TUNING_START_TAP_MASK 0xff
91 #define ESDHC_TUNING_STEP_MASK 0x00070000
92 #define ESDHC_TUNING_STEP_SHIFT 16
93
94 /* pinctrl state */
95 #define ESDHC_PINCTRL_STATE_100MHZ "state_100mhz"
96 #define ESDHC_PINCTRL_STATE_200MHZ "state_200mhz"
97
98 /*
99 * Our interpretation of the SDHCI_HOST_CONTROL register
100 */
101 #define ESDHC_CTRL_4BITBUS (0x1 << 1)
102 #define ESDHC_CTRL_8BITBUS (0x2 << 1)
103 #define ESDHC_CTRL_BUSWIDTH_MASK (0x3 << 1)
104
105 /*
106 * There is an INT DMA ERR mismatch between eSDHC and STD SDHC SPEC:
107 * Bit25 is used in STD SPEC, and is reserved in fsl eSDHC design,
108 * but bit28 is used as the INT DMA ERR in fsl eSDHC design.
109 * Define this macro DMA error INT for fsl eSDHC
110 */
111 #define ESDHC_INT_VENDOR_SPEC_DMA_ERR (1 << 28)
112
113 /* the address offset of CQHCI */
114 #define ESDHC_CQHCI_ADDR_OFFSET 0x100
115
116 /*
117 * The CMDTYPE of the CMD register (offset 0xE) should be set to
118 * "11" when the STOP CMD12 is issued on imx53 to abort one
119 * open ended multi-blk IO. Otherwise the TC INT wouldn't
120 * be generated.
121 * In exact block transfer, the controller doesn't complete the
122 * operations automatically as required at the end of the
123 * transfer and remains on hold if the abort command is not sent.
124 * As a result, the TC flag is not asserted and SW received timeout
125 * exception. Bit1 of Vendor Spec register is used to fix it.
126 */
127 #define ESDHC_FLAG_MULTIBLK_NO_INT BIT(1)
128 /*
129 * The flag tells that the ESDHC controller is an USDHC block that is
130 * integrated on the i.MX6 series.
131 */
132 #define ESDHC_FLAG_USDHC BIT(3)
133 /* The IP supports manual tuning process */
134 #define ESDHC_FLAG_MAN_TUNING BIT(4)
135 /* The IP supports standard tuning process */
136 #define ESDHC_FLAG_STD_TUNING BIT(5)
137 /* The IP has SDHCI_CAPABILITIES_1 register */
138 #define ESDHC_FLAG_HAVE_CAP1 BIT(6)
139 /*
140 * The IP has erratum ERR004536
141 * uSDHC: ADMA Length Mismatch Error occurs if the AHB read access is slow,
142 * when reading data from the card
143 * This flag is also set for i.MX25 and i.MX35 in order to get
144 * SDHCI_QUIRK_BROKEN_ADMA, but for different reasons (ADMA capability bits).
145 */
146 #define ESDHC_FLAG_ERR004536 BIT(7)
147 /* The IP supports HS200 mode */
148 #define ESDHC_FLAG_HS200 BIT(8)
149 /* The IP supports HS400 mode */
150 #define ESDHC_FLAG_HS400 BIT(9)
151 /*
152 * The IP has errata ERR010450
153 * uSDHC: Due to the I/O timing limit, for SDR mode, SD card clock can't
154 * exceed 150MHz, for DDR mode, SD card clock can't exceed 45MHz.
155 */
156 #define ESDHC_FLAG_ERR010450 BIT(10)
157 /* The IP supports HS400ES mode */
158 #define ESDHC_FLAG_HS400_ES BIT(11)
159 /* The IP has Host Controller Interface for Command Queuing */
160 #define ESDHC_FLAG_CQHCI BIT(12)
161 /* need request pmqos during low power */
162 #define ESDHC_FLAG_PMQOS BIT(13)
163
164 struct esdhc_soc_data {
165 u32 flags;
166 };
167
168 static const struct esdhc_soc_data esdhc_imx25_data = {
169 .flags = ESDHC_FLAG_ERR004536,
170 };
171
172 static const struct esdhc_soc_data esdhc_imx35_data = {
173 .flags = ESDHC_FLAG_ERR004536,
174 };
175
176 static const struct esdhc_soc_data esdhc_imx51_data = {
177 .flags = 0,
178 };
179
180 static const struct esdhc_soc_data esdhc_imx53_data = {
181 .flags = ESDHC_FLAG_MULTIBLK_NO_INT,
182 };
183
184 static const struct esdhc_soc_data usdhc_imx6q_data = {
185 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_MAN_TUNING,
186 };
187
188 static const struct esdhc_soc_data usdhc_imx6sl_data = {
189 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
190 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_ERR004536
191 | ESDHC_FLAG_HS200,
192 };
193
194 static const struct esdhc_soc_data usdhc_imx6sx_data = {
195 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
196 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200,
197 };
198
199 static const struct esdhc_soc_data usdhc_imx6ull_data = {
200 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
201 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
202 | ESDHC_FLAG_ERR010450,
203 };
204
205 static const struct esdhc_soc_data usdhc_imx7d_data = {
206 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
207 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
208 | ESDHC_FLAG_HS400,
209 };
210
211 static struct esdhc_soc_data usdhc_imx7ulp_data = {
212 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
213 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
214 | ESDHC_FLAG_PMQOS | ESDHC_FLAG_HS400,
215 };
216
217 static struct esdhc_soc_data usdhc_imx8qxp_data = {
218 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
219 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
220 | ESDHC_FLAG_HS400 | ESDHC_FLAG_HS400_ES
221 | ESDHC_FLAG_CQHCI,
222 };
223
224 struct pltfm_imx_data {
225 u32 scratchpad;
226 struct pinctrl *pinctrl;
227 struct pinctrl_state *pins_100mhz;
228 struct pinctrl_state *pins_200mhz;
229 const struct esdhc_soc_data *socdata;
230 struct esdhc_platform_data boarddata;
231 struct clk *clk_ipg;
232 struct clk *clk_ahb;
233 struct clk *clk_per;
234 unsigned int actual_clock;
235 enum {
236 NO_CMD_PENDING, /* no multiblock command pending */
237 MULTIBLK_IN_PROCESS, /* exact multiblock cmd in process */
238 WAIT_FOR_INT, /* sent CMD12, waiting for response INT */
239 } multiblock_status;
240 u32 is_ddr;
241 struct pm_qos_request pm_qos_req;
242 };
243
244 static const struct platform_device_id imx_esdhc_devtype[] = {
245 {
246 .name = "sdhci-esdhc-imx25",
247 .driver_data = (kernel_ulong_t) &esdhc_imx25_data,
248 }, {
249 .name = "sdhci-esdhc-imx35",
250 .driver_data = (kernel_ulong_t) &esdhc_imx35_data,
251 }, {
252 .name = "sdhci-esdhc-imx51",
253 .driver_data = (kernel_ulong_t) &esdhc_imx51_data,
254 }, {
255 /* sentinel */
256 }
257 };
258 MODULE_DEVICE_TABLE(platform, imx_esdhc_devtype);
259
260 static const struct of_device_id imx_esdhc_dt_ids[] = {
261 { .compatible = "fsl,imx25-esdhc", .data = &esdhc_imx25_data, },
262 { .compatible = "fsl,imx35-esdhc", .data = &esdhc_imx35_data, },
263 { .compatible = "fsl,imx51-esdhc", .data = &esdhc_imx51_data, },
264 { .compatible = "fsl,imx53-esdhc", .data = &esdhc_imx53_data, },
265 { .compatible = "fsl,imx6sx-usdhc", .data = &usdhc_imx6sx_data, },
266 { .compatible = "fsl,imx6sl-usdhc", .data = &usdhc_imx6sl_data, },
267 { .compatible = "fsl,imx6q-usdhc", .data = &usdhc_imx6q_data, },
268 { .compatible = "fsl,imx6ull-usdhc", .data = &usdhc_imx6ull_data, },
269 { .compatible = "fsl,imx7d-usdhc", .data = &usdhc_imx7d_data, },
270 { .compatible = "fsl,imx7ulp-usdhc", .data = &usdhc_imx7ulp_data, },
271 { .compatible = "fsl,imx8qxp-usdhc", .data = &usdhc_imx8qxp_data, },
272 { /* sentinel */ }
273 };
274 MODULE_DEVICE_TABLE(of, imx_esdhc_dt_ids);
275
276 static inline int is_imx25_esdhc(struct pltfm_imx_data *data)
277 {
278 return data->socdata == &esdhc_imx25_data;
279 }
280
281 static inline int is_imx53_esdhc(struct pltfm_imx_data *data)
282 {
283 return data->socdata == &esdhc_imx53_data;
284 }
285
286 static inline int is_imx6q_usdhc(struct pltfm_imx_data *data)
287 {
288 return data->socdata == &usdhc_imx6q_data;
289 }
290
291 static inline int esdhc_is_usdhc(struct pltfm_imx_data *data)
292 {
293 return !!(data->socdata->flags & ESDHC_FLAG_USDHC);
294 }
295
296 static inline void esdhc_clrset_le(struct sdhci_host *host, u32 mask, u32 val, int reg)
297 {
298 void __iomem *base = host->ioaddr + (reg & ~0x3);
299 u32 shift = (reg & 0x3) * 8;
300
301 writel(((readl(base) & ~(mask << shift)) | (val << shift)), base);
302 }
303
304 static u32 esdhc_readl_le(struct sdhci_host *host, int reg)
305 {
306 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
307 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
308 u32 val = readl(host->ioaddr + reg);
309
310 if (unlikely(reg == SDHCI_PRESENT_STATE)) {
311 u32 fsl_prss = val;
312 /* save the least 20 bits */
313 val = fsl_prss & 0x000FFFFF;
314 /* move dat[0-3] bits */
315 val |= (fsl_prss & 0x0F000000) >> 4;
316 /* move cmd line bit */
317 val |= (fsl_prss & 0x00800000) << 1;
318 }
319
320 if (unlikely(reg == SDHCI_CAPABILITIES)) {
321 /* ignore bit[0-15] as it stores cap_1 register val for mx6sl */
322 if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1)
323 val &= 0xffff0000;
324
325 /* In FSL esdhc IC module, only bit20 is used to indicate the
326 * ADMA2 capability of esdhc, but this bit is messed up on
327 * some SOCs (e.g. on MX25, MX35 this bit is set, but they
328 * don't actually support ADMA2). So set the BROKEN_ADMA
329 * quirk on MX25/35 platforms.
330 */
331
332 if (val & SDHCI_CAN_DO_ADMA1) {
333 val &= ~SDHCI_CAN_DO_ADMA1;
334 val |= SDHCI_CAN_DO_ADMA2;
335 }
336 }
337
338 if (unlikely(reg == SDHCI_CAPABILITIES_1)) {
339 if (esdhc_is_usdhc(imx_data)) {
340 if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1)
341 val = readl(host->ioaddr + SDHCI_CAPABILITIES) & 0xFFFF;
342 else
343 /* imx6q/dl does not have cap_1 register, fake one */
344 val = SDHCI_SUPPORT_DDR50 | SDHCI_SUPPORT_SDR104
345 | SDHCI_SUPPORT_SDR50
346 | SDHCI_USE_SDR50_TUNING
347 | (SDHCI_TUNING_MODE_3 << SDHCI_RETUNING_MODE_SHIFT);
348
349 if (imx_data->socdata->flags & ESDHC_FLAG_HS400)
350 val |= SDHCI_SUPPORT_HS400;
351
352 /*
353 * Do not advertise faster UHS modes if there are no
354 * pinctrl states for 100MHz/200MHz.
355 */
356 if (IS_ERR_OR_NULL(imx_data->pins_100mhz) ||
357 IS_ERR_OR_NULL(imx_data->pins_200mhz))
358 val &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_DDR50
359 | SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_HS400);
360 }
361 }
362
363 if (unlikely(reg == SDHCI_MAX_CURRENT) && esdhc_is_usdhc(imx_data)) {
364 val = 0;
365 val |= 0xFF << SDHCI_MAX_CURRENT_330_SHIFT;
366 val |= 0xFF << SDHCI_MAX_CURRENT_300_SHIFT;
367 val |= 0xFF << SDHCI_MAX_CURRENT_180_SHIFT;
368 }
369
370 if (unlikely(reg == SDHCI_INT_STATUS)) {
371 if (val & ESDHC_INT_VENDOR_SPEC_DMA_ERR) {
372 val &= ~ESDHC_INT_VENDOR_SPEC_DMA_ERR;
373 val |= SDHCI_INT_ADMA_ERROR;
374 }
375
376 /*
377 * mask off the interrupt we get in response to the manually
378 * sent CMD12
379 */
380 if ((imx_data->multiblock_status == WAIT_FOR_INT) &&
381 ((val & SDHCI_INT_RESPONSE) == SDHCI_INT_RESPONSE)) {
382 val &= ~SDHCI_INT_RESPONSE;
383 writel(SDHCI_INT_RESPONSE, host->ioaddr +
384 SDHCI_INT_STATUS);
385 imx_data->multiblock_status = NO_CMD_PENDING;
386 }
387 }
388
389 return val;
390 }
391
392 static void esdhc_writel_le(struct sdhci_host *host, u32 val, int reg)
393 {
394 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
395 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
396 u32 data;
397
398 if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE ||
399 reg == SDHCI_INT_STATUS)) {
400 if ((val & SDHCI_INT_CARD_INT) && !esdhc_is_usdhc(imx_data)) {
401 /*
402 * Clear and then set D3CD bit to avoid missing the
403 * card interrupt. This is an eSDHC controller problem
404 * so we need to apply the following workaround: clear
405 * and set D3CD bit will make eSDHC re-sample the card
406 * interrupt. In case a card interrupt was lost,
407 * re-sample it by the following steps.
408 */
409 data = readl(host->ioaddr + SDHCI_HOST_CONTROL);
410 data &= ~ESDHC_CTRL_D3CD;
411 writel(data, host->ioaddr + SDHCI_HOST_CONTROL);
412 data |= ESDHC_CTRL_D3CD;
413 writel(data, host->ioaddr + SDHCI_HOST_CONTROL);
414 }
415
416 if (val & SDHCI_INT_ADMA_ERROR) {
417 val &= ~SDHCI_INT_ADMA_ERROR;
418 val |= ESDHC_INT_VENDOR_SPEC_DMA_ERR;
419 }
420 }
421
422 if (unlikely((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT)
423 && (reg == SDHCI_INT_STATUS)
424 && (val & SDHCI_INT_DATA_END))) {
425 u32 v;
426 v = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
427 v &= ~ESDHC_VENDOR_SPEC_SDIO_QUIRK;
428 writel(v, host->ioaddr + ESDHC_VENDOR_SPEC);
429
430 if (imx_data->multiblock_status == MULTIBLK_IN_PROCESS)
431 {
432 /* send a manual CMD12 with RESPTYP=none */
433 data = MMC_STOP_TRANSMISSION << 24 |
434 SDHCI_CMD_ABORTCMD << 16;
435 writel(data, host->ioaddr + SDHCI_TRANSFER_MODE);
436 imx_data->multiblock_status = WAIT_FOR_INT;
437 }
438 }
439
440 writel(val, host->ioaddr + reg);
441 }
442
443 static u16 esdhc_readw_le(struct sdhci_host *host, int reg)
444 {
445 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
446 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
447 u16 ret = 0;
448 u32 val;
449
450 if (unlikely(reg == SDHCI_HOST_VERSION)) {
451 reg ^= 2;
452 if (esdhc_is_usdhc(imx_data)) {
453 /*
454 * The usdhc register returns a wrong host version.
455 * Correct it here.
456 */
457 return SDHCI_SPEC_300;
458 }
459 }
460
461 if (unlikely(reg == SDHCI_HOST_CONTROL2)) {
462 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
463 if (val & ESDHC_VENDOR_SPEC_VSELECT)
464 ret |= SDHCI_CTRL_VDD_180;
465
466 if (esdhc_is_usdhc(imx_data)) {
467 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING)
468 val = readl(host->ioaddr + ESDHC_MIX_CTRL);
469 else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING)
470 /* the std tuning bits is in ACMD12_ERR for imx6sl */
471 val = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS);
472 }
473
474 if (val & ESDHC_MIX_CTRL_EXE_TUNE)
475 ret |= SDHCI_CTRL_EXEC_TUNING;
476 if (val & ESDHC_MIX_CTRL_SMPCLK_SEL)
477 ret |= SDHCI_CTRL_TUNED_CLK;
478
479 ret &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
480
481 return ret;
482 }
483
484 if (unlikely(reg == SDHCI_TRANSFER_MODE)) {
485 if (esdhc_is_usdhc(imx_data)) {
486 u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
487 ret = m & ESDHC_MIX_CTRL_SDHCI_MASK;
488 /* Swap AC23 bit */
489 if (m & ESDHC_MIX_CTRL_AC23EN) {
490 ret &= ~ESDHC_MIX_CTRL_AC23EN;
491 ret |= SDHCI_TRNS_AUTO_CMD23;
492 }
493 } else {
494 ret = readw(host->ioaddr + SDHCI_TRANSFER_MODE);
495 }
496
497 return ret;
498 }
499
500 return readw(host->ioaddr + reg);
501 }
502
503 static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg)
504 {
505 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
506 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
507 u32 new_val = 0;
508
509 switch (reg) {
510 case SDHCI_CLOCK_CONTROL:
511 new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
512 if (val & SDHCI_CLOCK_CARD_EN)
513 new_val |= ESDHC_VENDOR_SPEC_FRC_SDCLK_ON;
514 else
515 new_val &= ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON;
516 writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC);
517 return;
518 case SDHCI_HOST_CONTROL2:
519 new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
520 if (val & SDHCI_CTRL_VDD_180)
521 new_val |= ESDHC_VENDOR_SPEC_VSELECT;
522 else
523 new_val &= ~ESDHC_VENDOR_SPEC_VSELECT;
524 writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC);
525 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) {
526 new_val = readl(host->ioaddr + ESDHC_MIX_CTRL);
527 if (val & SDHCI_CTRL_TUNED_CLK) {
528 new_val |= ESDHC_MIX_CTRL_SMPCLK_SEL;
529 new_val |= ESDHC_MIX_CTRL_AUTO_TUNE_EN;
530 } else {
531 new_val &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
532 new_val &= ~ESDHC_MIX_CTRL_AUTO_TUNE_EN;
533 }
534 writel(new_val , host->ioaddr + ESDHC_MIX_CTRL);
535 } else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) {
536 u32 v = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS);
537 u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
538 if (val & SDHCI_CTRL_TUNED_CLK) {
539 v |= ESDHC_MIX_CTRL_SMPCLK_SEL;
540 } else {
541 v &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
542 m &= ~ESDHC_MIX_CTRL_FBCLK_SEL;
543 m &= ~ESDHC_MIX_CTRL_AUTO_TUNE_EN;
544 }
545
546 if (val & SDHCI_CTRL_EXEC_TUNING) {
547 v |= ESDHC_MIX_CTRL_EXE_TUNE;
548 m |= ESDHC_MIX_CTRL_FBCLK_SEL;
549 m |= ESDHC_MIX_CTRL_AUTO_TUNE_EN;
550 } else {
551 v &= ~ESDHC_MIX_CTRL_EXE_TUNE;
552 }
553
554 writel(v, host->ioaddr + SDHCI_AUTO_CMD_STATUS);
555 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
556 }
557 return;
558 case SDHCI_TRANSFER_MODE:
559 if ((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT)
560 && (host->cmd->opcode == SD_IO_RW_EXTENDED)
561 && (host->cmd->data->blocks > 1)
562 && (host->cmd->data->flags & MMC_DATA_READ)) {
563 u32 v;
564 v = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
565 v |= ESDHC_VENDOR_SPEC_SDIO_QUIRK;
566 writel(v, host->ioaddr + ESDHC_VENDOR_SPEC);
567 }
568
569 if (esdhc_is_usdhc(imx_data)) {
570 u32 wml;
571 u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
572 /* Swap AC23 bit */
573 if (val & SDHCI_TRNS_AUTO_CMD23) {
574 val &= ~SDHCI_TRNS_AUTO_CMD23;
575 val |= ESDHC_MIX_CTRL_AC23EN;
576 }
577 m = val | (m & ~ESDHC_MIX_CTRL_SDHCI_MASK);
578 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
579
580 /* Set watermark levels for PIO access to maximum value
581 * (128 words) to accommodate full 512 bytes buffer.
582 * For DMA access restore the levels to default value.
583 */
584 m = readl(host->ioaddr + ESDHC_WTMK_LVL);
585 if (val & SDHCI_TRNS_DMA)
586 wml = ESDHC_WTMK_LVL_WML_VAL_DEF;
587 else
588 wml = ESDHC_WTMK_LVL_WML_VAL_MAX;
589 m &= ~(ESDHC_WTMK_LVL_RD_WML_MASK |
590 ESDHC_WTMK_LVL_WR_WML_MASK);
591 m |= (wml << ESDHC_WTMK_LVL_RD_WML_SHIFT) |
592 (wml << ESDHC_WTMK_LVL_WR_WML_SHIFT);
593 writel(m, host->ioaddr + ESDHC_WTMK_LVL);
594 } else {
595 /*
596 * Postpone this write, we must do it together with a
597 * command write that is down below.
598 */
599 imx_data->scratchpad = val;
600 }
601 return;
602 case SDHCI_COMMAND:
603 if (host->cmd->opcode == MMC_STOP_TRANSMISSION)
604 val |= SDHCI_CMD_ABORTCMD;
605
606 if ((host->cmd->opcode == MMC_SET_BLOCK_COUNT) &&
607 (imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT))
608 imx_data->multiblock_status = MULTIBLK_IN_PROCESS;
609
610 if (esdhc_is_usdhc(imx_data))
611 writel(val << 16,
612 host->ioaddr + SDHCI_TRANSFER_MODE);
613 else
614 writel(val << 16 | imx_data->scratchpad,
615 host->ioaddr + SDHCI_TRANSFER_MODE);
616 return;
617 case SDHCI_BLOCK_SIZE:
618 val &= ~SDHCI_MAKE_BLKSZ(0x7, 0);
619 break;
620 }
621 esdhc_clrset_le(host, 0xffff, val, reg);
622 }
623
624 static u8 esdhc_readb_le(struct sdhci_host *host, int reg)
625 {
626 u8 ret;
627 u32 val;
628
629 switch (reg) {
630 case SDHCI_HOST_CONTROL:
631 val = readl(host->ioaddr + reg);
632
633 ret = val & SDHCI_CTRL_LED;
634 ret |= (val >> 5) & SDHCI_CTRL_DMA_MASK;
635 ret |= (val & ESDHC_CTRL_4BITBUS);
636 ret |= (val & ESDHC_CTRL_8BITBUS) << 3;
637 return ret;
638 }
639
640 return readb(host->ioaddr + reg);
641 }
642
643 static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg)
644 {
645 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
646 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
647 u32 new_val = 0;
648 u32 mask;
649
650 switch (reg) {
651 case SDHCI_POWER_CONTROL:
652 /*
653 * FSL put some DMA bits here
654 * If your board has a regulator, code should be here
655 */
656 return;
657 case SDHCI_HOST_CONTROL:
658 /* FSL messed up here, so we need to manually compose it. */
659 new_val = val & SDHCI_CTRL_LED;
660 /* ensure the endianness */
661 new_val |= ESDHC_HOST_CONTROL_LE;
662 /* bits 8&9 are reserved on mx25 */
663 if (!is_imx25_esdhc(imx_data)) {
664 /* DMA mode bits are shifted */
665 new_val |= (val & SDHCI_CTRL_DMA_MASK) << 5;
666 }
667
668 /*
669 * Do not touch buswidth bits here. This is done in
670 * esdhc_pltfm_bus_width.
671 * Do not touch the D3CD bit either which is used for the
672 * SDIO interrupt erratum workaround.
673 */
674 mask = 0xffff & ~(ESDHC_CTRL_BUSWIDTH_MASK | ESDHC_CTRL_D3CD);
675
676 esdhc_clrset_le(host, mask, new_val, reg);
677 return;
678 case SDHCI_SOFTWARE_RESET:
679 if (val & SDHCI_RESET_DATA)
680 new_val = readl(host->ioaddr + SDHCI_HOST_CONTROL);
681 break;
682 }
683 esdhc_clrset_le(host, 0xff, val, reg);
684
685 if (reg == SDHCI_SOFTWARE_RESET) {
686 if (val & SDHCI_RESET_ALL) {
687 /*
688 * The esdhc has a design violation to SDHC spec which
689 * tells that software reset should not affect card
690 * detection circuit. But esdhc clears its SYSCTL
691 * register bits [0..2] during the software reset. This
692 * will stop those clocks that card detection circuit
693 * relies on. To work around it, we turn the clocks on
694 * back to keep card detection circuit functional.
695 */
696 esdhc_clrset_le(host, 0x7, 0x7, ESDHC_SYSTEM_CONTROL);
697 /*
698 * The reset on usdhc fails to clear MIX_CTRL register.
699 * Do it manually here.
700 */
701 if (esdhc_is_usdhc(imx_data)) {
702 /*
703 * the tuning bits should be kept during reset
704 */
705 new_val = readl(host->ioaddr + ESDHC_MIX_CTRL);
706 writel(new_val & ESDHC_MIX_CTRL_TUNING_MASK,
707 host->ioaddr + ESDHC_MIX_CTRL);
708 imx_data->is_ddr = 0;
709 }
710 } else if (val & SDHCI_RESET_DATA) {
711 /*
712 * The eSDHC DAT line software reset clears at least the
713 * data transfer width on i.MX25, so make sure that the
714 * Host Control register is unaffected.
715 */
716 esdhc_clrset_le(host, 0xff, new_val,
717 SDHCI_HOST_CONTROL);
718 }
719 }
720 }
721
722 static unsigned int esdhc_pltfm_get_max_clock(struct sdhci_host *host)
723 {
724 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
725
726 return pltfm_host->clock;
727 }
728
729 static unsigned int esdhc_pltfm_get_min_clock(struct sdhci_host *host)
730 {
731 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
732
733 return pltfm_host->clock / 256 / 16;
734 }
735
736 static inline void esdhc_pltfm_set_clock(struct sdhci_host *host,
737 unsigned int clock)
738 {
739 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
740 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
741 unsigned int host_clock = pltfm_host->clock;
742 int ddr_pre_div = imx_data->is_ddr ? 2 : 1;
743 int pre_div = 1;
744 int div = 1;
745 u32 temp, val;
746
747 if (esdhc_is_usdhc(imx_data)) {
748 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
749 writel(val & ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON,
750 host->ioaddr + ESDHC_VENDOR_SPEC);
751 }
752
753 if (clock == 0) {
754 host->mmc->actual_clock = 0;
755 return;
756 }
757
758 /* For i.MX53 eSDHCv3, SYSCTL.SDCLKFS may not be set to 0. */
759 if (is_imx53_esdhc(imx_data)) {
760 /*
761 * According to the i.MX53 reference manual, if DLLCTRL[10] can
762 * be set, then the controller is eSDHCv3, else it is eSDHCv2.
763 */
764 val = readl(host->ioaddr + ESDHC_DLL_CTRL);
765 writel(val | BIT(10), host->ioaddr + ESDHC_DLL_CTRL);
766 temp = readl(host->ioaddr + ESDHC_DLL_CTRL);
767 writel(val, host->ioaddr + ESDHC_DLL_CTRL);
768 if (temp & BIT(10))
769 pre_div = 2;
770 }
771
772 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
773 temp &= ~(ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN
774 | ESDHC_CLOCK_MASK);
775 sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
776
777 if (imx_data->socdata->flags & ESDHC_FLAG_ERR010450) {
778 unsigned int max_clock;
779
780 max_clock = imx_data->is_ddr ? 45000000 : 150000000;
781
782 clock = min(clock, max_clock);
783 }
784
785 while (host_clock / (16 * pre_div * ddr_pre_div) > clock &&
786 pre_div < 256)
787 pre_div *= 2;
788
789 while (host_clock / (div * pre_div * ddr_pre_div) > clock && div < 16)
790 div++;
791
792 host->mmc->actual_clock = host_clock / (div * pre_div * ddr_pre_div);
793 dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n",
794 clock, host->mmc->actual_clock);
795
796 pre_div >>= 1;
797 div--;
798
799 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
800 temp |= (ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN
801 | (div << ESDHC_DIVIDER_SHIFT)
802 | (pre_div << ESDHC_PREDIV_SHIFT));
803 sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
804
805 if (esdhc_is_usdhc(imx_data)) {
806 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
807 writel(val | ESDHC_VENDOR_SPEC_FRC_SDCLK_ON,
808 host->ioaddr + ESDHC_VENDOR_SPEC);
809 }
810
811 mdelay(1);
812 }
813
814 static unsigned int esdhc_pltfm_get_ro(struct sdhci_host *host)
815 {
816 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
817 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
818 struct esdhc_platform_data *boarddata = &imx_data->boarddata;
819
820 switch (boarddata->wp_type) {
821 case ESDHC_WP_GPIO:
822 return mmc_gpio_get_ro(host->mmc);
823 case ESDHC_WP_CONTROLLER:
824 return !(readl(host->ioaddr + SDHCI_PRESENT_STATE) &
825 SDHCI_WRITE_PROTECT);
826 case ESDHC_WP_NONE:
827 break;
828 }
829
830 return -ENOSYS;
831 }
832
833 static void esdhc_pltfm_set_bus_width(struct sdhci_host *host, int width)
834 {
835 u32 ctrl;
836
837 switch (width) {
838 case MMC_BUS_WIDTH_8:
839 ctrl = ESDHC_CTRL_8BITBUS;
840 break;
841 case MMC_BUS_WIDTH_4:
842 ctrl = ESDHC_CTRL_4BITBUS;
843 break;
844 default:
845 ctrl = 0;
846 break;
847 }
848
849 esdhc_clrset_le(host, ESDHC_CTRL_BUSWIDTH_MASK, ctrl,
850 SDHCI_HOST_CONTROL);
851 }
852
853 static int usdhc_execute_tuning(struct mmc_host *mmc, u32 opcode)
854 {
855 struct sdhci_host *host = mmc_priv(mmc);
856
857 /*
858 * i.MX uSDHC internally already uses a fixed optimized timing for
859 * DDR50, normally does not require tuning for DDR50 mode.
860 */
861 if (host->timing == MMC_TIMING_UHS_DDR50)
862 return 0;
863
864 return sdhci_execute_tuning(mmc, opcode);
865 }
866
867 static void esdhc_prepare_tuning(struct sdhci_host *host, u32 val)
868 {
869 u32 reg;
870
871 /* FIXME: delay a bit for card to be ready for next tuning due to errors */
872 mdelay(1);
873
874 reg = readl(host->ioaddr + ESDHC_MIX_CTRL);
875 reg |= ESDHC_MIX_CTRL_EXE_TUNE | ESDHC_MIX_CTRL_SMPCLK_SEL |
876 ESDHC_MIX_CTRL_FBCLK_SEL;
877 writel(reg, host->ioaddr + ESDHC_MIX_CTRL);
878 writel(val << 8, host->ioaddr + ESDHC_TUNE_CTRL_STATUS);
879 dev_dbg(mmc_dev(host->mmc),
880 "tuning with delay 0x%x ESDHC_TUNE_CTRL_STATUS 0x%x\n",
881 val, readl(host->ioaddr + ESDHC_TUNE_CTRL_STATUS));
882 }
883
884 static void esdhc_post_tuning(struct sdhci_host *host)
885 {
886 u32 reg;
887
888 reg = readl(host->ioaddr + ESDHC_MIX_CTRL);
889 reg &= ~ESDHC_MIX_CTRL_EXE_TUNE;
890 reg |= ESDHC_MIX_CTRL_AUTO_TUNE_EN;
891 writel(reg, host->ioaddr + ESDHC_MIX_CTRL);
892 }
893
894 static int esdhc_executing_tuning(struct sdhci_host *host, u32 opcode)
895 {
896 int min, max, avg, ret;
897
898 /* find the mininum delay first which can pass tuning */
899 min = ESDHC_TUNE_CTRL_MIN;
900 while (min < ESDHC_TUNE_CTRL_MAX) {
901 esdhc_prepare_tuning(host, min);
902 if (!mmc_send_tuning(host->mmc, opcode, NULL))
903 break;
904 min += ESDHC_TUNE_CTRL_STEP;
905 }
906
907 /* find the maxinum delay which can not pass tuning */
908 max = min + ESDHC_TUNE_CTRL_STEP;
909 while (max < ESDHC_TUNE_CTRL_MAX) {
910 esdhc_prepare_tuning(host, max);
911 if (mmc_send_tuning(host->mmc, opcode, NULL)) {
912 max -= ESDHC_TUNE_CTRL_STEP;
913 break;
914 }
915 max += ESDHC_TUNE_CTRL_STEP;
916 }
917
918 /* use average delay to get the best timing */
919 avg = (min + max) / 2;
920 esdhc_prepare_tuning(host, avg);
921 ret = mmc_send_tuning(host->mmc, opcode, NULL);
922 esdhc_post_tuning(host);
923
924 dev_dbg(mmc_dev(host->mmc), "tuning %s at 0x%x ret %d\n",
925 ret ? "failed" : "passed", avg, ret);
926
927 return ret;
928 }
929
930 static void esdhc_hs400_enhanced_strobe(struct mmc_host *mmc, struct mmc_ios *ios)
931 {
932 struct sdhci_host *host = mmc_priv(mmc);
933 u32 m;
934
935 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
936 if (ios->enhanced_strobe)
937 m |= ESDHC_MIX_CTRL_HS400_ES_EN;
938 else
939 m &= ~ESDHC_MIX_CTRL_HS400_ES_EN;
940 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
941 }
942
943 static int esdhc_change_pinstate(struct sdhci_host *host,
944 unsigned int uhs)
945 {
946 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
947 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
948 struct pinctrl_state *pinctrl;
949
950 dev_dbg(mmc_dev(host->mmc), "change pinctrl state for uhs %d\n", uhs);
951
952 if (IS_ERR(imx_data->pinctrl) ||
953 IS_ERR(imx_data->pins_100mhz) ||
954 IS_ERR(imx_data->pins_200mhz))
955 return -EINVAL;
956
957 switch (uhs) {
958 case MMC_TIMING_UHS_SDR50:
959 case MMC_TIMING_UHS_DDR50:
960 pinctrl = imx_data->pins_100mhz;
961 break;
962 case MMC_TIMING_UHS_SDR104:
963 case MMC_TIMING_MMC_HS200:
964 case MMC_TIMING_MMC_HS400:
965 pinctrl = imx_data->pins_200mhz;
966 break;
967 default:
968 /* back to default state for other legacy timing */
969 return pinctrl_select_default_state(mmc_dev(host->mmc));
970 }
971
972 return pinctrl_select_state(imx_data->pinctrl, pinctrl);
973 }
974
975 /*
976 * For HS400 eMMC, there is a data_strobe line. This signal is generated
977 * by the device and used for data output and CRC status response output
978 * in HS400 mode. The frequency of this signal follows the frequency of
979 * CLK generated by host. The host receives the data which is aligned to the
980 * edge of data_strobe line. Due to the time delay between CLK line and
981 * data_strobe line, if the delay time is larger than one clock cycle,
982 * then CLK and data_strobe line will be misaligned, read error shows up.
983 */
984 static void esdhc_set_strobe_dll(struct sdhci_host *host)
985 {
986 u32 v;
987
988 /* disable clock before enabling strobe dll */
989 writel(readl(host->ioaddr + ESDHC_VENDOR_SPEC) &
990 ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON,
991 host->ioaddr + ESDHC_VENDOR_SPEC);
992
993 /* force a reset on strobe dll */
994 writel(ESDHC_STROBE_DLL_CTRL_RESET,
995 host->ioaddr + ESDHC_STROBE_DLL_CTRL);
996 /* clear the reset bit on strobe dll before any setting */
997 writel(0, host->ioaddr + ESDHC_STROBE_DLL_CTRL);
998
999 /*
1000 * enable strobe dll ctrl and adjust the delay target
1001 * for the uSDHC loopback read clock
1002 */
1003 v = ESDHC_STROBE_DLL_CTRL_ENABLE |
1004 ESDHC_STROBE_DLL_CTRL_SLV_UPDATE_INT_DEFAULT |
1005 (7 << ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT);
1006 writel(v, host->ioaddr + ESDHC_STROBE_DLL_CTRL);
1007 /* wait 5us to make sure strobe dll status register stable */
1008 udelay(5);
1009 v = readl(host->ioaddr + ESDHC_STROBE_DLL_STATUS);
1010 if (!(v & ESDHC_STROBE_DLL_STS_REF_LOCK))
1011 dev_warn(mmc_dev(host->mmc),
1012 "warning! HS400 strobe DLL status REF not lock!\n");
1013 if (!(v & ESDHC_STROBE_DLL_STS_SLV_LOCK))
1014 dev_warn(mmc_dev(host->mmc),
1015 "warning! HS400 strobe DLL status SLV not lock!\n");
1016 }
1017
1018 static void esdhc_reset_tuning(struct sdhci_host *host)
1019 {
1020 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1021 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1022 u32 ctrl;
1023
1024 /* Reset the tuning circuit */
1025 if (esdhc_is_usdhc(imx_data)) {
1026 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) {
1027 ctrl = readl(host->ioaddr + ESDHC_MIX_CTRL);
1028 ctrl &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
1029 ctrl &= ~ESDHC_MIX_CTRL_FBCLK_SEL;
1030 writel(ctrl, host->ioaddr + ESDHC_MIX_CTRL);
1031 writel(0, host->ioaddr + ESDHC_TUNE_CTRL_STATUS);
1032 } else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) {
1033 ctrl = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS);
1034 ctrl &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
1035 writel(ctrl, host->ioaddr + SDHCI_AUTO_CMD_STATUS);
1036 }
1037 }
1038 }
1039
1040 static void esdhc_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
1041 {
1042 u32 m;
1043 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1044 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1045 struct esdhc_platform_data *boarddata = &imx_data->boarddata;
1046
1047 /* disable ddr mode and disable HS400 mode */
1048 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
1049 m &= ~(ESDHC_MIX_CTRL_DDREN | ESDHC_MIX_CTRL_HS400_EN);
1050 imx_data->is_ddr = 0;
1051
1052 switch (timing) {
1053 case MMC_TIMING_UHS_SDR12:
1054 case MMC_TIMING_UHS_SDR25:
1055 case MMC_TIMING_UHS_SDR50:
1056 case MMC_TIMING_UHS_SDR104:
1057 case MMC_TIMING_MMC_HS:
1058 case MMC_TIMING_MMC_HS200:
1059 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
1060 break;
1061 case MMC_TIMING_UHS_DDR50:
1062 case MMC_TIMING_MMC_DDR52:
1063 m |= ESDHC_MIX_CTRL_DDREN;
1064 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
1065 imx_data->is_ddr = 1;
1066 if (boarddata->delay_line) {
1067 u32 v;
1068 v = boarddata->delay_line <<
1069 ESDHC_DLL_OVERRIDE_VAL_SHIFT |
1070 (1 << ESDHC_DLL_OVERRIDE_EN_SHIFT);
1071 if (is_imx53_esdhc(imx_data))
1072 v <<= 1;
1073 writel(v, host->ioaddr + ESDHC_DLL_CTRL);
1074 }
1075 break;
1076 case MMC_TIMING_MMC_HS400:
1077 m |= ESDHC_MIX_CTRL_DDREN | ESDHC_MIX_CTRL_HS400_EN;
1078 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
1079 imx_data->is_ddr = 1;
1080 /* update clock after enable DDR for strobe DLL lock */
1081 host->ops->set_clock(host, host->clock);
1082 esdhc_set_strobe_dll(host);
1083 break;
1084 case MMC_TIMING_LEGACY:
1085 default:
1086 esdhc_reset_tuning(host);
1087 break;
1088 }
1089
1090 esdhc_change_pinstate(host, timing);
1091 }
1092
1093 static void esdhc_reset(struct sdhci_host *host, u8 mask)
1094 {
1095 sdhci_reset(host, mask);
1096
1097 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1098 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
1099 }
1100
1101 static unsigned int esdhc_get_max_timeout_count(struct sdhci_host *host)
1102 {
1103 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1104 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1105
1106 /* Doc Erratum: the uSDHC actual maximum timeout count is 1 << 29 */
1107 return esdhc_is_usdhc(imx_data) ? 1 << 29 : 1 << 27;
1108 }
1109
1110 static void esdhc_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
1111 {
1112 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1113 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1114
1115 /* use maximum timeout counter */
1116 esdhc_clrset_le(host, ESDHC_SYS_CTRL_DTOCV_MASK,
1117 esdhc_is_usdhc(imx_data) ? 0xF : 0xE,
1118 SDHCI_TIMEOUT_CONTROL);
1119 }
1120
1121 static u32 esdhc_cqhci_irq(struct sdhci_host *host, u32 intmask)
1122 {
1123 int cmd_error = 0;
1124 int data_error = 0;
1125
1126 if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error))
1127 return intmask;
1128
1129 cqhci_irq(host->mmc, intmask, cmd_error, data_error);
1130
1131 return 0;
1132 }
1133
1134 static struct sdhci_ops sdhci_esdhc_ops = {
1135 .read_l = esdhc_readl_le,
1136 .read_w = esdhc_readw_le,
1137 .read_b = esdhc_readb_le,
1138 .write_l = esdhc_writel_le,
1139 .write_w = esdhc_writew_le,
1140 .write_b = esdhc_writeb_le,
1141 .set_clock = esdhc_pltfm_set_clock,
1142 .get_max_clock = esdhc_pltfm_get_max_clock,
1143 .get_min_clock = esdhc_pltfm_get_min_clock,
1144 .get_max_timeout_count = esdhc_get_max_timeout_count,
1145 .get_ro = esdhc_pltfm_get_ro,
1146 .set_timeout = esdhc_set_timeout,
1147 .set_bus_width = esdhc_pltfm_set_bus_width,
1148 .set_uhs_signaling = esdhc_set_uhs_signaling,
1149 .reset = esdhc_reset,
1150 .irq = esdhc_cqhci_irq,
1151 };
1152
1153 static const struct sdhci_pltfm_data sdhci_esdhc_imx_pdata = {
1154 .quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_NO_HISPD_BIT
1155 | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC
1156 | SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC
1157 | SDHCI_QUIRK_BROKEN_CARD_DETECTION,
1158 .ops = &sdhci_esdhc_ops,
1159 };
1160
1161 static void sdhci_esdhc_imx_hwinit(struct sdhci_host *host)
1162 {
1163 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1164 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1165 int tmp;
1166
1167 if (esdhc_is_usdhc(imx_data)) {
1168 /*
1169 * The imx6q ROM code will change the default watermark
1170 * level setting to something insane. Change it back here.
1171 */
1172 writel(ESDHC_WTMK_DEFAULT_VAL, host->ioaddr + ESDHC_WTMK_LVL);
1173
1174 /*
1175 * ROM code will change the bit burst_length_enable setting
1176 * to zero if this usdhc is chosen to boot system. Change
1177 * it back here, otherwise it will impact the performance a
1178 * lot. This bit is used to enable/disable the burst length
1179 * for the external AHB2AXI bridge. It's useful especially
1180 * for INCR transfer because without burst length indicator,
1181 * the AHB2AXI bridge does not know the burst length in
1182 * advance. And without burst length indicator, AHB INCR
1183 * transfer can only be converted to singles on the AXI side.
1184 */
1185 writel(readl(host->ioaddr + SDHCI_HOST_CONTROL)
1186 | ESDHC_BURST_LEN_EN_INCR,
1187 host->ioaddr + SDHCI_HOST_CONTROL);
1188
1189 /*
1190 * erratum ESDHC_FLAG_ERR004536 fix for MX6Q TO1.2 and MX6DL
1191 * TO1.1, it's harmless for MX6SL
1192 */
1193 writel(readl(host->ioaddr + 0x6c) & ~BIT(7),
1194 host->ioaddr + 0x6c);
1195
1196 /* disable DLL_CTRL delay line settings */
1197 writel(0x0, host->ioaddr + ESDHC_DLL_CTRL);
1198
1199 /*
1200 * For the case of command with busy, if set the bit
1201 * ESDHC_VEND_SPEC2_EN_BUSY_IRQ, USDHC will generate a
1202 * transfer complete interrupt when busy is deasserted.
1203 * When CQHCI use DCMD to send a CMD need R1b respons,
1204 * CQHCI require to set ESDHC_VEND_SPEC2_EN_BUSY_IRQ,
1205 * otherwise DCMD will always meet timeout waiting for
1206 * hardware interrupt issue.
1207 */
1208 if (imx_data->socdata->flags & ESDHC_FLAG_CQHCI) {
1209 tmp = readl(host->ioaddr + ESDHC_VEND_SPEC2);
1210 tmp |= ESDHC_VEND_SPEC2_EN_BUSY_IRQ;
1211 writel(tmp, host->ioaddr + ESDHC_VEND_SPEC2);
1212
1213 host->quirks &= ~SDHCI_QUIRK_NO_BUSY_IRQ;
1214 }
1215
1216 if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) {
1217 tmp = readl(host->ioaddr + ESDHC_TUNING_CTRL);
1218 tmp |= ESDHC_STD_TUNING_EN |
1219 ESDHC_TUNING_START_TAP_DEFAULT;
1220 if (imx_data->boarddata.tuning_start_tap) {
1221 tmp &= ~ESDHC_TUNING_START_TAP_MASK;
1222 tmp |= imx_data->boarddata.tuning_start_tap;
1223 }
1224
1225 if (imx_data->boarddata.tuning_step) {
1226 tmp &= ~ESDHC_TUNING_STEP_MASK;
1227 tmp |= imx_data->boarddata.tuning_step
1228 << ESDHC_TUNING_STEP_SHIFT;
1229 }
1230 writel(tmp, host->ioaddr + ESDHC_TUNING_CTRL);
1231 } else if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) {
1232 /*
1233 * ESDHC_STD_TUNING_EN may be configed in bootloader
1234 * or ROM code, so clear this bit here to make sure
1235 * the manual tuning can work.
1236 */
1237 tmp = readl(host->ioaddr + ESDHC_TUNING_CTRL);
1238 tmp &= ~ESDHC_STD_TUNING_EN;
1239 writel(tmp, host->ioaddr + ESDHC_TUNING_CTRL);
1240 }
1241 }
1242 }
1243
1244 static void esdhc_cqe_enable(struct mmc_host *mmc)
1245 {
1246 struct sdhci_host *host = mmc_priv(mmc);
1247 struct cqhci_host *cq_host = mmc->cqe_private;
1248 u32 reg;
1249 u16 mode;
1250 int count = 10;
1251
1252 /*
1253 * CQE gets stuck if it sees Buffer Read Enable bit set, which can be
1254 * the case after tuning, so ensure the buffer is drained.
1255 */
1256 reg = sdhci_readl(host, SDHCI_PRESENT_STATE);
1257 while (reg & SDHCI_DATA_AVAILABLE) {
1258 sdhci_readl(host, SDHCI_BUFFER);
1259 reg = sdhci_readl(host, SDHCI_PRESENT_STATE);
1260 if (count-- == 0) {
1261 dev_warn(mmc_dev(host->mmc),
1262 "CQE may get stuck because the Buffer Read Enable bit is set\n");
1263 break;
1264 }
1265 mdelay(1);
1266 }
1267
1268 /*
1269 * Runtime resume will reset the entire host controller, which
1270 * will also clear the DMAEN/BCEN of register ESDHC_MIX_CTRL.
1271 * Here set DMAEN and BCEN when enable CMDQ.
1272 */
1273 mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
1274 if (host->flags & SDHCI_REQ_USE_DMA)
1275 mode |= SDHCI_TRNS_DMA;
1276 if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE))
1277 mode |= SDHCI_TRNS_BLK_CNT_EN;
1278 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
1279
1280 /*
1281 * Though Runtime resume reset the entire host controller,
1282 * but do not impact the CQHCI side, need to clear the
1283 * HALT bit, avoid CQHCI stuck in the first request when
1284 * system resume back.
1285 */
1286 cqhci_writel(cq_host, 0, CQHCI_CTL);
1287 if (cqhci_readl(cq_host, CQHCI_CTL) && CQHCI_HALT)
1288 dev_err(mmc_dev(host->mmc),
1289 "failed to exit halt state when enable CQE\n");
1290
1291
1292 sdhci_cqe_enable(mmc);
1293 }
1294
1295 static void esdhc_sdhci_dumpregs(struct mmc_host *mmc)
1296 {
1297 sdhci_dumpregs(mmc_priv(mmc));
1298 }
1299
1300 static const struct cqhci_host_ops esdhc_cqhci_ops = {
1301 .enable = esdhc_cqe_enable,
1302 .disable = sdhci_cqe_disable,
1303 .dumpregs = esdhc_sdhci_dumpregs,
1304 };
1305
1306 #ifdef CONFIG_OF
1307 static int
1308 sdhci_esdhc_imx_probe_dt(struct platform_device *pdev,
1309 struct sdhci_host *host,
1310 struct pltfm_imx_data *imx_data)
1311 {
1312 struct device_node *np = pdev->dev.of_node;
1313 struct esdhc_platform_data *boarddata = &imx_data->boarddata;
1314 int ret;
1315
1316 if (of_get_property(np, "fsl,wp-controller", NULL))
1317 boarddata->wp_type = ESDHC_WP_CONTROLLER;
1318
1319 /*
1320 * If we have this property, then activate WP check.
1321 * Retrieveing and requesting the actual WP GPIO will happen
1322 * in the call to mmc_of_parse().
1323 */
1324 if (of_property_read_bool(np, "wp-gpios"))
1325 boarddata->wp_type = ESDHC_WP_GPIO;
1326
1327 of_property_read_u32(np, "fsl,tuning-step", &boarddata->tuning_step);
1328 of_property_read_u32(np, "fsl,tuning-start-tap",
1329 &boarddata->tuning_start_tap);
1330
1331 if (of_find_property(np, "no-1-8-v", NULL))
1332 host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V;
1333
1334 if (of_property_read_u32(np, "fsl,delay-line", &boarddata->delay_line))
1335 boarddata->delay_line = 0;
1336
1337 mmc_of_parse_voltage(np, &host->ocr_mask);
1338
1339 if (esdhc_is_usdhc(imx_data)) {
1340 imx_data->pins_100mhz = pinctrl_lookup_state(imx_data->pinctrl,
1341 ESDHC_PINCTRL_STATE_100MHZ);
1342 imx_data->pins_200mhz = pinctrl_lookup_state(imx_data->pinctrl,
1343 ESDHC_PINCTRL_STATE_200MHZ);
1344 }
1345
1346 /* call to generic mmc_of_parse to support additional capabilities */
1347 ret = mmc_of_parse(host->mmc);
1348 if (ret)
1349 return ret;
1350
1351 if (mmc_gpio_get_cd(host->mmc) >= 0)
1352 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
1353
1354 return 0;
1355 }
1356 #else
1357 static inline int
1358 sdhci_esdhc_imx_probe_dt(struct platform_device *pdev,
1359 struct sdhci_host *host,
1360 struct pltfm_imx_data *imx_data)
1361 {
1362 return -ENODEV;
1363 }
1364 #endif
1365
1366 static int sdhci_esdhc_imx_probe_nondt(struct platform_device *pdev,
1367 struct sdhci_host *host,
1368 struct pltfm_imx_data *imx_data)
1369 {
1370 struct esdhc_platform_data *boarddata = &imx_data->boarddata;
1371 int err;
1372
1373 if (!host->mmc->parent->platform_data) {
1374 dev_err(mmc_dev(host->mmc), "no board data!\n");
1375 return -EINVAL;
1376 }
1377
1378 imx_data->boarddata = *((struct esdhc_platform_data *)
1379 host->mmc->parent->platform_data);
1380 /* write_protect */
1381 if (boarddata->wp_type == ESDHC_WP_GPIO) {
1382 host->mmc->caps2 |= MMC_CAP2_RO_ACTIVE_HIGH;
1383
1384 err = mmc_gpiod_request_ro(host->mmc, "wp", 0, 0);
1385 if (err) {
1386 dev_err(mmc_dev(host->mmc),
1387 "failed to request write-protect gpio!\n");
1388 return err;
1389 }
1390 }
1391
1392 /* card_detect */
1393 switch (boarddata->cd_type) {
1394 case ESDHC_CD_GPIO:
1395 err = mmc_gpiod_request_cd(host->mmc, "cd", 0, false, 0);
1396 if (err) {
1397 dev_err(mmc_dev(host->mmc),
1398 "failed to request card-detect gpio!\n");
1399 return err;
1400 }
1401 /* fall through */
1402
1403 case ESDHC_CD_CONTROLLER:
1404 /* we have a working card_detect back */
1405 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
1406 break;
1407
1408 case ESDHC_CD_PERMANENT:
1409 host->mmc->caps |= MMC_CAP_NONREMOVABLE;
1410 break;
1411
1412 case ESDHC_CD_NONE:
1413 break;
1414 }
1415
1416 switch (boarddata->max_bus_width) {
1417 case 8:
1418 host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA;
1419 break;
1420 case 4:
1421 host->mmc->caps |= MMC_CAP_4_BIT_DATA;
1422 break;
1423 case 1:
1424 default:
1425 host->quirks |= SDHCI_QUIRK_FORCE_1_BIT_DATA;
1426 break;
1427 }
1428
1429 return 0;
1430 }
1431
1432 static int sdhci_esdhc_imx_probe(struct platform_device *pdev)
1433 {
1434 const struct of_device_id *of_id =
1435 of_match_device(imx_esdhc_dt_ids, &pdev->dev);
1436 struct sdhci_pltfm_host *pltfm_host;
1437 struct sdhci_host *host;
1438 struct cqhci_host *cq_host;
1439 int err;
1440 struct pltfm_imx_data *imx_data;
1441
1442 host = sdhci_pltfm_init(pdev, &sdhci_esdhc_imx_pdata,
1443 sizeof(*imx_data));
1444 if (IS_ERR(host))
1445 return PTR_ERR(host);
1446
1447 pltfm_host = sdhci_priv(host);
1448
1449 imx_data = sdhci_pltfm_priv(pltfm_host);
1450
1451 imx_data->socdata = of_id ? of_id->data : (struct esdhc_soc_data *)
1452 pdev->id_entry->driver_data;
1453
1454 if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS)
1455 pm_qos_add_request(&imx_data->pm_qos_req,
1456 PM_QOS_CPU_DMA_LATENCY, 0);
1457
1458 imx_data->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1459 if (IS_ERR(imx_data->clk_ipg)) {
1460 err = PTR_ERR(imx_data->clk_ipg);
1461 goto free_sdhci;
1462 }
1463
1464 imx_data->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
1465 if (IS_ERR(imx_data->clk_ahb)) {
1466 err = PTR_ERR(imx_data->clk_ahb);
1467 goto free_sdhci;
1468 }
1469
1470 imx_data->clk_per = devm_clk_get(&pdev->dev, "per");
1471 if (IS_ERR(imx_data->clk_per)) {
1472 err = PTR_ERR(imx_data->clk_per);
1473 goto free_sdhci;
1474 }
1475
1476 pltfm_host->clk = imx_data->clk_per;
1477 pltfm_host->clock = clk_get_rate(pltfm_host->clk);
1478 err = clk_prepare_enable(imx_data->clk_per);
1479 if (err)
1480 goto free_sdhci;
1481 err = clk_prepare_enable(imx_data->clk_ipg);
1482 if (err)
1483 goto disable_per_clk;
1484 err = clk_prepare_enable(imx_data->clk_ahb);
1485 if (err)
1486 goto disable_ipg_clk;
1487
1488 imx_data->pinctrl = devm_pinctrl_get(&pdev->dev);
1489 if (IS_ERR(imx_data->pinctrl)) {
1490 err = PTR_ERR(imx_data->pinctrl);
1491 goto disable_ahb_clk;
1492 }
1493
1494 if (esdhc_is_usdhc(imx_data)) {
1495 host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN;
1496 host->mmc->caps |= MMC_CAP_1_8V_DDR | MMC_CAP_3_3V_DDR;
1497 if (!(imx_data->socdata->flags & ESDHC_FLAG_HS200))
1498 host->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200;
1499
1500 /* clear tuning bits in case ROM has set it already */
1501 writel(0x0, host->ioaddr + ESDHC_MIX_CTRL);
1502 writel(0x0, host->ioaddr + SDHCI_AUTO_CMD_STATUS);
1503 writel(0x0, host->ioaddr + ESDHC_TUNE_CTRL_STATUS);
1504
1505 /*
1506 * Link usdhc specific mmc_host_ops execute_tuning function,
1507 * to replace the standard one in sdhci_ops.
1508 */
1509 host->mmc_host_ops.execute_tuning = usdhc_execute_tuning;
1510 }
1511
1512 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING)
1513 sdhci_esdhc_ops.platform_execute_tuning =
1514 esdhc_executing_tuning;
1515
1516 if (imx_data->socdata->flags & ESDHC_FLAG_ERR004536)
1517 host->quirks |= SDHCI_QUIRK_BROKEN_ADMA;
1518
1519 if (imx_data->socdata->flags & ESDHC_FLAG_HS400)
1520 host->quirks2 |= SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400;
1521
1522 if (imx_data->socdata->flags & ESDHC_FLAG_HS400_ES) {
1523 host->mmc->caps2 |= MMC_CAP2_HS400_ES;
1524 host->mmc_host_ops.hs400_enhanced_strobe =
1525 esdhc_hs400_enhanced_strobe;
1526 }
1527
1528 if (imx_data->socdata->flags & ESDHC_FLAG_CQHCI) {
1529 host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD;
1530 cq_host = devm_kzalloc(&pdev->dev, sizeof(*cq_host), GFP_KERNEL);
1531 if (!cq_host) {
1532 err = -ENOMEM;
1533 goto disable_ahb_clk;
1534 }
1535
1536 cq_host->mmio = host->ioaddr + ESDHC_CQHCI_ADDR_OFFSET;
1537 cq_host->ops = &esdhc_cqhci_ops;
1538
1539 err = cqhci_init(cq_host, host->mmc, false);
1540 if (err)
1541 goto disable_ahb_clk;
1542 }
1543
1544 if (of_id)
1545 err = sdhci_esdhc_imx_probe_dt(pdev, host, imx_data);
1546 else
1547 err = sdhci_esdhc_imx_probe_nondt(pdev, host, imx_data);
1548 if (err)
1549 goto disable_ahb_clk;
1550
1551 host->tuning_delay = 1;
1552
1553 sdhci_esdhc_imx_hwinit(host);
1554
1555 err = sdhci_add_host(host);
1556 if (err)
1557 goto disable_ahb_clk;
1558
1559 pm_runtime_set_active(&pdev->dev);
1560 pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
1561 pm_runtime_use_autosuspend(&pdev->dev);
1562 pm_suspend_ignore_children(&pdev->dev, 1);
1563 pm_runtime_enable(&pdev->dev);
1564
1565 return 0;
1566
1567 disable_ahb_clk:
1568 clk_disable_unprepare(imx_data->clk_ahb);
1569 disable_ipg_clk:
1570 clk_disable_unprepare(imx_data->clk_ipg);
1571 disable_per_clk:
1572 clk_disable_unprepare(imx_data->clk_per);
1573 free_sdhci:
1574 if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS)
1575 pm_qos_remove_request(&imx_data->pm_qos_req);
1576 sdhci_pltfm_free(pdev);
1577 return err;
1578 }
1579
1580 static int sdhci_esdhc_imx_remove(struct platform_device *pdev)
1581 {
1582 struct sdhci_host *host = platform_get_drvdata(pdev);
1583 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1584 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1585 int dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff);
1586
1587 pm_runtime_get_sync(&pdev->dev);
1588 pm_runtime_disable(&pdev->dev);
1589 pm_runtime_put_noidle(&pdev->dev);
1590
1591 sdhci_remove_host(host, dead);
1592
1593 clk_disable_unprepare(imx_data->clk_per);
1594 clk_disable_unprepare(imx_data->clk_ipg);
1595 clk_disable_unprepare(imx_data->clk_ahb);
1596
1597 if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS)
1598 pm_qos_remove_request(&imx_data->pm_qos_req);
1599
1600 sdhci_pltfm_free(pdev);
1601
1602 return 0;
1603 }
1604
1605 #ifdef CONFIG_PM_SLEEP
1606 static int sdhci_esdhc_suspend(struct device *dev)
1607 {
1608 struct sdhci_host *host = dev_get_drvdata(dev);
1609 int ret;
1610
1611 if (host->mmc->caps2 & MMC_CAP2_CQE) {
1612 ret = cqhci_suspend(host->mmc);
1613 if (ret)
1614 return ret;
1615 }
1616
1617 if (host->tuning_mode != SDHCI_TUNING_MODE_3)
1618 mmc_retune_needed(host->mmc);
1619
1620 return sdhci_suspend_host(host);
1621 }
1622
1623 static int sdhci_esdhc_resume(struct device *dev)
1624 {
1625 struct sdhci_host *host = dev_get_drvdata(dev);
1626 int ret;
1627
1628 /* re-initialize hw state in case it's lost in low power mode */
1629 sdhci_esdhc_imx_hwinit(host);
1630
1631 ret = sdhci_resume_host(host);
1632 if (ret)
1633 return ret;
1634
1635 if (host->mmc->caps2 & MMC_CAP2_CQE)
1636 ret = cqhci_resume(host->mmc);
1637
1638 return ret;
1639 }
1640 #endif
1641
1642 #ifdef CONFIG_PM
1643 static int sdhci_esdhc_runtime_suspend(struct device *dev)
1644 {
1645 struct sdhci_host *host = dev_get_drvdata(dev);
1646 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1647 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1648 int ret;
1649
1650 if (host->mmc->caps2 & MMC_CAP2_CQE) {
1651 ret = cqhci_suspend(host->mmc);
1652 if (ret)
1653 return ret;
1654 }
1655
1656 ret = sdhci_runtime_suspend_host(host);
1657 if (ret)
1658 return ret;
1659
1660 if (host->tuning_mode != SDHCI_TUNING_MODE_3)
1661 mmc_retune_needed(host->mmc);
1662
1663 imx_data->actual_clock = host->mmc->actual_clock;
1664 esdhc_pltfm_set_clock(host, 0);
1665 clk_disable_unprepare(imx_data->clk_per);
1666 clk_disable_unprepare(imx_data->clk_ipg);
1667 clk_disable_unprepare(imx_data->clk_ahb);
1668
1669 if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS)
1670 pm_qos_remove_request(&imx_data->pm_qos_req);
1671
1672 return ret;
1673 }
1674
1675 static int sdhci_esdhc_runtime_resume(struct device *dev)
1676 {
1677 struct sdhci_host *host = dev_get_drvdata(dev);
1678 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1679 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1680 int err;
1681
1682 if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS)
1683 pm_qos_add_request(&imx_data->pm_qos_req,
1684 PM_QOS_CPU_DMA_LATENCY, 0);
1685
1686 err = clk_prepare_enable(imx_data->clk_ahb);
1687 if (err)
1688 goto remove_pm_qos_request;
1689
1690 err = clk_prepare_enable(imx_data->clk_per);
1691 if (err)
1692 goto disable_ahb_clk;
1693
1694 err = clk_prepare_enable(imx_data->clk_ipg);
1695 if (err)
1696 goto disable_per_clk;
1697
1698 esdhc_pltfm_set_clock(host, imx_data->actual_clock);
1699
1700 err = sdhci_runtime_resume_host(host, 0);
1701 if (err)
1702 goto disable_ipg_clk;
1703
1704 if (host->mmc->caps2 & MMC_CAP2_CQE)
1705 err = cqhci_resume(host->mmc);
1706
1707 return err;
1708
1709 disable_ipg_clk:
1710 clk_disable_unprepare(imx_data->clk_ipg);
1711 disable_per_clk:
1712 clk_disable_unprepare(imx_data->clk_per);
1713 disable_ahb_clk:
1714 clk_disable_unprepare(imx_data->clk_ahb);
1715 remove_pm_qos_request:
1716 if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS)
1717 pm_qos_remove_request(&imx_data->pm_qos_req);
1718 return err;
1719 }
1720 #endif
1721
1722 static const struct dev_pm_ops sdhci_esdhc_pmops = {
1723 SET_SYSTEM_SLEEP_PM_OPS(sdhci_esdhc_suspend, sdhci_esdhc_resume)
1724 SET_RUNTIME_PM_OPS(sdhci_esdhc_runtime_suspend,
1725 sdhci_esdhc_runtime_resume, NULL)
1726 };
1727
1728 static struct platform_driver sdhci_esdhc_imx_driver = {
1729 .driver = {
1730 .name = "sdhci-esdhc-imx",
1731 .of_match_table = imx_esdhc_dt_ids,
1732 .pm = &sdhci_esdhc_pmops,
1733 },
1734 .id_table = imx_esdhc_devtype,
1735 .probe = sdhci_esdhc_imx_probe,
1736 .remove = sdhci_esdhc_imx_remove,
1737 };
1738
1739 module_platform_driver(sdhci_esdhc_imx_driver);
1740
1741 MODULE_DESCRIPTION("SDHCI driver for Freescale i.MX eSDHC");
1742 MODULE_AUTHOR("Wolfram Sang <kernel@pengutronix.de>");
1743 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support