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treewide: remove redundant IS_ERR() before error code check
[linux/fpc-iii.git] / drivers / mmc / host / sdhci-sprd.c
blobd07b9793380f06b2dac0c1225ce58e71a59f3807
1 // SPDX-License-Identifier: GPL-2.0
2 //
3 // Secure Digital Host Controller
4 //
5 // Copyright (C) 2018 Spreadtrum, Inc.
6 // Author: Chunyan Zhang <chunyan.zhang@unisoc.com>
7
8 #include <linux/delay.h>
9 #include <linux/dma-mapping.h>
10 #include <linux/highmem.h>
11 #include <linux/module.h>
12 #include <linux/of.h>
13 #include <linux/of_device.h>
14 #include <linux/of_gpio.h>
15 #include <linux/pinctrl/consumer.h>
16 #include <linux/platform_device.h>
17 #include <linux/pm_runtime.h>
18 #include <linux/regulator/consumer.h>
19 #include <linux/slab.h>
20
21 #include "sdhci-pltfm.h"
22
23 /* SDHCI_ARGUMENT2 register high 16bit */
24 #define SDHCI_SPRD_ARG2_STUFF GENMASK(31, 16)
25
26 #define SDHCI_SPRD_REG_32_DLL_CFG 0x200
27 #define SDHCI_SPRD_DLL_ALL_CPST_EN (BIT(18) | BIT(24) | BIT(25) | BIT(26) | BIT(27))
28 #define SDHCI_SPRD_DLL_EN BIT(21)
29 #define SDHCI_SPRD_DLL_SEARCH_MODE BIT(16)
30 #define SDHCI_SPRD_DLL_INIT_COUNT 0xc00
31 #define SDHCI_SPRD_DLL_PHASE_INTERNAL 0x3
32
33 #define SDHCI_SPRD_REG_32_DLL_DLY 0x204
34
35 #define SDHCI_SPRD_REG_32_DLL_DLY_OFFSET 0x208
36 #define SDHCIBSPRD_IT_WR_DLY_INV BIT(5)
37 #define SDHCI_SPRD_BIT_CMD_DLY_INV BIT(13)
38 #define SDHCI_SPRD_BIT_POSRD_DLY_INV BIT(21)
39 #define SDHCI_SPRD_BIT_NEGRD_DLY_INV BIT(29)
40
41 #define SDHCI_SPRD_REG_32_BUSY_POSI 0x250
42 #define SDHCI_SPRD_BIT_OUTR_CLK_AUTO_EN BIT(25)
43 #define SDHCI_SPRD_BIT_INNR_CLK_AUTO_EN BIT(24)
44
45 #define SDHCI_SPRD_REG_DEBOUNCE 0x28C
46 #define SDHCI_SPRD_BIT_DLL_BAK BIT(0)
47 #define SDHCI_SPRD_BIT_DLL_VAL BIT(1)
48
49 #define SDHCI_SPRD_INT_SIGNAL_MASK 0x1B7F410B
50
51 /* SDHCI_HOST_CONTROL2 */
52 #define SDHCI_SPRD_CTRL_HS200 0x0005
53 #define SDHCI_SPRD_CTRL_HS400 0x0006
54 #define SDHCI_SPRD_CTRL_HS400ES 0x0007
55
56 /*
57 * According to the standard specification, BIT(3) of SDHCI_SOFTWARE_RESET is
58 * reserved, and only used on Spreadtrum's design, the hardware cannot work
59 * if this bit is cleared.
60 * 1 : normal work
61 * 0 : hardware reset
62 */
63 #define SDHCI_HW_RESET_CARD BIT(3)
64
65 #define SDHCI_SPRD_MAX_CUR 0xFFFFFF
66 #define SDHCI_SPRD_CLK_MAX_DIV 1023
67
68 #define SDHCI_SPRD_CLK_DEF_RATE 26000000
69 #define SDHCI_SPRD_PHY_DLL_CLK 52000000
70
71 struct sdhci_sprd_host {
72 u32 version;
73 struct clk *clk_sdio;
74 struct clk *clk_enable;
75 struct clk *clk_2x_enable;
76 struct pinctrl *pinctrl;
77 struct pinctrl_state *pins_uhs;
78 struct pinctrl_state *pins_default;
79 u32 base_rate;
80 int flags; /* backup of host attribute */
81 u32 phy_delay[MMC_TIMING_MMC_HS400 + 2];
82 };
83
84 struct sdhci_sprd_phy_cfg {
85 const char *property;
86 u8 timing;
87 };
88
89 static const struct sdhci_sprd_phy_cfg sdhci_sprd_phy_cfgs[] = {
90 { "sprd,phy-delay-legacy", MMC_TIMING_LEGACY, },
91 { "sprd,phy-delay-sd-highspeed", MMC_TIMING_SD_HS, },
92 { "sprd,phy-delay-sd-uhs-sdr50", MMC_TIMING_UHS_SDR50, },
93 { "sprd,phy-delay-sd-uhs-sdr104", MMC_TIMING_UHS_SDR104, },
94 { "sprd,phy-delay-mmc-highspeed", MMC_TIMING_MMC_HS, },
95 { "sprd,phy-delay-mmc-ddr52", MMC_TIMING_MMC_DDR52, },
96 { "sprd,phy-delay-mmc-hs200", MMC_TIMING_MMC_HS200, },
97 { "sprd,phy-delay-mmc-hs400", MMC_TIMING_MMC_HS400, },
98 { "sprd,phy-delay-mmc-hs400es", MMC_TIMING_MMC_HS400 + 1, },
99 };
100
101 #define TO_SPRD_HOST(host) sdhci_pltfm_priv(sdhci_priv(host))
102
103 static void sdhci_sprd_init_config(struct sdhci_host *host)
104 {
105 u16 val;
106
107 /* set dll backup mode */
108 val = sdhci_readl(host, SDHCI_SPRD_REG_DEBOUNCE);
109 val |= SDHCI_SPRD_BIT_DLL_BAK | SDHCI_SPRD_BIT_DLL_VAL;
110 sdhci_writel(host, val, SDHCI_SPRD_REG_DEBOUNCE);
111 }
112
113 static inline u32 sdhci_sprd_readl(struct sdhci_host *host, int reg)
114 {
115 if (unlikely(reg == SDHCI_MAX_CURRENT))
116 return SDHCI_SPRD_MAX_CUR;
117
118 return readl_relaxed(host->ioaddr + reg);
119 }
120
121 static inline void sdhci_sprd_writel(struct sdhci_host *host, u32 val, int reg)
122 {
123 /* SDHCI_MAX_CURRENT is reserved on Spreadtrum's platform */
124 if (unlikely(reg == SDHCI_MAX_CURRENT))
125 return;
126
127 if (unlikely(reg == SDHCI_SIGNAL_ENABLE || reg == SDHCI_INT_ENABLE))
128 val = val & SDHCI_SPRD_INT_SIGNAL_MASK;
129
130 writel_relaxed(val, host->ioaddr + reg);
131 }
132
133 static inline void sdhci_sprd_writew(struct sdhci_host *host, u16 val, int reg)
134 {
135 /* SDHCI_BLOCK_COUNT is Read Only on Spreadtrum's platform */
136 if (unlikely(reg == SDHCI_BLOCK_COUNT))
137 return;
138
139 writew_relaxed(val, host->ioaddr + reg);
140 }
141
142 static inline void sdhci_sprd_writeb(struct sdhci_host *host, u8 val, int reg)
143 {
144 /*
145 * Since BIT(3) of SDHCI_SOFTWARE_RESET is reserved according to the
146 * standard specification, sdhci_reset() write this register directly
147 * without checking other reserved bits, that will clear BIT(3) which
148 * is defined as hardware reset on Spreadtrum's platform and clearing
149 * it by mistake will lead the card not work. So here we need to work
150 * around it.
151 */
152 if (unlikely(reg == SDHCI_SOFTWARE_RESET)) {
153 if (readb_relaxed(host->ioaddr + reg) & SDHCI_HW_RESET_CARD)
154 val |= SDHCI_HW_RESET_CARD;
155 }
156
157 writeb_relaxed(val, host->ioaddr + reg);
158 }
159
160 static inline void sdhci_sprd_sd_clk_off(struct sdhci_host *host)
161 {
162 u16 ctrl = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
163
164 ctrl &= ~SDHCI_CLOCK_CARD_EN;
165 sdhci_writew(host, ctrl, SDHCI_CLOCK_CONTROL);
166 }
167
168 static inline void sdhci_sprd_sd_clk_on(struct sdhci_host *host)
169 {
170 u16 ctrl;
171
172 ctrl = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
173 ctrl |= SDHCI_CLOCK_CARD_EN;
174 sdhci_writew(host, ctrl, SDHCI_CLOCK_CONTROL);
175 }
176
177 static inline void
178 sdhci_sprd_set_dll_invert(struct sdhci_host *host, u32 mask, bool en)
179 {
180 u32 dll_dly_offset;
181
182 dll_dly_offset = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_DLY_OFFSET);
183 if (en)
184 dll_dly_offset |= mask;
185 else
186 dll_dly_offset &= ~mask;
187 sdhci_writel(host, dll_dly_offset, SDHCI_SPRD_REG_32_DLL_DLY_OFFSET);
188 }
189
190 static inline u32 sdhci_sprd_calc_div(u32 base_clk, u32 clk)
191 {
192 u32 div;
193
194 /* select 2x clock source */
195 if (base_clk <= clk * 2)
196 return 0;
197
198 div = (u32) (base_clk / (clk * 2));
199
200 if ((base_clk / div) > (clk * 2))
201 div++;
202
203 if (div > SDHCI_SPRD_CLK_MAX_DIV)
204 div = SDHCI_SPRD_CLK_MAX_DIV;
205
206 if (div % 2)
207 div = (div + 1) / 2;
208 else
209 div = div / 2;
210
211 return div;
212 }
213
214 static inline void _sdhci_sprd_set_clock(struct sdhci_host *host,
215 unsigned int clk)
216 {
217 struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
218 u32 div, val, mask;
219
220 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
221
222 div = sdhci_sprd_calc_div(sprd_host->base_rate, clk);
223 div = ((div & 0x300) >> 2) | ((div & 0xFF) << 8);
224 sdhci_enable_clk(host, div);
225
226 /* enable auto gate sdhc_enable_auto_gate */
227 val = sdhci_readl(host, SDHCI_SPRD_REG_32_BUSY_POSI);
228 mask = SDHCI_SPRD_BIT_OUTR_CLK_AUTO_EN |
229 SDHCI_SPRD_BIT_INNR_CLK_AUTO_EN;
230 if (mask != (val & mask)) {
231 val |= mask;
232 sdhci_writel(host, val, SDHCI_SPRD_REG_32_BUSY_POSI);
233 }
234 }
235
236 static void sdhci_sprd_enable_phy_dll(struct sdhci_host *host)
237 {
238 u32 tmp;
239
240 tmp = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_CFG);
241 tmp &= ~(SDHCI_SPRD_DLL_EN | SDHCI_SPRD_DLL_ALL_CPST_EN);
242 sdhci_writel(host, tmp, SDHCI_SPRD_REG_32_DLL_CFG);
243 /* wait 1ms */
244 usleep_range(1000, 1250);
245
246 tmp = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_CFG);
247 tmp |= SDHCI_SPRD_DLL_ALL_CPST_EN | SDHCI_SPRD_DLL_SEARCH_MODE |
248 SDHCI_SPRD_DLL_INIT_COUNT | SDHCI_SPRD_DLL_PHASE_INTERNAL;
249 sdhci_writel(host, tmp, SDHCI_SPRD_REG_32_DLL_CFG);
250 /* wait 1ms */
251 usleep_range(1000, 1250);
252
253 tmp = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_CFG);
254 tmp |= SDHCI_SPRD_DLL_EN;
255 sdhci_writel(host, tmp, SDHCI_SPRD_REG_32_DLL_CFG);
256 /* wait 1ms */
257 usleep_range(1000, 1250);
258 }
259
260 static void sdhci_sprd_set_clock(struct sdhci_host *host, unsigned int clock)
261 {
262 bool en = false, clk_changed = false;
263
264 if (clock == 0) {
265 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
266 } else if (clock != host->clock) {
267 sdhci_sprd_sd_clk_off(host);
268 _sdhci_sprd_set_clock(host, clock);
269
270 if (clock <= 400000)
271 en = true;
272 sdhci_sprd_set_dll_invert(host, SDHCI_SPRD_BIT_CMD_DLY_INV |
273 SDHCI_SPRD_BIT_POSRD_DLY_INV, en);
274 clk_changed = true;
275 } else {
276 _sdhci_sprd_set_clock(host, clock);
277 }
278
279 /*
280 * According to the Spreadtrum SD host specification, when we changed
281 * the clock to be more than 52M, we should enable the PHY DLL which
282 * is used to track the clock frequency to make the clock work more
283 * stable. Otherwise deviation may occur of the higher clock.
284 */
285 if (clk_changed && clock > SDHCI_SPRD_PHY_DLL_CLK)
286 sdhci_sprd_enable_phy_dll(host);
287 }
288
289 static unsigned int sdhci_sprd_get_max_clock(struct sdhci_host *host)
290 {
291 struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
292
293 return clk_round_rate(sprd_host->clk_sdio, ULONG_MAX);
294 }
295
296 static unsigned int sdhci_sprd_get_min_clock(struct sdhci_host *host)
297 {
298 return 400000;
299 }
300
301 static void sdhci_sprd_set_uhs_signaling(struct sdhci_host *host,
302 unsigned int timing)
303 {
304 struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
305 struct mmc_host *mmc = host->mmc;
306 u32 *p = sprd_host->phy_delay;
307 u16 ctrl_2;
308
309 if (timing == host->timing)
310 return;
311
312 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
313 /* Select Bus Speed Mode for host */
314 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
315 switch (timing) {
316 case MMC_TIMING_UHS_SDR12:
317 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
318 break;
319 case MMC_TIMING_MMC_HS:
320 case MMC_TIMING_SD_HS:
321 case MMC_TIMING_UHS_SDR25:
322 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
323 break;
324 case MMC_TIMING_UHS_SDR50:
325 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
326 break;
327 case MMC_TIMING_UHS_SDR104:
328 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
329 break;
330 case MMC_TIMING_UHS_DDR50:
331 case MMC_TIMING_MMC_DDR52:
332 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
333 break;
334 case MMC_TIMING_MMC_HS200:
335 ctrl_2 |= SDHCI_SPRD_CTRL_HS200;
336 break;
337 case MMC_TIMING_MMC_HS400:
338 ctrl_2 |= SDHCI_SPRD_CTRL_HS400;
339 break;
340 default:
341 break;
342 }
343
344 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
345
346 if (!mmc->ios.enhanced_strobe)
347 sdhci_writel(host, p[timing], SDHCI_SPRD_REG_32_DLL_DLY);
348 }
349
350 static void sdhci_sprd_hw_reset(struct sdhci_host *host)
351 {
352 int val;
353
354 /*
355 * Note: don't use sdhci_writeb() API here since it is redirected to
356 * sdhci_sprd_writeb() in which we have a workaround for
357 * SDHCI_SOFTWARE_RESET which would make bit SDHCI_HW_RESET_CARD can
358 * not be cleared.
359 */
360 val = readb_relaxed(host->ioaddr + SDHCI_SOFTWARE_RESET);
361 val &= ~SDHCI_HW_RESET_CARD;
362 writeb_relaxed(val, host->ioaddr + SDHCI_SOFTWARE_RESET);
363 /* wait for 10 us */
364 usleep_range(10, 20);
365
366 val |= SDHCI_HW_RESET_CARD;
367 writeb_relaxed(val, host->ioaddr + SDHCI_SOFTWARE_RESET);
368 usleep_range(300, 500);
369 }
370
371 static unsigned int sdhci_sprd_get_max_timeout_count(struct sdhci_host *host)
372 {
373 /* The Spredtrum controller actual maximum timeout count is 1 << 31 */
374 return 1 << 31;
375 }
376
377 static unsigned int sdhci_sprd_get_ro(struct sdhci_host *host)
378 {
379 return 0;
380 }
381
382 static struct sdhci_ops sdhci_sprd_ops = {
383 .read_l = sdhci_sprd_readl,
384 .write_l = sdhci_sprd_writel,
385 .write_b = sdhci_sprd_writeb,
386 .set_clock = sdhci_sprd_set_clock,
387 .get_max_clock = sdhci_sprd_get_max_clock,
388 .get_min_clock = sdhci_sprd_get_min_clock,
389 .set_bus_width = sdhci_set_bus_width,
390 .reset = sdhci_reset,
391 .set_uhs_signaling = sdhci_sprd_set_uhs_signaling,
392 .hw_reset = sdhci_sprd_hw_reset,
393 .get_max_timeout_count = sdhci_sprd_get_max_timeout_count,
394 .get_ro = sdhci_sprd_get_ro,
395 };
396
397 static void sdhci_sprd_request(struct mmc_host *mmc, struct mmc_request *mrq)
398 {
399 struct sdhci_host *host = mmc_priv(mmc);
400 struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
401
402 host->flags |= sprd_host->flags & SDHCI_AUTO_CMD23;
403
404 /*
405 * From version 4.10 onward, ARGUMENT2 register is also as 32-bit
406 * block count register which doesn't support stuff bits of
407 * CMD23 argument on Spreadtrum's sd host controller.
408 */
409 if (host->version >= SDHCI_SPEC_410 &&
410 mrq->sbc && (mrq->sbc->arg & SDHCI_SPRD_ARG2_STUFF) &&
411 (host->flags & SDHCI_AUTO_CMD23))
412 host->flags &= ~SDHCI_AUTO_CMD23;
413
414 sdhci_request(mmc, mrq);
415 }
416
417 static int sdhci_sprd_voltage_switch(struct mmc_host *mmc, struct mmc_ios *ios)
418 {
419 struct sdhci_host *host = mmc_priv(mmc);
420 struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
421 int ret;
422
423 if (!IS_ERR(mmc->supply.vqmmc)) {
424 ret = mmc_regulator_set_vqmmc(mmc, ios);
425 if (ret) {
426 pr_err("%s: Switching signalling voltage failed\n",
427 mmc_hostname(mmc));
428 return ret;
429 }
430 }
431
432 if (IS_ERR(sprd_host->pinctrl))
433 return 0;
434
435 switch (ios->signal_voltage) {
436 case MMC_SIGNAL_VOLTAGE_180:
437 ret = pinctrl_select_state(sprd_host->pinctrl,
438 sprd_host->pins_uhs);
439 if (ret) {
440 pr_err("%s: failed to select uhs pin state\n",
441 mmc_hostname(mmc));
442 return ret;
443 }
444 break;
445
446 default:
447 /* fall-through */
448 case MMC_SIGNAL_VOLTAGE_330:
449 ret = pinctrl_select_state(sprd_host->pinctrl,
450 sprd_host->pins_default);
451 if (ret) {
452 pr_err("%s: failed to select default pin state\n",
453 mmc_hostname(mmc));
454 return ret;
455 }
456 break;
457 }
458
459 /* Wait for 300 ~ 500 us for pin state stable */
460 usleep_range(300, 500);
461 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
462
463 return 0;
464 }
465
466 static void sdhci_sprd_hs400_enhanced_strobe(struct mmc_host *mmc,
467 struct mmc_ios *ios)
468 {
469 struct sdhci_host *host = mmc_priv(mmc);
470 struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
471 u32 *p = sprd_host->phy_delay;
472 u16 ctrl_2;
473
474 if (!ios->enhanced_strobe)
475 return;
476
477 sdhci_sprd_sd_clk_off(host);
478
479 /* Set HS400 enhanced strobe mode */
480 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
481 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
482 ctrl_2 |= SDHCI_SPRD_CTRL_HS400ES;
483 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
484
485 sdhci_sprd_sd_clk_on(host);
486
487 /* Set the PHY DLL delay value for HS400 enhanced strobe mode */
488 sdhci_writel(host, p[MMC_TIMING_MMC_HS400 + 1],
489 SDHCI_SPRD_REG_32_DLL_DLY);
490 }
491
492 static void sdhci_sprd_phy_param_parse(struct sdhci_sprd_host *sprd_host,
493 struct device_node *np)
494 {
495 u32 *p = sprd_host->phy_delay;
496 int ret, i, index;
497 u32 val[4];
498
499 for (i = 0; i < ARRAY_SIZE(sdhci_sprd_phy_cfgs); i++) {
500 ret = of_property_read_u32_array(np,
501 sdhci_sprd_phy_cfgs[i].property, val, 4);
502 if (ret)
503 continue;
504
505 index = sdhci_sprd_phy_cfgs[i].timing;
506 p[index] = val[0] | (val[1] << 8) | (val[2] << 16) | (val[3] << 24);
507 }
508 }
509
510 static const struct sdhci_pltfm_data sdhci_sprd_pdata = {
511 .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION |
512 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
513 SDHCI_QUIRK_MISSING_CAPS,
514 .quirks2 = SDHCI_QUIRK2_BROKEN_HS200 |
515 SDHCI_QUIRK2_USE_32BIT_BLK_CNT |
516 SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
517 .ops = &sdhci_sprd_ops,
518 };
519
520 static int sdhci_sprd_probe(struct platform_device *pdev)
521 {
522 struct sdhci_host *host;
523 struct sdhci_sprd_host *sprd_host;
524 struct clk *clk;
525 int ret = 0;
526
527 host = sdhci_pltfm_init(pdev, &sdhci_sprd_pdata, sizeof(*sprd_host));
528 if (IS_ERR(host))
529 return PTR_ERR(host);
530
531 host->dma_mask = DMA_BIT_MASK(64);
532 pdev->dev.dma_mask = &host->dma_mask;
533 host->mmc_host_ops.request = sdhci_sprd_request;
534 host->mmc_host_ops.hs400_enhanced_strobe =
535 sdhci_sprd_hs400_enhanced_strobe;
536 /*
537 * We can not use the standard ops to change and detect the voltage
538 * signal for Spreadtrum SD host controller, since our voltage regulator
539 * for I/O is fixed in hardware, that means we do not need control
540 * the standard SD host controller to change the I/O voltage.
541 */
542 host->mmc_host_ops.start_signal_voltage_switch =
543 sdhci_sprd_voltage_switch;
544
545 host->mmc->caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED |
546 MMC_CAP_ERASE | MMC_CAP_CMD23;
547 ret = mmc_of_parse(host->mmc);
548 if (ret)
549 goto pltfm_free;
550
551 sprd_host = TO_SPRD_HOST(host);
552 sdhci_sprd_phy_param_parse(sprd_host, pdev->dev.of_node);
553
554 sprd_host->pinctrl = devm_pinctrl_get(&pdev->dev);
555 if (!IS_ERR(sprd_host->pinctrl)) {
556 sprd_host->pins_uhs =
557 pinctrl_lookup_state(sprd_host->pinctrl, "state_uhs");
558 if (IS_ERR(sprd_host->pins_uhs)) {
559 ret = PTR_ERR(sprd_host->pins_uhs);
560 goto pltfm_free;
561 }
562
563 sprd_host->pins_default =
564 pinctrl_lookup_state(sprd_host->pinctrl, "default");
565 if (IS_ERR(sprd_host->pins_default)) {
566 ret = PTR_ERR(sprd_host->pins_default);
567 goto pltfm_free;
568 }
569 }
570
571 clk = devm_clk_get(&pdev->dev, "sdio");
572 if (IS_ERR(clk)) {
573 ret = PTR_ERR(clk);
574 goto pltfm_free;
575 }
576 sprd_host->clk_sdio = clk;
577 sprd_host->base_rate = clk_get_rate(sprd_host->clk_sdio);
578 if (!sprd_host->base_rate)
579 sprd_host->base_rate = SDHCI_SPRD_CLK_DEF_RATE;
580
581 clk = devm_clk_get(&pdev->dev, "enable");
582 if (IS_ERR(clk)) {
583 ret = PTR_ERR(clk);
584 goto pltfm_free;
585 }
586 sprd_host->clk_enable = clk;
587
588 clk = devm_clk_get(&pdev->dev, "2x_enable");
589 if (!IS_ERR(clk))
590 sprd_host->clk_2x_enable = clk;
591
592 ret = clk_prepare_enable(sprd_host->clk_sdio);
593 if (ret)
594 goto pltfm_free;
595
596 ret = clk_prepare_enable(sprd_host->clk_enable);
597 if (ret)
598 goto clk_disable;
599
600 ret = clk_prepare_enable(sprd_host->clk_2x_enable);
601 if (ret)
602 goto clk_disable2;
603
604 sdhci_sprd_init_config(host);
605 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
606 sprd_host->version = ((host->version & SDHCI_VENDOR_VER_MASK) >>
607 SDHCI_VENDOR_VER_SHIFT);
608
609 pm_runtime_get_noresume(&pdev->dev);
610 pm_runtime_set_active(&pdev->dev);
611 pm_runtime_enable(&pdev->dev);
612 pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
613 pm_runtime_use_autosuspend(&pdev->dev);
614 pm_suspend_ignore_children(&pdev->dev, 1);
615
616 sdhci_enable_v4_mode(host);
617
618 /*
619 * Supply the existing CAPS, but clear the UHS-I modes. This
620 * will allow these modes to be specified only by device
621 * tree properties through mmc_of_parse().
622 */
623 host->caps = sdhci_readl(host, SDHCI_CAPABILITIES);
624 host->caps1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
625 host->caps1 &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_SDR104 |
626 SDHCI_SUPPORT_DDR50);
627
628 ret = sdhci_setup_host(host);
629 if (ret)
630 goto pm_runtime_disable;
631
632 sprd_host->flags = host->flags;
633
634 ret = __sdhci_add_host(host);
635 if (ret)
636 goto err_cleanup_host;
637
638 pm_runtime_mark_last_busy(&pdev->dev);
639 pm_runtime_put_autosuspend(&pdev->dev);
640
641 return 0;
642
643 err_cleanup_host:
644 sdhci_cleanup_host(host);
645
646 pm_runtime_disable:
647 pm_runtime_put_noidle(&pdev->dev);
648 pm_runtime_disable(&pdev->dev);
649 pm_runtime_set_suspended(&pdev->dev);
650
651 clk_disable_unprepare(sprd_host->clk_2x_enable);
652
653 clk_disable2:
654 clk_disable_unprepare(sprd_host->clk_enable);
655
656 clk_disable:
657 clk_disable_unprepare(sprd_host->clk_sdio);
658
659 pltfm_free:
660 sdhci_pltfm_free(pdev);
661 return ret;
662 }
663
664 static int sdhci_sprd_remove(struct platform_device *pdev)
665 {
666 struct sdhci_host *host = platform_get_drvdata(pdev);
667 struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
668 struct mmc_host *mmc = host->mmc;
669
670 mmc_remove_host(mmc);
671 clk_disable_unprepare(sprd_host->clk_sdio);
672 clk_disable_unprepare(sprd_host->clk_enable);
673 clk_disable_unprepare(sprd_host->clk_2x_enable);
674
675 mmc_free_host(mmc);
676
677 return 0;
678 }
679
680 static const struct of_device_id sdhci_sprd_of_match[] = {
681 { .compatible = "sprd,sdhci-r11", },
682 { }
683 };
684 MODULE_DEVICE_TABLE(of, sdhci_sprd_of_match);
685
686 #ifdef CONFIG_PM
687 static int sdhci_sprd_runtime_suspend(struct device *dev)
688 {
689 struct sdhci_host *host = dev_get_drvdata(dev);
690 struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
691
692 sdhci_runtime_suspend_host(host);
693
694 clk_disable_unprepare(sprd_host->clk_sdio);
695 clk_disable_unprepare(sprd_host->clk_enable);
696 clk_disable_unprepare(sprd_host->clk_2x_enable);
697
698 return 0;
699 }
700
701 static int sdhci_sprd_runtime_resume(struct device *dev)
702 {
703 struct sdhci_host *host = dev_get_drvdata(dev);
704 struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
705 int ret;
706
707 ret = clk_prepare_enable(sprd_host->clk_2x_enable);
708 if (ret)
709 return ret;
710
711 ret = clk_prepare_enable(sprd_host->clk_enable);
712 if (ret)
713 goto clk_2x_disable;
714
715 ret = clk_prepare_enable(sprd_host->clk_sdio);
716 if (ret)
717 goto clk_disable;
718
719 sdhci_runtime_resume_host(host, 1);
720 return 0;
721
722 clk_disable:
723 clk_disable_unprepare(sprd_host->clk_enable);
724
725 clk_2x_disable:
726 clk_disable_unprepare(sprd_host->clk_2x_enable);
727
728 return ret;
729 }
730 #endif
731
732 static const struct dev_pm_ops sdhci_sprd_pm_ops = {
733 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
734 pm_runtime_force_resume)
735 SET_RUNTIME_PM_OPS(sdhci_sprd_runtime_suspend,
736 sdhci_sprd_runtime_resume, NULL)
737 };
738
739 static struct platform_driver sdhci_sprd_driver = {
740 .probe = sdhci_sprd_probe,
741 .remove = sdhci_sprd_remove,
742 .driver = {
743 .name = "sdhci_sprd_r11",
744 .of_match_table = of_match_ptr(sdhci_sprd_of_match),
745 .pm = &sdhci_sprd_pm_ops,
746 },
747 };
748 module_platform_driver(sdhci_sprd_driver);
749
750 MODULE_DESCRIPTION("Spreadtrum sdio host controller r11 driver");
751 MODULE_LICENSE("GPL v2");
752 MODULE_ALIAS("platform:sdhci-sprd-r11");
Linux with added FPC-III support