drivers/mmc/host/sdhci-xenon.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * Copyright (C) 2016 Marvell, All Rights Reserved.
   4  *
   5  * Author:      Hu Ziji <huziji@marvell.com>
   6  * Date:        2016-8-24
   7  */
   8 #ifndef SDHCI_XENON_H_
   9 #define SDHCI_XENON_H_
  10
  11 /* Register Offset of Xenon SDHC self-defined register */
  12 #define XENON_SYS_CFG_INFO                      0x0104
  13 #define XENON_SLOT_TYPE_SDIO_SHIFT              24
  14 #define XENON_NR_SUPPORTED_SLOT_MASK            0x7
  15
  16 #define XENON_SYS_OP_CTRL                       0x0108
  17 #define XENON_AUTO_CLKGATE_DISABLE_MASK         BIT(20)
  18 #define XENON_SDCLK_IDLEOFF_ENABLE_SHIFT        8
  19 #define XENON_SLOT_ENABLE_SHIFT                 0
  20
  21 #define XENON_SYS_EXT_OP_CTRL                   0x010C
  22 #define XENON_MASK_CMD_CONFLICT_ERR             BIT(8)
  23
  24 #define XENON_SLOT_OP_STATUS_CTRL               0x0128
  25 #define XENON_TUN_CONSECUTIVE_TIMES_SHIFT       16
  26 #define XENON_TUN_CONSECUTIVE_TIMES_MASK        0x7
  27 #define XENON_TUN_CONSECUTIVE_TIMES             0x4
  28 #define XENON_TUNING_STEP_SHIFT                 12
  29 #define XENON_TUNING_STEP_MASK                  0xF
  30 #define XENON_TUNING_STEP_DIVIDER               BIT(6)
  31
  32 #define XENON_SLOT_EMMC_CTRL                    0x0130
  33 #define XENON_ENABLE_RESP_STROBE                BIT(25)
  34 #define XENON_ENABLE_DATA_STROBE                BIT(24)
  35
  36 #define XENON_SLOT_RETUNING_REQ_CTRL            0x0144
  37 /* retuning compatible */
  38 #define XENON_RETUNING_COMPATIBLE               0x1
  39
  40 #define XENON_SLOT_EXT_PRESENT_STATE            0x014C
  41 #define XENON_DLL_LOCK_STATE                    0x1
  42
  43 #define XENON_SLOT_DLL_CUR_DLY_VAL              0x0150
  44
  45 /* Tuning Parameter */
  46 #define XENON_TMR_RETUN_NO_PRESENT              0xF
  47 #define XENON_DEF_TUNING_COUNT                  0x9
  48
  49 #define XENON_DEFAULT_SDCLK_FREQ                400000
  50 #define XENON_LOWEST_SDCLK_FREQ                 100000
  51
  52 /* Xenon specific Mode Select value */
  53 #define XENON_CTRL_HS200                        0x5
  54 #define XENON_CTRL_HS400                        0x6
  55
  56 struct xenon_priv {
  57         unsigned char   tuning_count;
  58         /* idx of SDHC */
  59         u8              sdhc_id;
  60
  61         /*
  62          * eMMC/SD/SDIO require different register settings.
  63          * Xenon driver has to recognize card type
  64          * before mmc_host->card is not available.
  65          * This field records the card type during init.
  66          * It is updated in xenon_init_card().
  67          *
  68          * It is only valid during initialization after it is updated.
  69          * Do not access this variable in normal transfers after
  70          * initialization completes.
  71          */
  72         unsigned int    init_card_type;
  73
  74         /*
  75          * The bus_width, timing, and clock fields in below
  76          * record the current ios setting of Xenon SDHC.
  77          * Driver will adjust PHY setting if any change to
  78          * ios affects PHY timing.
  79          */
  80         unsigned char   bus_width;
  81         unsigned char   timing;
  82         unsigned int    clock;
  83         struct clk      *axi_clk;
  84
  85         int             phy_type;
  86         /*
  87          * Contains board-specific PHY parameters
  88          * passed from device tree.
  89          */
  90         void            *phy_params;
  91         struct xenon_emmc_phy_regs *emmc_phy_regs;
  92         bool restore_needed;
  93 };
  94
  95 int xenon_phy_adj(struct sdhci_host *host, struct mmc_ios *ios);
  96 int xenon_phy_parse_dt(struct device_node *np,
  97                        struct sdhci_host *host);
  98 void xenon_soc_pad_ctrl(struct sdhci_host *host,
  99                         unsigned char signal_voltage);
 100 #endif