drivers/mmc/host/sdhci_am654.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * sdhci_am654.c - SDHCI driver for TI's AM654 SOCs
   4  *
   5  * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com
   6  *
   7  */
   8 #include <linux/clk.h>
   9 #include <linux/of.h>
  10 #include <linux/module.h>
  11 #include <linux/pm_runtime.h>
  12 #include <linux/property.h>
  13 #include <linux/regmap.h>
  14
  15 #include "cqhci.h"
  16 #include "sdhci-pltfm.h"
  17
  18 /* CTL_CFG Registers */
  19 #define CTL_CFG_2               0x14
  20
  21 #define SLOTTYPE_MASK           GENMASK(31, 30)
  22 #define SLOTTYPE_EMBEDDED       BIT(30)
  23
  24 /* PHY Registers */
  25 #define PHY_CTRL1       0x100
  26 #define PHY_CTRL2       0x104
  27 #define PHY_CTRL3       0x108
  28 #define PHY_CTRL4       0x10C
  29 #define PHY_CTRL5       0x110
  30 #define PHY_CTRL6       0x114
  31 #define PHY_STAT1       0x130
  32 #define PHY_STAT2       0x134
  33
  34 #define IOMUX_ENABLE_SHIFT      31
  35 #define IOMUX_ENABLE_MASK       BIT(IOMUX_ENABLE_SHIFT)
  36 #define OTAPDLYENA_SHIFT        20
  37 #define OTAPDLYENA_MASK         BIT(OTAPDLYENA_SHIFT)
  38 #define OTAPDLYSEL_SHIFT        12
  39 #define OTAPDLYSEL_MASK         GENMASK(15, 12)
  40 #define STRBSEL_SHIFT           24
  41 #define STRBSEL_4BIT_MASK       GENMASK(27, 24)
  42 #define STRBSEL_8BIT_MASK       GENMASK(31, 24)
  43 #define SEL50_SHIFT             8
  44 #define SEL50_MASK              BIT(SEL50_SHIFT)
  45 #define SEL100_SHIFT            9
  46 #define SEL100_MASK             BIT(SEL100_SHIFT)
  47 #define FREQSEL_SHIFT           8
  48 #define FREQSEL_MASK            GENMASK(10, 8)
  49 #define DLL_TRIM_ICP_SHIFT      4
  50 #define DLL_TRIM_ICP_MASK       GENMASK(7, 4)
  51 #define DR_TY_SHIFT             20
  52 #define DR_TY_MASK              GENMASK(22, 20)
  53 #define ENDLL_SHIFT             1
  54 #define ENDLL_MASK              BIT(ENDLL_SHIFT)
  55 #define DLLRDY_SHIFT            0
  56 #define DLLRDY_MASK             BIT(DLLRDY_SHIFT)
  57 #define PDB_SHIFT               0
  58 #define PDB_MASK                BIT(PDB_SHIFT)
  59 #define CALDONE_SHIFT           1
  60 #define CALDONE_MASK            BIT(CALDONE_SHIFT)
  61 #define RETRIM_SHIFT            17
  62 #define RETRIM_MASK             BIT(RETRIM_SHIFT)
  63
  64 #define DRIVER_STRENGTH_50_OHM  0x0
  65 #define DRIVER_STRENGTH_33_OHM  0x1
  66 #define DRIVER_STRENGTH_66_OHM  0x2
  67 #define DRIVER_STRENGTH_100_OHM 0x3
  68 #define DRIVER_STRENGTH_40_OHM  0x4
  69
  70 #define CLOCK_TOO_SLOW_HZ       400000
  71
  72 /* Command Queue Host Controller Interface Base address */
  73 #define SDHCI_AM654_CQE_BASE_ADDR 0x200
  74
  75 static struct regmap_config sdhci_am654_regmap_config = {
  76         .reg_bits = 32,
  77         .val_bits = 32,
  78         .reg_stride = 4,
  79         .fast_io = true,
  80 };
  81
  82 struct sdhci_am654_data {
  83         struct regmap *base;
  84         int otap_del_sel;
  85         int trm_icp;
  86         int drv_strength;
  87         bool dll_on;
  88         int strb_sel;
  89         u32 flags;
  90 };
  91
  92 struct sdhci_am654_driver_data {
  93         const struct sdhci_pltfm_data *pdata;
  94         u32 flags;
  95 #define IOMUX_PRESENT   (1 << 0)
  96 #define FREQSEL_2_BIT   (1 << 1)
  97 #define STRBSEL_4_BIT   (1 << 2)
  98 #define DLL_PRESENT     (1 << 3)
  99 };
 100
 101 static void sdhci_am654_set_clock(struct sdhci_host *host, unsigned int clock)
 102 {
 103         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 104         struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
 105         int sel50, sel100, freqsel;
 106         u32 mask, val;
 107         int ret;
 108
 109         if (sdhci_am654->dll_on) {
 110                 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK, 0);
 111
 112                 sdhci_am654->dll_on = false;
 113         }
 114
 115         sdhci_set_clock(host, clock);
 116
 117         if (clock > CLOCK_TOO_SLOW_HZ) {
 118                 /* Setup DLL Output TAP delay */
 119                 mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK;
 120                 val = (1 << OTAPDLYENA_SHIFT) |
 121                       (sdhci_am654->otap_del_sel << OTAPDLYSEL_SHIFT);
 122                 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val);
 123                 /* Write to STRBSEL for HS400 speed mode */
 124                 if (host->mmc->ios.timing == MMC_TIMING_MMC_HS400) {
 125                         if (sdhci_am654->flags & STRBSEL_4_BIT)
 126                                 mask = STRBSEL_4BIT_MASK;
 127                         else
 128                                 mask = STRBSEL_8BIT_MASK;
 129
 130                         regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask,
 131                                            sdhci_am654->strb_sel <<
 132                                            STRBSEL_SHIFT);
 133                 }
 134
 135                 if (sdhci_am654->flags & FREQSEL_2_BIT) {
 136                         switch (clock) {
 137                         case 200000000:
 138                                 sel50 = 0;
 139                                 sel100 = 0;
 140                                 break;
 141                         case 100000000:
 142                                 sel50 = 0;
 143                                 sel100 = 1;
 144                                 break;
 145                         default:
 146                                 sel50 = 1;
 147                                 sel100 = 0;
 148                         }
 149
 150                         /* Configure PHY DLL frequency */
 151                         mask = SEL50_MASK | SEL100_MASK;
 152                         val = (sel50 << SEL50_SHIFT) | (sel100 << SEL100_SHIFT);
 153                         regmap_update_bits(sdhci_am654->base, PHY_CTRL5, mask,
 154                                            val);
 155                 } else {
 156                         switch (clock) {
 157                         case 200000000:
 158                                 freqsel = 0x0;
 159                                 break;
 160                         default:
 161                                 freqsel = 0x4;
 162                         }
 163
 164                         regmap_update_bits(sdhci_am654->base, PHY_CTRL5,
 165                                            FREQSEL_MASK,
 166                                            freqsel << FREQSEL_SHIFT);
 167                 }
 168
 169                 /* Configure DLL TRIM */
 170                 mask = DLL_TRIM_ICP_MASK;
 171                 val = sdhci_am654->trm_icp << DLL_TRIM_ICP_SHIFT;
 172
 173                 /* Configure DLL driver strength */
 174                 mask |= DR_TY_MASK;
 175                 val |= sdhci_am654->drv_strength << DR_TY_SHIFT;
 176                 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, mask, val);
 177                 /* Enable DLL */
 178                 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK,
 179                                    0x1 << ENDLL_SHIFT);
 180                 /*
 181                  * Poll for DLL ready. Use a one second timeout.
 182                  * Works in all experiments done so far
 183                  */
 184                 ret = regmap_read_poll_timeout(sdhci_am654->base, PHY_STAT1,
 185                                                val, val & DLLRDY_MASK, 1000,
 186                                                1000000);
 187                 if (ret) {
 188                         dev_err(mmc_dev(host->mmc), "DLL failed to relock\n");
 189                         return;
 190                 }
 191
 192                 sdhci_am654->dll_on = true;
 193         }
 194 }
 195
 196 static void sdhci_j721e_4bit_set_clock(struct sdhci_host *host,
 197                                        unsigned int clock)
 198 {
 199         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 200         struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
 201         int val, mask;
 202
 203         mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK;
 204         val = (1 << OTAPDLYENA_SHIFT) |
 205               (sdhci_am654->otap_del_sel << OTAPDLYSEL_SHIFT);
 206         regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val);
 207
 208         sdhci_set_clock(host, clock);
 209 }
 210
 211 static void sdhci_am654_set_power(struct sdhci_host *host, unsigned char mode,
 212                                   unsigned short vdd)
 213 {
 214         if (!IS_ERR(host->mmc->supply.vmmc)) {
 215                 struct mmc_host *mmc = host->mmc;
 216
 217                 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
 218         }
 219         sdhci_set_power_noreg(host, mode, vdd);
 220 }
 221
 222 static void sdhci_am654_write_b(struct sdhci_host *host, u8 val, int reg)
 223 {
 224         unsigned char timing = host->mmc->ios.timing;
 225
 226         if (reg == SDHCI_HOST_CONTROL) {
 227                 switch (timing) {
 228                 /*
 229                  * According to the data manual, HISPD bit
 230                  * should not be set in these speed modes.
 231                  */
 232                 case MMC_TIMING_SD_HS:
 233                 case MMC_TIMING_MMC_HS:
 234                 case MMC_TIMING_UHS_SDR12:
 235                 case MMC_TIMING_UHS_SDR25:
 236                         val &= ~SDHCI_CTRL_HISPD;
 237                 }
 238         }
 239
 240         writeb(val, host->ioaddr + reg);
 241 }
 242
 243 static int sdhci_am654_execute_tuning(struct mmc_host *mmc, u32 opcode)
 244 {
 245         struct sdhci_host *host = mmc_priv(mmc);
 246         int err = sdhci_execute_tuning(mmc, opcode);
 247
 248         if (err)
 249                 return err;
 250         /*
 251          * Tuning data remains in the buffer after tuning.
 252          * Do a command and data reset to get rid of it
 253          */
 254         sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
 255
 256         return 0;
 257 }
 258
 259 static u32 sdhci_am654_cqhci_irq(struct sdhci_host *host, u32 intmask)
 260 {
 261         int cmd_error = 0;
 262         int data_error = 0;
 263
 264         if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error))
 265                 return intmask;
 266
 267         cqhci_irq(host->mmc, intmask, cmd_error, data_error);
 268
 269         return 0;
 270 }
 271
 272 static struct sdhci_ops sdhci_am654_ops = {
 273         .get_max_clock = sdhci_pltfm_clk_get_max_clock,
 274         .get_timeout_clock = sdhci_pltfm_clk_get_max_clock,
 275         .set_uhs_signaling = sdhci_set_uhs_signaling,
 276         .set_bus_width = sdhci_set_bus_width,
 277         .set_power = sdhci_am654_set_power,
 278         .set_clock = sdhci_am654_set_clock,
 279         .write_b = sdhci_am654_write_b,
 280         .irq = sdhci_am654_cqhci_irq,
 281         .reset = sdhci_reset,
 282 };
 283
 284 static const struct sdhci_pltfm_data sdhci_am654_pdata = {
 285         .ops = &sdhci_am654_ops,
 286         .quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12,
 287         .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
 288 };
 289
 290 static const struct sdhci_am654_driver_data sdhci_am654_drvdata = {
 291         .pdata = &sdhci_am654_pdata,
 292         .flags = IOMUX_PRESENT | FREQSEL_2_BIT | STRBSEL_4_BIT | DLL_PRESENT,
 293 };
 294
 295 static struct sdhci_ops sdhci_j721e_8bit_ops = {
 296         .get_max_clock = sdhci_pltfm_clk_get_max_clock,
 297         .get_timeout_clock = sdhci_pltfm_clk_get_max_clock,
 298         .set_uhs_signaling = sdhci_set_uhs_signaling,
 299         .set_bus_width = sdhci_set_bus_width,
 300         .set_power = sdhci_am654_set_power,
 301         .set_clock = sdhci_am654_set_clock,
 302         .write_b = sdhci_am654_write_b,
 303         .irq = sdhci_am654_cqhci_irq,
 304         .reset = sdhci_reset,
 305 };
 306
 307 static const struct sdhci_pltfm_data sdhci_j721e_8bit_pdata = {
 308         .ops = &sdhci_j721e_8bit_ops,
 309         .quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12,
 310         .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
 311 };
 312
 313 static const struct sdhci_am654_driver_data sdhci_j721e_8bit_drvdata = {
 314         .pdata = &sdhci_j721e_8bit_pdata,
 315         .flags = DLL_PRESENT,
 316 };
 317
 318 static struct sdhci_ops sdhci_j721e_4bit_ops = {
 319         .get_max_clock = sdhci_pltfm_clk_get_max_clock,
 320         .get_timeout_clock = sdhci_pltfm_clk_get_max_clock,
 321         .set_uhs_signaling = sdhci_set_uhs_signaling,
 322         .set_bus_width = sdhci_set_bus_width,
 323         .set_power = sdhci_am654_set_power,
 324         .set_clock = sdhci_j721e_4bit_set_clock,
 325         .write_b = sdhci_am654_write_b,
 326         .irq = sdhci_am654_cqhci_irq,
 327         .reset = sdhci_reset,
 328 };
 329
 330 static const struct sdhci_pltfm_data sdhci_j721e_4bit_pdata = {
 331         .ops = &sdhci_j721e_4bit_ops,
 332         .quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12,
 333         .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
 334 };
 335
 336 static const struct sdhci_am654_driver_data sdhci_j721e_4bit_drvdata = {
 337         .pdata = &sdhci_j721e_4bit_pdata,
 338         .flags = IOMUX_PRESENT,
 339 };
 340
 341 static void sdhci_am654_dumpregs(struct mmc_host *mmc)
 342 {
 343         sdhci_dumpregs(mmc_priv(mmc));
 344 }
 345
 346 static const struct cqhci_host_ops sdhci_am654_cqhci_ops = {
 347         .enable         = sdhci_cqe_enable,
 348         .disable        = sdhci_cqe_disable,
 349         .dumpregs       = sdhci_am654_dumpregs,
 350 };
 351
 352 static int sdhci_am654_cqe_add_host(struct sdhci_host *host)
 353 {
 354         struct cqhci_host *cq_host;
 355         int ret;
 356
 357         cq_host = devm_kzalloc(host->mmc->parent, sizeof(struct cqhci_host),
 358                                GFP_KERNEL);
 359         if (!cq_host)
 360                 return -ENOMEM;
 361
 362         cq_host->mmio = host->ioaddr + SDHCI_AM654_CQE_BASE_ADDR;
 363         cq_host->quirks |= CQHCI_QUIRK_SHORT_TXFR_DESC_SZ;
 364         cq_host->caps |= CQHCI_TASK_DESC_SZ_128;
 365         cq_host->ops = &sdhci_am654_cqhci_ops;
 366
 367         host->mmc->caps2 |= MMC_CAP2_CQE;
 368
 369         ret = cqhci_init(cq_host, host->mmc, 1);
 370
 371         return ret;
 372 }
 373
 374 static int sdhci_am654_init(struct sdhci_host *host)
 375 {
 376         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 377         struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
 378         u32 ctl_cfg_2 = 0;
 379         u32 mask;
 380         u32 val;
 381         int ret;
 382
 383         /* Reset OTAP to default value */
 384         mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK;
 385         regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, 0x0);
 386
 387         if (sdhci_am654->flags & DLL_PRESENT) {
 388                 regmap_read(sdhci_am654->base, PHY_STAT1, &val);
 389                 if (~val & CALDONE_MASK) {
 390                         /* Calibrate IO lines */
 391                         regmap_update_bits(sdhci_am654->base, PHY_CTRL1,
 392                                            PDB_MASK, PDB_MASK);
 393                         ret = regmap_read_poll_timeout(sdhci_am654->base,
 394                                                        PHY_STAT1, val,
 395                                                        val & CALDONE_MASK,
 396                                                        1, 20);
 397                         if (ret)
 398                                 return ret;
 399                 }
 400         }
 401
 402         /* Enable pins by setting IO mux to 0 */
 403         if (sdhci_am654->flags & IOMUX_PRESENT)
 404                 regmap_update_bits(sdhci_am654->base, PHY_CTRL1,
 405                                    IOMUX_ENABLE_MASK, 0);
 406
 407         /* Set slot type based on SD or eMMC */
 408         if (host->mmc->caps & MMC_CAP_NONREMOVABLE)
 409                 ctl_cfg_2 = SLOTTYPE_EMBEDDED;
 410
 411         regmap_update_bits(sdhci_am654->base, CTL_CFG_2, SLOTTYPE_MASK,
 412                            ctl_cfg_2);
 413
 414         ret = sdhci_setup_host(host);
 415         if (ret)
 416                 return ret;
 417
 418         ret = sdhci_am654_cqe_add_host(host);
 419         if (ret)
 420                 goto err_cleanup_host;
 421
 422         ret = __sdhci_add_host(host);
 423         if (ret)
 424                 goto err_cleanup_host;
 425
 426         return 0;
 427
 428 err_cleanup_host:
 429         sdhci_cleanup_host(host);
 430         return ret;
 431 }
 432
 433 static int sdhci_am654_get_of_property(struct platform_device *pdev,
 434                                         struct sdhci_am654_data *sdhci_am654)
 435 {
 436         struct device *dev = &pdev->dev;
 437         int drv_strength;
 438         int ret;
 439
 440         ret = device_property_read_u32(dev, "ti,otap-del-sel",
 441                                        &sdhci_am654->otap_del_sel);
 442         if (ret)
 443                 return ret;
 444
 445         if (sdhci_am654->flags & DLL_PRESENT) {
 446                 ret = device_property_read_u32(dev, "ti,trm-icp",
 447                                                &sdhci_am654->trm_icp);
 448                 if (ret)
 449                         return ret;
 450
 451                 ret = device_property_read_u32(dev, "ti,driver-strength-ohm",
 452                                                &drv_strength);
 453                 if (ret)
 454                         return ret;
 455
 456                 switch (drv_strength) {
 457                 case 50:
 458                         sdhci_am654->drv_strength = DRIVER_STRENGTH_50_OHM;
 459                         break;
 460                 case 33:
 461                         sdhci_am654->drv_strength = DRIVER_STRENGTH_33_OHM;
 462                         break;
 463                 case 66:
 464                         sdhci_am654->drv_strength = DRIVER_STRENGTH_66_OHM;
 465                         break;
 466                 case 100:
 467                         sdhci_am654->drv_strength = DRIVER_STRENGTH_100_OHM;
 468                         break;
 469                 case 40:
 470                         sdhci_am654->drv_strength = DRIVER_STRENGTH_40_OHM;
 471                         break;
 472                 default:
 473                         dev_err(dev, "Invalid driver strength\n");
 474                         return -EINVAL;
 475                 }
 476         }
 477
 478         device_property_read_u32(dev, "ti,strobe-sel", &sdhci_am654->strb_sel);
 479
 480         sdhci_get_of_property(pdev);
 481
 482         return 0;
 483 }
 484
 485 static const struct of_device_id sdhci_am654_of_match[] = {
 486         {
 487                 .compatible = "ti,am654-sdhci-5.1",
 488                 .data = &sdhci_am654_drvdata,
 489         },
 490         {
 491                 .compatible = "ti,j721e-sdhci-8bit",
 492                 .data = &sdhci_j721e_8bit_drvdata,
 493         },
 494         {
 495                 .compatible = "ti,j721e-sdhci-4bit",
 496                 .data = &sdhci_j721e_4bit_drvdata,
 497         },
 498         { /* sentinel */ }
 499 };
 500
 501 static int sdhci_am654_probe(struct platform_device *pdev)
 502 {
 503         const struct sdhci_am654_driver_data *drvdata;
 504         struct sdhci_pltfm_host *pltfm_host;
 505         struct sdhci_am654_data *sdhci_am654;
 506         const struct of_device_id *match;
 507         struct sdhci_host *host;
 508         struct clk *clk_xin;
 509         struct device *dev = &pdev->dev;
 510         void __iomem *base;
 511         int ret;
 512
 513         match = of_match_node(sdhci_am654_of_match, pdev->dev.of_node);
 514         drvdata = match->data;
 515         host = sdhci_pltfm_init(pdev, drvdata->pdata, sizeof(*sdhci_am654));
 516         if (IS_ERR(host))
 517                 return PTR_ERR(host);
 518
 519         pltfm_host = sdhci_priv(host);
 520         sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
 521         sdhci_am654->flags = drvdata->flags;
 522
 523         clk_xin = devm_clk_get(dev, "clk_xin");
 524         if (IS_ERR(clk_xin)) {
 525                 dev_err(dev, "clk_xin clock not found.\n");
 526                 ret = PTR_ERR(clk_xin);
 527                 goto err_pltfm_free;
 528         }
 529
 530         pltfm_host->clk = clk_xin;
 531
 532         /* Clocks are enabled using pm_runtime */
 533         pm_runtime_enable(dev);
 534         ret = pm_runtime_get_sync(dev);
 535         if (ret < 0) {
 536                 pm_runtime_put_noidle(dev);
 537                 goto pm_runtime_disable;
 538         }
 539
 540         base = devm_platform_ioremap_resource(pdev, 1);
 541         if (IS_ERR(base)) {
 542                 ret = PTR_ERR(base);
 543                 goto pm_runtime_put;
 544         }
 545
 546         sdhci_am654->base = devm_regmap_init_mmio(dev, base,
 547                                                   &sdhci_am654_regmap_config);
 548         if (IS_ERR(sdhci_am654->base)) {
 549                 dev_err(dev, "Failed to initialize regmap\n");
 550                 ret = PTR_ERR(sdhci_am654->base);
 551                 goto pm_runtime_put;
 552         }
 553
 554         ret = sdhci_am654_get_of_property(pdev, sdhci_am654);
 555         if (ret)
 556                 goto pm_runtime_put;
 557
 558         ret = mmc_of_parse(host->mmc);
 559         if (ret) {
 560                 dev_err(dev, "parsing dt failed (%d)\n", ret);
 561                 goto pm_runtime_put;
 562         }
 563
 564         host->mmc_host_ops.execute_tuning = sdhci_am654_execute_tuning;
 565
 566         ret = sdhci_am654_init(host);
 567         if (ret)
 568                 goto pm_runtime_put;
 569
 570         return 0;
 571
 572 pm_runtime_put:
 573         pm_runtime_put_sync(dev);
 574 pm_runtime_disable:
 575         pm_runtime_disable(dev);
 576 err_pltfm_free:
 577         sdhci_pltfm_free(pdev);
 578         return ret;
 579 }
 580
 581 static int sdhci_am654_remove(struct platform_device *pdev)
 582 {
 583         struct sdhci_host *host = platform_get_drvdata(pdev);
 584         int ret;
 585
 586         sdhci_remove_host(host, true);
 587         ret = pm_runtime_put_sync(&pdev->dev);
 588         if (ret < 0)
 589                 return ret;
 590
 591         pm_runtime_disable(&pdev->dev);
 592         sdhci_pltfm_free(pdev);
 593
 594         return 0;
 595 }
 596
 597 static struct platform_driver sdhci_am654_driver = {
 598         .driver = {
 599                 .name = "sdhci-am654",
 600                 .of_match_table = sdhci_am654_of_match,
 601         },
 602         .probe = sdhci_am654_probe,
 603         .remove = sdhci_am654_remove,
 604 };
 605
 606 module_platform_driver(sdhci_am654_driver);
 607
 608 MODULE_DESCRIPTION("Driver for SDHCI Controller on TI's AM654 devices");
 609 MODULE_AUTHOR("Faiz Abbas <faiz_abbas@ti.com>");
 610 MODULE_LICENSE("GPL");