drivers/mtd/nand/raw/mpc5121_nfc.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Copyright 2004-2008 Freescale Semiconductor, Inc.
   4  * Copyright 2009 Semihalf.
   5  *
   6  * Approved as OSADL project by a majority of OSADL members and funded
   7  * by OSADL membership fees in 2009;  for details see www.osadl.org.
   8  *
   9  * Based on original driver from Freescale Semiconductor
  10  * written by John Rigby <jrigby@freescale.com> on basis of mxc_nand.c.
  11  * Reworked and extended by Piotr Ziecik <kosmo@semihalf.com>.
  12  */
  13
  14 #include <linux/module.h>
  15 #include <linux/clk.h>
  16 #include <linux/gfp.h>
  17 #include <linux/delay.h>
  18 #include <linux/err.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/io.h>
  21 #include <linux/mtd/mtd.h>
  22 #include <linux/mtd/rawnand.h>
  23 #include <linux/mtd/partitions.h>
  24 #include <linux/of_address.h>
  25 #include <linux/of_device.h>
  26 #include <linux/of_irq.h>
  27 #include <linux/of_platform.h>
  28
  29 #include <asm/mpc5121.h>
  30
  31 /* Addresses for NFC MAIN RAM BUFFER areas */
  32 #define NFC_MAIN_AREA(n)        ((n) *  0x200)
  33
  34 /* Addresses for NFC SPARE BUFFER areas */
  35 #define NFC_SPARE_BUFFERS       8
  36 #define NFC_SPARE_LEN           0x40
  37 #define NFC_SPARE_AREA(n)       (0x1000 + ((n) * NFC_SPARE_LEN))
  38
  39 /* MPC5121 NFC registers */
  40 #define NFC_BUF_ADDR            0x1E04
  41 #define NFC_FLASH_ADDR          0x1E06
  42 #define NFC_FLASH_CMD           0x1E08
  43 #define NFC_CONFIG              0x1E0A
  44 #define NFC_ECC_STATUS1         0x1E0C
  45 #define NFC_ECC_STATUS2         0x1E0E
  46 #define NFC_SPAS                0x1E10
  47 #define NFC_WRPROT              0x1E12
  48 #define NFC_NF_WRPRST           0x1E18
  49 #define NFC_CONFIG1             0x1E1A
  50 #define NFC_CONFIG2             0x1E1C
  51 #define NFC_UNLOCKSTART_BLK0    0x1E20
  52 #define NFC_UNLOCKEND_BLK0      0x1E22
  53 #define NFC_UNLOCKSTART_BLK1    0x1E24
  54 #define NFC_UNLOCKEND_BLK1      0x1E26
  55 #define NFC_UNLOCKSTART_BLK2    0x1E28
  56 #define NFC_UNLOCKEND_BLK2      0x1E2A
  57 #define NFC_UNLOCKSTART_BLK3    0x1E2C
  58 #define NFC_UNLOCKEND_BLK3      0x1E2E
  59
  60 /* Bit Definitions: NFC_BUF_ADDR */
  61 #define NFC_RBA_MASK            (7 << 0)
  62 #define NFC_ACTIVE_CS_SHIFT     5
  63 #define NFC_ACTIVE_CS_MASK      (3 << NFC_ACTIVE_CS_SHIFT)
  64
  65 /* Bit Definitions: NFC_CONFIG */
  66 #define NFC_BLS_UNLOCKED        (1 << 1)
  67
  68 /* Bit Definitions: NFC_CONFIG1 */
  69 #define NFC_ECC_4BIT            (1 << 0)
  70 #define NFC_FULL_PAGE_DMA       (1 << 1)
  71 #define NFC_SPARE_ONLY          (1 << 2)
  72 #define NFC_ECC_ENABLE          (1 << 3)
  73 #define NFC_INT_MASK            (1 << 4)
  74 #define NFC_BIG_ENDIAN          (1 << 5)
  75 #define NFC_RESET               (1 << 6)
  76 #define NFC_CE                  (1 << 7)
  77 #define NFC_ONE_CYCLE           (1 << 8)
  78 #define NFC_PPB_32              (0 << 9)
  79 #define NFC_PPB_64              (1 << 9)
  80 #define NFC_PPB_128             (2 << 9)
  81 #define NFC_PPB_256             (3 << 9)
  82 #define NFC_PPB_MASK            (3 << 9)
  83 #define NFC_FULL_PAGE_INT       (1 << 11)
  84
  85 /* Bit Definitions: NFC_CONFIG2 */
  86 #define NFC_COMMAND             (1 << 0)
  87 #define NFC_ADDRESS             (1 << 1)
  88 #define NFC_INPUT               (1 << 2)
  89 #define NFC_OUTPUT              (1 << 3)
  90 #define NFC_ID                  (1 << 4)
  91 #define NFC_STATUS              (1 << 5)
  92 #define NFC_CMD_FAIL            (1 << 15)
  93 #define NFC_INT                 (1 << 15)
  94
  95 /* Bit Definitions: NFC_WRPROT */
  96 #define NFC_WPC_LOCK_TIGHT      (1 << 0)
  97 #define NFC_WPC_LOCK            (1 << 1)
  98 #define NFC_WPC_UNLOCK          (1 << 2)
  99
 100 #define DRV_NAME                "mpc5121_nfc"
 101
 102 /* Timeouts */
 103 #define NFC_RESET_TIMEOUT       1000            /* 1 ms */
 104 #define NFC_TIMEOUT             (HZ / 10)       /* 1/10 s */
 105
 106 struct mpc5121_nfc_prv {
 107         struct nand_chip        chip;
 108         int                     irq;
 109         void __iomem            *regs;
 110         struct clk              *clk;
 111         wait_queue_head_t       irq_waitq;
 112         uint                    column;
 113         int                     spareonly;
 114         void __iomem            *csreg;
 115         struct device           *dev;
 116 };
 117
 118 static void mpc5121_nfc_done(struct mtd_info *mtd);
 119
 120 /* Read NFC register */
 121 static inline u16 nfc_read(struct mtd_info *mtd, uint reg)
 122 {
 123         struct nand_chip *chip = mtd_to_nand(mtd);
 124         struct mpc5121_nfc_prv *prv = nand_get_controller_data(chip);
 125
 126         return in_be16(prv->regs + reg);
 127 }
 128
 129 /* Write NFC register */
 130 static inline void nfc_write(struct mtd_info *mtd, uint reg, u16 val)
 131 {
 132         struct nand_chip *chip = mtd_to_nand(mtd);
 133         struct mpc5121_nfc_prv *prv = nand_get_controller_data(chip);
 134
 135         out_be16(prv->regs + reg, val);
 136 }
 137
 138 /* Set bits in NFC register */
 139 static inline void nfc_set(struct mtd_info *mtd, uint reg, u16 bits)
 140 {
 141         nfc_write(mtd, reg, nfc_read(mtd, reg) | bits);
 142 }
 143
 144 /* Clear bits in NFC register */
 145 static inline void nfc_clear(struct mtd_info *mtd, uint reg, u16 bits)
 146 {
 147         nfc_write(mtd, reg, nfc_read(mtd, reg) & ~bits);
 148 }
 149
 150 /* Invoke address cycle */
 151 static inline void mpc5121_nfc_send_addr(struct mtd_info *mtd, u16 addr)
 152 {
 153         nfc_write(mtd, NFC_FLASH_ADDR, addr);
 154         nfc_write(mtd, NFC_CONFIG2, NFC_ADDRESS);
 155         mpc5121_nfc_done(mtd);
 156 }
 157
 158 /* Invoke command cycle */
 159 static inline void mpc5121_nfc_send_cmd(struct mtd_info *mtd, u16 cmd)
 160 {
 161         nfc_write(mtd, NFC_FLASH_CMD, cmd);
 162         nfc_write(mtd, NFC_CONFIG2, NFC_COMMAND);
 163         mpc5121_nfc_done(mtd);
 164 }
 165
 166 /* Send data from NFC buffers to NAND flash */
 167 static inline void mpc5121_nfc_send_prog_page(struct mtd_info *mtd)
 168 {
 169         nfc_clear(mtd, NFC_BUF_ADDR, NFC_RBA_MASK);
 170         nfc_write(mtd, NFC_CONFIG2, NFC_INPUT);
 171         mpc5121_nfc_done(mtd);
 172 }
 173
 174 /* Receive data from NAND flash */
 175 static inline void mpc5121_nfc_send_read_page(struct mtd_info *mtd)
 176 {
 177         nfc_clear(mtd, NFC_BUF_ADDR, NFC_RBA_MASK);
 178         nfc_write(mtd, NFC_CONFIG2, NFC_OUTPUT);
 179         mpc5121_nfc_done(mtd);
 180 }
 181
 182 /* Receive ID from NAND flash */
 183 static inline void mpc5121_nfc_send_read_id(struct mtd_info *mtd)
 184 {
 185         nfc_clear(mtd, NFC_BUF_ADDR, NFC_RBA_MASK);
 186         nfc_write(mtd, NFC_CONFIG2, NFC_ID);
 187         mpc5121_nfc_done(mtd);
 188 }
 189
 190 /* Receive status from NAND flash */
 191 static inline void mpc5121_nfc_send_read_status(struct mtd_info *mtd)
 192 {
 193         nfc_clear(mtd, NFC_BUF_ADDR, NFC_RBA_MASK);
 194         nfc_write(mtd, NFC_CONFIG2, NFC_STATUS);
 195         mpc5121_nfc_done(mtd);
 196 }
 197
 198 /* NFC interrupt handler */
 199 static irqreturn_t mpc5121_nfc_irq(int irq, void *data)
 200 {
 201         struct mtd_info *mtd = data;
 202         struct nand_chip *chip = mtd_to_nand(mtd);
 203         struct mpc5121_nfc_prv *prv = nand_get_controller_data(chip);
 204
 205         nfc_set(mtd, NFC_CONFIG1, NFC_INT_MASK);
 206         wake_up(&prv->irq_waitq);
 207
 208         return IRQ_HANDLED;
 209 }
 210
 211 /* Wait for operation complete */
 212 static void mpc5121_nfc_done(struct mtd_info *mtd)
 213 {
 214         struct nand_chip *chip = mtd_to_nand(mtd);
 215         struct mpc5121_nfc_prv *prv = nand_get_controller_data(chip);
 216         int rv;
 217
 218         if ((nfc_read(mtd, NFC_CONFIG2) & NFC_INT) == 0) {
 219                 nfc_clear(mtd, NFC_CONFIG1, NFC_INT_MASK);
 220                 rv = wait_event_timeout(prv->irq_waitq,
 221                         (nfc_read(mtd, NFC_CONFIG2) & NFC_INT), NFC_TIMEOUT);
 222
 223                 if (!rv)
 224                         dev_warn(prv->dev,
 225                                 "Timeout while waiting for interrupt.\n");
 226         }
 227
 228         nfc_clear(mtd, NFC_CONFIG2, NFC_INT);
 229 }
 230
 231 /* Do address cycle(s) */
 232 static void mpc5121_nfc_addr_cycle(struct mtd_info *mtd, int column, int page)
 233 {
 234         struct nand_chip *chip = mtd_to_nand(mtd);
 235         u32 pagemask = chip->pagemask;
 236
 237         if (column != -1) {
 238                 mpc5121_nfc_send_addr(mtd, column);
 239                 if (mtd->writesize > 512)
 240                         mpc5121_nfc_send_addr(mtd, column >> 8);
 241         }
 242
 243         if (page != -1) {
 244                 do {
 245                         mpc5121_nfc_send_addr(mtd, page & 0xFF);
 246                         page >>= 8;
 247                         pagemask >>= 8;
 248                 } while (pagemask);
 249         }
 250 }
 251
 252 /* Control chip select signals */
 253 static void mpc5121_nfc_select_chip(struct nand_chip *nand, int chip)
 254 {
 255         struct mtd_info *mtd = nand_to_mtd(nand);
 256
 257         if (chip < 0) {
 258                 nfc_clear(mtd, NFC_CONFIG1, NFC_CE);
 259                 return;
 260         }
 261
 262         nfc_clear(mtd, NFC_BUF_ADDR, NFC_ACTIVE_CS_MASK);
 263         nfc_set(mtd, NFC_BUF_ADDR, (chip << NFC_ACTIVE_CS_SHIFT) &
 264                                                         NFC_ACTIVE_CS_MASK);
 265         nfc_set(mtd, NFC_CONFIG1, NFC_CE);
 266 }
 267
 268 /* Init external chip select logic on ADS5121 board */
 269 static int ads5121_chipselect_init(struct mtd_info *mtd)
 270 {
 271         struct nand_chip *chip = mtd_to_nand(mtd);
 272         struct mpc5121_nfc_prv *prv = nand_get_controller_data(chip);
 273         struct device_node *dn;
 274
 275         dn = of_find_compatible_node(NULL, NULL, "fsl,mpc5121ads-cpld");
 276         if (dn) {
 277                 prv->csreg = of_iomap(dn, 0);
 278                 of_node_put(dn);
 279                 if (!prv->csreg)
 280                         return -ENOMEM;
 281
 282                 /* CPLD Register 9 controls NAND /CE Lines */
 283                 prv->csreg += 9;
 284                 return 0;
 285         }
 286
 287         return -EINVAL;
 288 }
 289
 290 /* Control chips select signal on ADS5121 board */
 291 static void ads5121_select_chip(struct nand_chip *nand, int chip)
 292 {
 293         struct mtd_info *mtd = nand_to_mtd(nand);
 294         struct mpc5121_nfc_prv *prv = nand_get_controller_data(nand);
 295         u8 v;
 296
 297         v = in_8(prv->csreg);
 298         v |= 0x0F;
 299
 300         if (chip >= 0) {
 301                 mpc5121_nfc_select_chip(nand, 0);
 302                 v &= ~(1 << chip);
 303         } else
 304                 mpc5121_nfc_select_chip(nand, -1);
 305
 306         out_8(prv->csreg, v);
 307 }
 308
 309 /* Read NAND Ready/Busy signal */
 310 static int mpc5121_nfc_dev_ready(struct nand_chip *nand)
 311 {
 312         /*
 313          * NFC handles ready/busy signal internally. Therefore, this function
 314          * always returns status as ready.
 315          */
 316         return 1;
 317 }
 318
 319 /* Write command to NAND flash */
 320 static void mpc5121_nfc_command(struct nand_chip *chip, unsigned command,
 321                                 int column, int page)
 322 {
 323         struct mtd_info *mtd = nand_to_mtd(chip);
 324         struct mpc5121_nfc_prv *prv = nand_get_controller_data(chip);
 325
 326         prv->column = (column >= 0) ? column : 0;
 327         prv->spareonly = 0;
 328
 329         switch (command) {
 330         case NAND_CMD_PAGEPROG:
 331                 mpc5121_nfc_send_prog_page(mtd);
 332                 break;
 333         /*
 334          * NFC does not support sub-page reads and writes,
 335          * so emulate them using full page transfers.
 336          */
 337         case NAND_CMD_READ0:
 338                 column = 0;
 339                 break;
 340
 341         case NAND_CMD_READ1:
 342                 prv->column += 256;
 343                 command = NAND_CMD_READ0;
 344                 column = 0;
 345                 break;
 346
 347         case NAND_CMD_READOOB:
 348                 prv->spareonly = 1;
 349                 command = NAND_CMD_READ0;
 350                 column = 0;
 351                 break;
 352
 353         case NAND_CMD_SEQIN:
 354                 mpc5121_nfc_command(chip, NAND_CMD_READ0, column, page);
 355                 column = 0;
 356                 break;
 357
 358         case NAND_CMD_ERASE1:
 359         case NAND_CMD_ERASE2:
 360         case NAND_CMD_READID:
 361         case NAND_CMD_STATUS:
 362                 break;
 363
 364         default:
 365                 return;
 366         }
 367
 368         mpc5121_nfc_send_cmd(mtd, command);
 369         mpc5121_nfc_addr_cycle(mtd, column, page);
 370
 371         switch (command) {
 372         case NAND_CMD_READ0:
 373                 if (mtd->writesize > 512)
 374                         mpc5121_nfc_send_cmd(mtd, NAND_CMD_READSTART);
 375                 mpc5121_nfc_send_read_page(mtd);
 376                 break;
 377
 378         case NAND_CMD_READID:
 379                 mpc5121_nfc_send_read_id(mtd);
 380                 break;
 381
 382         case NAND_CMD_STATUS:
 383                 mpc5121_nfc_send_read_status(mtd);
 384                 if (chip->options & NAND_BUSWIDTH_16)
 385                         prv->column = 1;
 386                 else
 387                         prv->column = 0;
 388                 break;
 389         }
 390 }
 391
 392 /* Copy data from/to NFC spare buffers. */
 393 static void mpc5121_nfc_copy_spare(struct mtd_info *mtd, uint offset,
 394                                                 u8 *buffer, uint size, int wr)
 395 {
 396         struct nand_chip *nand = mtd_to_nand(mtd);
 397         struct mpc5121_nfc_prv *prv = nand_get_controller_data(nand);
 398         uint o, s, sbsize, blksize;
 399
 400         /*
 401          * NAND spare area is available through NFC spare buffers.
 402          * The NFC divides spare area into (page_size / 512) chunks.
 403          * Each chunk is placed into separate spare memory area, using
 404          * first (spare_size / num_of_chunks) bytes of the buffer.
 405          *
 406          * For NAND device in which the spare area is not divided fully
 407          * by the number of chunks, number of used bytes in each spare
 408          * buffer is rounded down to the nearest even number of bytes,
 409          * and all remaining bytes are added to the last used spare area.
 410          *
 411          * For more information read section 26.6.10 of MPC5121e
 412          * Microcontroller Reference Manual, Rev. 3.
 413          */
 414
 415         /* Calculate number of valid bytes in each spare buffer */
 416         sbsize = (mtd->oobsize / (mtd->writesize / 512)) & ~1;
 417
 418         while (size) {
 419                 /* Calculate spare buffer number */
 420                 s = offset / sbsize;
 421                 if (s > NFC_SPARE_BUFFERS - 1)
 422                         s = NFC_SPARE_BUFFERS - 1;
 423
 424                 /*
 425                  * Calculate offset to requested data block in selected spare
 426                  * buffer and its size.
 427                  */
 428                 o = offset - (s * sbsize);
 429                 blksize = min(sbsize - o, size);
 430
 431                 if (wr)
 432                         memcpy_toio(prv->regs + NFC_SPARE_AREA(s) + o,
 433                                                         buffer, blksize);
 434                 else
 435                         memcpy_fromio(buffer,
 436                                 prv->regs + NFC_SPARE_AREA(s) + o, blksize);
 437
 438                 buffer += blksize;
 439                 offset += blksize;
 440                 size -= blksize;
 441         }
 442 }
 443
 444 /* Copy data from/to NFC main and spare buffers */
 445 static void mpc5121_nfc_buf_copy(struct mtd_info *mtd, u_char *buf, int len,
 446                                                                         int wr)
 447 {
 448         struct nand_chip *chip = mtd_to_nand(mtd);
 449         struct mpc5121_nfc_prv *prv = nand_get_controller_data(chip);
 450         uint c = prv->column;
 451         uint l;
 452
 453         /* Handle spare area access */
 454         if (prv->spareonly || c >= mtd->writesize) {
 455                 /* Calculate offset from beginning of spare area */
 456                 if (c >= mtd->writesize)
 457                         c -= mtd->writesize;
 458
 459                 prv->column += len;
 460                 mpc5121_nfc_copy_spare(mtd, c, buf, len, wr);
 461                 return;
 462         }
 463
 464         /*
 465          * Handle main area access - limit copy length to prevent
 466          * crossing main/spare boundary.
 467          */
 468         l = min((uint)len, mtd->writesize - c);
 469         prv->column += l;
 470
 471         if (wr)
 472                 memcpy_toio(prv->regs + NFC_MAIN_AREA(0) + c, buf, l);
 473         else
 474                 memcpy_fromio(buf, prv->regs + NFC_MAIN_AREA(0) + c, l);
 475
 476         /* Handle crossing main/spare boundary */
 477         if (l != len) {
 478                 buf += l;
 479                 len -= l;
 480                 mpc5121_nfc_buf_copy(mtd, buf, len, wr);
 481         }
 482 }
 483
 484 /* Read data from NFC buffers */
 485 static void mpc5121_nfc_read_buf(struct nand_chip *chip, u_char *buf, int len)
 486 {
 487         mpc5121_nfc_buf_copy(nand_to_mtd(chip), buf, len, 0);
 488 }
 489
 490 /* Write data to NFC buffers */
 491 static void mpc5121_nfc_write_buf(struct nand_chip *chip, const u_char *buf,
 492                                   int len)
 493 {
 494         mpc5121_nfc_buf_copy(nand_to_mtd(chip), (u_char *)buf, len, 1);
 495 }
 496
 497 /* Read byte from NFC buffers */
 498 static u8 mpc5121_nfc_read_byte(struct nand_chip *chip)
 499 {
 500         u8 tmp;
 501
 502         mpc5121_nfc_read_buf(chip, &tmp, sizeof(tmp));
 503
 504         return tmp;
 505 }
 506
 507 /*
 508  * Read NFC configuration from Reset Config Word
 509  *
 510  * NFC is configured during reset in basis of information stored
 511  * in Reset Config Word. There is no other way to set NAND block
 512  * size, spare size and bus width.
 513  */
 514 static int mpc5121_nfc_read_hw_config(struct mtd_info *mtd)
 515 {
 516         struct nand_chip *chip = mtd_to_nand(mtd);
 517         struct mpc5121_nfc_prv *prv = nand_get_controller_data(chip);
 518         struct mpc512x_reset_module *rm;
 519         struct device_node *rmnode;
 520         uint rcw_pagesize = 0;
 521         uint rcw_sparesize = 0;
 522         uint rcw_width;
 523         uint rcwh;
 524         uint romloc, ps;
 525         int ret = 0;
 526
 527         rmnode = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-reset");
 528         if (!rmnode) {
 529                 dev_err(prv->dev, "Missing 'fsl,mpc5121-reset' "
 530                                         "node in device tree!\n");
 531                 return -ENODEV;
 532         }
 533
 534         rm = of_iomap(rmnode, 0);
 535         if (!rm) {
 536                 dev_err(prv->dev, "Error mapping reset module node!\n");
 537                 ret = -EBUSY;
 538                 goto out;
 539         }
 540
 541         rcwh = in_be32(&rm->rcwhr);
 542
 543         /* Bit 6: NFC bus width */
 544         rcw_width = ((rcwh >> 6) & 0x1) ? 2 : 1;
 545
 546         /* Bit 7: NFC Page/Spare size */
 547         ps = (rcwh >> 7) & 0x1;
 548
 549         /* Bits [22:21]: ROM Location */
 550         romloc = (rcwh >> 21) & 0x3;
 551
 552         /* Decode RCW bits */
 553         switch ((ps << 2) | romloc) {
 554         case 0x00:
 555         case 0x01:
 556                 rcw_pagesize = 512;
 557                 rcw_sparesize = 16;
 558                 break;
 559         case 0x02:
 560         case 0x03:
 561                 rcw_pagesize = 4096;
 562                 rcw_sparesize = 128;
 563                 break;
 564         case 0x04:
 565         case 0x05:
 566                 rcw_pagesize = 2048;
 567                 rcw_sparesize = 64;
 568                 break;
 569         case 0x06:
 570         case 0x07:
 571                 rcw_pagesize = 4096;
 572                 rcw_sparesize = 218;
 573                 break;
 574         }
 575
 576         mtd->writesize = rcw_pagesize;
 577         mtd->oobsize = rcw_sparesize;
 578         if (rcw_width == 2)
 579                 chip->options |= NAND_BUSWIDTH_16;
 580
 581         dev_notice(prv->dev, "Configured for "
 582                                 "%u-bit NAND, page size %u "
 583                                 "with %u spare.\n",
 584                                 rcw_width * 8, rcw_pagesize,
 585                                 rcw_sparesize);
 586         iounmap(rm);
 587 out:
 588         of_node_put(rmnode);
 589         return ret;
 590 }
 591
 592 /* Free driver resources */
 593 static void mpc5121_nfc_free(struct device *dev, struct mtd_info *mtd)
 594 {
 595         struct nand_chip *chip = mtd_to_nand(mtd);
 596         struct mpc5121_nfc_prv *prv = nand_get_controller_data(chip);
 597
 598         if (prv->clk)
 599                 clk_disable_unprepare(prv->clk);
 600
 601         if (prv->csreg)
 602                 iounmap(prv->csreg);
 603 }
 604
 605 static int mpc5121_nfc_probe(struct platform_device *op)
 606 {
 607         struct device_node *dn = op->dev.of_node;
 608         struct clk *clk;
 609         struct device *dev = &op->dev;
 610         struct mpc5121_nfc_prv *prv;
 611         struct resource res;
 612         struct mtd_info *mtd;
 613         struct nand_chip *chip;
 614         unsigned long regs_paddr, regs_size;
 615         const __be32 *chips_no;
 616         int resettime = 0;
 617         int retval = 0;
 618         int rev, len;
 619
 620         /*
 621          * Check SoC revision. This driver supports only NFC
 622          * in MPC5121 revision 2 and MPC5123 revision 3.
 623          */
 624         rev = (mfspr(SPRN_SVR) >> 4) & 0xF;
 625         if ((rev != 2) && (rev != 3)) {
 626                 dev_err(dev, "SoC revision %u is not supported!\n", rev);
 627                 return -ENXIO;
 628         }
 629
 630         prv = devm_kzalloc(dev, sizeof(*prv), GFP_KERNEL);
 631         if (!prv)
 632                 return -ENOMEM;
 633
 634         chip = &prv->chip;
 635         mtd = nand_to_mtd(chip);
 636
 637         mtd->dev.parent = dev;
 638         nand_set_controller_data(chip, prv);
 639         nand_set_flash_node(chip, dn);
 640         prv->dev = dev;
 641
 642         /* Read NFC configuration from Reset Config Word */
 643         retval = mpc5121_nfc_read_hw_config(mtd);
 644         if (retval) {
 645                 dev_err(dev, "Unable to read NFC config!\n");
 646                 return retval;
 647         }
 648
 649         prv->irq = irq_of_parse_and_map(dn, 0);
 650         if (prv->irq == NO_IRQ) {
 651                 dev_err(dev, "Error mapping IRQ!\n");
 652                 return -EINVAL;
 653         }
 654
 655         retval = of_address_to_resource(dn, 0, &res);
 656         if (retval) {
 657                 dev_err(dev, "Error parsing memory region!\n");
 658                 return retval;
 659         }
 660
 661         chips_no = of_get_property(dn, "chips", &len);
 662         if (!chips_no || len != sizeof(*chips_no)) {
 663                 dev_err(dev, "Invalid/missing 'chips' property!\n");
 664                 return -EINVAL;
 665         }
 666
 667         regs_paddr = res.start;
 668         regs_size = resource_size(&res);
 669
 670         if (!devm_request_mem_region(dev, regs_paddr, regs_size, DRV_NAME)) {
 671                 dev_err(dev, "Error requesting memory region!\n");
 672                 return -EBUSY;
 673         }
 674
 675         prv->regs = devm_ioremap(dev, regs_paddr, regs_size);
 676         if (!prv->regs) {
 677                 dev_err(dev, "Error mapping memory region!\n");
 678                 return -ENOMEM;
 679         }
 680
 681         mtd->name = "MPC5121 NAND";
 682         chip->legacy.dev_ready = mpc5121_nfc_dev_ready;
 683         chip->legacy.cmdfunc = mpc5121_nfc_command;
 684         chip->legacy.read_byte = mpc5121_nfc_read_byte;
 685         chip->legacy.read_buf = mpc5121_nfc_read_buf;
 686         chip->legacy.write_buf = mpc5121_nfc_write_buf;
 687         chip->legacy.select_chip = mpc5121_nfc_select_chip;
 688         chip->legacy.set_features = nand_get_set_features_notsupp;
 689         chip->legacy.get_features = nand_get_set_features_notsupp;
 690         chip->bbt_options = NAND_BBT_USE_FLASH;
 691         chip->ecc.mode = NAND_ECC_SOFT;
 692         chip->ecc.algo = NAND_ECC_HAMMING;
 693
 694         /* Support external chip-select logic on ADS5121 board */
 695         if (of_machine_is_compatible("fsl,mpc5121ads")) {
 696                 retval = ads5121_chipselect_init(mtd);
 697                 if (retval) {
 698                         dev_err(dev, "Chipselect init error!\n");
 699                         return retval;
 700                 }
 701
 702                 chip->legacy.select_chip = ads5121_select_chip;
 703         }
 704
 705         /* Enable NFC clock */
 706         clk = devm_clk_get(dev, "ipg");
 707         if (IS_ERR(clk)) {
 708                 dev_err(dev, "Unable to acquire NFC clock!\n");
 709                 retval = PTR_ERR(clk);
 710                 goto error;
 711         }
 712         retval = clk_prepare_enable(clk);
 713         if (retval) {
 714                 dev_err(dev, "Unable to enable NFC clock!\n");
 715                 goto error;
 716         }
 717         prv->clk = clk;
 718
 719         /* Reset NAND Flash controller */
 720         nfc_set(mtd, NFC_CONFIG1, NFC_RESET);
 721         while (nfc_read(mtd, NFC_CONFIG1) & NFC_RESET) {
 722                 if (resettime++ >= NFC_RESET_TIMEOUT) {
 723                         dev_err(dev, "Timeout while resetting NFC!\n");
 724                         retval = -EINVAL;
 725                         goto error;
 726                 }
 727
 728                 udelay(1);
 729         }
 730
 731         /* Enable write to NFC memory */
 732         nfc_write(mtd, NFC_CONFIG, NFC_BLS_UNLOCKED);
 733
 734         /* Enable write to all NAND pages */
 735         nfc_write(mtd, NFC_UNLOCKSTART_BLK0, 0x0000);
 736         nfc_write(mtd, NFC_UNLOCKEND_BLK0, 0xFFFF);
 737         nfc_write(mtd, NFC_WRPROT, NFC_WPC_UNLOCK);
 738
 739         /*
 740          * Setup NFC:
 741          *      - Big Endian transfers,
 742          *      - Interrupt after full page read/write.
 743          */
 744         nfc_write(mtd, NFC_CONFIG1, NFC_BIG_ENDIAN | NFC_INT_MASK |
 745                                                         NFC_FULL_PAGE_INT);
 746
 747         /* Set spare area size */
 748         nfc_write(mtd, NFC_SPAS, mtd->oobsize >> 1);
 749
 750         init_waitqueue_head(&prv->irq_waitq);
 751         retval = devm_request_irq(dev, prv->irq, &mpc5121_nfc_irq, 0, DRV_NAME,
 752                                                                         mtd);
 753         if (retval) {
 754                 dev_err(dev, "Error requesting IRQ!\n");
 755                 goto error;
 756         }
 757
 758         /* Detect NAND chips */
 759         retval = nand_scan(chip, be32_to_cpup(chips_no));
 760         if (retval) {
 761                 dev_err(dev, "NAND Flash not found !\n");
 762                 goto error;
 763         }
 764
 765         /* Set erase block size */
 766         switch (mtd->erasesize / mtd->writesize) {
 767         case 32:
 768                 nfc_set(mtd, NFC_CONFIG1, NFC_PPB_32);
 769                 break;
 770
 771         case 64:
 772                 nfc_set(mtd, NFC_CONFIG1, NFC_PPB_64);
 773                 break;
 774
 775         case 128:
 776                 nfc_set(mtd, NFC_CONFIG1, NFC_PPB_128);
 777                 break;
 778
 779         case 256:
 780                 nfc_set(mtd, NFC_CONFIG1, NFC_PPB_256);
 781                 break;
 782
 783         default:
 784                 dev_err(dev, "Unsupported NAND flash!\n");
 785                 retval = -ENXIO;
 786                 goto error;
 787         }
 788
 789         dev_set_drvdata(dev, mtd);
 790
 791         /* Register device in MTD */
 792         retval = mtd_device_register(mtd, NULL, 0);
 793         if (retval) {
 794                 dev_err(dev, "Error adding MTD device!\n");
 795                 goto error;
 796         }
 797
 798         return 0;
 799 error:
 800         mpc5121_nfc_free(dev, mtd);
 801         return retval;
 802 }
 803
 804 static int mpc5121_nfc_remove(struct platform_device *op)
 805 {
 806         struct device *dev = &op->dev;
 807         struct mtd_info *mtd = dev_get_drvdata(dev);
 808
 809         nand_release(mtd_to_nand(mtd));
 810         mpc5121_nfc_free(dev, mtd);
 811
 812         return 0;
 813 }
 814
 815 static const struct of_device_id mpc5121_nfc_match[] = {
 816         { .compatible = "fsl,mpc5121-nfc", },
 817         {},
 818 };
 819 MODULE_DEVICE_TABLE(of, mpc5121_nfc_match);
 820
 821 static struct platform_driver mpc5121_nfc_driver = {
 822         .probe          = mpc5121_nfc_probe,
 823         .remove         = mpc5121_nfc_remove,
 824         .driver         = {
 825                 .name = DRV_NAME,
 826                 .of_match_table = mpc5121_nfc_match,
 827         },
 828 };
 829
 830 module_platform_driver(mpc5121_nfc_driver);
 831
 832 MODULE_AUTHOR("Freescale Semiconductor, Inc.");
 833 MODULE_DESCRIPTION("MPC5121 NAND MTD driver");
 834 MODULE_LICENSE("GPL");