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treewide: remove redundant IS_ERR() before error code check
[linux/fpc-iii.git] / drivers / mtd / nand / raw / tegra_nand.c
blob3cc9a4c41443aa4b2205cf5ac522d27fc799fbb5
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2018 Stefan Agner <stefan@agner.ch>
4 * Copyright (C) 2014-2015 Lucas Stach <dev@lynxeye.de>
5 * Copyright (C) 2012 Avionic Design GmbH
6 */
7
8 #include <linux/clk.h>
9 #include <linux/completion.h>
10 #include <linux/dma-mapping.h>
11 #include <linux/err.h>
12 #include <linux/gpio/consumer.h>
13 #include <linux/interrupt.h>
14 #include <linux/io.h>
15 #include <linux/module.h>
16 #include <linux/mtd/partitions.h>
17 #include <linux/mtd/rawnand.h>
18 #include <linux/of.h>
19 #include <linux/platform_device.h>
20 #include <linux/reset.h>
21
22 #define COMMAND 0x00
23 #define COMMAND_GO BIT(31)
24 #define COMMAND_CLE BIT(30)
25 #define COMMAND_ALE BIT(29)
26 #define COMMAND_PIO BIT(28)
27 #define COMMAND_TX BIT(27)
28 #define COMMAND_RX BIT(26)
29 #define COMMAND_SEC_CMD BIT(25)
30 #define COMMAND_AFT_DAT BIT(24)
31 #define COMMAND_TRANS_SIZE(size) ((((size) - 1) & 0xf) << 20)
32 #define COMMAND_A_VALID BIT(19)
33 #define COMMAND_B_VALID BIT(18)
34 #define COMMAND_RD_STATUS_CHK BIT(17)
35 #define COMMAND_RBSY_CHK BIT(16)
36 #define COMMAND_CE(x) BIT(8 + ((x) & 0x7))
37 #define COMMAND_CLE_SIZE(size) ((((size) - 1) & 0x3) << 4)
38 #define COMMAND_ALE_SIZE(size) ((((size) - 1) & 0xf) << 0)
39
40 #define STATUS 0x04
41
42 #define ISR 0x08
43 #define ISR_CORRFAIL_ERR BIT(24)
44 #define ISR_UND BIT(7)
45 #define ISR_OVR BIT(6)
46 #define ISR_CMD_DONE BIT(5)
47 #define ISR_ECC_ERR BIT(4)
48
49 #define IER 0x0c
50 #define IER_ERR_TRIG_VAL(x) (((x) & 0xf) << 16)
51 #define IER_UND BIT(7)
52 #define IER_OVR BIT(6)
53 #define IER_CMD_DONE BIT(5)
54 #define IER_ECC_ERR BIT(4)
55 #define IER_GIE BIT(0)
56
57 #define CONFIG 0x10
58 #define CONFIG_HW_ECC BIT(31)
59 #define CONFIG_ECC_SEL BIT(30)
60 #define CONFIG_ERR_COR BIT(29)
61 #define CONFIG_PIPE_EN BIT(28)
62 #define CONFIG_TVAL_4 (0 << 24)
63 #define CONFIG_TVAL_6 (1 << 24)
64 #define CONFIG_TVAL_8 (2 << 24)
65 #define CONFIG_SKIP_SPARE BIT(23)
66 #define CONFIG_BUS_WIDTH_16 BIT(21)
67 #define CONFIG_COM_BSY BIT(20)
68 #define CONFIG_PS_256 (0 << 16)
69 #define CONFIG_PS_512 (1 << 16)
70 #define CONFIG_PS_1024 (2 << 16)
71 #define CONFIG_PS_2048 (3 << 16)
72 #define CONFIG_PS_4096 (4 << 16)
73 #define CONFIG_SKIP_SPARE_SIZE_4 (0 << 14)
74 #define CONFIG_SKIP_SPARE_SIZE_8 (1 << 14)
75 #define CONFIG_SKIP_SPARE_SIZE_12 (2 << 14)
76 #define CONFIG_SKIP_SPARE_SIZE_16 (3 << 14)
77 #define CONFIG_TAG_BYTE_SIZE(x) ((x) & 0xff)
78
79 #define TIMING_1 0x14
80 #define TIMING_TRP_RESP(x) (((x) & 0xf) << 28)
81 #define TIMING_TWB(x) (((x) & 0xf) << 24)
82 #define TIMING_TCR_TAR_TRR(x) (((x) & 0xf) << 20)
83 #define TIMING_TWHR(x) (((x) & 0xf) << 16)
84 #define TIMING_TCS(x) (((x) & 0x3) << 14)
85 #define TIMING_TWH(x) (((x) & 0x3) << 12)
86 #define TIMING_TWP(x) (((x) & 0xf) << 8)
87 #define TIMING_TRH(x) (((x) & 0x3) << 4)
88 #define TIMING_TRP(x) (((x) & 0xf) << 0)
89
90 #define RESP 0x18
91
92 #define TIMING_2 0x1c
93 #define TIMING_TADL(x) ((x) & 0xf)
94
95 #define CMD_REG1 0x20
96 #define CMD_REG2 0x24
97 #define ADDR_REG1 0x28
98 #define ADDR_REG2 0x2c
99
100 #define DMA_MST_CTRL 0x30
101 #define DMA_MST_CTRL_GO BIT(31)
102 #define DMA_MST_CTRL_IN (0 << 30)
103 #define DMA_MST_CTRL_OUT BIT(30)
104 #define DMA_MST_CTRL_PERF_EN BIT(29)
105 #define DMA_MST_CTRL_IE_DONE BIT(28)
106 #define DMA_MST_CTRL_REUSE BIT(27)
107 #define DMA_MST_CTRL_BURST_1 (2 << 24)
108 #define DMA_MST_CTRL_BURST_4 (3 << 24)
109 #define DMA_MST_CTRL_BURST_8 (4 << 24)
110 #define DMA_MST_CTRL_BURST_16 (5 << 24)
111 #define DMA_MST_CTRL_IS_DONE BIT(20)
112 #define DMA_MST_CTRL_EN_A BIT(2)
113 #define DMA_MST_CTRL_EN_B BIT(1)
114
115 #define DMA_CFG_A 0x34
116 #define DMA_CFG_B 0x38
117
118 #define FIFO_CTRL 0x3c
119 #define FIFO_CTRL_CLR_ALL BIT(3)
120
121 #define DATA_PTR 0x40
122 #define TAG_PTR 0x44
123 #define ECC_PTR 0x48
124
125 #define DEC_STATUS 0x4c
126 #define DEC_STATUS_A_ECC_FAIL BIT(1)
127 #define DEC_STATUS_ERR_COUNT_MASK 0x00ff0000
128 #define DEC_STATUS_ERR_COUNT_SHIFT 16
129
130 #define HWSTATUS_CMD 0x50
131 #define HWSTATUS_MASK 0x54
132 #define HWSTATUS_RDSTATUS_MASK(x) (((x) & 0xff) << 24)
133 #define HWSTATUS_RDSTATUS_VALUE(x) (((x) & 0xff) << 16)
134 #define HWSTATUS_RBSY_MASK(x) (((x) & 0xff) << 8)
135 #define HWSTATUS_RBSY_VALUE(x) (((x) & 0xff) << 0)
136
137 #define BCH_CONFIG 0xcc
138 #define BCH_ENABLE BIT(0)
139 #define BCH_TVAL_4 (0 << 4)
140 #define BCH_TVAL_8 (1 << 4)
141 #define BCH_TVAL_14 (2 << 4)
142 #define BCH_TVAL_16 (3 << 4)
143
144 #define DEC_STAT_RESULT 0xd0
145 #define DEC_STAT_BUF 0xd4
146 #define DEC_STAT_BUF_FAIL_SEC_FLAG_MASK 0xff000000
147 #define DEC_STAT_BUF_FAIL_SEC_FLAG_SHIFT 24
148 #define DEC_STAT_BUF_CORR_SEC_FLAG_MASK 0x00ff0000
149 #define DEC_STAT_BUF_CORR_SEC_FLAG_SHIFT 16
150 #define DEC_STAT_BUF_MAX_CORR_CNT_MASK 0x00001f00
151 #define DEC_STAT_BUF_MAX_CORR_CNT_SHIFT 8
152
153 #define OFFSET(val, off) ((val) < (off) ? 0 : (val) - (off))
154
155 #define SKIP_SPARE_BYTES 4
156 #define BITS_PER_STEP_RS 18
157 #define BITS_PER_STEP_BCH 13
158
159 #define INT_MASK (IER_UND | IER_OVR | IER_CMD_DONE | IER_GIE)
160 #define HWSTATUS_CMD_DEFAULT NAND_STATUS_READY
161 #define HWSTATUS_MASK_DEFAULT (HWSTATUS_RDSTATUS_MASK(1) | \
162 HWSTATUS_RDSTATUS_VALUE(0) | \
163 HWSTATUS_RBSY_MASK(NAND_STATUS_READY) | \
164 HWSTATUS_RBSY_VALUE(NAND_STATUS_READY))
165
166 struct tegra_nand_controller {
167 struct nand_controller controller;
168 struct device *dev;
169 void __iomem *regs;
170 int irq;
171 struct clk *clk;
172 struct completion command_complete;
173 struct completion dma_complete;
174 bool last_read_error;
175 int cur_cs;
176 struct nand_chip *chip;
177 };
178
179 struct tegra_nand_chip {
180 struct nand_chip chip;
181 struct gpio_desc *wp_gpio;
182 struct mtd_oob_region ecc;
183 u32 config;
184 u32 config_ecc;
185 u32 bch_config;
186 int cs[1];
187 };
188
189 static inline struct tegra_nand_controller *
190 to_tegra_ctrl(struct nand_controller *hw_ctrl)
191 {
192 return container_of(hw_ctrl, struct tegra_nand_controller, controller);
193 }
194
195 static inline struct tegra_nand_chip *to_tegra_chip(struct nand_chip *chip)
196 {
197 return container_of(chip, struct tegra_nand_chip, chip);
198 }
199
200 static int tegra_nand_ooblayout_rs_ecc(struct mtd_info *mtd, int section,
201 struct mtd_oob_region *oobregion)
202 {
203 struct nand_chip *chip = mtd_to_nand(mtd);
204 int bytes_per_step = DIV_ROUND_UP(BITS_PER_STEP_RS * chip->ecc.strength,
205 BITS_PER_BYTE);
206
207 if (section > 0)
208 return -ERANGE;
209
210 oobregion->offset = SKIP_SPARE_BYTES;
211 oobregion->length = round_up(bytes_per_step * chip->ecc.steps, 4);
212
213 return 0;
214 }
215
216 static int tegra_nand_ooblayout_no_free(struct mtd_info *mtd, int section,
217 struct mtd_oob_region *oobregion)
218 {
219 return -ERANGE;
220 }
221
222 static const struct mtd_ooblayout_ops tegra_nand_oob_rs_ops = {
223 .ecc = tegra_nand_ooblayout_rs_ecc,
224 .free = tegra_nand_ooblayout_no_free,
225 };
226
227 static int tegra_nand_ooblayout_bch_ecc(struct mtd_info *mtd, int section,
228 struct mtd_oob_region *oobregion)
229 {
230 struct nand_chip *chip = mtd_to_nand(mtd);
231 int bytes_per_step = DIV_ROUND_UP(BITS_PER_STEP_BCH * chip->ecc.strength,
232 BITS_PER_BYTE);
233
234 if (section > 0)
235 return -ERANGE;
236
237 oobregion->offset = SKIP_SPARE_BYTES;
238 oobregion->length = round_up(bytes_per_step * chip->ecc.steps, 4);
239
240 return 0;
241 }
242
243 static const struct mtd_ooblayout_ops tegra_nand_oob_bch_ops = {
244 .ecc = tegra_nand_ooblayout_bch_ecc,
245 .free = tegra_nand_ooblayout_no_free,
246 };
247
248 static irqreturn_t tegra_nand_irq(int irq, void *data)
249 {
250 struct tegra_nand_controller *ctrl = data;
251 u32 isr, dma;
252
253 isr = readl_relaxed(ctrl->regs + ISR);
254 dma = readl_relaxed(ctrl->regs + DMA_MST_CTRL);
255 dev_dbg(ctrl->dev, "isr %08x\n", isr);
256
257 if (!isr && !(dma & DMA_MST_CTRL_IS_DONE))
258 return IRQ_NONE;
259
260 /*
261 * The bit name is somewhat missleading: This is also set when
262 * HW ECC was successful. The data sheet states:
263 * Correctable OR Un-correctable errors occurred in the DMA transfer...
264 */
265 if (isr & ISR_CORRFAIL_ERR)
266 ctrl->last_read_error = true;
267
268 if (isr & ISR_CMD_DONE)
269 complete(&ctrl->command_complete);
270
271 if (isr & ISR_UND)
272 dev_err(ctrl->dev, "FIFO underrun\n");
273
274 if (isr & ISR_OVR)
275 dev_err(ctrl->dev, "FIFO overrun\n");
276
277 /* handle DMA interrupts */
278 if (dma & DMA_MST_CTRL_IS_DONE) {
279 writel_relaxed(dma, ctrl->regs + DMA_MST_CTRL);
280 complete(&ctrl->dma_complete);
281 }
282
283 /* clear interrupts */
284 writel_relaxed(isr, ctrl->regs + ISR);
285
286 return IRQ_HANDLED;
287 }
288
289 static const char * const tegra_nand_reg_names[] = {
290 "COMMAND",
291 "STATUS",
292 "ISR",
293 "IER",
294 "CONFIG",
295 "TIMING",
296 NULL,
297 "TIMING2",
298 "CMD_REG1",
299 "CMD_REG2",
300 "ADDR_REG1",
301 "ADDR_REG2",
302 "DMA_MST_CTRL",
303 "DMA_CFG_A",
304 "DMA_CFG_B",
305 "FIFO_CTRL",
306 };
307
308 static void tegra_nand_dump_reg(struct tegra_nand_controller *ctrl)
309 {
310 u32 reg;
311 int i;
312
313 dev_err(ctrl->dev, "Tegra NAND controller register dump\n");
314 for (i = 0; i < ARRAY_SIZE(tegra_nand_reg_names); i++) {
315 const char *reg_name = tegra_nand_reg_names[i];
316
317 if (!reg_name)
318 continue;
319
320 reg = readl_relaxed(ctrl->regs + (i * 4));
321 dev_err(ctrl->dev, "%s: 0x%08x\n", reg_name, reg);
322 }
323 }
324
325 static void tegra_nand_controller_abort(struct tegra_nand_controller *ctrl)
326 {
327 u32 isr, dma;
328
329 disable_irq(ctrl->irq);
330
331 /* Abort current command/DMA operation */
332 writel_relaxed(0, ctrl->regs + DMA_MST_CTRL);
333 writel_relaxed(0, ctrl->regs + COMMAND);
334
335 /* clear interrupts */
336 isr = readl_relaxed(ctrl->regs + ISR);
337 writel_relaxed(isr, ctrl->regs + ISR);
338 dma = readl_relaxed(ctrl->regs + DMA_MST_CTRL);
339 writel_relaxed(dma, ctrl->regs + DMA_MST_CTRL);
340
341 reinit_completion(&ctrl->command_complete);
342 reinit_completion(&ctrl->dma_complete);
343
344 enable_irq(ctrl->irq);
345 }
346
347 static int tegra_nand_cmd(struct nand_chip *chip,
348 const struct nand_subop *subop)
349 {
350 const struct nand_op_instr *instr;
351 const struct nand_op_instr *instr_data_in = NULL;
352 struct tegra_nand_controller *ctrl = to_tegra_ctrl(chip->controller);
353 unsigned int op_id, size = 0, offset = 0;
354 bool first_cmd = true;
355 u32 reg, cmd = 0;
356 int ret;
357
358 for (op_id = 0; op_id < subop->ninstrs; op_id++) {
359 unsigned int naddrs, i;
360 const u8 *addrs;
361 u32 addr1 = 0, addr2 = 0;
362
363 instr = &subop->instrs[op_id];
364
365 switch (instr->type) {
366 case NAND_OP_CMD_INSTR:
367 if (first_cmd) {
368 cmd |= COMMAND_CLE;
369 writel_relaxed(instr->ctx.cmd.opcode,
370 ctrl->regs + CMD_REG1);
371 } else {
372 cmd |= COMMAND_SEC_CMD;
373 writel_relaxed(instr->ctx.cmd.opcode,
374 ctrl->regs + CMD_REG2);
375 }
376 first_cmd = false;
377 break;
378
379 case NAND_OP_ADDR_INSTR:
380 offset = nand_subop_get_addr_start_off(subop, op_id);
381 naddrs = nand_subop_get_num_addr_cyc(subop, op_id);
382 addrs = &instr->ctx.addr.addrs[offset];
383
384 cmd |= COMMAND_ALE | COMMAND_ALE_SIZE(naddrs);
385 for (i = 0; i < min_t(unsigned int, 4, naddrs); i++)
386 addr1 |= *addrs++ << (BITS_PER_BYTE * i);
387 naddrs -= i;
388 for (i = 0; i < min_t(unsigned int, 4, naddrs); i++)
389 addr2 |= *addrs++ << (BITS_PER_BYTE * i);
390
391 writel_relaxed(addr1, ctrl->regs + ADDR_REG1);
392 writel_relaxed(addr2, ctrl->regs + ADDR_REG2);
393 break;
394
395 case NAND_OP_DATA_IN_INSTR:
396 size = nand_subop_get_data_len(subop, op_id);
397 offset = nand_subop_get_data_start_off(subop, op_id);
398
399 cmd |= COMMAND_TRANS_SIZE(size) | COMMAND_PIO |
400 COMMAND_RX | COMMAND_A_VALID;
401
402 instr_data_in = instr;
403 break;
404
405 case NAND_OP_DATA_OUT_INSTR:
406 size = nand_subop_get_data_len(subop, op_id);
407 offset = nand_subop_get_data_start_off(subop, op_id);
408
409 cmd |= COMMAND_TRANS_SIZE(size) | COMMAND_PIO |
410 COMMAND_TX | COMMAND_A_VALID;
411 memcpy(&reg, instr->ctx.data.buf.out + offset, size);
412
413 writel_relaxed(reg, ctrl->regs + RESP);
414 break;
415
416 case NAND_OP_WAITRDY_INSTR:
417 cmd |= COMMAND_RBSY_CHK;
418 break;
419 }
420 }
421
422 cmd |= COMMAND_GO | COMMAND_CE(ctrl->cur_cs);
423 writel_relaxed(cmd, ctrl->regs + COMMAND);
424 ret = wait_for_completion_timeout(&ctrl->command_complete,
425 msecs_to_jiffies(500));
426 if (!ret) {
427 dev_err(ctrl->dev, "COMMAND timeout\n");
428 tegra_nand_dump_reg(ctrl);
429 tegra_nand_controller_abort(ctrl);
430 return -ETIMEDOUT;
431 }
432
433 if (instr_data_in) {
434 reg = readl_relaxed(ctrl->regs + RESP);
435 memcpy(instr_data_in->ctx.data.buf.in + offset, &reg, size);
436 }
437
438 return 0;
439 }
440
441 static const struct nand_op_parser tegra_nand_op_parser = NAND_OP_PARSER(
442 NAND_OP_PARSER_PATTERN(tegra_nand_cmd,
443 NAND_OP_PARSER_PAT_CMD_ELEM(true),
444 NAND_OP_PARSER_PAT_ADDR_ELEM(true, 8),
445 NAND_OP_PARSER_PAT_CMD_ELEM(true),
446 NAND_OP_PARSER_PAT_WAITRDY_ELEM(true)),
447 NAND_OP_PARSER_PATTERN(tegra_nand_cmd,
448 NAND_OP_PARSER_PAT_DATA_OUT_ELEM(false, 4)),
449 NAND_OP_PARSER_PATTERN(tegra_nand_cmd,
450 NAND_OP_PARSER_PAT_CMD_ELEM(true),
451 NAND_OP_PARSER_PAT_ADDR_ELEM(true, 8),
452 NAND_OP_PARSER_PAT_CMD_ELEM(true),
453 NAND_OP_PARSER_PAT_WAITRDY_ELEM(true),
454 NAND_OP_PARSER_PAT_DATA_IN_ELEM(true, 4)),
455 );
456
457 static void tegra_nand_select_target(struct nand_chip *chip,
458 unsigned int die_nr)
459 {
460 struct tegra_nand_chip *nand = to_tegra_chip(chip);
461 struct tegra_nand_controller *ctrl = to_tegra_ctrl(chip->controller);
462
463 ctrl->cur_cs = nand->cs[die_nr];
464 }
465
466 static int tegra_nand_exec_op(struct nand_chip *chip,
467 const struct nand_operation *op,
468 bool check_only)
469 {
470 tegra_nand_select_target(chip, op->cs);
471 return nand_op_parser_exec_op(chip, &tegra_nand_op_parser, op,
472 check_only);
473 }
474
475 static void tegra_nand_hw_ecc(struct tegra_nand_controller *ctrl,
476 struct nand_chip *chip, bool enable)
477 {
478 struct tegra_nand_chip *nand = to_tegra_chip(chip);
479
480 if (chip->ecc.algo == NAND_ECC_BCH && enable)
481 writel_relaxed(nand->bch_config, ctrl->regs + BCH_CONFIG);
482 else
483 writel_relaxed(0, ctrl->regs + BCH_CONFIG);
484
485 if (enable)
486 writel_relaxed(nand->config_ecc, ctrl->regs + CONFIG);
487 else
488 writel_relaxed(nand->config, ctrl->regs + CONFIG);
489 }
490
491 static int tegra_nand_page_xfer(struct mtd_info *mtd, struct nand_chip *chip,
492 void *buf, void *oob_buf, int oob_len, int page,
493 bool read)
494 {
495 struct tegra_nand_controller *ctrl = to_tegra_ctrl(chip->controller);
496 enum dma_data_direction dir = read ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
497 dma_addr_t dma_addr = 0, dma_addr_oob = 0;
498 u32 addr1, cmd, dma_ctrl;
499 int ret;
500
501 tegra_nand_select_target(chip, chip->cur_cs);
502
503 if (read) {
504 writel_relaxed(NAND_CMD_READ0, ctrl->regs + CMD_REG1);
505 writel_relaxed(NAND_CMD_READSTART, ctrl->regs + CMD_REG2);
506 } else {
507 writel_relaxed(NAND_CMD_SEQIN, ctrl->regs + CMD_REG1);
508 writel_relaxed(NAND_CMD_PAGEPROG, ctrl->regs + CMD_REG2);
509 }
510 cmd = COMMAND_CLE | COMMAND_SEC_CMD;
511
512 /* Lower 16-bits are column, by default 0 */
513 addr1 = page << 16;
514
515 if (!buf)
516 addr1 |= mtd->writesize;
517 writel_relaxed(addr1, ctrl->regs + ADDR_REG1);
518
519 if (chip->options & NAND_ROW_ADDR_3) {
520 writel_relaxed(page >> 16, ctrl->regs + ADDR_REG2);
521 cmd |= COMMAND_ALE | COMMAND_ALE_SIZE(5);
522 } else {
523 cmd |= COMMAND_ALE | COMMAND_ALE_SIZE(4);
524 }
525
526 if (buf) {
527 dma_addr = dma_map_single(ctrl->dev, buf, mtd->writesize, dir);
528 ret = dma_mapping_error(ctrl->dev, dma_addr);
529 if (ret) {
530 dev_err(ctrl->dev, "dma mapping error\n");
531 return -EINVAL;
532 }
533
534 writel_relaxed(mtd->writesize - 1, ctrl->regs + DMA_CFG_A);
535 writel_relaxed(dma_addr, ctrl->regs + DATA_PTR);
536 }
537
538 if (oob_buf) {
539 dma_addr_oob = dma_map_single(ctrl->dev, oob_buf, mtd->oobsize,
540 dir);
541 ret = dma_mapping_error(ctrl->dev, dma_addr_oob);
542 if (ret) {
543 dev_err(ctrl->dev, "dma mapping error\n");
544 ret = -EINVAL;
545 goto err_unmap_dma_page;
546 }
547
548 writel_relaxed(oob_len - 1, ctrl->regs + DMA_CFG_B);
549 writel_relaxed(dma_addr_oob, ctrl->regs + TAG_PTR);
550 }
551
552 dma_ctrl = DMA_MST_CTRL_GO | DMA_MST_CTRL_PERF_EN |
553 DMA_MST_CTRL_IE_DONE | DMA_MST_CTRL_IS_DONE |
554 DMA_MST_CTRL_BURST_16;
555
556 if (buf)
557 dma_ctrl |= DMA_MST_CTRL_EN_A;
558 if (oob_buf)
559 dma_ctrl |= DMA_MST_CTRL_EN_B;
560
561 if (read)
562 dma_ctrl |= DMA_MST_CTRL_IN | DMA_MST_CTRL_REUSE;
563 else
564 dma_ctrl |= DMA_MST_CTRL_OUT;
565
566 writel_relaxed(dma_ctrl, ctrl->regs + DMA_MST_CTRL);
567
568 cmd |= COMMAND_GO | COMMAND_RBSY_CHK | COMMAND_TRANS_SIZE(9) |
569 COMMAND_CE(ctrl->cur_cs);
570
571 if (buf)
572 cmd |= COMMAND_A_VALID;
573 if (oob_buf)
574 cmd |= COMMAND_B_VALID;
575
576 if (read)
577 cmd |= COMMAND_RX;
578 else
579 cmd |= COMMAND_TX | COMMAND_AFT_DAT;
580
581 writel_relaxed(cmd, ctrl->regs + COMMAND);
582
583 ret = wait_for_completion_timeout(&ctrl->command_complete,
584 msecs_to_jiffies(500));
585 if (!ret) {
586 dev_err(ctrl->dev, "COMMAND timeout\n");
587 tegra_nand_dump_reg(ctrl);
588 tegra_nand_controller_abort(ctrl);
589 ret = -ETIMEDOUT;
590 goto err_unmap_dma;
591 }
592
593 ret = wait_for_completion_timeout(&ctrl->dma_complete,
594 msecs_to_jiffies(500));
595 if (!ret) {
596 dev_err(ctrl->dev, "DMA timeout\n");
597 tegra_nand_dump_reg(ctrl);
598 tegra_nand_controller_abort(ctrl);
599 ret = -ETIMEDOUT;
600 goto err_unmap_dma;
601 }
602 ret = 0;
603
604 err_unmap_dma:
605 if (oob_buf)
606 dma_unmap_single(ctrl->dev, dma_addr_oob, mtd->oobsize, dir);
607 err_unmap_dma_page:
608 if (buf)
609 dma_unmap_single(ctrl->dev, dma_addr, mtd->writesize, dir);
610
611 return ret;
612 }
613
614 static int tegra_nand_read_page_raw(struct nand_chip *chip, u8 *buf,
615 int oob_required, int page)
616 {
617 struct mtd_info *mtd = nand_to_mtd(chip);
618 void *oob_buf = oob_required ? chip->oob_poi : NULL;
619
620 return tegra_nand_page_xfer(mtd, chip, buf, oob_buf,
621 mtd->oobsize, page, true);
622 }
623
624 static int tegra_nand_write_page_raw(struct nand_chip *chip, const u8 *buf,
625 int oob_required, int page)
626 {
627 struct mtd_info *mtd = nand_to_mtd(chip);
628 void *oob_buf = oob_required ? chip->oob_poi : NULL;
629
630 return tegra_nand_page_xfer(mtd, chip, (void *)buf, oob_buf,
631 mtd->oobsize, page, false);
632 }
633
634 static int tegra_nand_read_oob(struct nand_chip *chip, int page)
635 {
636 struct mtd_info *mtd = nand_to_mtd(chip);
637
638 return tegra_nand_page_xfer(mtd, chip, NULL, chip->oob_poi,
639 mtd->oobsize, page, true);
640 }
641
642 static int tegra_nand_write_oob(struct nand_chip *chip, int page)
643 {
644 struct mtd_info *mtd = nand_to_mtd(chip);
645
646 return tegra_nand_page_xfer(mtd, chip, NULL, chip->oob_poi,
647 mtd->oobsize, page, false);
648 }
649
650 static int tegra_nand_read_page_hwecc(struct nand_chip *chip, u8 *buf,
651 int oob_required, int page)
652 {
653 struct mtd_info *mtd = nand_to_mtd(chip);
654 struct tegra_nand_controller *ctrl = to_tegra_ctrl(chip->controller);
655 struct tegra_nand_chip *nand = to_tegra_chip(chip);
656 void *oob_buf = oob_required ? chip->oob_poi : NULL;
657 u32 dec_stat, max_corr_cnt;
658 unsigned long fail_sec_flag;
659 int ret;
660
661 tegra_nand_hw_ecc(ctrl, chip, true);
662 ret = tegra_nand_page_xfer(mtd, chip, buf, oob_buf, 0, page, true);
663 tegra_nand_hw_ecc(ctrl, chip, false);
664 if (ret)
665 return ret;
666
667 /* No correctable or un-correctable errors, page must have 0 bitflips */
668 if (!ctrl->last_read_error)
669 return 0;
670
671 /*
672 * Correctable or un-correctable errors occurred. Use DEC_STAT_BUF
673 * which contains information for all ECC selections.
674 *
675 * Note that since we do not use Command Queues DEC_RESULT does not
676 * state the number of pages we can read from the DEC_STAT_BUF. But
677 * since CORRFAIL_ERR did occur during page read we do have a valid
678 * result in DEC_STAT_BUF.
679 */
680 ctrl->last_read_error = false;
681 dec_stat = readl_relaxed(ctrl->regs + DEC_STAT_BUF);
682
683 fail_sec_flag = (dec_stat & DEC_STAT_BUF_FAIL_SEC_FLAG_MASK) >>
684 DEC_STAT_BUF_FAIL_SEC_FLAG_SHIFT;
685
686 max_corr_cnt = (dec_stat & DEC_STAT_BUF_MAX_CORR_CNT_MASK) >>
687 DEC_STAT_BUF_MAX_CORR_CNT_SHIFT;
688
689 if (fail_sec_flag) {
690 int bit, max_bitflips = 0;
691
692 /*
693 * Since we do not support subpage writes, a complete page
694 * is either written or not. We can take a shortcut here by
695 * checking wheather any of the sector has been successful
696 * read. If at least one sectors has been read successfully,
697 * the page must have been a written previously. It cannot
698 * be an erased page.
699 *
700 * E.g. controller might return fail_sec_flag with 0x4, which
701 * would mean only the third sector failed to correct. The
702 * page must have been written and the third sector is really
703 * not correctable anymore.
704 */
705 if (fail_sec_flag ^ GENMASK(chip->ecc.steps - 1, 0)) {
706 mtd->ecc_stats.failed += hweight8(fail_sec_flag);
707 return max_corr_cnt;
708 }
709
710 /*
711 * All sectors failed to correct, but the ECC isn't smart
712 * enough to figure out if a page is really just erased.
713 * Read OOB data and check whether data/OOB is completely
714 * erased or if error correction just failed for all sub-
715 * pages.
716 */
717 ret = tegra_nand_read_oob(chip, page);
718 if (ret < 0)
719 return ret;
720
721 for_each_set_bit(bit, &fail_sec_flag, chip->ecc.steps) {
722 u8 *data = buf + (chip->ecc.size * bit);
723 u8 *oob = chip->oob_poi + nand->ecc.offset +
724 (chip->ecc.bytes * bit);
725
726 ret = nand_check_erased_ecc_chunk(data, chip->ecc.size,
727 oob, chip->ecc.bytes,
728 NULL, 0,
729 chip->ecc.strength);
730 if (ret < 0) {
731 mtd->ecc_stats.failed++;
732 } else {
733 mtd->ecc_stats.corrected += ret;
734 max_bitflips = max(ret, max_bitflips);
735 }
736 }
737
738 return max_t(unsigned int, max_corr_cnt, max_bitflips);
739 } else {
740 int corr_sec_flag;
741
742 corr_sec_flag = (dec_stat & DEC_STAT_BUF_CORR_SEC_FLAG_MASK) >>
743 DEC_STAT_BUF_CORR_SEC_FLAG_SHIFT;
744
745 /*
746 * The value returned in the register is the maximum of
747 * bitflips encountered in any of the ECC regions. As there is
748 * no way to get the number of bitflips in a specific regions
749 * we are not able to deliver correct stats but instead
750 * overestimate the number of corrected bitflips by assuming
751 * that all regions where errors have been corrected
752 * encountered the maximum number of bitflips.
753 */
754 mtd->ecc_stats.corrected += max_corr_cnt * hweight8(corr_sec_flag);
755
756 return max_corr_cnt;
757 }
758 }
759
760 static int tegra_nand_write_page_hwecc(struct nand_chip *chip, const u8 *buf,
761 int oob_required, int page)
762 {
763 struct mtd_info *mtd = nand_to_mtd(chip);
764 struct tegra_nand_controller *ctrl = to_tegra_ctrl(chip->controller);
765 void *oob_buf = oob_required ? chip->oob_poi : NULL;
766 int ret;
767
768 tegra_nand_hw_ecc(ctrl, chip, true);
769 ret = tegra_nand_page_xfer(mtd, chip, (void *)buf, oob_buf,
770 0, page, false);
771 tegra_nand_hw_ecc(ctrl, chip, false);
772
773 return ret;
774 }
775
776 static void tegra_nand_setup_timing(struct tegra_nand_controller *ctrl,
777 const struct nand_sdr_timings *timings)
778 {
779 /*
780 * The period (and all other timings in this function) is in ps,
781 * so need to take care here to avoid integer overflows.
782 */
783 unsigned int rate = clk_get_rate(ctrl->clk) / 1000000;
784 unsigned int period = DIV_ROUND_UP(1000000, rate);
785 u32 val, reg = 0;
786
787 val = DIV_ROUND_UP(max3(timings->tAR_min, timings->tRR_min,
788 timings->tRC_min), period);
789 reg |= TIMING_TCR_TAR_TRR(OFFSET(val, 3));
790
791 val = DIV_ROUND_UP(max(max(timings->tCS_min, timings->tCH_min),
792 max(timings->tALS_min, timings->tALH_min)),
793 period);
794 reg |= TIMING_TCS(OFFSET(val, 2));
795
796 val = DIV_ROUND_UP(max(timings->tRP_min, timings->tREA_max) + 6000,
797 period);
798 reg |= TIMING_TRP(OFFSET(val, 1)) | TIMING_TRP_RESP(OFFSET(val, 1));
799
800 reg |= TIMING_TWB(OFFSET(DIV_ROUND_UP(timings->tWB_max, period), 1));
801 reg |= TIMING_TWHR(OFFSET(DIV_ROUND_UP(timings->tWHR_min, period), 1));
802 reg |= TIMING_TWH(OFFSET(DIV_ROUND_UP(timings->tWH_min, period), 1));
803 reg |= TIMING_TWP(OFFSET(DIV_ROUND_UP(timings->tWP_min, period), 1));
804 reg |= TIMING_TRH(OFFSET(DIV_ROUND_UP(timings->tREH_min, period), 1));
805
806 writel_relaxed(reg, ctrl->regs + TIMING_1);
807
808 val = DIV_ROUND_UP(timings->tADL_min, period);
809 reg = TIMING_TADL(OFFSET(val, 3));
810
811 writel_relaxed(reg, ctrl->regs + TIMING_2);
812 }
813
814 static int tegra_nand_setup_data_interface(struct nand_chip *chip, int csline,
815 const struct nand_data_interface *conf)
816 {
817 struct tegra_nand_controller *ctrl = to_tegra_ctrl(chip->controller);
818 const struct nand_sdr_timings *timings;
819
820 timings = nand_get_sdr_timings(conf);
821 if (IS_ERR(timings))
822 return PTR_ERR(timings);
823
824 if (csline == NAND_DATA_IFACE_CHECK_ONLY)
825 return 0;
826
827 tegra_nand_setup_timing(ctrl, timings);
828
829 return 0;
830 }
831
832 static const int rs_strength_bootable[] = { 4 };
833 static const int rs_strength[] = { 4, 6, 8 };
834 static const int bch_strength_bootable[] = { 8, 16 };
835 static const int bch_strength[] = { 4, 8, 14, 16 };
836
837 static int tegra_nand_get_strength(struct nand_chip *chip, const int *strength,
838 int strength_len, int bits_per_step,
839 int oobsize)
840 {
841 bool maximize = chip->ecc.options & NAND_ECC_MAXIMIZE;
842 int i;
843
844 /*
845 * Loop through available strengths. Backwards in case we try to
846 * maximize the BCH strength.
847 */
848 for (i = 0; i < strength_len; i++) {
849 int strength_sel, bytes_per_step, bytes_per_page;
850
851 if (maximize) {
852 strength_sel = strength[strength_len - i - 1];
853 } else {
854 strength_sel = strength[i];
855
856 if (strength_sel < chip->base.eccreq.strength)
857 continue;
858 }
859
860 bytes_per_step = DIV_ROUND_UP(bits_per_step * strength_sel,
861 BITS_PER_BYTE);
862 bytes_per_page = round_up(bytes_per_step * chip->ecc.steps, 4);
863
864 /* Check whether strength fits OOB */
865 if (bytes_per_page < (oobsize - SKIP_SPARE_BYTES))
866 return strength_sel;
867 }
868
869 return -EINVAL;
870 }
871
872 static int tegra_nand_select_strength(struct nand_chip *chip, int oobsize)
873 {
874 const int *strength;
875 int strength_len, bits_per_step;
876
877 switch (chip->ecc.algo) {
878 case NAND_ECC_RS:
879 bits_per_step = BITS_PER_STEP_RS;
880 if (chip->options & NAND_IS_BOOT_MEDIUM) {
881 strength = rs_strength_bootable;
882 strength_len = ARRAY_SIZE(rs_strength_bootable);
883 } else {
884 strength = rs_strength;
885 strength_len = ARRAY_SIZE(rs_strength);
886 }
887 break;
888 case NAND_ECC_BCH:
889 bits_per_step = BITS_PER_STEP_BCH;
890 if (chip->options & NAND_IS_BOOT_MEDIUM) {
891 strength = bch_strength_bootable;
892 strength_len = ARRAY_SIZE(bch_strength_bootable);
893 } else {
894 strength = bch_strength;
895 strength_len = ARRAY_SIZE(bch_strength);
896 }
897 break;
898 default:
899 return -EINVAL;
900 }
901
902 return tegra_nand_get_strength(chip, strength, strength_len,
903 bits_per_step, oobsize);
904 }
905
906 static int tegra_nand_attach_chip(struct nand_chip *chip)
907 {
908 struct tegra_nand_controller *ctrl = to_tegra_ctrl(chip->controller);
909 struct tegra_nand_chip *nand = to_tegra_chip(chip);
910 struct mtd_info *mtd = nand_to_mtd(chip);
911 int bits_per_step;
912 int ret;
913
914 if (chip->bbt_options & NAND_BBT_USE_FLASH)
915 chip->bbt_options |= NAND_BBT_NO_OOB;
916
917 chip->ecc.mode = NAND_ECC_HW;
918 chip->ecc.size = 512;
919 chip->ecc.steps = mtd->writesize / chip->ecc.size;
920 if (chip->base.eccreq.step_size != 512) {
921 dev_err(ctrl->dev, "Unsupported step size %d\n",
922 chip->base.eccreq.step_size);
923 return -EINVAL;
924 }
925
926 chip->ecc.read_page = tegra_nand_read_page_hwecc;
927 chip->ecc.write_page = tegra_nand_write_page_hwecc;
928 chip->ecc.read_page_raw = tegra_nand_read_page_raw;
929 chip->ecc.write_page_raw = tegra_nand_write_page_raw;
930 chip->ecc.read_oob = tegra_nand_read_oob;
931 chip->ecc.write_oob = tegra_nand_write_oob;
932
933 if (chip->options & NAND_BUSWIDTH_16)
934 nand->config |= CONFIG_BUS_WIDTH_16;
935
936 if (chip->ecc.algo == NAND_ECC_UNKNOWN) {
937 if (mtd->writesize < 2048)
938 chip->ecc.algo = NAND_ECC_RS;
939 else
940 chip->ecc.algo = NAND_ECC_BCH;
941 }
942
943 if (chip->ecc.algo == NAND_ECC_BCH && mtd->writesize < 2048) {
944 dev_err(ctrl->dev, "BCH supports 2K or 4K page size only\n");
945 return -EINVAL;
946 }
947
948 if (!chip->ecc.strength) {
949 ret = tegra_nand_select_strength(chip, mtd->oobsize);
950 if (ret < 0) {
951 dev_err(ctrl->dev,
952 "No valid strength found, minimum %d\n",
953 chip->base.eccreq.strength);
954 return ret;
955 }
956
957 chip->ecc.strength = ret;
958 }
959
960 nand->config_ecc = CONFIG_PIPE_EN | CONFIG_SKIP_SPARE |
961 CONFIG_SKIP_SPARE_SIZE_4;
962
963 switch (chip->ecc.algo) {
964 case NAND_ECC_RS:
965 bits_per_step = BITS_PER_STEP_RS * chip->ecc.strength;
966 mtd_set_ooblayout(mtd, &tegra_nand_oob_rs_ops);
967 nand->config_ecc |= CONFIG_HW_ECC | CONFIG_ECC_SEL |
968 CONFIG_ERR_COR;
969 switch (chip->ecc.strength) {
970 case 4:
971 nand->config_ecc |= CONFIG_TVAL_4;
972 break;
973 case 6:
974 nand->config_ecc |= CONFIG_TVAL_6;
975 break;
976 case 8:
977 nand->config_ecc |= CONFIG_TVAL_8;
978 break;
979 default:
980 dev_err(ctrl->dev, "ECC strength %d not supported\n",
981 chip->ecc.strength);
982 return -EINVAL;
983 }
984 break;
985 case NAND_ECC_BCH:
986 bits_per_step = BITS_PER_STEP_BCH * chip->ecc.strength;
987 mtd_set_ooblayout(mtd, &tegra_nand_oob_bch_ops);
988 nand->bch_config = BCH_ENABLE;
989 switch (chip->ecc.strength) {
990 case 4:
991 nand->bch_config |= BCH_TVAL_4;
992 break;
993 case 8:
994 nand->bch_config |= BCH_TVAL_8;
995 break;
996 case 14:
997 nand->bch_config |= BCH_TVAL_14;
998 break;
999 case 16:
1000 nand->bch_config |= BCH_TVAL_16;
1001 break;
1002 default:
1003 dev_err(ctrl->dev, "ECC strength %d not supported\n",
1004 chip->ecc.strength);
1005 return -EINVAL;
1006 }
1007 break;
1008 default:
1009 dev_err(ctrl->dev, "ECC algorithm not supported\n");
1010 return -EINVAL;
1011 }
1012
1013 dev_info(ctrl->dev, "Using %s with strength %d per 512 byte step\n",
1014 chip->ecc.algo == NAND_ECC_BCH ? "BCH" : "RS",
1015 chip->ecc.strength);
1016
1017 chip->ecc.bytes = DIV_ROUND_UP(bits_per_step, BITS_PER_BYTE);
1018
1019 switch (mtd->writesize) {
1020 case 256:
1021 nand->config |= CONFIG_PS_256;
1022 break;
1023 case 512:
1024 nand->config |= CONFIG_PS_512;
1025 break;
1026 case 1024:
1027 nand->config |= CONFIG_PS_1024;
1028 break;
1029 case 2048:
1030 nand->config |= CONFIG_PS_2048;
1031 break;
1032 case 4096:
1033 nand->config |= CONFIG_PS_4096;
1034 break;
1035 default:
1036 dev_err(ctrl->dev, "Unsupported writesize %d\n",
1037 mtd->writesize);
1038 return -ENODEV;
1039 }
1040
1041 /* Store complete configuration for HW ECC in config_ecc */
1042 nand->config_ecc |= nand->config;
1043
1044 /* Non-HW ECC read/writes complete OOB */
1045 nand->config |= CONFIG_TAG_BYTE_SIZE(mtd->oobsize - 1);
1046 writel_relaxed(nand->config, ctrl->regs + CONFIG);
1047
1048 return 0;
1049 }
1050
1051 static const struct nand_controller_ops tegra_nand_controller_ops = {
1052 .attach_chip = &tegra_nand_attach_chip,
1053 .exec_op = tegra_nand_exec_op,
1054 .setup_data_interface = tegra_nand_setup_data_interface,
1055 };
1056
1057 static int tegra_nand_chips_init(struct device *dev,
1058 struct tegra_nand_controller *ctrl)
1059 {
1060 struct device_node *np = dev->of_node;
1061 struct device_node *np_nand;
1062 int nsels, nchips = of_get_child_count(np);
1063 struct tegra_nand_chip *nand;
1064 struct mtd_info *mtd;
1065 struct nand_chip *chip;
1066 int ret;
1067 u32 cs;
1068
1069 if (nchips != 1) {
1070 dev_err(dev, "Currently only one NAND chip supported\n");
1071 return -EINVAL;
1072 }
1073
1074 np_nand = of_get_next_child(np, NULL);
1075
1076 nsels = of_property_count_elems_of_size(np_nand, "reg", sizeof(u32));
1077 if (nsels != 1) {
1078 dev_err(dev, "Missing/invalid reg property\n");
1079 return -EINVAL;
1080 }
1081
1082 /* Retrieve CS id, currently only single die NAND supported */
1083 ret = of_property_read_u32(np_nand, "reg", &cs);
1084 if (ret) {
1085 dev_err(dev, "could not retrieve reg property: %d\n", ret);
1086 return ret;
1087 }
1088
1089 nand = devm_kzalloc(dev, sizeof(*nand), GFP_KERNEL);
1090 if (!nand)
1091 return -ENOMEM;
1092
1093 nand->cs[0] = cs;
1094
1095 nand->wp_gpio = devm_gpiod_get_optional(dev, "wp", GPIOD_OUT_LOW);
1096
1097 if (IS_ERR(nand->wp_gpio)) {
1098 ret = PTR_ERR(nand->wp_gpio);
1099 dev_err(dev, "Failed to request WP GPIO: %d\n", ret);
1100 return ret;
1101 }
1102
1103 chip = &nand->chip;
1104 chip->controller = &ctrl->controller;
1105
1106 mtd = nand_to_mtd(chip);
1107
1108 mtd->dev.parent = dev;
1109 mtd->owner = THIS_MODULE;
1110
1111 nand_set_flash_node(chip, np_nand);
1112
1113 if (!mtd->name)
1114 mtd->name = "tegra_nand";
1115
1116 chip->options = NAND_NO_SUBPAGE_WRITE | NAND_USE_BOUNCE_BUFFER;
1117
1118 ret = nand_scan(chip, 1);
1119 if (ret)
1120 return ret;
1121
1122 mtd_ooblayout_ecc(mtd, 0, &nand->ecc);
1123
1124 ret = mtd_device_register(mtd, NULL, 0);
1125 if (ret) {
1126 dev_err(dev, "Failed to register mtd device: %d\n", ret);
1127 nand_cleanup(chip);
1128 return ret;
1129 }
1130
1131 ctrl->chip = chip;
1132
1133 return 0;
1134 }
1135
1136 static int tegra_nand_probe(struct platform_device *pdev)
1137 {
1138 struct reset_control *rst;
1139 struct tegra_nand_controller *ctrl;
1140 struct resource *res;
1141 int err = 0;
1142
1143 ctrl = devm_kzalloc(&pdev->dev, sizeof(*ctrl), GFP_KERNEL);
1144 if (!ctrl)
1145 return -ENOMEM;
1146
1147 ctrl->dev = &pdev->dev;
1148 nand_controller_init(&ctrl->controller);
1149 ctrl->controller.ops = &tegra_nand_controller_ops;
1150
1151 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1152 ctrl->regs = devm_ioremap_resource(&pdev->dev, res);
1153 if (IS_ERR(ctrl->regs))
1154 return PTR_ERR(ctrl->regs);
1155
1156 rst = devm_reset_control_get(&pdev->dev, "nand");
1157 if (IS_ERR(rst))
1158 return PTR_ERR(rst);
1159
1160 ctrl->clk = devm_clk_get(&pdev->dev, "nand");
1161 if (IS_ERR(ctrl->clk))
1162 return PTR_ERR(ctrl->clk);
1163
1164 err = clk_prepare_enable(ctrl->clk);
1165 if (err)
1166 return err;
1167
1168 err = reset_control_reset(rst);
1169 if (err) {
1170 dev_err(ctrl->dev, "Failed to reset HW: %d\n", err);
1171 goto err_disable_clk;
1172 }
1173
1174 writel_relaxed(HWSTATUS_CMD_DEFAULT, ctrl->regs + HWSTATUS_CMD);
1175 writel_relaxed(HWSTATUS_MASK_DEFAULT, ctrl->regs + HWSTATUS_MASK);
1176 writel_relaxed(INT_MASK, ctrl->regs + IER);
1177
1178 init_completion(&ctrl->command_complete);
1179 init_completion(&ctrl->dma_complete);
1180
1181 ctrl->irq = platform_get_irq(pdev, 0);
1182 err = devm_request_irq(&pdev->dev, ctrl->irq, tegra_nand_irq, 0,
1183 dev_name(&pdev->dev), ctrl);
1184 if (err) {
1185 dev_err(ctrl->dev, "Failed to get IRQ: %d\n", err);
1186 goto err_disable_clk;
1187 }
1188
1189 writel_relaxed(DMA_MST_CTRL_IS_DONE, ctrl->regs + DMA_MST_CTRL);
1190
1191 err = tegra_nand_chips_init(ctrl->dev, ctrl);
1192 if (err)
1193 goto err_disable_clk;
1194
1195 platform_set_drvdata(pdev, ctrl);
1196
1197 return 0;
1198
1199 err_disable_clk:
1200 clk_disable_unprepare(ctrl->clk);
1201 return err;
1202 }
1203
1204 static int tegra_nand_remove(struct platform_device *pdev)
1205 {
1206 struct tegra_nand_controller *ctrl = platform_get_drvdata(pdev);
1207 struct nand_chip *chip = ctrl->chip;
1208 struct mtd_info *mtd = nand_to_mtd(chip);
1209 int ret;
1210
1211 ret = mtd_device_unregister(mtd);
1212 if (ret)
1213 return ret;
1214
1215 nand_cleanup(chip);
1216
1217 clk_disable_unprepare(ctrl->clk);
1218
1219 return 0;
1220 }
1221
1222 static const struct of_device_id tegra_nand_of_match[] = {
1223 { .compatible = "nvidia,tegra20-nand" },
1224 { /* sentinel */ }
1225 };
1226 MODULE_DEVICE_TABLE(of, tegra_nand_of_match);
1227
1228 static struct platform_driver tegra_nand_driver = {
1229 .driver = {
1230 .name = "tegra-nand",
1231 .of_match_table = tegra_nand_of_match,
1232 },
1233 .probe = tegra_nand_probe,
1234 .remove = tegra_nand_remove,
1235 };
1236 module_platform_driver(tegra_nand_driver);
1237
1238 MODULE_DESCRIPTION("NVIDIA Tegra NAND driver");
1239 MODULE_AUTHOR("Thierry Reding <thierry.reding@nvidia.com>");
1240 MODULE_AUTHOR("Lucas Stach <dev@lynxeye.de>");
1241 MODULE_AUTHOR("Stefan Agner <stefan@agner.ch>");
1242 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support