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treewide: remove redundant IS_ERR() before error code check
[linux/fpc-iii.git] / drivers / mtd / spi-nor / cadence-quadspi.c
blob494dcab4aaaab2341a1ab0e66b0c81f5ad22d247
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Driver for Cadence QSPI Controller
4 *
5 * Copyright Altera Corporation (C) 2012-2014. All rights reserved.
6 */
7 #include <linux/clk.h>
8 #include <linux/completion.h>
9 #include <linux/delay.h>
10 #include <linux/dma-mapping.h>
11 #include <linux/dmaengine.h>
12 #include <linux/err.h>
13 #include <linux/errno.h>
14 #include <linux/interrupt.h>
15 #include <linux/io.h>
16 #include <linux/iopoll.h>
17 #include <linux/jiffies.h>
18 #include <linux/kernel.h>
19 #include <linux/module.h>
20 #include <linux/mtd/mtd.h>
21 #include <linux/mtd/partitions.h>
22 #include <linux/mtd/spi-nor.h>
23 #include <linux/of_device.h>
24 #include <linux/of.h>
25 #include <linux/platform_device.h>
26 #include <linux/pm_runtime.h>
27 #include <linux/reset.h>
28 #include <linux/sched.h>
29 #include <linux/spi/spi.h>
30 #include <linux/timer.h>
31
32 #define CQSPI_NAME "cadence-qspi"
33 #define CQSPI_MAX_CHIPSELECT 16
34
35 /* Quirks */
36 #define CQSPI_NEEDS_WR_DELAY BIT(0)
37
38 /* Capabilities mask */
39 #define CQSPI_BASE_HWCAPS_MASK \
40 (SNOR_HWCAPS_READ | SNOR_HWCAPS_READ_FAST | \
41 SNOR_HWCAPS_READ_1_1_2 | SNOR_HWCAPS_READ_1_1_4 | \
42 SNOR_HWCAPS_PP)
43
44 struct cqspi_st;
45
46 struct cqspi_flash_pdata {
47 struct spi_nor nor;
48 struct cqspi_st *cqspi;
49 u32 clk_rate;
50 u32 read_delay;
51 u32 tshsl_ns;
52 u32 tsd2d_ns;
53 u32 tchsh_ns;
54 u32 tslch_ns;
55 u8 inst_width;
56 u8 addr_width;
57 u8 data_width;
58 u8 cs;
59 bool registered;
60 bool use_direct_mode;
61 };
62
63 struct cqspi_st {
64 struct platform_device *pdev;
65
66 struct clk *clk;
67 unsigned int sclk;
68
69 void __iomem *iobase;
70 void __iomem *ahb_base;
71 resource_size_t ahb_size;
72 struct completion transfer_complete;
73 struct mutex bus_mutex;
74
75 struct dma_chan *rx_chan;
76 struct completion rx_dma_complete;
77 dma_addr_t mmap_phys_base;
78
79 int current_cs;
80 int current_page_size;
81 int current_erase_size;
82 int current_addr_width;
83 unsigned long master_ref_clk_hz;
84 bool is_decoded_cs;
85 u32 fifo_depth;
86 u32 fifo_width;
87 bool rclk_en;
88 u32 trigger_address;
89 u32 wr_delay;
90 struct cqspi_flash_pdata f_pdata[CQSPI_MAX_CHIPSELECT];
91 };
92
93 struct cqspi_driver_platdata {
94 u32 hwcaps_mask;
95 u8 quirks;
96 };
97
98 /* Operation timeout value */
99 #define CQSPI_TIMEOUT_MS 500
100 #define CQSPI_READ_TIMEOUT_MS 10
101
102 /* Instruction type */
103 #define CQSPI_INST_TYPE_SINGLE 0
104 #define CQSPI_INST_TYPE_DUAL 1
105 #define CQSPI_INST_TYPE_QUAD 2
106 #define CQSPI_INST_TYPE_OCTAL 3
107
108 #define CQSPI_DUMMY_CLKS_PER_BYTE 8
109 #define CQSPI_DUMMY_BYTES_MAX 4
110 #define CQSPI_DUMMY_CLKS_MAX 31
111
112 #define CQSPI_STIG_DATA_LEN_MAX 8
113
114 /* Register map */
115 #define CQSPI_REG_CONFIG 0x00
116 #define CQSPI_REG_CONFIG_ENABLE_MASK BIT(0)
117 #define CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL BIT(7)
118 #define CQSPI_REG_CONFIG_DECODE_MASK BIT(9)
119 #define CQSPI_REG_CONFIG_CHIPSELECT_LSB 10
120 #define CQSPI_REG_CONFIG_DMA_MASK BIT(15)
121 #define CQSPI_REG_CONFIG_BAUD_LSB 19
122 #define CQSPI_REG_CONFIG_IDLE_LSB 31
123 #define CQSPI_REG_CONFIG_CHIPSELECT_MASK 0xF
124 #define CQSPI_REG_CONFIG_BAUD_MASK 0xF
125
126 #define CQSPI_REG_RD_INSTR 0x04
127 #define CQSPI_REG_RD_INSTR_OPCODE_LSB 0
128 #define CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB 8
129 #define CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB 12
130 #define CQSPI_REG_RD_INSTR_TYPE_DATA_LSB 16
131 #define CQSPI_REG_RD_INSTR_MODE_EN_LSB 20
132 #define CQSPI_REG_RD_INSTR_DUMMY_LSB 24
133 #define CQSPI_REG_RD_INSTR_TYPE_INSTR_MASK 0x3
134 #define CQSPI_REG_RD_INSTR_TYPE_ADDR_MASK 0x3
135 #define CQSPI_REG_RD_INSTR_TYPE_DATA_MASK 0x3
136 #define CQSPI_REG_RD_INSTR_DUMMY_MASK 0x1F
137
138 #define CQSPI_REG_WR_INSTR 0x08
139 #define CQSPI_REG_WR_INSTR_OPCODE_LSB 0
140 #define CQSPI_REG_WR_INSTR_TYPE_ADDR_LSB 12
141 #define CQSPI_REG_WR_INSTR_TYPE_DATA_LSB 16
142
143 #define CQSPI_REG_DELAY 0x0C
144 #define CQSPI_REG_DELAY_TSLCH_LSB 0
145 #define CQSPI_REG_DELAY_TCHSH_LSB 8
146 #define CQSPI_REG_DELAY_TSD2D_LSB 16
147 #define CQSPI_REG_DELAY_TSHSL_LSB 24
148 #define CQSPI_REG_DELAY_TSLCH_MASK 0xFF
149 #define CQSPI_REG_DELAY_TCHSH_MASK 0xFF
150 #define CQSPI_REG_DELAY_TSD2D_MASK 0xFF
151 #define CQSPI_REG_DELAY_TSHSL_MASK 0xFF
152
153 #define CQSPI_REG_READCAPTURE 0x10
154 #define CQSPI_REG_READCAPTURE_BYPASS_LSB 0
155 #define CQSPI_REG_READCAPTURE_DELAY_LSB 1
156 #define CQSPI_REG_READCAPTURE_DELAY_MASK 0xF
157
158 #define CQSPI_REG_SIZE 0x14
159 #define CQSPI_REG_SIZE_ADDRESS_LSB 0
160 #define CQSPI_REG_SIZE_PAGE_LSB 4
161 #define CQSPI_REG_SIZE_BLOCK_LSB 16
162 #define CQSPI_REG_SIZE_ADDRESS_MASK 0xF
163 #define CQSPI_REG_SIZE_PAGE_MASK 0xFFF
164 #define CQSPI_REG_SIZE_BLOCK_MASK 0x3F
165
166 #define CQSPI_REG_SRAMPARTITION 0x18
167 #define CQSPI_REG_INDIRECTTRIGGER 0x1C
168
169 #define CQSPI_REG_DMA 0x20
170 #define CQSPI_REG_DMA_SINGLE_LSB 0
171 #define CQSPI_REG_DMA_BURST_LSB 8
172 #define CQSPI_REG_DMA_SINGLE_MASK 0xFF
173 #define CQSPI_REG_DMA_BURST_MASK 0xFF
174
175 #define CQSPI_REG_REMAP 0x24
176 #define CQSPI_REG_MODE_BIT 0x28
177
178 #define CQSPI_REG_SDRAMLEVEL 0x2C
179 #define CQSPI_REG_SDRAMLEVEL_RD_LSB 0
180 #define CQSPI_REG_SDRAMLEVEL_WR_LSB 16
181 #define CQSPI_REG_SDRAMLEVEL_RD_MASK 0xFFFF
182 #define CQSPI_REG_SDRAMLEVEL_WR_MASK 0xFFFF
183
184 #define CQSPI_REG_IRQSTATUS 0x40
185 #define CQSPI_REG_IRQMASK 0x44
186
187 #define CQSPI_REG_INDIRECTRD 0x60
188 #define CQSPI_REG_INDIRECTRD_START_MASK BIT(0)
189 #define CQSPI_REG_INDIRECTRD_CANCEL_MASK BIT(1)
190 #define CQSPI_REG_INDIRECTRD_DONE_MASK BIT(5)
191
192 #define CQSPI_REG_INDIRECTRDWATERMARK 0x64
193 #define CQSPI_REG_INDIRECTRDSTARTADDR 0x68
194 #define CQSPI_REG_INDIRECTRDBYTES 0x6C
195
196 #define CQSPI_REG_CMDCTRL 0x90
197 #define CQSPI_REG_CMDCTRL_EXECUTE_MASK BIT(0)
198 #define CQSPI_REG_CMDCTRL_INPROGRESS_MASK BIT(1)
199 #define CQSPI_REG_CMDCTRL_WR_BYTES_LSB 12
200 #define CQSPI_REG_CMDCTRL_WR_EN_LSB 15
201 #define CQSPI_REG_CMDCTRL_ADD_BYTES_LSB 16
202 #define CQSPI_REG_CMDCTRL_ADDR_EN_LSB 19
203 #define CQSPI_REG_CMDCTRL_RD_BYTES_LSB 20
204 #define CQSPI_REG_CMDCTRL_RD_EN_LSB 23
205 #define CQSPI_REG_CMDCTRL_OPCODE_LSB 24
206 #define CQSPI_REG_CMDCTRL_WR_BYTES_MASK 0x7
207 #define CQSPI_REG_CMDCTRL_ADD_BYTES_MASK 0x3
208 #define CQSPI_REG_CMDCTRL_RD_BYTES_MASK 0x7
209
210 #define CQSPI_REG_INDIRECTWR 0x70
211 #define CQSPI_REG_INDIRECTWR_START_MASK BIT(0)
212 #define CQSPI_REG_INDIRECTWR_CANCEL_MASK BIT(1)
213 #define CQSPI_REG_INDIRECTWR_DONE_MASK BIT(5)
214
215 #define CQSPI_REG_INDIRECTWRWATERMARK 0x74
216 #define CQSPI_REG_INDIRECTWRSTARTADDR 0x78
217 #define CQSPI_REG_INDIRECTWRBYTES 0x7C
218
219 #define CQSPI_REG_CMDADDRESS 0x94
220 #define CQSPI_REG_CMDREADDATALOWER 0xA0
221 #define CQSPI_REG_CMDREADDATAUPPER 0xA4
222 #define CQSPI_REG_CMDWRITEDATALOWER 0xA8
223 #define CQSPI_REG_CMDWRITEDATAUPPER 0xAC
224
225 /* Interrupt status bits */
226 #define CQSPI_REG_IRQ_MODE_ERR BIT(0)
227 #define CQSPI_REG_IRQ_UNDERFLOW BIT(1)
228 #define CQSPI_REG_IRQ_IND_COMP BIT(2)
229 #define CQSPI_REG_IRQ_IND_RD_REJECT BIT(3)
230 #define CQSPI_REG_IRQ_WR_PROTECTED_ERR BIT(4)
231 #define CQSPI_REG_IRQ_ILLEGAL_AHB_ERR BIT(5)
232 #define CQSPI_REG_IRQ_WATERMARK BIT(6)
233 #define CQSPI_REG_IRQ_IND_SRAM_FULL BIT(12)
234
235 #define CQSPI_IRQ_MASK_RD (CQSPI_REG_IRQ_WATERMARK | \
236 CQSPI_REG_IRQ_IND_SRAM_FULL | \
237 CQSPI_REG_IRQ_IND_COMP)
238
239 #define CQSPI_IRQ_MASK_WR (CQSPI_REG_IRQ_IND_COMP | \
240 CQSPI_REG_IRQ_WATERMARK | \
241 CQSPI_REG_IRQ_UNDERFLOW)
242
243 #define CQSPI_IRQ_STATUS_MASK 0x1FFFF
244
245 static int cqspi_wait_for_bit(void __iomem *reg, const u32 mask, bool clr)
246 {
247 u32 val;
248
249 return readl_relaxed_poll_timeout(reg, val,
250 (((clr ? ~val : val) & mask) == mask),
251 10, CQSPI_TIMEOUT_MS * 1000);
252 }
253
254 static bool cqspi_is_idle(struct cqspi_st *cqspi)
255 {
256 u32 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
257
258 return reg & (1 << CQSPI_REG_CONFIG_IDLE_LSB);
259 }
260
261 static u32 cqspi_get_rd_sram_level(struct cqspi_st *cqspi)
262 {
263 u32 reg = readl(cqspi->iobase + CQSPI_REG_SDRAMLEVEL);
264
265 reg >>= CQSPI_REG_SDRAMLEVEL_RD_LSB;
266 return reg & CQSPI_REG_SDRAMLEVEL_RD_MASK;
267 }
268
269 static irqreturn_t cqspi_irq_handler(int this_irq, void *dev)
270 {
271 struct cqspi_st *cqspi = dev;
272 unsigned int irq_status;
273
274 /* Read interrupt status */
275 irq_status = readl(cqspi->iobase + CQSPI_REG_IRQSTATUS);
276
277 /* Clear interrupt */
278 writel(irq_status, cqspi->iobase + CQSPI_REG_IRQSTATUS);
279
280 irq_status &= CQSPI_IRQ_MASK_RD | CQSPI_IRQ_MASK_WR;
281
282 if (irq_status)
283 complete(&cqspi->transfer_complete);
284
285 return IRQ_HANDLED;
286 }
287
288 static unsigned int cqspi_calc_rdreg(struct spi_nor *nor)
289 {
290 struct cqspi_flash_pdata *f_pdata = nor->priv;
291 u32 rdreg = 0;
292
293 rdreg |= f_pdata->inst_width << CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB;
294 rdreg |= f_pdata->addr_width << CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB;
295 rdreg |= f_pdata->data_width << CQSPI_REG_RD_INSTR_TYPE_DATA_LSB;
296
297 return rdreg;
298 }
299
300 static int cqspi_wait_idle(struct cqspi_st *cqspi)
301 {
302 const unsigned int poll_idle_retry = 3;
303 unsigned int count = 0;
304 unsigned long timeout;
305
306 timeout = jiffies + msecs_to_jiffies(CQSPI_TIMEOUT_MS);
307 while (1) {
308 /*
309 * Read few times in succession to ensure the controller
310 * is indeed idle, that is, the bit does not transition
311 * low again.
312 */
313 if (cqspi_is_idle(cqspi))
314 count++;
315 else
316 count = 0;
317
318 if (count >= poll_idle_retry)
319 return 0;
320
321 if (time_after(jiffies, timeout)) {
322 /* Timeout, in busy mode. */
323 dev_err(&cqspi->pdev->dev,
324 "QSPI is still busy after %dms timeout.\n",
325 CQSPI_TIMEOUT_MS);
326 return -ETIMEDOUT;
327 }
328
329 cpu_relax();
330 }
331 }
332
333 static int cqspi_exec_flash_cmd(struct cqspi_st *cqspi, unsigned int reg)
334 {
335 void __iomem *reg_base = cqspi->iobase;
336 int ret;
337
338 /* Write the CMDCTRL without start execution. */
339 writel(reg, reg_base + CQSPI_REG_CMDCTRL);
340 /* Start execute */
341 reg |= CQSPI_REG_CMDCTRL_EXECUTE_MASK;
342 writel(reg, reg_base + CQSPI_REG_CMDCTRL);
343
344 /* Polling for completion. */
345 ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_CMDCTRL,
346 CQSPI_REG_CMDCTRL_INPROGRESS_MASK, 1);
347 if (ret) {
348 dev_err(&cqspi->pdev->dev,
349 "Flash command execution timed out.\n");
350 return ret;
351 }
352
353 /* Polling QSPI idle status. */
354 return cqspi_wait_idle(cqspi);
355 }
356
357 static int cqspi_command_read(struct spi_nor *nor, u8 opcode,
358 u8 *rxbuf, size_t n_rx)
359 {
360 struct cqspi_flash_pdata *f_pdata = nor->priv;
361 struct cqspi_st *cqspi = f_pdata->cqspi;
362 void __iomem *reg_base = cqspi->iobase;
363 unsigned int rdreg;
364 unsigned int reg;
365 size_t read_len;
366 int status;
367
368 if (!n_rx || n_rx > CQSPI_STIG_DATA_LEN_MAX || !rxbuf) {
369 dev_err(nor->dev,
370 "Invalid input argument, len %zu rxbuf 0x%p\n",
371 n_rx, rxbuf);
372 return -EINVAL;
373 }
374
375 reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB;
376
377 rdreg = cqspi_calc_rdreg(nor);
378 writel(rdreg, reg_base + CQSPI_REG_RD_INSTR);
379
380 reg |= (0x1 << CQSPI_REG_CMDCTRL_RD_EN_LSB);
381
382 /* 0 means 1 byte. */
383 reg |= (((n_rx - 1) & CQSPI_REG_CMDCTRL_RD_BYTES_MASK)
384 << CQSPI_REG_CMDCTRL_RD_BYTES_LSB);
385 status = cqspi_exec_flash_cmd(cqspi, reg);
386 if (status)
387 return status;
388
389 reg = readl(reg_base + CQSPI_REG_CMDREADDATALOWER);
390
391 /* Put the read value into rx_buf */
392 read_len = (n_rx > 4) ? 4 : n_rx;
393 memcpy(rxbuf, &reg, read_len);
394 rxbuf += read_len;
395
396 if (n_rx > 4) {
397 reg = readl(reg_base + CQSPI_REG_CMDREADDATAUPPER);
398
399 read_len = n_rx - read_len;
400 memcpy(rxbuf, &reg, read_len);
401 }
402
403 return 0;
404 }
405
406 static int cqspi_command_write(struct spi_nor *nor, const u8 opcode,
407 const u8 *txbuf, size_t n_tx)
408 {
409 struct cqspi_flash_pdata *f_pdata = nor->priv;
410 struct cqspi_st *cqspi = f_pdata->cqspi;
411 void __iomem *reg_base = cqspi->iobase;
412 unsigned int reg;
413 unsigned int data;
414 size_t write_len;
415 int ret;
416
417 if (n_tx > CQSPI_STIG_DATA_LEN_MAX || (n_tx && !txbuf)) {
418 dev_err(nor->dev,
419 "Invalid input argument, cmdlen %zu txbuf 0x%p\n",
420 n_tx, txbuf);
421 return -EINVAL;
422 }
423
424 reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB;
425 if (n_tx) {
426 reg |= (0x1 << CQSPI_REG_CMDCTRL_WR_EN_LSB);
427 reg |= ((n_tx - 1) & CQSPI_REG_CMDCTRL_WR_BYTES_MASK)
428 << CQSPI_REG_CMDCTRL_WR_BYTES_LSB;
429 data = 0;
430 write_len = (n_tx > 4) ? 4 : n_tx;
431 memcpy(&data, txbuf, write_len);
432 txbuf += write_len;
433 writel(data, reg_base + CQSPI_REG_CMDWRITEDATALOWER);
434
435 if (n_tx > 4) {
436 data = 0;
437 write_len = n_tx - 4;
438 memcpy(&data, txbuf, write_len);
439 writel(data, reg_base + CQSPI_REG_CMDWRITEDATAUPPER);
440 }
441 }
442 ret = cqspi_exec_flash_cmd(cqspi, reg);
443 return ret;
444 }
445
446 static int cqspi_command_write_addr(struct spi_nor *nor,
447 const u8 opcode, const unsigned int addr)
448 {
449 struct cqspi_flash_pdata *f_pdata = nor->priv;
450 struct cqspi_st *cqspi = f_pdata->cqspi;
451 void __iomem *reg_base = cqspi->iobase;
452 unsigned int reg;
453
454 reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB;
455 reg |= (0x1 << CQSPI_REG_CMDCTRL_ADDR_EN_LSB);
456 reg |= ((nor->addr_width - 1) & CQSPI_REG_CMDCTRL_ADD_BYTES_MASK)
457 << CQSPI_REG_CMDCTRL_ADD_BYTES_LSB;
458
459 writel(addr, reg_base + CQSPI_REG_CMDADDRESS);
460
461 return cqspi_exec_flash_cmd(cqspi, reg);
462 }
463
464 static int cqspi_read_setup(struct spi_nor *nor)
465 {
466 struct cqspi_flash_pdata *f_pdata = nor->priv;
467 struct cqspi_st *cqspi = f_pdata->cqspi;
468 void __iomem *reg_base = cqspi->iobase;
469 unsigned int dummy_clk = 0;
470 unsigned int reg;
471
472 reg = nor->read_opcode << CQSPI_REG_RD_INSTR_OPCODE_LSB;
473 reg |= cqspi_calc_rdreg(nor);
474
475 /* Setup dummy clock cycles */
476 dummy_clk = nor->read_dummy;
477 if (dummy_clk > CQSPI_DUMMY_CLKS_MAX)
478 dummy_clk = CQSPI_DUMMY_CLKS_MAX;
479
480 if (dummy_clk / 8) {
481 reg |= (1 << CQSPI_REG_RD_INSTR_MODE_EN_LSB);
482 /* Set mode bits high to ensure chip doesn't enter XIP */
483 writel(0xFF, reg_base + CQSPI_REG_MODE_BIT);
484
485 /* Need to subtract the mode byte (8 clocks). */
486 if (f_pdata->inst_width != CQSPI_INST_TYPE_QUAD)
487 dummy_clk -= 8;
488
489 if (dummy_clk)
490 reg |= (dummy_clk & CQSPI_REG_RD_INSTR_DUMMY_MASK)
491 << CQSPI_REG_RD_INSTR_DUMMY_LSB;
492 }
493
494 writel(reg, reg_base + CQSPI_REG_RD_INSTR);
495
496 /* Set address width */
497 reg = readl(reg_base + CQSPI_REG_SIZE);
498 reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
499 reg |= (nor->addr_width - 1);
500 writel(reg, reg_base + CQSPI_REG_SIZE);
501 return 0;
502 }
503
504 static int cqspi_indirect_read_execute(struct spi_nor *nor, u8 *rxbuf,
505 loff_t from_addr, const size_t n_rx)
506 {
507 struct cqspi_flash_pdata *f_pdata = nor->priv;
508 struct cqspi_st *cqspi = f_pdata->cqspi;
509 void __iomem *reg_base = cqspi->iobase;
510 void __iomem *ahb_base = cqspi->ahb_base;
511 unsigned int remaining = n_rx;
512 unsigned int mod_bytes = n_rx % 4;
513 unsigned int bytes_to_read = 0;
514 u8 *rxbuf_end = rxbuf + n_rx;
515 int ret = 0;
516
517 writel(from_addr, reg_base + CQSPI_REG_INDIRECTRDSTARTADDR);
518 writel(remaining, reg_base + CQSPI_REG_INDIRECTRDBYTES);
519
520 /* Clear all interrupts. */
521 writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS);
522
523 writel(CQSPI_IRQ_MASK_RD, reg_base + CQSPI_REG_IRQMASK);
524
525 reinit_completion(&cqspi->transfer_complete);
526 writel(CQSPI_REG_INDIRECTRD_START_MASK,
527 reg_base + CQSPI_REG_INDIRECTRD);
528
529 while (remaining > 0) {
530 if (!wait_for_completion_timeout(&cqspi->transfer_complete,
531 msecs_to_jiffies(CQSPI_READ_TIMEOUT_MS)))
532 ret = -ETIMEDOUT;
533
534 bytes_to_read = cqspi_get_rd_sram_level(cqspi);
535
536 if (ret && bytes_to_read == 0) {
537 dev_err(nor->dev, "Indirect read timeout, no bytes\n");
538 goto failrd;
539 }
540
541 while (bytes_to_read != 0) {
542 unsigned int word_remain = round_down(remaining, 4);
543
544 bytes_to_read *= cqspi->fifo_width;
545 bytes_to_read = bytes_to_read > remaining ?
546 remaining : bytes_to_read;
547 bytes_to_read = round_down(bytes_to_read, 4);
548 /* Read 4 byte word chunks then single bytes */
549 if (bytes_to_read) {
550 ioread32_rep(ahb_base, rxbuf,
551 (bytes_to_read / 4));
552 } else if (!word_remain && mod_bytes) {
553 unsigned int temp = ioread32(ahb_base);
554
555 bytes_to_read = mod_bytes;
556 memcpy(rxbuf, &temp, min((unsigned int)
557 (rxbuf_end - rxbuf),
558 bytes_to_read));
559 }
560 rxbuf += bytes_to_read;
561 remaining -= bytes_to_read;
562 bytes_to_read = cqspi_get_rd_sram_level(cqspi);
563 }
564
565 if (remaining > 0)
566 reinit_completion(&cqspi->transfer_complete);
567 }
568
569 /* Check indirect done status */
570 ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_INDIRECTRD,
571 CQSPI_REG_INDIRECTRD_DONE_MASK, 0);
572 if (ret) {
573 dev_err(nor->dev,
574 "Indirect read completion error (%i)\n", ret);
575 goto failrd;
576 }
577
578 /* Disable interrupt */
579 writel(0, reg_base + CQSPI_REG_IRQMASK);
580
581 /* Clear indirect completion status */
582 writel(CQSPI_REG_INDIRECTRD_DONE_MASK, reg_base + CQSPI_REG_INDIRECTRD);
583
584 return 0;
585
586 failrd:
587 /* Disable interrupt */
588 writel(0, reg_base + CQSPI_REG_IRQMASK);
589
590 /* Cancel the indirect read */
591 writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK,
592 reg_base + CQSPI_REG_INDIRECTRD);
593 return ret;
594 }
595
596 static int cqspi_write_setup(struct spi_nor *nor)
597 {
598 unsigned int reg;
599 struct cqspi_flash_pdata *f_pdata = nor->priv;
600 struct cqspi_st *cqspi = f_pdata->cqspi;
601 void __iomem *reg_base = cqspi->iobase;
602
603 /* Set opcode. */
604 reg = nor->program_opcode << CQSPI_REG_WR_INSTR_OPCODE_LSB;
605 writel(reg, reg_base + CQSPI_REG_WR_INSTR);
606 reg = cqspi_calc_rdreg(nor);
607 writel(reg, reg_base + CQSPI_REG_RD_INSTR);
608
609 reg = readl(reg_base + CQSPI_REG_SIZE);
610 reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
611 reg |= (nor->addr_width - 1);
612 writel(reg, reg_base + CQSPI_REG_SIZE);
613 return 0;
614 }
615
616 static int cqspi_indirect_write_execute(struct spi_nor *nor, loff_t to_addr,
617 const u8 *txbuf, const size_t n_tx)
618 {
619 const unsigned int page_size = nor->page_size;
620 struct cqspi_flash_pdata *f_pdata = nor->priv;
621 struct cqspi_st *cqspi = f_pdata->cqspi;
622 void __iomem *reg_base = cqspi->iobase;
623 unsigned int remaining = n_tx;
624 unsigned int write_bytes;
625 int ret;
626
627 writel(to_addr, reg_base + CQSPI_REG_INDIRECTWRSTARTADDR);
628 writel(remaining, reg_base + CQSPI_REG_INDIRECTWRBYTES);
629
630 /* Clear all interrupts. */
631 writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS);
632
633 writel(CQSPI_IRQ_MASK_WR, reg_base + CQSPI_REG_IRQMASK);
634
635 reinit_completion(&cqspi->transfer_complete);
636 writel(CQSPI_REG_INDIRECTWR_START_MASK,
637 reg_base + CQSPI_REG_INDIRECTWR);
638 /*
639 * As per 66AK2G02 TRM SPRUHY8F section 11.15.5.3 Indirect Access
640 * Controller programming sequence, couple of cycles of
641 * QSPI_REF_CLK delay is required for the above bit to
642 * be internally synchronized by the QSPI module. Provide 5
643 * cycles of delay.
644 */
645 if (cqspi->wr_delay)
646 ndelay(cqspi->wr_delay);
647
648 while (remaining > 0) {
649 size_t write_words, mod_bytes;
650
651 write_bytes = remaining > page_size ? page_size : remaining;
652 write_words = write_bytes / 4;
653 mod_bytes = write_bytes % 4;
654 /* Write 4 bytes at a time then single bytes. */
655 if (write_words) {
656 iowrite32_rep(cqspi->ahb_base, txbuf, write_words);
657 txbuf += (write_words * 4);
658 }
659 if (mod_bytes) {
660 unsigned int temp = 0xFFFFFFFF;
661
662 memcpy(&temp, txbuf, mod_bytes);
663 iowrite32(temp, cqspi->ahb_base);
664 txbuf += mod_bytes;
665 }
666
667 if (!wait_for_completion_timeout(&cqspi->transfer_complete,
668 msecs_to_jiffies(CQSPI_TIMEOUT_MS))) {
669 dev_err(nor->dev, "Indirect write timeout\n");
670 ret = -ETIMEDOUT;
671 goto failwr;
672 }
673
674 remaining -= write_bytes;
675
676 if (remaining > 0)
677 reinit_completion(&cqspi->transfer_complete);
678 }
679
680 /* Check indirect done status */
681 ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_INDIRECTWR,
682 CQSPI_REG_INDIRECTWR_DONE_MASK, 0);
683 if (ret) {
684 dev_err(nor->dev,
685 "Indirect write completion error (%i)\n", ret);
686 goto failwr;
687 }
688
689 /* Disable interrupt. */
690 writel(0, reg_base + CQSPI_REG_IRQMASK);
691
692 /* Clear indirect completion status */
693 writel(CQSPI_REG_INDIRECTWR_DONE_MASK, reg_base + CQSPI_REG_INDIRECTWR);
694
695 cqspi_wait_idle(cqspi);
696
697 return 0;
698
699 failwr:
700 /* Disable interrupt. */
701 writel(0, reg_base + CQSPI_REG_IRQMASK);
702
703 /* Cancel the indirect write */
704 writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK,
705 reg_base + CQSPI_REG_INDIRECTWR);
706 return ret;
707 }
708
709 static void cqspi_chipselect(struct spi_nor *nor)
710 {
711 struct cqspi_flash_pdata *f_pdata = nor->priv;
712 struct cqspi_st *cqspi = f_pdata->cqspi;
713 void __iomem *reg_base = cqspi->iobase;
714 unsigned int chip_select = f_pdata->cs;
715 unsigned int reg;
716
717 reg = readl(reg_base + CQSPI_REG_CONFIG);
718 if (cqspi->is_decoded_cs) {
719 reg |= CQSPI_REG_CONFIG_DECODE_MASK;
720 } else {
721 reg &= ~CQSPI_REG_CONFIG_DECODE_MASK;
722
723 /* Convert CS if without decoder.
724 * CS0 to 4b'1110
725 * CS1 to 4b'1101
726 * CS2 to 4b'1011
727 * CS3 to 4b'0111
728 */
729 chip_select = 0xF & ~(1 << chip_select);
730 }
731
732 reg &= ~(CQSPI_REG_CONFIG_CHIPSELECT_MASK
733 << CQSPI_REG_CONFIG_CHIPSELECT_LSB);
734 reg |= (chip_select & CQSPI_REG_CONFIG_CHIPSELECT_MASK)
735 << CQSPI_REG_CONFIG_CHIPSELECT_LSB;
736 writel(reg, reg_base + CQSPI_REG_CONFIG);
737 }
738
739 static void cqspi_configure_cs_and_sizes(struct spi_nor *nor)
740 {
741 struct cqspi_flash_pdata *f_pdata = nor->priv;
742 struct cqspi_st *cqspi = f_pdata->cqspi;
743 void __iomem *iobase = cqspi->iobase;
744 unsigned int reg;
745
746 /* configure page size and block size. */
747 reg = readl(iobase + CQSPI_REG_SIZE);
748 reg &= ~(CQSPI_REG_SIZE_PAGE_MASK << CQSPI_REG_SIZE_PAGE_LSB);
749 reg &= ~(CQSPI_REG_SIZE_BLOCK_MASK << CQSPI_REG_SIZE_BLOCK_LSB);
750 reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
751 reg |= (nor->page_size << CQSPI_REG_SIZE_PAGE_LSB);
752 reg |= (ilog2(nor->mtd.erasesize) << CQSPI_REG_SIZE_BLOCK_LSB);
753 reg |= (nor->addr_width - 1);
754 writel(reg, iobase + CQSPI_REG_SIZE);
755
756 /* configure the chip select */
757 cqspi_chipselect(nor);
758
759 /* Store the new configuration of the controller */
760 cqspi->current_page_size = nor->page_size;
761 cqspi->current_erase_size = nor->mtd.erasesize;
762 cqspi->current_addr_width = nor->addr_width;
763 }
764
765 static unsigned int calculate_ticks_for_ns(const unsigned int ref_clk_hz,
766 const unsigned int ns_val)
767 {
768 unsigned int ticks;
769
770 ticks = ref_clk_hz / 1000; /* kHz */
771 ticks = DIV_ROUND_UP(ticks * ns_val, 1000000);
772
773 return ticks;
774 }
775
776 static void cqspi_delay(struct spi_nor *nor)
777 {
778 struct cqspi_flash_pdata *f_pdata = nor->priv;
779 struct cqspi_st *cqspi = f_pdata->cqspi;
780 void __iomem *iobase = cqspi->iobase;
781 const unsigned int ref_clk_hz = cqspi->master_ref_clk_hz;
782 unsigned int tshsl, tchsh, tslch, tsd2d;
783 unsigned int reg;
784 unsigned int tsclk;
785
786 /* calculate the number of ref ticks for one sclk tick */
787 tsclk = DIV_ROUND_UP(ref_clk_hz, cqspi->sclk);
788
789 tshsl = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tshsl_ns);
790 /* this particular value must be at least one sclk */
791 if (tshsl < tsclk)
792 tshsl = tsclk;
793
794 tchsh = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tchsh_ns);
795 tslch = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tslch_ns);
796 tsd2d = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tsd2d_ns);
797
798 reg = (tshsl & CQSPI_REG_DELAY_TSHSL_MASK)
799 << CQSPI_REG_DELAY_TSHSL_LSB;
800 reg |= (tchsh & CQSPI_REG_DELAY_TCHSH_MASK)
801 << CQSPI_REG_DELAY_TCHSH_LSB;
802 reg |= (tslch & CQSPI_REG_DELAY_TSLCH_MASK)
803 << CQSPI_REG_DELAY_TSLCH_LSB;
804 reg |= (tsd2d & CQSPI_REG_DELAY_TSD2D_MASK)
805 << CQSPI_REG_DELAY_TSD2D_LSB;
806 writel(reg, iobase + CQSPI_REG_DELAY);
807 }
808
809 static void cqspi_config_baudrate_div(struct cqspi_st *cqspi)
810 {
811 const unsigned int ref_clk_hz = cqspi->master_ref_clk_hz;
812 void __iomem *reg_base = cqspi->iobase;
813 u32 reg, div;
814
815 /* Recalculate the baudrate divisor based on QSPI specification. */
816 div = DIV_ROUND_UP(ref_clk_hz, 2 * cqspi->sclk) - 1;
817
818 reg = readl(reg_base + CQSPI_REG_CONFIG);
819 reg &= ~(CQSPI_REG_CONFIG_BAUD_MASK << CQSPI_REG_CONFIG_BAUD_LSB);
820 reg |= (div & CQSPI_REG_CONFIG_BAUD_MASK) << CQSPI_REG_CONFIG_BAUD_LSB;
821 writel(reg, reg_base + CQSPI_REG_CONFIG);
822 }
823
824 static void cqspi_readdata_capture(struct cqspi_st *cqspi,
825 const bool bypass,
826 const unsigned int delay)
827 {
828 void __iomem *reg_base = cqspi->iobase;
829 unsigned int reg;
830
831 reg = readl(reg_base + CQSPI_REG_READCAPTURE);
832
833 if (bypass)
834 reg |= (1 << CQSPI_REG_READCAPTURE_BYPASS_LSB);
835 else
836 reg &= ~(1 << CQSPI_REG_READCAPTURE_BYPASS_LSB);
837
838 reg &= ~(CQSPI_REG_READCAPTURE_DELAY_MASK
839 << CQSPI_REG_READCAPTURE_DELAY_LSB);
840
841 reg |= (delay & CQSPI_REG_READCAPTURE_DELAY_MASK)
842 << CQSPI_REG_READCAPTURE_DELAY_LSB;
843
844 writel(reg, reg_base + CQSPI_REG_READCAPTURE);
845 }
846
847 static void cqspi_controller_enable(struct cqspi_st *cqspi, bool enable)
848 {
849 void __iomem *reg_base = cqspi->iobase;
850 unsigned int reg;
851
852 reg = readl(reg_base + CQSPI_REG_CONFIG);
853
854 if (enable)
855 reg |= CQSPI_REG_CONFIG_ENABLE_MASK;
856 else
857 reg &= ~CQSPI_REG_CONFIG_ENABLE_MASK;
858
859 writel(reg, reg_base + CQSPI_REG_CONFIG);
860 }
861
862 static void cqspi_configure(struct spi_nor *nor)
863 {
864 struct cqspi_flash_pdata *f_pdata = nor->priv;
865 struct cqspi_st *cqspi = f_pdata->cqspi;
866 const unsigned int sclk = f_pdata->clk_rate;
867 int switch_cs = (cqspi->current_cs != f_pdata->cs);
868 int switch_ck = (cqspi->sclk != sclk);
869
870 if ((cqspi->current_page_size != nor->page_size) ||
871 (cqspi->current_erase_size != nor->mtd.erasesize) ||
872 (cqspi->current_addr_width != nor->addr_width))
873 switch_cs = 1;
874
875 if (switch_cs || switch_ck)
876 cqspi_controller_enable(cqspi, 0);
877
878 /* Switch chip select. */
879 if (switch_cs) {
880 cqspi->current_cs = f_pdata->cs;
881 cqspi_configure_cs_and_sizes(nor);
882 }
883
884 /* Setup baudrate divisor and delays */
885 if (switch_ck) {
886 cqspi->sclk = sclk;
887 cqspi_config_baudrate_div(cqspi);
888 cqspi_delay(nor);
889 cqspi_readdata_capture(cqspi, !cqspi->rclk_en,
890 f_pdata->read_delay);
891 }
892
893 if (switch_cs || switch_ck)
894 cqspi_controller_enable(cqspi, 1);
895 }
896
897 static int cqspi_set_protocol(struct spi_nor *nor, const int read)
898 {
899 struct cqspi_flash_pdata *f_pdata = nor->priv;
900
901 f_pdata->inst_width = CQSPI_INST_TYPE_SINGLE;
902 f_pdata->addr_width = CQSPI_INST_TYPE_SINGLE;
903 f_pdata->data_width = CQSPI_INST_TYPE_SINGLE;
904
905 if (read) {
906 switch (nor->read_proto) {
907 case SNOR_PROTO_1_1_1:
908 f_pdata->data_width = CQSPI_INST_TYPE_SINGLE;
909 break;
910 case SNOR_PROTO_1_1_2:
911 f_pdata->data_width = CQSPI_INST_TYPE_DUAL;
912 break;
913 case SNOR_PROTO_1_1_4:
914 f_pdata->data_width = CQSPI_INST_TYPE_QUAD;
915 break;
916 case SNOR_PROTO_1_1_8:
917 f_pdata->data_width = CQSPI_INST_TYPE_OCTAL;
918 break;
919 default:
920 return -EINVAL;
921 }
922 }
923
924 cqspi_configure(nor);
925
926 return 0;
927 }
928
929 static ssize_t cqspi_write(struct spi_nor *nor, loff_t to,
930 size_t len, const u_char *buf)
931 {
932 struct cqspi_flash_pdata *f_pdata = nor->priv;
933 struct cqspi_st *cqspi = f_pdata->cqspi;
934 int ret;
935
936 ret = cqspi_set_protocol(nor, 0);
937 if (ret)
938 return ret;
939
940 ret = cqspi_write_setup(nor);
941 if (ret)
942 return ret;
943
944 if (f_pdata->use_direct_mode) {
945 memcpy_toio(cqspi->ahb_base + to, buf, len);
946 ret = cqspi_wait_idle(cqspi);
947 } else {
948 ret = cqspi_indirect_write_execute(nor, to, buf, len);
949 }
950 if (ret)
951 return ret;
952
953 return len;
954 }
955
956 static void cqspi_rx_dma_callback(void *param)
957 {
958 struct cqspi_st *cqspi = param;
959
960 complete(&cqspi->rx_dma_complete);
961 }
962
963 static int cqspi_direct_read_execute(struct spi_nor *nor, u_char *buf,
964 loff_t from, size_t len)
965 {
966 struct cqspi_flash_pdata *f_pdata = nor->priv;
967 struct cqspi_st *cqspi = f_pdata->cqspi;
968 enum dma_ctrl_flags flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
969 dma_addr_t dma_src = (dma_addr_t)cqspi->mmap_phys_base + from;
970 int ret = 0;
971 struct dma_async_tx_descriptor *tx;
972 dma_cookie_t cookie;
973 dma_addr_t dma_dst;
974
975 if (!cqspi->rx_chan || !virt_addr_valid(buf)) {
976 memcpy_fromio(buf, cqspi->ahb_base + from, len);
977 return 0;
978 }
979
980 dma_dst = dma_map_single(nor->dev, buf, len, DMA_FROM_DEVICE);
981 if (dma_mapping_error(nor->dev, dma_dst)) {
982 dev_err(nor->dev, "dma mapping failed\n");
983 return -ENOMEM;
984 }
985 tx = dmaengine_prep_dma_memcpy(cqspi->rx_chan, dma_dst, dma_src,
986 len, flags);
987 if (!tx) {
988 dev_err(nor->dev, "device_prep_dma_memcpy error\n");
989 ret = -EIO;
990 goto err_unmap;
991 }
992
993 tx->callback = cqspi_rx_dma_callback;
994 tx->callback_param = cqspi;
995 cookie = tx->tx_submit(tx);
996 reinit_completion(&cqspi->rx_dma_complete);
997
998 ret = dma_submit_error(cookie);
999 if (ret) {
1000 dev_err(nor->dev, "dma_submit_error %d\n", cookie);
1001 ret = -EIO;
1002 goto err_unmap;
1003 }
1004
1005 dma_async_issue_pending(cqspi->rx_chan);
1006 if (!wait_for_completion_timeout(&cqspi->rx_dma_complete,
1007 msecs_to_jiffies(len))) {
1008 dmaengine_terminate_sync(cqspi->rx_chan);
1009 dev_err(nor->dev, "DMA wait_for_completion_timeout\n");
1010 ret = -ETIMEDOUT;
1011 goto err_unmap;
1012 }
1013
1014 err_unmap:
1015 dma_unmap_single(nor->dev, dma_dst, len, DMA_FROM_DEVICE);
1016
1017 return ret;
1018 }
1019
1020 static ssize_t cqspi_read(struct spi_nor *nor, loff_t from,
1021 size_t len, u_char *buf)
1022 {
1023 struct cqspi_flash_pdata *f_pdata = nor->priv;
1024 int ret;
1025
1026 ret = cqspi_set_protocol(nor, 1);
1027 if (ret)
1028 return ret;
1029
1030 ret = cqspi_read_setup(nor);
1031 if (ret)
1032 return ret;
1033
1034 if (f_pdata->use_direct_mode)
1035 ret = cqspi_direct_read_execute(nor, buf, from, len);
1036 else
1037 ret = cqspi_indirect_read_execute(nor, buf, from, len);
1038 if (ret)
1039 return ret;
1040
1041 return len;
1042 }
1043
1044 static int cqspi_erase(struct spi_nor *nor, loff_t offs)
1045 {
1046 int ret;
1047
1048 ret = cqspi_set_protocol(nor, 0);
1049 if (ret)
1050 return ret;
1051
1052 /* Send write enable, then erase commands. */
1053 ret = nor->controller_ops->write_reg(nor, SPINOR_OP_WREN, NULL, 0);
1054 if (ret)
1055 return ret;
1056
1057 /* Set up command buffer. */
1058 ret = cqspi_command_write_addr(nor, nor->erase_opcode, offs);
1059 if (ret)
1060 return ret;
1061
1062 return 0;
1063 }
1064
1065 static int cqspi_prep(struct spi_nor *nor)
1066 {
1067 struct cqspi_flash_pdata *f_pdata = nor->priv;
1068 struct cqspi_st *cqspi = f_pdata->cqspi;
1069
1070 mutex_lock(&cqspi->bus_mutex);
1071
1072 return 0;
1073 }
1074
1075 static void cqspi_unprep(struct spi_nor *nor)
1076 {
1077 struct cqspi_flash_pdata *f_pdata = nor->priv;
1078 struct cqspi_st *cqspi = f_pdata->cqspi;
1079
1080 mutex_unlock(&cqspi->bus_mutex);
1081 }
1082
1083 static int cqspi_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf, size_t len)
1084 {
1085 int ret;
1086
1087 ret = cqspi_set_protocol(nor, 0);
1088 if (!ret)
1089 ret = cqspi_command_read(nor, opcode, buf, len);
1090
1091 return ret;
1092 }
1093
1094 static int cqspi_write_reg(struct spi_nor *nor, u8 opcode, const u8 *buf,
1095 size_t len)
1096 {
1097 int ret;
1098
1099 ret = cqspi_set_protocol(nor, 0);
1100 if (!ret)
1101 ret = cqspi_command_write(nor, opcode, buf, len);
1102
1103 return ret;
1104 }
1105
1106 static int cqspi_of_get_flash_pdata(struct platform_device *pdev,
1107 struct cqspi_flash_pdata *f_pdata,
1108 struct device_node *np)
1109 {
1110 if (of_property_read_u32(np, "cdns,read-delay", &f_pdata->read_delay)) {
1111 dev_err(&pdev->dev, "couldn't determine read-delay\n");
1112 return -ENXIO;
1113 }
1114
1115 if (of_property_read_u32(np, "cdns,tshsl-ns", &f_pdata->tshsl_ns)) {
1116 dev_err(&pdev->dev, "couldn't determine tshsl-ns\n");
1117 return -ENXIO;
1118 }
1119
1120 if (of_property_read_u32(np, "cdns,tsd2d-ns", &f_pdata->tsd2d_ns)) {
1121 dev_err(&pdev->dev, "couldn't determine tsd2d-ns\n");
1122 return -ENXIO;
1123 }
1124
1125 if (of_property_read_u32(np, "cdns,tchsh-ns", &f_pdata->tchsh_ns)) {
1126 dev_err(&pdev->dev, "couldn't determine tchsh-ns\n");
1127 return -ENXIO;
1128 }
1129
1130 if (of_property_read_u32(np, "cdns,tslch-ns", &f_pdata->tslch_ns)) {
1131 dev_err(&pdev->dev, "couldn't determine tslch-ns\n");
1132 return -ENXIO;
1133 }
1134
1135 if (of_property_read_u32(np, "spi-max-frequency", &f_pdata->clk_rate)) {
1136 dev_err(&pdev->dev, "couldn't determine spi-max-frequency\n");
1137 return -ENXIO;
1138 }
1139
1140 return 0;
1141 }
1142
1143 static int cqspi_of_get_pdata(struct platform_device *pdev)
1144 {
1145 struct device_node *np = pdev->dev.of_node;
1146 struct cqspi_st *cqspi = platform_get_drvdata(pdev);
1147
1148 cqspi->is_decoded_cs = of_property_read_bool(np, "cdns,is-decoded-cs");
1149
1150 if (of_property_read_u32(np, "cdns,fifo-depth", &cqspi->fifo_depth)) {
1151 dev_err(&pdev->dev, "couldn't determine fifo-depth\n");
1152 return -ENXIO;
1153 }
1154
1155 if (of_property_read_u32(np, "cdns,fifo-width", &cqspi->fifo_width)) {
1156 dev_err(&pdev->dev, "couldn't determine fifo-width\n");
1157 return -ENXIO;
1158 }
1159
1160 if (of_property_read_u32(np, "cdns,trigger-address",
1161 &cqspi->trigger_address)) {
1162 dev_err(&pdev->dev, "couldn't determine trigger-address\n");
1163 return -ENXIO;
1164 }
1165
1166 cqspi->rclk_en = of_property_read_bool(np, "cdns,rclk-en");
1167
1168 return 0;
1169 }
1170
1171 static void cqspi_controller_init(struct cqspi_st *cqspi)
1172 {
1173 u32 reg;
1174
1175 cqspi_controller_enable(cqspi, 0);
1176
1177 /* Configure the remap address register, no remap */
1178 writel(0, cqspi->iobase + CQSPI_REG_REMAP);
1179
1180 /* Disable all interrupts. */
1181 writel(0, cqspi->iobase + CQSPI_REG_IRQMASK);
1182
1183 /* Configure the SRAM split to 1:1 . */
1184 writel(cqspi->fifo_depth / 2, cqspi->iobase + CQSPI_REG_SRAMPARTITION);
1185
1186 /* Load indirect trigger address. */
1187 writel(cqspi->trigger_address,
1188 cqspi->iobase + CQSPI_REG_INDIRECTTRIGGER);
1189
1190 /* Program read watermark -- 1/2 of the FIFO. */
1191 writel(cqspi->fifo_depth * cqspi->fifo_width / 2,
1192 cqspi->iobase + CQSPI_REG_INDIRECTRDWATERMARK);
1193 /* Program write watermark -- 1/8 of the FIFO. */
1194 writel(cqspi->fifo_depth * cqspi->fifo_width / 8,
1195 cqspi->iobase + CQSPI_REG_INDIRECTWRWATERMARK);
1196
1197 /* Enable Direct Access Controller */
1198 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
1199 reg |= CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL;
1200 writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);
1201
1202 cqspi_controller_enable(cqspi, 1);
1203 }
1204
1205 static void cqspi_request_mmap_dma(struct cqspi_st *cqspi)
1206 {
1207 dma_cap_mask_t mask;
1208
1209 dma_cap_zero(mask);
1210 dma_cap_set(DMA_MEMCPY, mask);
1211
1212 cqspi->rx_chan = dma_request_chan_by_mask(&mask);
1213 if (IS_ERR(cqspi->rx_chan)) {
1214 dev_err(&cqspi->pdev->dev, "No Rx DMA available\n");
1215 cqspi->rx_chan = NULL;
1216 }
1217 init_completion(&cqspi->rx_dma_complete);
1218 }
1219
1220 static const struct spi_nor_controller_ops cqspi_controller_ops = {
1221 .prepare = cqspi_prep,
1222 .unprepare = cqspi_unprep,
1223 .read_reg = cqspi_read_reg,
1224 .write_reg = cqspi_write_reg,
1225 .read = cqspi_read,
1226 .write = cqspi_write,
1227 .erase = cqspi_erase,
1228 };
1229
1230 static int cqspi_setup_flash(struct cqspi_st *cqspi, struct device_node *np)
1231 {
1232 struct platform_device *pdev = cqspi->pdev;
1233 struct device *dev = &pdev->dev;
1234 const struct cqspi_driver_platdata *ddata;
1235 struct spi_nor_hwcaps hwcaps;
1236 struct cqspi_flash_pdata *f_pdata;
1237 struct spi_nor *nor;
1238 struct mtd_info *mtd;
1239 unsigned int cs;
1240 int i, ret;
1241
1242 ddata = of_device_get_match_data(dev);
1243 if (!ddata) {
1244 dev_err(dev, "Couldn't find driver data\n");
1245 return -EINVAL;
1246 }
1247 hwcaps.mask = ddata->hwcaps_mask;
1248
1249 /* Get flash device data */
1250 for_each_available_child_of_node(dev->of_node, np) {
1251 ret = of_property_read_u32(np, "reg", &cs);
1252 if (ret) {
1253 dev_err(dev, "Couldn't determine chip select.\n");
1254 goto err;
1255 }
1256
1257 if (cs >= CQSPI_MAX_CHIPSELECT) {
1258 ret = -EINVAL;
1259 dev_err(dev, "Chip select %d out of range.\n", cs);
1260 goto err;
1261 }
1262
1263 f_pdata = &cqspi->f_pdata[cs];
1264 f_pdata->cqspi = cqspi;
1265 f_pdata->cs = cs;
1266
1267 ret = cqspi_of_get_flash_pdata(pdev, f_pdata, np);
1268 if (ret)
1269 goto err;
1270
1271 nor = &f_pdata->nor;
1272 mtd = &nor->mtd;
1273
1274 mtd->priv = nor;
1275
1276 nor->dev = dev;
1277 spi_nor_set_flash_node(nor, np);
1278 nor->priv = f_pdata;
1279 nor->controller_ops = &cqspi_controller_ops;
1280
1281 mtd->name = devm_kasprintf(dev, GFP_KERNEL, "%s.%d",
1282 dev_name(dev), cs);
1283 if (!mtd->name) {
1284 ret = -ENOMEM;
1285 goto err;
1286 }
1287
1288 ret = spi_nor_scan(nor, NULL, &hwcaps);
1289 if (ret)
1290 goto err;
1291
1292 ret = mtd_device_register(mtd, NULL, 0);
1293 if (ret)
1294 goto err;
1295
1296 f_pdata->registered = true;
1297
1298 if (mtd->size <= cqspi->ahb_size) {
1299 f_pdata->use_direct_mode = true;
1300 dev_dbg(nor->dev, "using direct mode for %s\n",
1301 mtd->name);
1302
1303 if (!cqspi->rx_chan)
1304 cqspi_request_mmap_dma(cqspi);
1305 }
1306 }
1307
1308 return 0;
1309
1310 err:
1311 for (i = 0; i < CQSPI_MAX_CHIPSELECT; i++)
1312 if (cqspi->f_pdata[i].registered)
1313 mtd_device_unregister(&cqspi->f_pdata[i].nor.mtd);
1314 return ret;
1315 }
1316
1317 static int cqspi_probe(struct platform_device *pdev)
1318 {
1319 struct device_node *np = pdev->dev.of_node;
1320 struct device *dev = &pdev->dev;
1321 struct cqspi_st *cqspi;
1322 struct resource *res;
1323 struct resource *res_ahb;
1324 struct reset_control *rstc, *rstc_ocp;
1325 const struct cqspi_driver_platdata *ddata;
1326 int ret;
1327 int irq;
1328
1329 cqspi = devm_kzalloc(dev, sizeof(*cqspi), GFP_KERNEL);
1330 if (!cqspi)
1331 return -ENOMEM;
1332
1333 mutex_init(&cqspi->bus_mutex);
1334 cqspi->pdev = pdev;
1335 platform_set_drvdata(pdev, cqspi);
1336
1337 /* Obtain configuration from OF. */
1338 ret = cqspi_of_get_pdata(pdev);
1339 if (ret) {
1340 dev_err(dev, "Cannot get mandatory OF data.\n");
1341 return -ENODEV;
1342 }
1343
1344 /* Obtain QSPI clock. */
1345 cqspi->clk = devm_clk_get(dev, NULL);
1346 if (IS_ERR(cqspi->clk)) {
1347 dev_err(dev, "Cannot claim QSPI clock.\n");
1348 return PTR_ERR(cqspi->clk);
1349 }
1350
1351 /* Obtain and remap controller address. */
1352 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1353 cqspi->iobase = devm_ioremap_resource(dev, res);
1354 if (IS_ERR(cqspi->iobase)) {
1355 dev_err(dev, "Cannot remap controller address.\n");
1356 return PTR_ERR(cqspi->iobase);
1357 }
1358
1359 /* Obtain and remap AHB address. */
1360 res_ahb = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1361 cqspi->ahb_base = devm_ioremap_resource(dev, res_ahb);
1362 if (IS_ERR(cqspi->ahb_base)) {
1363 dev_err(dev, "Cannot remap AHB address.\n");
1364 return PTR_ERR(cqspi->ahb_base);
1365 }
1366 cqspi->mmap_phys_base = (dma_addr_t)res_ahb->start;
1367 cqspi->ahb_size = resource_size(res_ahb);
1368
1369 init_completion(&cqspi->transfer_complete);
1370
1371 /* Obtain IRQ line. */
1372 irq = platform_get_irq(pdev, 0);
1373 if (irq < 0)
1374 return -ENXIO;
1375
1376 pm_runtime_enable(dev);
1377 ret = pm_runtime_get_sync(dev);
1378 if (ret < 0) {
1379 pm_runtime_put_noidle(dev);
1380 return ret;
1381 }
1382
1383 ret = clk_prepare_enable(cqspi->clk);
1384 if (ret) {
1385 dev_err(dev, "Cannot enable QSPI clock.\n");
1386 goto probe_clk_failed;
1387 }
1388
1389 /* Obtain QSPI reset control */
1390 rstc = devm_reset_control_get_optional_exclusive(dev, "qspi");
1391 if (IS_ERR(rstc)) {
1392 dev_err(dev, "Cannot get QSPI reset.\n");
1393 return PTR_ERR(rstc);
1394 }
1395
1396 rstc_ocp = devm_reset_control_get_optional_exclusive(dev, "qspi-ocp");
1397 if (IS_ERR(rstc_ocp)) {
1398 dev_err(dev, "Cannot get QSPI OCP reset.\n");
1399 return PTR_ERR(rstc_ocp);
1400 }
1401
1402 reset_control_assert(rstc);
1403 reset_control_deassert(rstc);
1404
1405 reset_control_assert(rstc_ocp);
1406 reset_control_deassert(rstc_ocp);
1407
1408 cqspi->master_ref_clk_hz = clk_get_rate(cqspi->clk);
1409 ddata = of_device_get_match_data(dev);
1410 if (ddata && (ddata->quirks & CQSPI_NEEDS_WR_DELAY))
1411 cqspi->wr_delay = 5 * DIV_ROUND_UP(NSEC_PER_SEC,
1412 cqspi->master_ref_clk_hz);
1413
1414 ret = devm_request_irq(dev, irq, cqspi_irq_handler, 0,
1415 pdev->name, cqspi);
1416 if (ret) {
1417 dev_err(dev, "Cannot request IRQ.\n");
1418 goto probe_irq_failed;
1419 }
1420
1421 cqspi_wait_idle(cqspi);
1422 cqspi_controller_init(cqspi);
1423 cqspi->current_cs = -1;
1424 cqspi->sclk = 0;
1425
1426 ret = cqspi_setup_flash(cqspi, np);
1427 if (ret) {
1428 dev_err(dev, "Cadence QSPI NOR probe failed %d\n", ret);
1429 goto probe_setup_failed;
1430 }
1431
1432 return ret;
1433 probe_setup_failed:
1434 cqspi_controller_enable(cqspi, 0);
1435 probe_irq_failed:
1436 clk_disable_unprepare(cqspi->clk);
1437 probe_clk_failed:
1438 pm_runtime_put_sync(dev);
1439 pm_runtime_disable(dev);
1440 return ret;
1441 }
1442
1443 static int cqspi_remove(struct platform_device *pdev)
1444 {
1445 struct cqspi_st *cqspi = platform_get_drvdata(pdev);
1446 int i;
1447
1448 for (i = 0; i < CQSPI_MAX_CHIPSELECT; i++)
1449 if (cqspi->f_pdata[i].registered)
1450 mtd_device_unregister(&cqspi->f_pdata[i].nor.mtd);
1451
1452 cqspi_controller_enable(cqspi, 0);
1453
1454 if (cqspi->rx_chan)
1455 dma_release_channel(cqspi->rx_chan);
1456
1457 clk_disable_unprepare(cqspi->clk);
1458
1459 pm_runtime_put_sync(&pdev->dev);
1460 pm_runtime_disable(&pdev->dev);
1461
1462 return 0;
1463 }
1464
1465 #ifdef CONFIG_PM_SLEEP
1466 static int cqspi_suspend(struct device *dev)
1467 {
1468 struct cqspi_st *cqspi = dev_get_drvdata(dev);
1469
1470 cqspi_controller_enable(cqspi, 0);
1471 return 0;
1472 }
1473
1474 static int cqspi_resume(struct device *dev)
1475 {
1476 struct cqspi_st *cqspi = dev_get_drvdata(dev);
1477
1478 cqspi_controller_enable(cqspi, 1);
1479 return 0;
1480 }
1481
1482 static const struct dev_pm_ops cqspi__dev_pm_ops = {
1483 .suspend = cqspi_suspend,
1484 .resume = cqspi_resume,
1485 };
1486
1487 #define CQSPI_DEV_PM_OPS (&cqspi__dev_pm_ops)
1488 #else
1489 #define CQSPI_DEV_PM_OPS NULL
1490 #endif
1491
1492 static const struct cqspi_driver_platdata cdns_qspi = {
1493 .hwcaps_mask = CQSPI_BASE_HWCAPS_MASK,
1494 };
1495
1496 static const struct cqspi_driver_platdata k2g_qspi = {
1497 .hwcaps_mask = CQSPI_BASE_HWCAPS_MASK,
1498 .quirks = CQSPI_NEEDS_WR_DELAY,
1499 };
1500
1501 static const struct cqspi_driver_platdata am654_ospi = {
1502 .hwcaps_mask = CQSPI_BASE_HWCAPS_MASK | SNOR_HWCAPS_READ_1_1_8,
1503 .quirks = CQSPI_NEEDS_WR_DELAY,
1504 };
1505
1506 static const struct of_device_id cqspi_dt_ids[] = {
1507 {
1508 .compatible = "cdns,qspi-nor",
1509 .data = &cdns_qspi,
1510 },
1511 {
1512 .compatible = "ti,k2g-qspi",
1513 .data = &k2g_qspi,
1514 },
1515 {
1516 .compatible = "ti,am654-ospi",
1517 .data = &am654_ospi,
1518 },
1519 { /* end of table */ }
1520 };
1521
1522 MODULE_DEVICE_TABLE(of, cqspi_dt_ids);
1523
1524 static struct platform_driver cqspi_platform_driver = {
1525 .probe = cqspi_probe,
1526 .remove = cqspi_remove,
1527 .driver = {
1528 .name = CQSPI_NAME,
1529 .pm = CQSPI_DEV_PM_OPS,
1530 .of_match_table = cqspi_dt_ids,
1531 },
1532 };
1533
1534 module_platform_driver(cqspi_platform_driver);
1535
1536 MODULE_DESCRIPTION("Cadence QSPI Controller Driver");
1537 MODULE_LICENSE("GPL v2");
1538 MODULE_ALIAS("platform:" CQSPI_NAME);
1539 MODULE_AUTHOR("Ley Foon Tan <lftan@altera.com>");
1540 MODULE_AUTHOR("Graham Moore <grmoore@opensource.altera.com>");
Linux with added FPC-III support