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treewide: remove redundant IS_ERR() before error code check
[linux/fpc-iii.git] / drivers / net / can / rcar / rcar_canfd.c
blobde59dd6aad29918633ccfc4a237fccc26643b1d5
1 // SPDX-License-Identifier: GPL-2.0+
2 /* Renesas R-Car CAN FD device driver
3 *
4 * Copyright (C) 2015 Renesas Electronics Corp.
5 */
6
7 /* The R-Car CAN FD controller can operate in either one of the below two modes
8 * - CAN FD only mode
9 * - Classical CAN (CAN 2.0) only mode
10 *
11 * This driver puts the controller in CAN FD only mode by default. In this
12 * mode, the controller acts as a CAN FD node that can also interoperate with
13 * CAN 2.0 nodes.
14 *
15 * To switch the controller to Classical CAN (CAN 2.0) only mode, add
16 * "renesas,no-can-fd" optional property to the device tree node. A h/w reset is
17 * also required to switch modes.
18 *
19 * Note: The h/w manual register naming convention is clumsy and not acceptable
20 * to use as it is in the driver. However, those names are added as comments
21 * wherever it is modified to a readable name.
22 */
23
24 #include <linux/module.h>
25 #include <linux/moduleparam.h>
26 #include <linux/kernel.h>
27 #include <linux/types.h>
28 #include <linux/interrupt.h>
29 #include <linux/errno.h>
30 #include <linux/netdevice.h>
31 #include <linux/platform_device.h>
32 #include <linux/can/led.h>
33 #include <linux/can/dev.h>
34 #include <linux/clk.h>
35 #include <linux/of.h>
36 #include <linux/of_device.h>
37 #include <linux/bitmap.h>
38 #include <linux/bitops.h>
39 #include <linux/iopoll.h>
40
41 #define RCANFD_DRV_NAME "rcar_canfd"
42
43 /* Global register bits */
44
45 /* RSCFDnCFDGRMCFG */
46 #define RCANFD_GRMCFG_RCMC BIT(0)
47
48 /* RSCFDnCFDGCFG / RSCFDnGCFG */
49 #define RCANFD_GCFG_EEFE BIT(6)
50 #define RCANFD_GCFG_CMPOC BIT(5) /* CAN FD only */
51 #define RCANFD_GCFG_DCS BIT(4)
52 #define RCANFD_GCFG_DCE BIT(1)
53 #define RCANFD_GCFG_TPRI BIT(0)
54
55 /* RSCFDnCFDGCTR / RSCFDnGCTR */
56 #define RCANFD_GCTR_TSRST BIT(16)
57 #define RCANFD_GCTR_CFMPOFIE BIT(11) /* CAN FD only */
58 #define RCANFD_GCTR_THLEIE BIT(10)
59 #define RCANFD_GCTR_MEIE BIT(9)
60 #define RCANFD_GCTR_DEIE BIT(8)
61 #define RCANFD_GCTR_GSLPR BIT(2)
62 #define RCANFD_GCTR_GMDC_MASK (0x3)
63 #define RCANFD_GCTR_GMDC_GOPM (0x0)
64 #define RCANFD_GCTR_GMDC_GRESET (0x1)
65 #define RCANFD_GCTR_GMDC_GTEST (0x2)
66
67 /* RSCFDnCFDGSTS / RSCFDnGSTS */
68 #define RCANFD_GSTS_GRAMINIT BIT(3)
69 #define RCANFD_GSTS_GSLPSTS BIT(2)
70 #define RCANFD_GSTS_GHLTSTS BIT(1)
71 #define RCANFD_GSTS_GRSTSTS BIT(0)
72 /* Non-operational status */
73 #define RCANFD_GSTS_GNOPM (BIT(0) | BIT(1) | BIT(2) | BIT(3))
74
75 /* RSCFDnCFDGERFL / RSCFDnGERFL */
76 #define RCANFD_GERFL_EEF1 BIT(17)
77 #define RCANFD_GERFL_EEF0 BIT(16)
78 #define RCANFD_GERFL_CMPOF BIT(3) /* CAN FD only */
79 #define RCANFD_GERFL_THLES BIT(2)
80 #define RCANFD_GERFL_MES BIT(1)
81 #define RCANFD_GERFL_DEF BIT(0)
82
83 #define RCANFD_GERFL_ERR(gpriv, x) ((x) & (RCANFD_GERFL_EEF1 |\
84 RCANFD_GERFL_EEF0 | RCANFD_GERFL_MES |\
85 (gpriv->fdmode ?\
86 RCANFD_GERFL_CMPOF : 0)))
87
88 /* AFL Rx rules registers */
89
90 /* RSCFDnCFDGAFLCFG0 / RSCFDnGAFLCFG0 */
91 #define RCANFD_GAFLCFG_SETRNC(n, x) (((x) & 0xff) << (24 - n * 8))
92 #define RCANFD_GAFLCFG_GETRNC(n, x) (((x) >> (24 - n * 8)) & 0xff)
93
94 /* RSCFDnCFDGAFLECTR / RSCFDnGAFLECTR */
95 #define RCANFD_GAFLECTR_AFLDAE BIT(8)
96 #define RCANFD_GAFLECTR_AFLPN(x) ((x) & 0x1f)
97
98 /* RSCFDnCFDGAFLIDj / RSCFDnGAFLIDj */
99 #define RCANFD_GAFLID_GAFLLB BIT(29)
100
101 /* RSCFDnCFDGAFLP1_j / RSCFDnGAFLP1_j */
102 #define RCANFD_GAFLP1_GAFLFDP(x) (1 << (x))
103
104 /* Channel register bits */
105
106 /* RSCFDnCmCFG - Classical CAN only */
107 #define RCANFD_CFG_SJW(x) (((x) & 0x3) << 24)
108 #define RCANFD_CFG_TSEG2(x) (((x) & 0x7) << 20)
109 #define RCANFD_CFG_TSEG1(x) (((x) & 0xf) << 16)
110 #define RCANFD_CFG_BRP(x) (((x) & 0x3ff) << 0)
111
112 /* RSCFDnCFDCmNCFG - CAN FD only */
113 #define RCANFD_NCFG_NTSEG2(x) (((x) & 0x1f) << 24)
114 #define RCANFD_NCFG_NTSEG1(x) (((x) & 0x7f) << 16)
115 #define RCANFD_NCFG_NSJW(x) (((x) & 0x1f) << 11)
116 #define RCANFD_NCFG_NBRP(x) (((x) & 0x3ff) << 0)
117
118 /* RSCFDnCFDCmCTR / RSCFDnCmCTR */
119 #define RCANFD_CCTR_CTME BIT(24)
120 #define RCANFD_CCTR_ERRD BIT(23)
121 #define RCANFD_CCTR_BOM_MASK (0x3 << 21)
122 #define RCANFD_CCTR_BOM_ISO (0x0 << 21)
123 #define RCANFD_CCTR_BOM_BENTRY (0x1 << 21)
124 #define RCANFD_CCTR_BOM_BEND (0x2 << 21)
125 #define RCANFD_CCTR_TDCVFIE BIT(19)
126 #define RCANFD_CCTR_SOCOIE BIT(18)
127 #define RCANFD_CCTR_EOCOIE BIT(17)
128 #define RCANFD_CCTR_TAIE BIT(16)
129 #define RCANFD_CCTR_ALIE BIT(15)
130 #define RCANFD_CCTR_BLIE BIT(14)
131 #define RCANFD_CCTR_OLIE BIT(13)
132 #define RCANFD_CCTR_BORIE BIT(12)
133 #define RCANFD_CCTR_BOEIE BIT(11)
134 #define RCANFD_CCTR_EPIE BIT(10)
135 #define RCANFD_CCTR_EWIE BIT(9)
136 #define RCANFD_CCTR_BEIE BIT(8)
137 #define RCANFD_CCTR_CSLPR BIT(2)
138 #define RCANFD_CCTR_CHMDC_MASK (0x3)
139 #define RCANFD_CCTR_CHDMC_COPM (0x0)
140 #define RCANFD_CCTR_CHDMC_CRESET (0x1)
141 #define RCANFD_CCTR_CHDMC_CHLT (0x2)
142
143 /* RSCFDnCFDCmSTS / RSCFDnCmSTS */
144 #define RCANFD_CSTS_COMSTS BIT(7)
145 #define RCANFD_CSTS_RECSTS BIT(6)
146 #define RCANFD_CSTS_TRMSTS BIT(5)
147 #define RCANFD_CSTS_BOSTS BIT(4)
148 #define RCANFD_CSTS_EPSTS BIT(3)
149 #define RCANFD_CSTS_SLPSTS BIT(2)
150 #define RCANFD_CSTS_HLTSTS BIT(1)
151 #define RCANFD_CSTS_CRSTSTS BIT(0)
152
153 #define RCANFD_CSTS_TECCNT(x) (((x) >> 24) & 0xff)
154 #define RCANFD_CSTS_RECCNT(x) (((x) >> 16) & 0xff)
155
156 /* RSCFDnCFDCmERFL / RSCFDnCmERFL */
157 #define RCANFD_CERFL_ADERR BIT(14)
158 #define RCANFD_CERFL_B0ERR BIT(13)
159 #define RCANFD_CERFL_B1ERR BIT(12)
160 #define RCANFD_CERFL_CERR BIT(11)
161 #define RCANFD_CERFL_AERR BIT(10)
162 #define RCANFD_CERFL_FERR BIT(9)
163 #define RCANFD_CERFL_SERR BIT(8)
164 #define RCANFD_CERFL_ALF BIT(7)
165 #define RCANFD_CERFL_BLF BIT(6)
166 #define RCANFD_CERFL_OVLF BIT(5)
167 #define RCANFD_CERFL_BORF BIT(4)
168 #define RCANFD_CERFL_BOEF BIT(3)
169 #define RCANFD_CERFL_EPF BIT(2)
170 #define RCANFD_CERFL_EWF BIT(1)
171 #define RCANFD_CERFL_BEF BIT(0)
172
173 #define RCANFD_CERFL_ERR(x) ((x) & (0x7fff)) /* above bits 14:0 */
174
175 /* RSCFDnCFDCmDCFG */
176 #define RCANFD_DCFG_DSJW(x) (((x) & 0x7) << 24)
177 #define RCANFD_DCFG_DTSEG2(x) (((x) & 0x7) << 20)
178 #define RCANFD_DCFG_DTSEG1(x) (((x) & 0xf) << 16)
179 #define RCANFD_DCFG_DBRP(x) (((x) & 0xff) << 0)
180
181 /* RSCFDnCFDCmFDCFG */
182 #define RCANFD_FDCFG_TDCE BIT(9)
183 #define RCANFD_FDCFG_TDCOC BIT(8)
184 #define RCANFD_FDCFG_TDCO(x) (((x) & 0x7f) >> 16)
185
186 /* RSCFDnCFDRFCCx */
187 #define RCANFD_RFCC_RFIM BIT(12)
188 #define RCANFD_RFCC_RFDC(x) (((x) & 0x7) << 8)
189 #define RCANFD_RFCC_RFPLS(x) (((x) & 0x7) << 4)
190 #define RCANFD_RFCC_RFIE BIT(1)
191 #define RCANFD_RFCC_RFE BIT(0)
192
193 /* RSCFDnCFDRFSTSx */
194 #define RCANFD_RFSTS_RFIF BIT(3)
195 #define RCANFD_RFSTS_RFMLT BIT(2)
196 #define RCANFD_RFSTS_RFFLL BIT(1)
197 #define RCANFD_RFSTS_RFEMP BIT(0)
198
199 /* RSCFDnCFDRFIDx */
200 #define RCANFD_RFID_RFIDE BIT(31)
201 #define RCANFD_RFID_RFRTR BIT(30)
202
203 /* RSCFDnCFDRFPTRx */
204 #define RCANFD_RFPTR_RFDLC(x) (((x) >> 28) & 0xf)
205 #define RCANFD_RFPTR_RFPTR(x) (((x) >> 16) & 0xfff)
206 #define RCANFD_RFPTR_RFTS(x) (((x) >> 0) & 0xffff)
207
208 /* RSCFDnCFDRFFDSTSx */
209 #define RCANFD_RFFDSTS_RFFDF BIT(2)
210 #define RCANFD_RFFDSTS_RFBRS BIT(1)
211 #define RCANFD_RFFDSTS_RFESI BIT(0)
212
213 /* Common FIFO bits */
214
215 /* RSCFDnCFDCFCCk */
216 #define RCANFD_CFCC_CFTML(x) (((x) & 0xf) << 20)
217 #define RCANFD_CFCC_CFM(x) (((x) & 0x3) << 16)
218 #define RCANFD_CFCC_CFIM BIT(12)
219 #define RCANFD_CFCC_CFDC(x) (((x) & 0x7) << 8)
220 #define RCANFD_CFCC_CFPLS(x) (((x) & 0x7) << 4)
221 #define RCANFD_CFCC_CFTXIE BIT(2)
222 #define RCANFD_CFCC_CFE BIT(0)
223
224 /* RSCFDnCFDCFSTSk */
225 #define RCANFD_CFSTS_CFMC(x) (((x) >> 8) & 0xff)
226 #define RCANFD_CFSTS_CFTXIF BIT(4)
227 #define RCANFD_CFSTS_CFMLT BIT(2)
228 #define RCANFD_CFSTS_CFFLL BIT(1)
229 #define RCANFD_CFSTS_CFEMP BIT(0)
230
231 /* RSCFDnCFDCFIDk */
232 #define RCANFD_CFID_CFIDE BIT(31)
233 #define RCANFD_CFID_CFRTR BIT(30)
234 #define RCANFD_CFID_CFID_MASK(x) ((x) & 0x1fffffff)
235
236 /* RSCFDnCFDCFPTRk */
237 #define RCANFD_CFPTR_CFDLC(x) (((x) & 0xf) << 28)
238 #define RCANFD_CFPTR_CFPTR(x) (((x) & 0xfff) << 16)
239 #define RCANFD_CFPTR_CFTS(x) (((x) & 0xff) << 0)
240
241 /* RSCFDnCFDCFFDCSTSk */
242 #define RCANFD_CFFDCSTS_CFFDF BIT(2)
243 #define RCANFD_CFFDCSTS_CFBRS BIT(1)
244 #define RCANFD_CFFDCSTS_CFESI BIT(0)
245
246 /* This controller supports either Classical CAN only mode or CAN FD only mode.
247 * These modes are supported in two separate set of register maps & names.
248 * However, some of the register offsets are common for both modes. Those
249 * offsets are listed below as Common registers.
250 *
251 * The CAN FD only mode specific registers & Classical CAN only mode specific
252 * registers are listed separately. Their register names starts with
253 * RCANFD_F_xxx & RCANFD_C_xxx respectively.
254 */
255
256 /* Common registers */
257
258 /* RSCFDnCFDCmNCFG / RSCFDnCmCFG */
259 #define RCANFD_CCFG(m) (0x0000 + (0x10 * (m)))
260 /* RSCFDnCFDCmCTR / RSCFDnCmCTR */
261 #define RCANFD_CCTR(m) (0x0004 + (0x10 * (m)))
262 /* RSCFDnCFDCmSTS / RSCFDnCmSTS */
263 #define RCANFD_CSTS(m) (0x0008 + (0x10 * (m)))
264 /* RSCFDnCFDCmERFL / RSCFDnCmERFL */
265 #define RCANFD_CERFL(m) (0x000C + (0x10 * (m)))
266
267 /* RSCFDnCFDGCFG / RSCFDnGCFG */
268 #define RCANFD_GCFG (0x0084)
269 /* RSCFDnCFDGCTR / RSCFDnGCTR */
270 #define RCANFD_GCTR (0x0088)
271 /* RSCFDnCFDGCTS / RSCFDnGCTS */
272 #define RCANFD_GSTS (0x008c)
273 /* RSCFDnCFDGERFL / RSCFDnGERFL */
274 #define RCANFD_GERFL (0x0090)
275 /* RSCFDnCFDGTSC / RSCFDnGTSC */
276 #define RCANFD_GTSC (0x0094)
277 /* RSCFDnCFDGAFLECTR / RSCFDnGAFLECTR */
278 #define RCANFD_GAFLECTR (0x0098)
279 /* RSCFDnCFDGAFLCFG0 / RSCFDnGAFLCFG0 */
280 #define RCANFD_GAFLCFG0 (0x009c)
281 /* RSCFDnCFDGAFLCFG1 / RSCFDnGAFLCFG1 */
282 #define RCANFD_GAFLCFG1 (0x00a0)
283 /* RSCFDnCFDRMNB / RSCFDnRMNB */
284 #define RCANFD_RMNB (0x00a4)
285 /* RSCFDnCFDRMND / RSCFDnRMND */
286 #define RCANFD_RMND(y) (0x00a8 + (0x04 * (y)))
287
288 /* RSCFDnCFDRFCCx / RSCFDnRFCCx */
289 #define RCANFD_RFCC(x) (0x00b8 + (0x04 * (x)))
290 /* RSCFDnCFDRFSTSx / RSCFDnRFSTSx */
291 #define RCANFD_RFSTS(x) (0x00d8 + (0x04 * (x)))
292 /* RSCFDnCFDRFPCTRx / RSCFDnRFPCTRx */
293 #define RCANFD_RFPCTR(x) (0x00f8 + (0x04 * (x)))
294
295 /* Common FIFO Control registers */
296
297 /* RSCFDnCFDCFCCx / RSCFDnCFCCx */
298 #define RCANFD_CFCC(ch, idx) (0x0118 + (0x0c * (ch)) + \
299 (0x04 * (idx)))
300 /* RSCFDnCFDCFSTSx / RSCFDnCFSTSx */
301 #define RCANFD_CFSTS(ch, idx) (0x0178 + (0x0c * (ch)) + \
302 (0x04 * (idx)))
303 /* RSCFDnCFDCFPCTRx / RSCFDnCFPCTRx */
304 #define RCANFD_CFPCTR(ch, idx) (0x01d8 + (0x0c * (ch)) + \
305 (0x04 * (idx)))
306
307 /* RSCFDnCFDFESTS / RSCFDnFESTS */
308 #define RCANFD_FESTS (0x0238)
309 /* RSCFDnCFDFFSTS / RSCFDnFFSTS */
310 #define RCANFD_FFSTS (0x023c)
311 /* RSCFDnCFDFMSTS / RSCFDnFMSTS */
312 #define RCANFD_FMSTS (0x0240)
313 /* RSCFDnCFDRFISTS / RSCFDnRFISTS */
314 #define RCANFD_RFISTS (0x0244)
315 /* RSCFDnCFDCFRISTS / RSCFDnCFRISTS */
316 #define RCANFD_CFRISTS (0x0248)
317 /* RSCFDnCFDCFTISTS / RSCFDnCFTISTS */
318 #define RCANFD_CFTISTS (0x024c)
319
320 /* RSCFDnCFDTMCp / RSCFDnTMCp */
321 #define RCANFD_TMC(p) (0x0250 + (0x01 * (p)))
322 /* RSCFDnCFDTMSTSp / RSCFDnTMSTSp */
323 #define RCANFD_TMSTS(p) (0x02d0 + (0x01 * (p)))
324
325 /* RSCFDnCFDTMTRSTSp / RSCFDnTMTRSTSp */
326 #define RCANFD_TMTRSTS(y) (0x0350 + (0x04 * (y)))
327 /* RSCFDnCFDTMTARSTSp / RSCFDnTMTARSTSp */
328 #define RCANFD_TMTARSTS(y) (0x0360 + (0x04 * (y)))
329 /* RSCFDnCFDTMTCSTSp / RSCFDnTMTCSTSp */
330 #define RCANFD_TMTCSTS(y) (0x0370 + (0x04 * (y)))
331 /* RSCFDnCFDTMTASTSp / RSCFDnTMTASTSp */
332 #define RCANFD_TMTASTS(y) (0x0380 + (0x04 * (y)))
333 /* RSCFDnCFDTMIECy / RSCFDnTMIECy */
334 #define RCANFD_TMIEC(y) (0x0390 + (0x04 * (y)))
335
336 /* RSCFDnCFDTXQCCm / RSCFDnTXQCCm */
337 #define RCANFD_TXQCC(m) (0x03a0 + (0x04 * (m)))
338 /* RSCFDnCFDTXQSTSm / RSCFDnTXQSTSm */
339 #define RCANFD_TXQSTS(m) (0x03c0 + (0x04 * (m)))
340 /* RSCFDnCFDTXQPCTRm / RSCFDnTXQPCTRm */
341 #define RCANFD_TXQPCTR(m) (0x03e0 + (0x04 * (m)))
342
343 /* RSCFDnCFDTHLCCm / RSCFDnTHLCCm */
344 #define RCANFD_THLCC(m) (0x0400 + (0x04 * (m)))
345 /* RSCFDnCFDTHLSTSm / RSCFDnTHLSTSm */
346 #define RCANFD_THLSTS(m) (0x0420 + (0x04 * (m)))
347 /* RSCFDnCFDTHLPCTRm / RSCFDnTHLPCTRm */
348 #define RCANFD_THLPCTR(m) (0x0440 + (0x04 * (m)))
349
350 /* RSCFDnCFDGTINTSTS0 / RSCFDnGTINTSTS0 */
351 #define RCANFD_GTINTSTS0 (0x0460)
352 /* RSCFDnCFDGTINTSTS1 / RSCFDnGTINTSTS1 */
353 #define RCANFD_GTINTSTS1 (0x0464)
354 /* RSCFDnCFDGTSTCFG / RSCFDnGTSTCFG */
355 #define RCANFD_GTSTCFG (0x0468)
356 /* RSCFDnCFDGTSTCTR / RSCFDnGTSTCTR */
357 #define RCANFD_GTSTCTR (0x046c)
358 /* RSCFDnCFDGLOCKK / RSCFDnGLOCKK */
359 #define RCANFD_GLOCKK (0x047c)
360 /* RSCFDnCFDGRMCFG */
361 #define RCANFD_GRMCFG (0x04fc)
362
363 /* RSCFDnCFDGAFLIDj / RSCFDnGAFLIDj */
364 #define RCANFD_GAFLID(offset, j) ((offset) + (0x10 * (j)))
365 /* RSCFDnCFDGAFLMj / RSCFDnGAFLMj */
366 #define RCANFD_GAFLM(offset, j) ((offset) + 0x04 + (0x10 * (j)))
367 /* RSCFDnCFDGAFLP0j / RSCFDnGAFLP0j */
368 #define RCANFD_GAFLP0(offset, j) ((offset) + 0x08 + (0x10 * (j)))
369 /* RSCFDnCFDGAFLP1j / RSCFDnGAFLP1j */
370 #define RCANFD_GAFLP1(offset, j) ((offset) + 0x0c + (0x10 * (j)))
371
372 /* Classical CAN only mode register map */
373
374 /* RSCFDnGAFLXXXj offset */
375 #define RCANFD_C_GAFL_OFFSET (0x0500)
376
377 /* RSCFDnRMXXXq -> RCANFD_C_RMXXX(q) */
378 #define RCANFD_C_RMID(q) (0x0600 + (0x10 * (q)))
379 #define RCANFD_C_RMPTR(q) (0x0604 + (0x10 * (q)))
380 #define RCANFD_C_RMDF0(q) (0x0608 + (0x10 * (q)))
381 #define RCANFD_C_RMDF1(q) (0x060c + (0x10 * (q)))
382
383 /* RSCFDnRFXXx -> RCANFD_C_RFXX(x) */
384 #define RCANFD_C_RFOFFSET (0x0e00)
385 #define RCANFD_C_RFID(x) (RCANFD_C_RFOFFSET + (0x10 * (x)))
386 #define RCANFD_C_RFPTR(x) (RCANFD_C_RFOFFSET + 0x04 + \
387 (0x10 * (x)))
388 #define RCANFD_C_RFDF(x, df) (RCANFD_C_RFOFFSET + 0x08 + \
389 (0x10 * (x)) + (0x04 * (df)))
390
391 /* RSCFDnCFXXk -> RCANFD_C_CFXX(ch, k) */
392 #define RCANFD_C_CFOFFSET (0x0e80)
393 #define RCANFD_C_CFID(ch, idx) (RCANFD_C_CFOFFSET + (0x30 * (ch)) + \
394 (0x10 * (idx)))
395 #define RCANFD_C_CFPTR(ch, idx) (RCANFD_C_CFOFFSET + 0x04 + \
396 (0x30 * (ch)) + (0x10 * (idx)))
397 #define RCANFD_C_CFDF(ch, idx, df) (RCANFD_C_CFOFFSET + 0x08 + \
398 (0x30 * (ch)) + (0x10 * (idx)) + \
399 (0x04 * (df)))
400
401 /* RSCFDnTMXXp -> RCANFD_C_TMXX(p) */
402 #define RCANFD_C_TMID(p) (0x1000 + (0x10 * (p)))
403 #define RCANFD_C_TMPTR(p) (0x1004 + (0x10 * (p)))
404 #define RCANFD_C_TMDF0(p) (0x1008 + (0x10 * (p)))
405 #define RCANFD_C_TMDF1(p) (0x100c + (0x10 * (p)))
406
407 /* RSCFDnTHLACCm */
408 #define RCANFD_C_THLACC(m) (0x1800 + (0x04 * (m)))
409 /* RSCFDnRPGACCr */
410 #define RCANFD_C_RPGACC(r) (0x1900 + (0x04 * (r)))
411
412 /* CAN FD mode specific register map */
413
414 /* RSCFDnCFDCmXXX -> RCANFD_F_XXX(m) */
415 #define RCANFD_F_DCFG(m) (0x0500 + (0x20 * (m)))
416 #define RCANFD_F_CFDCFG(m) (0x0504 + (0x20 * (m)))
417 #define RCANFD_F_CFDCTR(m) (0x0508 + (0x20 * (m)))
418 #define RCANFD_F_CFDSTS(m) (0x050c + (0x20 * (m)))
419 #define RCANFD_F_CFDCRC(m) (0x0510 + (0x20 * (m)))
420
421 /* RSCFDnCFDGAFLXXXj offset */
422 #define RCANFD_F_GAFL_OFFSET (0x1000)
423
424 /* RSCFDnCFDRMXXXq -> RCANFD_F_RMXXX(q) */
425 #define RCANFD_F_RMID(q) (0x2000 + (0x20 * (q)))
426 #define RCANFD_F_RMPTR(q) (0x2004 + (0x20 * (q)))
427 #define RCANFD_F_RMFDSTS(q) (0x2008 + (0x20 * (q)))
428 #define RCANFD_F_RMDF(q, b) (0x200c + (0x04 * (b)) + (0x20 * (q)))
429
430 /* RSCFDnCFDRFXXx -> RCANFD_F_RFXX(x) */
431 #define RCANFD_F_RFOFFSET (0x3000)
432 #define RCANFD_F_RFID(x) (RCANFD_F_RFOFFSET + (0x80 * (x)))
433 #define RCANFD_F_RFPTR(x) (RCANFD_F_RFOFFSET + 0x04 + \
434 (0x80 * (x)))
435 #define RCANFD_F_RFFDSTS(x) (RCANFD_F_RFOFFSET + 0x08 + \
436 (0x80 * (x)))
437 #define RCANFD_F_RFDF(x, df) (RCANFD_F_RFOFFSET + 0x0c + \
438 (0x80 * (x)) + (0x04 * (df)))
439
440 /* RSCFDnCFDCFXXk -> RCANFD_F_CFXX(ch, k) */
441 #define RCANFD_F_CFOFFSET (0x3400)
442 #define RCANFD_F_CFID(ch, idx) (RCANFD_F_CFOFFSET + (0x180 * (ch)) + \
443 (0x80 * (idx)))
444 #define RCANFD_F_CFPTR(ch, idx) (RCANFD_F_CFOFFSET + 0x04 + \
445 (0x180 * (ch)) + (0x80 * (idx)))
446 #define RCANFD_F_CFFDCSTS(ch, idx) (RCANFD_F_CFOFFSET + 0x08 + \
447 (0x180 * (ch)) + (0x80 * (idx)))
448 #define RCANFD_F_CFDF(ch, idx, df) (RCANFD_F_CFOFFSET + 0x0c + \
449 (0x180 * (ch)) + (0x80 * (idx)) + \
450 (0x04 * (df)))
451
452 /* RSCFDnCFDTMXXp -> RCANFD_F_TMXX(p) */
453 #define RCANFD_F_TMID(p) (0x4000 + (0x20 * (p)))
454 #define RCANFD_F_TMPTR(p) (0x4004 + (0x20 * (p)))
455 #define RCANFD_F_TMFDCTR(p) (0x4008 + (0x20 * (p)))
456 #define RCANFD_F_TMDF(p, b) (0x400c + (0x20 * (p)) + (0x04 * (b)))
457
458 /* RSCFDnCFDTHLACCm */
459 #define RCANFD_F_THLACC(m) (0x6000 + (0x04 * (m)))
460 /* RSCFDnCFDRPGACCr */
461 #define RCANFD_F_RPGACC(r) (0x6400 + (0x04 * (r)))
462
463 /* Constants */
464 #define RCANFD_FIFO_DEPTH 8 /* Tx FIFO depth */
465 #define RCANFD_NAPI_WEIGHT 8 /* Rx poll quota */
466
467 #define RCANFD_NUM_CHANNELS 2 /* Two channels max */
468 #define RCANFD_CHANNELS_MASK BIT((RCANFD_NUM_CHANNELS) - 1)
469
470 #define RCANFD_GAFL_PAGENUM(entry) ((entry) / 16)
471 #define RCANFD_CHANNEL_NUMRULES 1 /* only one rule per channel */
472
473 /* Rx FIFO is a global resource of the controller. There are 8 such FIFOs
474 * available. Each channel gets a dedicated Rx FIFO (i.e.) the channel
475 * number is added to RFFIFO index.
476 */
477 #define RCANFD_RFFIFO_IDX 0
478
479 /* Tx/Rx or Common FIFO is a per channel resource. Each channel has 3 Common
480 * FIFOs dedicated to them. Use the first (index 0) FIFO out of the 3 for Tx.
481 */
482 #define RCANFD_CFFIFO_IDX 0
483
484 /* fCAN clock select register settings */
485 enum rcar_canfd_fcanclk {
486 RCANFD_CANFDCLK = 0, /* CANFD clock */
487 RCANFD_EXTCLK, /* Externally input clock */
488 };
489
490 struct rcar_canfd_global;
491
492 /* Channel priv data */
493 struct rcar_canfd_channel {
494 struct can_priv can; /* Must be the first member */
495 struct net_device *ndev;
496 struct rcar_canfd_global *gpriv; /* Controller reference */
497 void __iomem *base; /* Register base address */
498 struct napi_struct napi;
499 u8 tx_len[RCANFD_FIFO_DEPTH]; /* For net stats */
500 u32 tx_head; /* Incremented on xmit */
501 u32 tx_tail; /* Incremented on xmit done */
502 u32 channel; /* Channel number */
503 spinlock_t tx_lock; /* To protect tx path */
504 };
505
506 /* Global priv data */
507 struct rcar_canfd_global {
508 struct rcar_canfd_channel *ch[RCANFD_NUM_CHANNELS];
509 void __iomem *base; /* Register base address */
510 struct platform_device *pdev; /* Respective platform device */
511 struct clk *clkp; /* Peripheral clock */
512 struct clk *can_clk; /* fCAN clock */
513 enum rcar_canfd_fcanclk fcan; /* CANFD or Ext clock */
514 unsigned long channels_mask; /* Enabled channels mask */
515 bool fdmode; /* CAN FD or Classical CAN only mode */
516 };
517
518 /* CAN FD mode nominal rate constants */
519 static const struct can_bittiming_const rcar_canfd_nom_bittiming_const = {
520 .name = RCANFD_DRV_NAME,
521 .tseg1_min = 2,
522 .tseg1_max = 128,
523 .tseg2_min = 2,
524 .tseg2_max = 32,
525 .sjw_max = 32,
526 .brp_min = 1,
527 .brp_max = 1024,
528 .brp_inc = 1,
529 };
530
531 /* CAN FD mode data rate constants */
532 static const struct can_bittiming_const rcar_canfd_data_bittiming_const = {
533 .name = RCANFD_DRV_NAME,
534 .tseg1_min = 2,
535 .tseg1_max = 16,
536 .tseg2_min = 2,
537 .tseg2_max = 8,
538 .sjw_max = 8,
539 .brp_min = 1,
540 .brp_max = 256,
541 .brp_inc = 1,
542 };
543
544 /* Classical CAN mode bitrate constants */
545 static const struct can_bittiming_const rcar_canfd_bittiming_const = {
546 .name = RCANFD_DRV_NAME,
547 .tseg1_min = 4,
548 .tseg1_max = 16,
549 .tseg2_min = 2,
550 .tseg2_max = 8,
551 .sjw_max = 4,
552 .brp_min = 1,
553 .brp_max = 1024,
554 .brp_inc = 1,
555 };
556
557 /* Helper functions */
558 static inline void rcar_canfd_update(u32 mask, u32 val, u32 __iomem *reg)
559 {
560 u32 data = readl(reg);
561
562 data &= ~mask;
563 data |= (val & mask);
564 writel(data, reg);
565 }
566
567 static inline u32 rcar_canfd_read(void __iomem *base, u32 offset)
568 {
569 return readl(base + (offset));
570 }
571
572 static inline void rcar_canfd_write(void __iomem *base, u32 offset, u32 val)
573 {
574 writel(val, base + (offset));
575 }
576
577 static void rcar_canfd_set_bit(void __iomem *base, u32 reg, u32 val)
578 {
579 rcar_canfd_update(val, val, base + (reg));
580 }
581
582 static void rcar_canfd_clear_bit(void __iomem *base, u32 reg, u32 val)
583 {
584 rcar_canfd_update(val, 0, base + (reg));
585 }
586
587 static void rcar_canfd_update_bit(void __iomem *base, u32 reg,
588 u32 mask, u32 val)
589 {
590 rcar_canfd_update(mask, val, base + (reg));
591 }
592
593 static void rcar_canfd_get_data(struct rcar_canfd_channel *priv,
594 struct canfd_frame *cf, u32 off)
595 {
596 u32 i, lwords;
597
598 lwords = DIV_ROUND_UP(cf->len, sizeof(u32));
599 for (i = 0; i < lwords; i++)
600 *((u32 *)cf->data + i) =
601 rcar_canfd_read(priv->base, off + (i * sizeof(u32)));
602 }
603
604 static void rcar_canfd_put_data(struct rcar_canfd_channel *priv,
605 struct canfd_frame *cf, u32 off)
606 {
607 u32 i, lwords;
608
609 lwords = DIV_ROUND_UP(cf->len, sizeof(u32));
610 for (i = 0; i < lwords; i++)
611 rcar_canfd_write(priv->base, off + (i * sizeof(u32)),
612 *((u32 *)cf->data + i));
613 }
614
615 static void rcar_canfd_tx_failure_cleanup(struct net_device *ndev)
616 {
617 u32 i;
618
619 for (i = 0; i < RCANFD_FIFO_DEPTH; i++)
620 can_free_echo_skb(ndev, i);
621 }
622
623 static int rcar_canfd_reset_controller(struct rcar_canfd_global *gpriv)
624 {
625 u32 sts, ch;
626 int err;
627
628 /* Check RAMINIT flag as CAN RAM initialization takes place
629 * after the MCU reset
630 */
631 err = readl_poll_timeout((gpriv->base + RCANFD_GSTS), sts,
632 !(sts & RCANFD_GSTS_GRAMINIT), 2, 500000);
633 if (err) {
634 dev_dbg(&gpriv->pdev->dev, "global raminit failed\n");
635 return err;
636 }
637
638 /* Transition to Global Reset mode */
639 rcar_canfd_clear_bit(gpriv->base, RCANFD_GCTR, RCANFD_GCTR_GSLPR);
640 rcar_canfd_update_bit(gpriv->base, RCANFD_GCTR,
641 RCANFD_GCTR_GMDC_MASK, RCANFD_GCTR_GMDC_GRESET);
642
643 /* Ensure Global reset mode */
644 err = readl_poll_timeout((gpriv->base + RCANFD_GSTS), sts,
645 (sts & RCANFD_GSTS_GRSTSTS), 2, 500000);
646 if (err) {
647 dev_dbg(&gpriv->pdev->dev, "global reset failed\n");
648 return err;
649 }
650
651 /* Reset Global error flags */
652 rcar_canfd_write(gpriv->base, RCANFD_GERFL, 0x0);
653
654 /* Set the controller into appropriate mode */
655 if (gpriv->fdmode)
656 rcar_canfd_set_bit(gpriv->base, RCANFD_GRMCFG,
657 RCANFD_GRMCFG_RCMC);
658 else
659 rcar_canfd_clear_bit(gpriv->base, RCANFD_GRMCFG,
660 RCANFD_GRMCFG_RCMC);
661
662 /* Transition all Channels to reset mode */
663 for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS) {
664 rcar_canfd_clear_bit(gpriv->base,
665 RCANFD_CCTR(ch), RCANFD_CCTR_CSLPR);
666
667 rcar_canfd_update_bit(gpriv->base, RCANFD_CCTR(ch),
668 RCANFD_CCTR_CHMDC_MASK,
669 RCANFD_CCTR_CHDMC_CRESET);
670
671 /* Ensure Channel reset mode */
672 err = readl_poll_timeout((gpriv->base + RCANFD_CSTS(ch)), sts,
673 (sts & RCANFD_CSTS_CRSTSTS),
674 2, 500000);
675 if (err) {
676 dev_dbg(&gpriv->pdev->dev,
677 "channel %u reset failed\n", ch);
678 return err;
679 }
680 }
681 return 0;
682 }
683
684 static void rcar_canfd_configure_controller(struct rcar_canfd_global *gpriv)
685 {
686 u32 cfg, ch;
687
688 /* Global configuration settings */
689
690 /* ECC Error flag Enable */
691 cfg = RCANFD_GCFG_EEFE;
692
693 if (gpriv->fdmode)
694 /* Truncate payload to configured message size RFPLS */
695 cfg |= RCANFD_GCFG_CMPOC;
696
697 /* Set External Clock if selected */
698 if (gpriv->fcan != RCANFD_CANFDCLK)
699 cfg |= RCANFD_GCFG_DCS;
700
701 rcar_canfd_set_bit(gpriv->base, RCANFD_GCFG, cfg);
702
703 /* Channel configuration settings */
704 for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS) {
705 rcar_canfd_set_bit(gpriv->base, RCANFD_CCTR(ch),
706 RCANFD_CCTR_ERRD);
707 rcar_canfd_update_bit(gpriv->base, RCANFD_CCTR(ch),
708 RCANFD_CCTR_BOM_MASK,
709 RCANFD_CCTR_BOM_BENTRY);
710 }
711 }
712
713 static void rcar_canfd_configure_afl_rules(struct rcar_canfd_global *gpriv,
714 u32 ch)
715 {
716 u32 cfg;
717 int offset, start, page, num_rules = RCANFD_CHANNEL_NUMRULES;
718 u32 ridx = ch + RCANFD_RFFIFO_IDX;
719
720 if (ch == 0) {
721 start = 0; /* Channel 0 always starts from 0th rule */
722 } else {
723 /* Get number of Channel 0 rules and adjust */
724 cfg = rcar_canfd_read(gpriv->base, RCANFD_GAFLCFG0);
725 start = RCANFD_GAFLCFG_GETRNC(0, cfg);
726 }
727
728 /* Enable write access to entry */
729 page = RCANFD_GAFL_PAGENUM(start);
730 rcar_canfd_set_bit(gpriv->base, RCANFD_GAFLECTR,
731 (RCANFD_GAFLECTR_AFLPN(page) |
732 RCANFD_GAFLECTR_AFLDAE));
733
734 /* Write number of rules for channel */
735 rcar_canfd_set_bit(gpriv->base, RCANFD_GAFLCFG0,
736 RCANFD_GAFLCFG_SETRNC(ch, num_rules));
737 if (gpriv->fdmode)
738 offset = RCANFD_F_GAFL_OFFSET;
739 else
740 offset = RCANFD_C_GAFL_OFFSET;
741
742 /* Accept all IDs */
743 rcar_canfd_write(gpriv->base, RCANFD_GAFLID(offset, start), 0);
744 /* IDE or RTR is not considered for matching */
745 rcar_canfd_write(gpriv->base, RCANFD_GAFLM(offset, start), 0);
746 /* Any data length accepted */
747 rcar_canfd_write(gpriv->base, RCANFD_GAFLP0(offset, start), 0);
748 /* Place the msg in corresponding Rx FIFO entry */
749 rcar_canfd_write(gpriv->base, RCANFD_GAFLP1(offset, start),
750 RCANFD_GAFLP1_GAFLFDP(ridx));
751
752 /* Disable write access to page */
753 rcar_canfd_clear_bit(gpriv->base,
754 RCANFD_GAFLECTR, RCANFD_GAFLECTR_AFLDAE);
755 }
756
757 static void rcar_canfd_configure_rx(struct rcar_canfd_global *gpriv, u32 ch)
758 {
759 /* Rx FIFO is used for reception */
760 u32 cfg;
761 u16 rfdc, rfpls;
762
763 /* Select Rx FIFO based on channel */
764 u32 ridx = ch + RCANFD_RFFIFO_IDX;
765
766 rfdc = 2; /* b010 - 8 messages Rx FIFO depth */
767 if (gpriv->fdmode)
768 rfpls = 7; /* b111 - Max 64 bytes payload */
769 else
770 rfpls = 0; /* b000 - Max 8 bytes payload */
771
772 cfg = (RCANFD_RFCC_RFIM | RCANFD_RFCC_RFDC(rfdc) |
773 RCANFD_RFCC_RFPLS(rfpls) | RCANFD_RFCC_RFIE);
774 rcar_canfd_write(gpriv->base, RCANFD_RFCC(ridx), cfg);
775 }
776
777 static void rcar_canfd_configure_tx(struct rcar_canfd_global *gpriv, u32 ch)
778 {
779 /* Tx/Rx(Common) FIFO configured in Tx mode is
780 * used for transmission
781 *
782 * Each channel has 3 Common FIFO dedicated to them.
783 * Use the 1st (index 0) out of 3
784 */
785 u32 cfg;
786 u16 cftml, cfm, cfdc, cfpls;
787
788 cftml = 0; /* 0th buffer */
789 cfm = 1; /* b01 - Transmit mode */
790 cfdc = 2; /* b010 - 8 messages Tx FIFO depth */
791 if (gpriv->fdmode)
792 cfpls = 7; /* b111 - Max 64 bytes payload */
793 else
794 cfpls = 0; /* b000 - Max 8 bytes payload */
795
796 cfg = (RCANFD_CFCC_CFTML(cftml) | RCANFD_CFCC_CFM(cfm) |
797 RCANFD_CFCC_CFIM | RCANFD_CFCC_CFDC(cfdc) |
798 RCANFD_CFCC_CFPLS(cfpls) | RCANFD_CFCC_CFTXIE);
799 rcar_canfd_write(gpriv->base, RCANFD_CFCC(ch, RCANFD_CFFIFO_IDX), cfg);
800
801 if (gpriv->fdmode)
802 /* Clear FD mode specific control/status register */
803 rcar_canfd_write(gpriv->base,
804 RCANFD_F_CFFDCSTS(ch, RCANFD_CFFIFO_IDX), 0);
805 }
806
807 static void rcar_canfd_enable_global_interrupts(struct rcar_canfd_global *gpriv)
808 {
809 u32 ctr;
810
811 /* Clear any stray error interrupt flags */
812 rcar_canfd_write(gpriv->base, RCANFD_GERFL, 0);
813
814 /* Global interrupts setup */
815 ctr = RCANFD_GCTR_MEIE;
816 if (gpriv->fdmode)
817 ctr |= RCANFD_GCTR_CFMPOFIE;
818
819 rcar_canfd_set_bit(gpriv->base, RCANFD_GCTR, ctr);
820 }
821
822 static void rcar_canfd_disable_global_interrupts(struct rcar_canfd_global
823 *gpriv)
824 {
825 /* Disable all interrupts */
826 rcar_canfd_write(gpriv->base, RCANFD_GCTR, 0);
827
828 /* Clear any stray error interrupt flags */
829 rcar_canfd_write(gpriv->base, RCANFD_GERFL, 0);
830 }
831
832 static void rcar_canfd_enable_channel_interrupts(struct rcar_canfd_channel
833 *priv)
834 {
835 u32 ctr, ch = priv->channel;
836
837 /* Clear any stray error flags */
838 rcar_canfd_write(priv->base, RCANFD_CERFL(ch), 0);
839
840 /* Channel interrupts setup */
841 ctr = (RCANFD_CCTR_TAIE |
842 RCANFD_CCTR_ALIE | RCANFD_CCTR_BLIE |
843 RCANFD_CCTR_OLIE | RCANFD_CCTR_BORIE |
844 RCANFD_CCTR_BOEIE | RCANFD_CCTR_EPIE |
845 RCANFD_CCTR_EWIE | RCANFD_CCTR_BEIE);
846 rcar_canfd_set_bit(priv->base, RCANFD_CCTR(ch), ctr);
847 }
848
849 static void rcar_canfd_disable_channel_interrupts(struct rcar_canfd_channel
850 *priv)
851 {
852 u32 ctr, ch = priv->channel;
853
854 ctr = (RCANFD_CCTR_TAIE |
855 RCANFD_CCTR_ALIE | RCANFD_CCTR_BLIE |
856 RCANFD_CCTR_OLIE | RCANFD_CCTR_BORIE |
857 RCANFD_CCTR_BOEIE | RCANFD_CCTR_EPIE |
858 RCANFD_CCTR_EWIE | RCANFD_CCTR_BEIE);
859 rcar_canfd_clear_bit(priv->base, RCANFD_CCTR(ch), ctr);
860
861 /* Clear any stray error flags */
862 rcar_canfd_write(priv->base, RCANFD_CERFL(ch), 0);
863 }
864
865 static void rcar_canfd_global_error(struct net_device *ndev)
866 {
867 struct rcar_canfd_channel *priv = netdev_priv(ndev);
868 struct rcar_canfd_global *gpriv = priv->gpriv;
869 struct net_device_stats *stats = &ndev->stats;
870 u32 ch = priv->channel;
871 u32 gerfl, sts;
872 u32 ridx = ch + RCANFD_RFFIFO_IDX;
873
874 gerfl = rcar_canfd_read(priv->base, RCANFD_GERFL);
875 if ((gerfl & RCANFD_GERFL_EEF0) && (ch == 0)) {
876 netdev_dbg(ndev, "Ch0: ECC Error flag\n");
877 stats->tx_dropped++;
878 }
879 if ((gerfl & RCANFD_GERFL_EEF1) && (ch == 1)) {
880 netdev_dbg(ndev, "Ch1: ECC Error flag\n");
881 stats->tx_dropped++;
882 }
883 if (gerfl & RCANFD_GERFL_MES) {
884 sts = rcar_canfd_read(priv->base,
885 RCANFD_CFSTS(ch, RCANFD_CFFIFO_IDX));
886 if (sts & RCANFD_CFSTS_CFMLT) {
887 netdev_dbg(ndev, "Tx Message Lost flag\n");
888 stats->tx_dropped++;
889 rcar_canfd_write(priv->base,
890 RCANFD_CFSTS(ch, RCANFD_CFFIFO_IDX),
891 sts & ~RCANFD_CFSTS_CFMLT);
892 }
893
894 sts = rcar_canfd_read(priv->base, RCANFD_RFSTS(ridx));
895 if (sts & RCANFD_RFSTS_RFMLT) {
896 netdev_dbg(ndev, "Rx Message Lost flag\n");
897 stats->rx_dropped++;
898 rcar_canfd_write(priv->base, RCANFD_RFSTS(ridx),
899 sts & ~RCANFD_RFSTS_RFMLT);
900 }
901 }
902 if (gpriv->fdmode && gerfl & RCANFD_GERFL_CMPOF) {
903 /* Message Lost flag will be set for respective channel
904 * when this condition happens with counters and flags
905 * already updated.
906 */
907 netdev_dbg(ndev, "global payload overflow interrupt\n");
908 }
909
910 /* Clear all global error interrupts. Only affected channels bits
911 * get cleared
912 */
913 rcar_canfd_write(priv->base, RCANFD_GERFL, 0);
914 }
915
916 static void rcar_canfd_error(struct net_device *ndev, u32 cerfl,
917 u16 txerr, u16 rxerr)
918 {
919 struct rcar_canfd_channel *priv = netdev_priv(ndev);
920 struct net_device_stats *stats = &ndev->stats;
921 struct can_frame *cf;
922 struct sk_buff *skb;
923 u32 ch = priv->channel;
924
925 netdev_dbg(ndev, "ch erfl %x txerr %u rxerr %u\n", cerfl, txerr, rxerr);
926
927 /* Propagate the error condition to the CAN stack */
928 skb = alloc_can_err_skb(ndev, &cf);
929 if (!skb) {
930 stats->rx_dropped++;
931 return;
932 }
933
934 /* Channel error interrupts */
935 if (cerfl & RCANFD_CERFL_BEF) {
936 netdev_dbg(ndev, "Bus error\n");
937 cf->can_id |= CAN_ERR_BUSERROR | CAN_ERR_PROT;
938 cf->data[2] = CAN_ERR_PROT_UNSPEC;
939 priv->can.can_stats.bus_error++;
940 }
941 if (cerfl & RCANFD_CERFL_ADERR) {
942 netdev_dbg(ndev, "ACK Delimiter Error\n");
943 stats->tx_errors++;
944 cf->data[3] |= CAN_ERR_PROT_LOC_ACK_DEL;
945 }
946 if (cerfl & RCANFD_CERFL_B0ERR) {
947 netdev_dbg(ndev, "Bit Error (dominant)\n");
948 stats->tx_errors++;
949 cf->data[2] |= CAN_ERR_PROT_BIT0;
950 }
951 if (cerfl & RCANFD_CERFL_B1ERR) {
952 netdev_dbg(ndev, "Bit Error (recessive)\n");
953 stats->tx_errors++;
954 cf->data[2] |= CAN_ERR_PROT_BIT1;
955 }
956 if (cerfl & RCANFD_CERFL_CERR) {
957 netdev_dbg(ndev, "CRC Error\n");
958 stats->rx_errors++;
959 cf->data[3] |= CAN_ERR_PROT_LOC_CRC_SEQ;
960 }
961 if (cerfl & RCANFD_CERFL_AERR) {
962 netdev_dbg(ndev, "ACK Error\n");
963 stats->tx_errors++;
964 cf->can_id |= CAN_ERR_ACK;
965 cf->data[3] |= CAN_ERR_PROT_LOC_ACK;
966 }
967 if (cerfl & RCANFD_CERFL_FERR) {
968 netdev_dbg(ndev, "Form Error\n");
969 stats->rx_errors++;
970 cf->data[2] |= CAN_ERR_PROT_FORM;
971 }
972 if (cerfl & RCANFD_CERFL_SERR) {
973 netdev_dbg(ndev, "Stuff Error\n");
974 stats->rx_errors++;
975 cf->data[2] |= CAN_ERR_PROT_STUFF;
976 }
977 if (cerfl & RCANFD_CERFL_ALF) {
978 netdev_dbg(ndev, "Arbitration lost Error\n");
979 priv->can.can_stats.arbitration_lost++;
980 cf->can_id |= CAN_ERR_LOSTARB;
981 cf->data[0] |= CAN_ERR_LOSTARB_UNSPEC;
982 }
983 if (cerfl & RCANFD_CERFL_BLF) {
984 netdev_dbg(ndev, "Bus Lock Error\n");
985 stats->rx_errors++;
986 cf->can_id |= CAN_ERR_BUSERROR;
987 }
988 if (cerfl & RCANFD_CERFL_EWF) {
989 netdev_dbg(ndev, "Error warning interrupt\n");
990 priv->can.state = CAN_STATE_ERROR_WARNING;
991 priv->can.can_stats.error_warning++;
992 cf->can_id |= CAN_ERR_CRTL;
993 cf->data[1] = txerr > rxerr ? CAN_ERR_CRTL_TX_WARNING :
994 CAN_ERR_CRTL_RX_WARNING;
995 cf->data[6] = txerr;
996 cf->data[7] = rxerr;
997 }
998 if (cerfl & RCANFD_CERFL_EPF) {
999 netdev_dbg(ndev, "Error passive interrupt\n");
1000 priv->can.state = CAN_STATE_ERROR_PASSIVE;
1001 priv->can.can_stats.error_passive++;
1002 cf->can_id |= CAN_ERR_CRTL;
1003 cf->data[1] = txerr > rxerr ? CAN_ERR_CRTL_TX_PASSIVE :
1004 CAN_ERR_CRTL_RX_PASSIVE;
1005 cf->data[6] = txerr;
1006 cf->data[7] = rxerr;
1007 }
1008 if (cerfl & RCANFD_CERFL_BOEF) {
1009 netdev_dbg(ndev, "Bus-off entry interrupt\n");
1010 rcar_canfd_tx_failure_cleanup(ndev);
1011 priv->can.state = CAN_STATE_BUS_OFF;
1012 priv->can.can_stats.bus_off++;
1013 can_bus_off(ndev);
1014 cf->can_id |= CAN_ERR_BUSOFF;
1015 }
1016 if (cerfl & RCANFD_CERFL_OVLF) {
1017 netdev_dbg(ndev,
1018 "Overload Frame Transmission error interrupt\n");
1019 stats->tx_errors++;
1020 cf->can_id |= CAN_ERR_PROT;
1021 cf->data[2] |= CAN_ERR_PROT_OVERLOAD;
1022 }
1023
1024 /* Clear channel error interrupts that are handled */
1025 rcar_canfd_write(priv->base, RCANFD_CERFL(ch),
1026 RCANFD_CERFL_ERR(~cerfl));
1027 stats->rx_packets++;
1028 stats->rx_bytes += cf->can_dlc;
1029 netif_rx(skb);
1030 }
1031
1032 static void rcar_canfd_tx_done(struct net_device *ndev)
1033 {
1034 struct rcar_canfd_channel *priv = netdev_priv(ndev);
1035 struct net_device_stats *stats = &ndev->stats;
1036 u32 sts;
1037 unsigned long flags;
1038 u32 ch = priv->channel;
1039
1040 do {
1041 u8 unsent, sent;
1042
1043 sent = priv->tx_tail % RCANFD_FIFO_DEPTH;
1044 stats->tx_packets++;
1045 stats->tx_bytes += priv->tx_len[sent];
1046 priv->tx_len[sent] = 0;
1047 can_get_echo_skb(ndev, sent);
1048
1049 spin_lock_irqsave(&priv->tx_lock, flags);
1050 priv->tx_tail++;
1051 sts = rcar_canfd_read(priv->base,
1052 RCANFD_CFSTS(ch, RCANFD_CFFIFO_IDX));
1053 unsent = RCANFD_CFSTS_CFMC(sts);
1054
1055 /* Wake producer only when there is room */
1056 if (unsent != RCANFD_FIFO_DEPTH)
1057 netif_wake_queue(ndev);
1058
1059 if (priv->tx_head - priv->tx_tail <= unsent) {
1060 spin_unlock_irqrestore(&priv->tx_lock, flags);
1061 break;
1062 }
1063 spin_unlock_irqrestore(&priv->tx_lock, flags);
1064
1065 } while (1);
1066
1067 /* Clear interrupt */
1068 rcar_canfd_write(priv->base, RCANFD_CFSTS(ch, RCANFD_CFFIFO_IDX),
1069 sts & ~RCANFD_CFSTS_CFTXIF);
1070 can_led_event(ndev, CAN_LED_EVENT_TX);
1071 }
1072
1073 static irqreturn_t rcar_canfd_global_interrupt(int irq, void *dev_id)
1074 {
1075 struct rcar_canfd_global *gpriv = dev_id;
1076 struct net_device *ndev;
1077 struct rcar_canfd_channel *priv;
1078 u32 sts, gerfl;
1079 u32 ch, ridx;
1080
1081 /* Global error interrupts still indicate a condition specific
1082 * to a channel. RxFIFO interrupt is a global interrupt.
1083 */
1084 for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS) {
1085 priv = gpriv->ch[ch];
1086 ndev = priv->ndev;
1087 ridx = ch + RCANFD_RFFIFO_IDX;
1088
1089 /* Global error interrupts */
1090 gerfl = rcar_canfd_read(priv->base, RCANFD_GERFL);
1091 if (unlikely(RCANFD_GERFL_ERR(gpriv, gerfl)))
1092 rcar_canfd_global_error(ndev);
1093
1094 /* Handle Rx interrupts */
1095 sts = rcar_canfd_read(priv->base, RCANFD_RFSTS(ridx));
1096 if (likely(sts & RCANFD_RFSTS_RFIF)) {
1097 if (napi_schedule_prep(&priv->napi)) {
1098 /* Disable Rx FIFO interrupts */
1099 rcar_canfd_clear_bit(priv->base,
1100 RCANFD_RFCC(ridx),
1101 RCANFD_RFCC_RFIE);
1102 __napi_schedule(&priv->napi);
1103 }
1104 }
1105 }
1106 return IRQ_HANDLED;
1107 }
1108
1109 static void rcar_canfd_state_change(struct net_device *ndev,
1110 u16 txerr, u16 rxerr)
1111 {
1112 struct rcar_canfd_channel *priv = netdev_priv(ndev);
1113 struct net_device_stats *stats = &ndev->stats;
1114 enum can_state rx_state, tx_state, state = priv->can.state;
1115 struct can_frame *cf;
1116 struct sk_buff *skb;
1117
1118 /* Handle transition from error to normal states */
1119 if (txerr < 96 && rxerr < 96)
1120 state = CAN_STATE_ERROR_ACTIVE;
1121 else if (txerr < 128 && rxerr < 128)
1122 state = CAN_STATE_ERROR_WARNING;
1123
1124 if (state != priv->can.state) {
1125 netdev_dbg(ndev, "state: new %d, old %d: txerr %u, rxerr %u\n",
1126 state, priv->can.state, txerr, rxerr);
1127 skb = alloc_can_err_skb(ndev, &cf);
1128 if (!skb) {
1129 stats->rx_dropped++;
1130 return;
1131 }
1132 tx_state = txerr >= rxerr ? state : 0;
1133 rx_state = txerr <= rxerr ? state : 0;
1134
1135 can_change_state(ndev, cf, tx_state, rx_state);
1136 stats->rx_packets++;
1137 stats->rx_bytes += cf->can_dlc;
1138 netif_rx(skb);
1139 }
1140 }
1141
1142 static irqreturn_t rcar_canfd_channel_interrupt(int irq, void *dev_id)
1143 {
1144 struct rcar_canfd_global *gpriv = dev_id;
1145 struct net_device *ndev;
1146 struct rcar_canfd_channel *priv;
1147 u32 sts, ch, cerfl;
1148 u16 txerr, rxerr;
1149
1150 /* Common FIFO is a per channel resource */
1151 for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS) {
1152 priv = gpriv->ch[ch];
1153 ndev = priv->ndev;
1154
1155 /* Channel error interrupts */
1156 cerfl = rcar_canfd_read(priv->base, RCANFD_CERFL(ch));
1157 sts = rcar_canfd_read(priv->base, RCANFD_CSTS(ch));
1158 txerr = RCANFD_CSTS_TECCNT(sts);
1159 rxerr = RCANFD_CSTS_RECCNT(sts);
1160 if (unlikely(RCANFD_CERFL_ERR(cerfl)))
1161 rcar_canfd_error(ndev, cerfl, txerr, rxerr);
1162
1163 /* Handle state change to lower states */
1164 if (unlikely((priv->can.state != CAN_STATE_ERROR_ACTIVE) &&
1165 (priv->can.state != CAN_STATE_BUS_OFF)))
1166 rcar_canfd_state_change(ndev, txerr, rxerr);
1167
1168 /* Handle Tx interrupts */
1169 sts = rcar_canfd_read(priv->base,
1170 RCANFD_CFSTS(ch, RCANFD_CFFIFO_IDX));
1171 if (likely(sts & RCANFD_CFSTS_CFTXIF))
1172 rcar_canfd_tx_done(ndev);
1173 }
1174 return IRQ_HANDLED;
1175 }
1176
1177 static void rcar_canfd_set_bittiming(struct net_device *dev)
1178 {
1179 struct rcar_canfd_channel *priv = netdev_priv(dev);
1180 const struct can_bittiming *bt = &priv->can.bittiming;
1181 const struct can_bittiming *dbt = &priv->can.data_bittiming;
1182 u16 brp, sjw, tseg1, tseg2;
1183 u32 cfg;
1184 u32 ch = priv->channel;
1185
1186 /* Nominal bit timing settings */
1187 brp = bt->brp - 1;
1188 sjw = bt->sjw - 1;
1189 tseg1 = bt->prop_seg + bt->phase_seg1 - 1;
1190 tseg2 = bt->phase_seg2 - 1;
1191
1192 if (priv->can.ctrlmode & CAN_CTRLMODE_FD) {
1193 /* CAN FD only mode */
1194 cfg = (RCANFD_NCFG_NTSEG1(tseg1) | RCANFD_NCFG_NBRP(brp) |
1195 RCANFD_NCFG_NSJW(sjw) | RCANFD_NCFG_NTSEG2(tseg2));
1196
1197 rcar_canfd_write(priv->base, RCANFD_CCFG(ch), cfg);
1198 netdev_dbg(priv->ndev, "nrate: brp %u, sjw %u, tseg1 %u, tseg2 %u\n",
1199 brp, sjw, tseg1, tseg2);
1200
1201 /* Data bit timing settings */
1202 brp = dbt->brp - 1;
1203 sjw = dbt->sjw - 1;
1204 tseg1 = dbt->prop_seg + dbt->phase_seg1 - 1;
1205 tseg2 = dbt->phase_seg2 - 1;
1206
1207 cfg = (RCANFD_DCFG_DTSEG1(tseg1) | RCANFD_DCFG_DBRP(brp) |
1208 RCANFD_DCFG_DSJW(sjw) | RCANFD_DCFG_DTSEG2(tseg2));
1209
1210 rcar_canfd_write(priv->base, RCANFD_F_DCFG(ch), cfg);
1211 netdev_dbg(priv->ndev, "drate: brp %u, sjw %u, tseg1 %u, tseg2 %u\n",
1212 brp, sjw, tseg1, tseg2);
1213 } else {
1214 /* Classical CAN only mode */
1215 cfg = (RCANFD_CFG_TSEG1(tseg1) | RCANFD_CFG_BRP(brp) |
1216 RCANFD_CFG_SJW(sjw) | RCANFD_CFG_TSEG2(tseg2));
1217
1218 rcar_canfd_write(priv->base, RCANFD_CCFG(ch), cfg);
1219 netdev_dbg(priv->ndev,
1220 "rate: brp %u, sjw %u, tseg1 %u, tseg2 %u\n",
1221 brp, sjw, tseg1, tseg2);
1222 }
1223 }
1224
1225 static int rcar_canfd_start(struct net_device *ndev)
1226 {
1227 struct rcar_canfd_channel *priv = netdev_priv(ndev);
1228 int err = -EOPNOTSUPP;
1229 u32 sts, ch = priv->channel;
1230 u32 ridx = ch + RCANFD_RFFIFO_IDX;
1231
1232 rcar_canfd_set_bittiming(ndev);
1233
1234 rcar_canfd_enable_channel_interrupts(priv);
1235
1236 /* Set channel to Operational mode */
1237 rcar_canfd_update_bit(priv->base, RCANFD_CCTR(ch),
1238 RCANFD_CCTR_CHMDC_MASK, RCANFD_CCTR_CHDMC_COPM);
1239
1240 /* Verify channel mode change */
1241 err = readl_poll_timeout((priv->base + RCANFD_CSTS(ch)), sts,
1242 (sts & RCANFD_CSTS_COMSTS), 2, 500000);
1243 if (err) {
1244 netdev_err(ndev, "channel %u communication state failed\n", ch);
1245 goto fail_mode_change;
1246 }
1247
1248 /* Enable Common & Rx FIFO */
1249 rcar_canfd_set_bit(priv->base, RCANFD_CFCC(ch, RCANFD_CFFIFO_IDX),
1250 RCANFD_CFCC_CFE);
1251 rcar_canfd_set_bit(priv->base, RCANFD_RFCC(ridx), RCANFD_RFCC_RFE);
1252
1253 priv->can.state = CAN_STATE_ERROR_ACTIVE;
1254 return 0;
1255
1256 fail_mode_change:
1257 rcar_canfd_disable_channel_interrupts(priv);
1258 return err;
1259 }
1260
1261 static int rcar_canfd_open(struct net_device *ndev)
1262 {
1263 struct rcar_canfd_channel *priv = netdev_priv(ndev);
1264 struct rcar_canfd_global *gpriv = priv->gpriv;
1265 int err;
1266
1267 /* Peripheral clock is already enabled in probe */
1268 err = clk_prepare_enable(gpriv->can_clk);
1269 if (err) {
1270 netdev_err(ndev, "failed to enable CAN clock, error %d\n", err);
1271 goto out_clock;
1272 }
1273
1274 err = open_candev(ndev);
1275 if (err) {
1276 netdev_err(ndev, "open_candev() failed, error %d\n", err);
1277 goto out_can_clock;
1278 }
1279
1280 napi_enable(&priv->napi);
1281 err = rcar_canfd_start(ndev);
1282 if (err)
1283 goto out_close;
1284 netif_start_queue(ndev);
1285 can_led_event(ndev, CAN_LED_EVENT_OPEN);
1286 return 0;
1287 out_close:
1288 napi_disable(&priv->napi);
1289 close_candev(ndev);
1290 out_can_clock:
1291 clk_disable_unprepare(gpriv->can_clk);
1292 out_clock:
1293 return err;
1294 }
1295
1296 static void rcar_canfd_stop(struct net_device *ndev)
1297 {
1298 struct rcar_canfd_channel *priv = netdev_priv(ndev);
1299 int err;
1300 u32 sts, ch = priv->channel;
1301 u32 ridx = ch + RCANFD_RFFIFO_IDX;
1302
1303 /* Transition to channel reset mode */
1304 rcar_canfd_update_bit(priv->base, RCANFD_CCTR(ch),
1305 RCANFD_CCTR_CHMDC_MASK, RCANFD_CCTR_CHDMC_CRESET);
1306
1307 /* Check Channel reset mode */
1308 err = readl_poll_timeout((priv->base + RCANFD_CSTS(ch)), sts,
1309 (sts & RCANFD_CSTS_CRSTSTS), 2, 500000);
1310 if (err)
1311 netdev_err(ndev, "channel %u reset failed\n", ch);
1312
1313 rcar_canfd_disable_channel_interrupts(priv);
1314
1315 /* Disable Common & Rx FIFO */
1316 rcar_canfd_clear_bit(priv->base, RCANFD_CFCC(ch, RCANFD_CFFIFO_IDX),
1317 RCANFD_CFCC_CFE);
1318 rcar_canfd_clear_bit(priv->base, RCANFD_RFCC(ridx), RCANFD_RFCC_RFE);
1319
1320 /* Set the state as STOPPED */
1321 priv->can.state = CAN_STATE_STOPPED;
1322 }
1323
1324 static int rcar_canfd_close(struct net_device *ndev)
1325 {
1326 struct rcar_canfd_channel *priv = netdev_priv(ndev);
1327 struct rcar_canfd_global *gpriv = priv->gpriv;
1328
1329 netif_stop_queue(ndev);
1330 rcar_canfd_stop(ndev);
1331 napi_disable(&priv->napi);
1332 clk_disable_unprepare(gpriv->can_clk);
1333 close_candev(ndev);
1334 can_led_event(ndev, CAN_LED_EVENT_STOP);
1335 return 0;
1336 }
1337
1338 static netdev_tx_t rcar_canfd_start_xmit(struct sk_buff *skb,
1339 struct net_device *ndev)
1340 {
1341 struct rcar_canfd_channel *priv = netdev_priv(ndev);
1342 struct canfd_frame *cf = (struct canfd_frame *)skb->data;
1343 u32 sts = 0, id, dlc;
1344 unsigned long flags;
1345 u32 ch = priv->channel;
1346
1347 if (can_dropped_invalid_skb(ndev, skb))
1348 return NETDEV_TX_OK;
1349
1350 if (cf->can_id & CAN_EFF_FLAG) {
1351 id = cf->can_id & CAN_EFF_MASK;
1352 id |= RCANFD_CFID_CFIDE;
1353 } else {
1354 id = cf->can_id & CAN_SFF_MASK;
1355 }
1356
1357 if (cf->can_id & CAN_RTR_FLAG)
1358 id |= RCANFD_CFID_CFRTR;
1359
1360 dlc = RCANFD_CFPTR_CFDLC(can_len2dlc(cf->len));
1361
1362 if (priv->can.ctrlmode & CAN_CTRLMODE_FD) {
1363 rcar_canfd_write(priv->base,
1364 RCANFD_F_CFID(ch, RCANFD_CFFIFO_IDX), id);
1365 rcar_canfd_write(priv->base,
1366 RCANFD_F_CFPTR(ch, RCANFD_CFFIFO_IDX), dlc);
1367
1368 if (can_is_canfd_skb(skb)) {
1369 /* CAN FD frame format */
1370 sts |= RCANFD_CFFDCSTS_CFFDF;
1371 if (cf->flags & CANFD_BRS)
1372 sts |= RCANFD_CFFDCSTS_CFBRS;
1373
1374 if (priv->can.state == CAN_STATE_ERROR_PASSIVE)
1375 sts |= RCANFD_CFFDCSTS_CFESI;
1376 }
1377
1378 rcar_canfd_write(priv->base,
1379 RCANFD_F_CFFDCSTS(ch, RCANFD_CFFIFO_IDX), sts);
1380
1381 rcar_canfd_put_data(priv, cf,
1382 RCANFD_F_CFDF(ch, RCANFD_CFFIFO_IDX, 0));
1383 } else {
1384 rcar_canfd_write(priv->base,
1385 RCANFD_C_CFID(ch, RCANFD_CFFIFO_IDX), id);
1386 rcar_canfd_write(priv->base,
1387 RCANFD_C_CFPTR(ch, RCANFD_CFFIFO_IDX), dlc);
1388 rcar_canfd_put_data(priv, cf,
1389 RCANFD_C_CFDF(ch, RCANFD_CFFIFO_IDX, 0));
1390 }
1391
1392 priv->tx_len[priv->tx_head % RCANFD_FIFO_DEPTH] = cf->len;
1393 can_put_echo_skb(skb, ndev, priv->tx_head % RCANFD_FIFO_DEPTH);
1394
1395 spin_lock_irqsave(&priv->tx_lock, flags);
1396 priv->tx_head++;
1397
1398 /* Stop the queue if we've filled all FIFO entries */
1399 if (priv->tx_head - priv->tx_tail >= RCANFD_FIFO_DEPTH)
1400 netif_stop_queue(ndev);
1401
1402 /* Start Tx: Write 0xff to CFPC to increment the CPU-side
1403 * pointer for the Common FIFO
1404 */
1405 rcar_canfd_write(priv->base,
1406 RCANFD_CFPCTR(ch, RCANFD_CFFIFO_IDX), 0xff);
1407
1408 spin_unlock_irqrestore(&priv->tx_lock, flags);
1409 return NETDEV_TX_OK;
1410 }
1411
1412 static void rcar_canfd_rx_pkt(struct rcar_canfd_channel *priv)
1413 {
1414 struct net_device_stats *stats = &priv->ndev->stats;
1415 struct canfd_frame *cf;
1416 struct sk_buff *skb;
1417 u32 sts = 0, id, dlc;
1418 u32 ch = priv->channel;
1419 u32 ridx = ch + RCANFD_RFFIFO_IDX;
1420
1421 if (priv->can.ctrlmode & CAN_CTRLMODE_FD) {
1422 id = rcar_canfd_read(priv->base, RCANFD_F_RFID(ridx));
1423 dlc = rcar_canfd_read(priv->base, RCANFD_F_RFPTR(ridx));
1424
1425 sts = rcar_canfd_read(priv->base, RCANFD_F_RFFDSTS(ridx));
1426 if (sts & RCANFD_RFFDSTS_RFFDF)
1427 skb = alloc_canfd_skb(priv->ndev, &cf);
1428 else
1429 skb = alloc_can_skb(priv->ndev,
1430 (struct can_frame **)&cf);
1431 } else {
1432 id = rcar_canfd_read(priv->base, RCANFD_C_RFID(ridx));
1433 dlc = rcar_canfd_read(priv->base, RCANFD_C_RFPTR(ridx));
1434 skb = alloc_can_skb(priv->ndev, (struct can_frame **)&cf);
1435 }
1436
1437 if (!skb) {
1438 stats->rx_dropped++;
1439 return;
1440 }
1441
1442 if (id & RCANFD_RFID_RFIDE)
1443 cf->can_id = (id & CAN_EFF_MASK) | CAN_EFF_FLAG;
1444 else
1445 cf->can_id = id & CAN_SFF_MASK;
1446
1447 if (priv->can.ctrlmode & CAN_CTRLMODE_FD) {
1448 if (sts & RCANFD_RFFDSTS_RFFDF)
1449 cf->len = can_dlc2len(RCANFD_RFPTR_RFDLC(dlc));
1450 else
1451 cf->len = get_can_dlc(RCANFD_RFPTR_RFDLC(dlc));
1452
1453 if (sts & RCANFD_RFFDSTS_RFESI) {
1454 cf->flags |= CANFD_ESI;
1455 netdev_dbg(priv->ndev, "ESI Error\n");
1456 }
1457
1458 if (!(sts & RCANFD_RFFDSTS_RFFDF) && (id & RCANFD_RFID_RFRTR)) {
1459 cf->can_id |= CAN_RTR_FLAG;
1460 } else {
1461 if (sts & RCANFD_RFFDSTS_RFBRS)
1462 cf->flags |= CANFD_BRS;
1463
1464 rcar_canfd_get_data(priv, cf, RCANFD_F_RFDF(ridx, 0));
1465 }
1466 } else {
1467 cf->len = get_can_dlc(RCANFD_RFPTR_RFDLC(dlc));
1468 if (id & RCANFD_RFID_RFRTR)
1469 cf->can_id |= CAN_RTR_FLAG;
1470 else
1471 rcar_canfd_get_data(priv, cf, RCANFD_C_RFDF(ridx, 0));
1472 }
1473
1474 /* Write 0xff to RFPC to increment the CPU-side
1475 * pointer of the Rx FIFO
1476 */
1477 rcar_canfd_write(priv->base, RCANFD_RFPCTR(ridx), 0xff);
1478
1479 can_led_event(priv->ndev, CAN_LED_EVENT_RX);
1480
1481 stats->rx_bytes += cf->len;
1482 stats->rx_packets++;
1483 netif_receive_skb(skb);
1484 }
1485
1486 static int rcar_canfd_rx_poll(struct napi_struct *napi, int quota)
1487 {
1488 struct rcar_canfd_channel *priv =
1489 container_of(napi, struct rcar_canfd_channel, napi);
1490 int num_pkts;
1491 u32 sts;
1492 u32 ch = priv->channel;
1493 u32 ridx = ch + RCANFD_RFFIFO_IDX;
1494
1495 for (num_pkts = 0; num_pkts < quota; num_pkts++) {
1496 sts = rcar_canfd_read(priv->base, RCANFD_RFSTS(ridx));
1497 /* Check FIFO empty condition */
1498 if (sts & RCANFD_RFSTS_RFEMP)
1499 break;
1500
1501 rcar_canfd_rx_pkt(priv);
1502
1503 /* Clear interrupt bit */
1504 if (sts & RCANFD_RFSTS_RFIF)
1505 rcar_canfd_write(priv->base, RCANFD_RFSTS(ridx),
1506 sts & ~RCANFD_RFSTS_RFIF);
1507 }
1508
1509 /* All packets processed */
1510 if (num_pkts < quota) {
1511 if (napi_complete_done(napi, num_pkts)) {
1512 /* Enable Rx FIFO interrupts */
1513 rcar_canfd_set_bit(priv->base, RCANFD_RFCC(ridx),
1514 RCANFD_RFCC_RFIE);
1515 }
1516 }
1517 return num_pkts;
1518 }
1519
1520 static int rcar_canfd_do_set_mode(struct net_device *ndev, enum can_mode mode)
1521 {
1522 int err;
1523
1524 switch (mode) {
1525 case CAN_MODE_START:
1526 err = rcar_canfd_start(ndev);
1527 if (err)
1528 return err;
1529 netif_wake_queue(ndev);
1530 return 0;
1531 default:
1532 return -EOPNOTSUPP;
1533 }
1534 }
1535
1536 static int rcar_canfd_get_berr_counter(const struct net_device *dev,
1537 struct can_berr_counter *bec)
1538 {
1539 struct rcar_canfd_channel *priv = netdev_priv(dev);
1540 u32 val, ch = priv->channel;
1541
1542 /* Peripheral clock is already enabled in probe */
1543 val = rcar_canfd_read(priv->base, RCANFD_CSTS(ch));
1544 bec->txerr = RCANFD_CSTS_TECCNT(val);
1545 bec->rxerr = RCANFD_CSTS_RECCNT(val);
1546 return 0;
1547 }
1548
1549 static const struct net_device_ops rcar_canfd_netdev_ops = {
1550 .ndo_open = rcar_canfd_open,
1551 .ndo_stop = rcar_canfd_close,
1552 .ndo_start_xmit = rcar_canfd_start_xmit,
1553 .ndo_change_mtu = can_change_mtu,
1554 };
1555
1556 static int rcar_canfd_channel_probe(struct rcar_canfd_global *gpriv, u32 ch,
1557 u32 fcan_freq)
1558 {
1559 struct platform_device *pdev = gpriv->pdev;
1560 struct rcar_canfd_channel *priv;
1561 struct net_device *ndev;
1562 int err = -ENODEV;
1563
1564 ndev = alloc_candev(sizeof(*priv), RCANFD_FIFO_DEPTH);
1565 if (!ndev) {
1566 dev_err(&pdev->dev, "alloc_candev() failed\n");
1567 err = -ENOMEM;
1568 goto fail;
1569 }
1570 priv = netdev_priv(ndev);
1571
1572 ndev->netdev_ops = &rcar_canfd_netdev_ops;
1573 ndev->flags |= IFF_ECHO;
1574 priv->ndev = ndev;
1575 priv->base = gpriv->base;
1576 priv->channel = ch;
1577 priv->can.clock.freq = fcan_freq;
1578 dev_info(&pdev->dev, "can_clk rate is %u\n", priv->can.clock.freq);
1579
1580 if (gpriv->fdmode) {
1581 priv->can.bittiming_const = &rcar_canfd_nom_bittiming_const;
1582 priv->can.data_bittiming_const =
1583 &rcar_canfd_data_bittiming_const;
1584
1585 /* Controller starts in CAN FD only mode */
1586 can_set_static_ctrlmode(ndev, CAN_CTRLMODE_FD);
1587 priv->can.ctrlmode_supported = CAN_CTRLMODE_BERR_REPORTING;
1588 } else {
1589 /* Controller starts in Classical CAN only mode */
1590 priv->can.bittiming_const = &rcar_canfd_bittiming_const;
1591 priv->can.ctrlmode_supported = CAN_CTRLMODE_BERR_REPORTING;
1592 }
1593
1594 priv->can.do_set_mode = rcar_canfd_do_set_mode;
1595 priv->can.do_get_berr_counter = rcar_canfd_get_berr_counter;
1596 priv->gpriv = gpriv;
1597 SET_NETDEV_DEV(ndev, &pdev->dev);
1598
1599 netif_napi_add(ndev, &priv->napi, rcar_canfd_rx_poll,
1600 RCANFD_NAPI_WEIGHT);
1601 err = register_candev(ndev);
1602 if (err) {
1603 dev_err(&pdev->dev,
1604 "register_candev() failed, error %d\n", err);
1605 goto fail_candev;
1606 }
1607 spin_lock_init(&priv->tx_lock);
1608 devm_can_led_init(ndev);
1609 gpriv->ch[priv->channel] = priv;
1610 dev_info(&pdev->dev, "device registered (channel %u)\n", priv->channel);
1611 return 0;
1612
1613 fail_candev:
1614 netif_napi_del(&priv->napi);
1615 free_candev(ndev);
1616 fail:
1617 return err;
1618 }
1619
1620 static void rcar_canfd_channel_remove(struct rcar_canfd_global *gpriv, u32 ch)
1621 {
1622 struct rcar_canfd_channel *priv = gpriv->ch[ch];
1623
1624 if (priv) {
1625 unregister_candev(priv->ndev);
1626 netif_napi_del(&priv->napi);
1627 free_candev(priv->ndev);
1628 }
1629 }
1630
1631 static int rcar_canfd_probe(struct platform_device *pdev)
1632 {
1633 void __iomem *addr;
1634 u32 sts, ch, fcan_freq;
1635 struct rcar_canfd_global *gpriv;
1636 struct device_node *of_child;
1637 unsigned long channels_mask = 0;
1638 int err, ch_irq, g_irq;
1639 bool fdmode = true; /* CAN FD only mode - default */
1640
1641 if (of_property_read_bool(pdev->dev.of_node, "renesas,no-can-fd"))
1642 fdmode = false; /* Classical CAN only mode */
1643
1644 of_child = of_get_child_by_name(pdev->dev.of_node, "channel0");
1645 if (of_child && of_device_is_available(of_child))
1646 channels_mask |= BIT(0); /* Channel 0 */
1647
1648 of_child = of_get_child_by_name(pdev->dev.of_node, "channel1");
1649 if (of_child && of_device_is_available(of_child))
1650 channels_mask |= BIT(1); /* Channel 1 */
1651
1652 ch_irq = platform_get_irq(pdev, 0);
1653 if (ch_irq < 0) {
1654 err = ch_irq;
1655 goto fail_dev;
1656 }
1657
1658 g_irq = platform_get_irq(pdev, 1);
1659 if (g_irq < 0) {
1660 err = g_irq;
1661 goto fail_dev;
1662 }
1663
1664 /* Global controller context */
1665 gpriv = devm_kzalloc(&pdev->dev, sizeof(*gpriv), GFP_KERNEL);
1666 if (!gpriv) {
1667 err = -ENOMEM;
1668 goto fail_dev;
1669 }
1670 gpriv->pdev = pdev;
1671 gpriv->channels_mask = channels_mask;
1672 gpriv->fdmode = fdmode;
1673
1674 /* Peripheral clock */
1675 gpriv->clkp = devm_clk_get(&pdev->dev, "fck");
1676 if (IS_ERR(gpriv->clkp)) {
1677 err = PTR_ERR(gpriv->clkp);
1678 dev_err(&pdev->dev, "cannot get peripheral clock, error %d\n",
1679 err);
1680 goto fail_dev;
1681 }
1682
1683 /* fCAN clock: Pick External clock. If not available fallback to
1684 * CANFD clock
1685 */
1686 gpriv->can_clk = devm_clk_get(&pdev->dev, "can_clk");
1687 if (IS_ERR(gpriv->can_clk) || (clk_get_rate(gpriv->can_clk) == 0)) {
1688 gpriv->can_clk = devm_clk_get(&pdev->dev, "canfd");
1689 if (IS_ERR(gpriv->can_clk)) {
1690 err = PTR_ERR(gpriv->can_clk);
1691 dev_err(&pdev->dev,
1692 "cannot get canfd clock, error %d\n", err);
1693 goto fail_dev;
1694 }
1695 gpriv->fcan = RCANFD_CANFDCLK;
1696
1697 } else {
1698 gpriv->fcan = RCANFD_EXTCLK;
1699 }
1700 fcan_freq = clk_get_rate(gpriv->can_clk);
1701
1702 if (gpriv->fcan == RCANFD_CANFDCLK)
1703 /* CANFD clock is further divided by (1/2) within the IP */
1704 fcan_freq /= 2;
1705
1706 addr = devm_platform_ioremap_resource(pdev, 0);
1707 if (IS_ERR(addr)) {
1708 err = PTR_ERR(addr);
1709 goto fail_dev;
1710 }
1711 gpriv->base = addr;
1712
1713 /* Request IRQ that's common for both channels */
1714 err = devm_request_irq(&pdev->dev, ch_irq,
1715 rcar_canfd_channel_interrupt, 0,
1716 "canfd.chn", gpriv);
1717 if (err) {
1718 dev_err(&pdev->dev, "devm_request_irq(%d) failed, error %d\n",
1719 ch_irq, err);
1720 goto fail_dev;
1721 }
1722 err = devm_request_irq(&pdev->dev, g_irq,
1723 rcar_canfd_global_interrupt, 0,
1724 "canfd.gbl", gpriv);
1725 if (err) {
1726 dev_err(&pdev->dev, "devm_request_irq(%d) failed, error %d\n",
1727 g_irq, err);
1728 goto fail_dev;
1729 }
1730
1731 /* Enable peripheral clock for register access */
1732 err = clk_prepare_enable(gpriv->clkp);
1733 if (err) {
1734 dev_err(&pdev->dev,
1735 "failed to enable peripheral clock, error %d\n", err);
1736 goto fail_dev;
1737 }
1738
1739 err = rcar_canfd_reset_controller(gpriv);
1740 if (err) {
1741 dev_err(&pdev->dev, "reset controller failed\n");
1742 goto fail_clk;
1743 }
1744
1745 /* Controller in Global reset & Channel reset mode */
1746 rcar_canfd_configure_controller(gpriv);
1747
1748 /* Configure per channel attributes */
1749 for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS) {
1750 /* Configure Channel's Rx fifo */
1751 rcar_canfd_configure_rx(gpriv, ch);
1752
1753 /* Configure Channel's Tx (Common) fifo */
1754 rcar_canfd_configure_tx(gpriv, ch);
1755
1756 /* Configure receive rules */
1757 rcar_canfd_configure_afl_rules(gpriv, ch);
1758 }
1759
1760 /* Configure common interrupts */
1761 rcar_canfd_enable_global_interrupts(gpriv);
1762
1763 /* Start Global operation mode */
1764 rcar_canfd_update_bit(gpriv->base, RCANFD_GCTR, RCANFD_GCTR_GMDC_MASK,
1765 RCANFD_GCTR_GMDC_GOPM);
1766
1767 /* Verify mode change */
1768 err = readl_poll_timeout((gpriv->base + RCANFD_GSTS), sts,
1769 !(sts & RCANFD_GSTS_GNOPM), 2, 500000);
1770 if (err) {
1771 dev_err(&pdev->dev, "global operational mode failed\n");
1772 goto fail_mode;
1773 }
1774
1775 for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS) {
1776 err = rcar_canfd_channel_probe(gpriv, ch, fcan_freq);
1777 if (err)
1778 goto fail_channel;
1779 }
1780
1781 platform_set_drvdata(pdev, gpriv);
1782 dev_info(&pdev->dev, "global operational state (clk %d, fdmode %d)\n",
1783 gpriv->fcan, gpriv->fdmode);
1784 return 0;
1785
1786 fail_channel:
1787 for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS)
1788 rcar_canfd_channel_remove(gpriv, ch);
1789 fail_mode:
1790 rcar_canfd_disable_global_interrupts(gpriv);
1791 fail_clk:
1792 clk_disable_unprepare(gpriv->clkp);
1793 fail_dev:
1794 return err;
1795 }
1796
1797 static int rcar_canfd_remove(struct platform_device *pdev)
1798 {
1799 struct rcar_canfd_global *gpriv = platform_get_drvdata(pdev);
1800 u32 ch;
1801
1802 rcar_canfd_reset_controller(gpriv);
1803 rcar_canfd_disable_global_interrupts(gpriv);
1804
1805 for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS) {
1806 rcar_canfd_disable_channel_interrupts(gpriv->ch[ch]);
1807 rcar_canfd_channel_remove(gpriv, ch);
1808 }
1809
1810 /* Enter global sleep mode */
1811 rcar_canfd_set_bit(gpriv->base, RCANFD_GCTR, RCANFD_GCTR_GSLPR);
1812 clk_disable_unprepare(gpriv->clkp);
1813 return 0;
1814 }
1815
1816 static int __maybe_unused rcar_canfd_suspend(struct device *dev)
1817 {
1818 return 0;
1819 }
1820
1821 static int __maybe_unused rcar_canfd_resume(struct device *dev)
1822 {
1823 return 0;
1824 }
1825
1826 static SIMPLE_DEV_PM_OPS(rcar_canfd_pm_ops, rcar_canfd_suspend,
1827 rcar_canfd_resume);
1828
1829 static const struct of_device_id rcar_canfd_of_table[] = {
1830 { .compatible = "renesas,rcar-gen3-canfd" },
1831 { }
1832 };
1833
1834 MODULE_DEVICE_TABLE(of, rcar_canfd_of_table);
1835
1836 static struct platform_driver rcar_canfd_driver = {
1837 .driver = {
1838 .name = RCANFD_DRV_NAME,
1839 .of_match_table = of_match_ptr(rcar_canfd_of_table),
1840 .pm = &rcar_canfd_pm_ops,
1841 },
1842 .probe = rcar_canfd_probe,
1843 .remove = rcar_canfd_remove,
1844 };
1845
1846 module_platform_driver(rcar_canfd_driver);
1847
1848 MODULE_AUTHOR("Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>");
1849 MODULE_LICENSE("GPL");
1850 MODULE_DESCRIPTION("CAN FD driver for Renesas R-Car SoC");
1851 MODULE_ALIAS("platform:" RCANFD_DRV_NAME);
Linux with added FPC-III support