?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
treewide: remove redundant IS_ERR() before error code check
[linux/fpc-iii.git] / drivers / net / dsa / bcm_sf2.c
blob3e8635311d0de1517d6d63b5dc4556cf30ead192
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Broadcom Starfighter 2 DSA switch driver
4 *
5 * Copyright (C) 2014, Broadcom Corporation
6 */
7
8 #include <linux/list.h>
9 #include <linux/module.h>
10 #include <linux/netdevice.h>
11 #include <linux/interrupt.h>
12 #include <linux/platform_device.h>
13 #include <linux/phy.h>
14 #include <linux/phy_fixed.h>
15 #include <linux/phylink.h>
16 #include <linux/mii.h>
17 #include <linux/of.h>
18 #include <linux/of_irq.h>
19 #include <linux/of_address.h>
20 #include <linux/of_net.h>
21 #include <linux/of_mdio.h>
22 #include <net/dsa.h>
23 #include <linux/ethtool.h>
24 #include <linux/if_bridge.h>
25 #include <linux/brcmphy.h>
26 #include <linux/etherdevice.h>
27 #include <linux/platform_data/b53.h>
28
29 #include "bcm_sf2.h"
30 #include "bcm_sf2_regs.h"
31 #include "b53/b53_priv.h"
32 #include "b53/b53_regs.h"
33
34 static void bcm_sf2_imp_setup(struct dsa_switch *ds, int port)
35 {
36 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
37 unsigned int i;
38 u32 reg, offset;
39
40 /* Enable the port memories */
41 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
42 reg &= ~P_TXQ_PSM_VDD(port);
43 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
44
45 /* Enable forwarding */
46 core_writel(priv, SW_FWDG_EN, CORE_SWMODE);
47
48 /* Enable IMP port in dumb mode */
49 reg = core_readl(priv, CORE_SWITCH_CTRL);
50 reg |= MII_DUMB_FWDG_EN;
51 core_writel(priv, reg, CORE_SWITCH_CTRL);
52
53 /* Configure Traffic Class to QoS mapping, allow each priority to map
54 * to a different queue number
55 */
56 reg = core_readl(priv, CORE_PORT_TC2_QOS_MAP_PORT(port));
57 for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++)
58 reg |= i << (PRT_TO_QID_SHIFT * i);
59 core_writel(priv, reg, CORE_PORT_TC2_QOS_MAP_PORT(port));
60
61 b53_brcm_hdr_setup(ds, port);
62
63 if (port == 8) {
64 if (priv->type == BCM7445_DEVICE_ID)
65 offset = CORE_STS_OVERRIDE_IMP;
66 else
67 offset = CORE_STS_OVERRIDE_IMP2;
68
69 /* Force link status for IMP port */
70 reg = core_readl(priv, offset);
71 reg |= (MII_SW_OR | LINK_STS | GMII_SPEED_UP_2G);
72 core_writel(priv, reg, offset);
73
74 /* Enable Broadcast, Multicast, Unicast forwarding to IMP port */
75 reg = core_readl(priv, CORE_IMP_CTL);
76 reg |= (RX_BCST_EN | RX_MCST_EN | RX_UCST_EN);
77 reg &= ~(RX_DIS | TX_DIS);
78 core_writel(priv, reg, CORE_IMP_CTL);
79 } else {
80 reg = core_readl(priv, CORE_G_PCTL_PORT(port));
81 reg &= ~(RX_DIS | TX_DIS);
82 core_writel(priv, reg, CORE_G_PCTL_PORT(port));
83 }
84 }
85
86 static void bcm_sf2_gphy_enable_set(struct dsa_switch *ds, bool enable)
87 {
88 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
89 u32 reg;
90
91 reg = reg_readl(priv, REG_SPHY_CNTRL);
92 if (enable) {
93 reg |= PHY_RESET;
94 reg &= ~(EXT_PWR_DOWN | IDDQ_BIAS | IDDQ_GLOBAL_PWR | CK25_DIS);
95 reg_writel(priv, reg, REG_SPHY_CNTRL);
96 udelay(21);
97 reg = reg_readl(priv, REG_SPHY_CNTRL);
98 reg &= ~PHY_RESET;
99 } else {
100 reg |= EXT_PWR_DOWN | IDDQ_BIAS | PHY_RESET;
101 reg_writel(priv, reg, REG_SPHY_CNTRL);
102 mdelay(1);
103 reg |= CK25_DIS;
104 }
105 reg_writel(priv, reg, REG_SPHY_CNTRL);
106
107 /* Use PHY-driven LED signaling */
108 if (!enable) {
109 reg = reg_readl(priv, REG_LED_CNTRL(0));
110 reg |= SPDLNK_SRC_SEL;
111 reg_writel(priv, reg, REG_LED_CNTRL(0));
112 }
113 }
114
115 static inline void bcm_sf2_port_intr_enable(struct bcm_sf2_priv *priv,
116 int port)
117 {
118 unsigned int off;
119
120 switch (port) {
121 case 7:
122 off = P7_IRQ_OFF;
123 break;
124 case 0:
125 /* Port 0 interrupts are located on the first bank */
126 intrl2_0_mask_clear(priv, P_IRQ_MASK(P0_IRQ_OFF));
127 return;
128 default:
129 off = P_IRQ_OFF(port);
130 break;
131 }
132
133 intrl2_1_mask_clear(priv, P_IRQ_MASK(off));
134 }
135
136 static inline void bcm_sf2_port_intr_disable(struct bcm_sf2_priv *priv,
137 int port)
138 {
139 unsigned int off;
140
141 switch (port) {
142 case 7:
143 off = P7_IRQ_OFF;
144 break;
145 case 0:
146 /* Port 0 interrupts are located on the first bank */
147 intrl2_0_mask_set(priv, P_IRQ_MASK(P0_IRQ_OFF));
148 intrl2_0_writel(priv, P_IRQ_MASK(P0_IRQ_OFF), INTRL2_CPU_CLEAR);
149 return;
150 default:
151 off = P_IRQ_OFF(port);
152 break;
153 }
154
155 intrl2_1_mask_set(priv, P_IRQ_MASK(off));
156 intrl2_1_writel(priv, P_IRQ_MASK(off), INTRL2_CPU_CLEAR);
157 }
158
159 static int bcm_sf2_port_setup(struct dsa_switch *ds, int port,
160 struct phy_device *phy)
161 {
162 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
163 unsigned int i;
164 u32 reg;
165
166 if (!dsa_is_user_port(ds, port))
167 return 0;
168
169 /* Clear the memory power down */
170 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
171 reg &= ~P_TXQ_PSM_VDD(port);
172 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
173
174 /* Enable learning */
175 reg = core_readl(priv, CORE_DIS_LEARN);
176 reg &= ~BIT(port);
177 core_writel(priv, reg, CORE_DIS_LEARN);
178
179 /* Enable Broadcom tags for that port if requested */
180 if (priv->brcm_tag_mask & BIT(port))
181 b53_brcm_hdr_setup(ds, port);
182
183 /* Configure Traffic Class to QoS mapping, allow each priority to map
184 * to a different queue number
185 */
186 reg = core_readl(priv, CORE_PORT_TC2_QOS_MAP_PORT(port));
187 for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++)
188 reg |= i << (PRT_TO_QID_SHIFT * i);
189 core_writel(priv, reg, CORE_PORT_TC2_QOS_MAP_PORT(port));
190
191 /* Re-enable the GPHY and re-apply workarounds */
192 if (priv->int_phy_mask & 1 << port && priv->hw_params.num_gphy == 1) {
193 bcm_sf2_gphy_enable_set(ds, true);
194 if (phy) {
195 /* if phy_stop() has been called before, phy
196 * will be in halted state, and phy_start()
197 * will call resume.
198 *
199 * the resume path does not configure back
200 * autoneg settings, and since we hard reset
201 * the phy manually here, we need to reset the
202 * state machine also.
203 */
204 phy->state = PHY_READY;
205 phy_init_hw(phy);
206 }
207 }
208
209 /* Enable MoCA port interrupts to get notified */
210 if (port == priv->moca_port)
211 bcm_sf2_port_intr_enable(priv, port);
212
213 /* Set per-queue pause threshold to 32 */
214 core_writel(priv, 32, CORE_TXQ_THD_PAUSE_QN_PORT(port));
215
216 /* Set ACB threshold to 24 */
217 for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++) {
218 reg = acb_readl(priv, ACB_QUEUE_CFG(port *
219 SF2_NUM_EGRESS_QUEUES + i));
220 reg &= ~XOFF_THRESHOLD_MASK;
221 reg |= 24;
222 acb_writel(priv, reg, ACB_QUEUE_CFG(port *
223 SF2_NUM_EGRESS_QUEUES + i));
224 }
225
226 return b53_enable_port(ds, port, phy);
227 }
228
229 static void bcm_sf2_port_disable(struct dsa_switch *ds, int port)
230 {
231 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
232 u32 reg;
233
234 /* Disable learning while in WoL mode */
235 if (priv->wol_ports_mask & (1 << port)) {
236 reg = core_readl(priv, CORE_DIS_LEARN);
237 reg |= BIT(port);
238 core_writel(priv, reg, CORE_DIS_LEARN);
239 return;
240 }
241
242 if (port == priv->moca_port)
243 bcm_sf2_port_intr_disable(priv, port);
244
245 if (priv->int_phy_mask & 1 << port && priv->hw_params.num_gphy == 1)
246 bcm_sf2_gphy_enable_set(ds, false);
247
248 b53_disable_port(ds, port);
249
250 /* Power down the port memory */
251 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
252 reg |= P_TXQ_PSM_VDD(port);
253 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
254 }
255
256
257 static int bcm_sf2_sw_indir_rw(struct bcm_sf2_priv *priv, int op, int addr,
258 int regnum, u16 val)
259 {
260 int ret = 0;
261 u32 reg;
262
263 reg = reg_readl(priv, REG_SWITCH_CNTRL);
264 reg |= MDIO_MASTER_SEL;
265 reg_writel(priv, reg, REG_SWITCH_CNTRL);
266
267 /* Page << 8 | offset */
268 reg = 0x70;
269 reg <<= 2;
270 core_writel(priv, addr, reg);
271
272 /* Page << 8 | offset */
273 reg = 0x80 << 8 | regnum << 1;
274 reg <<= 2;
275
276 if (op)
277 ret = core_readl(priv, reg);
278 else
279 core_writel(priv, val, reg);
280
281 reg = reg_readl(priv, REG_SWITCH_CNTRL);
282 reg &= ~MDIO_MASTER_SEL;
283 reg_writel(priv, reg, REG_SWITCH_CNTRL);
284
285 return ret & 0xffff;
286 }
287
288 static int bcm_sf2_sw_mdio_read(struct mii_bus *bus, int addr, int regnum)
289 {
290 struct bcm_sf2_priv *priv = bus->priv;
291
292 /* Intercept reads from Broadcom pseudo-PHY address, else, send
293 * them to our master MDIO bus controller
294 */
295 if (addr == BRCM_PSEUDO_PHY_ADDR && priv->indir_phy_mask & BIT(addr))
296 return bcm_sf2_sw_indir_rw(priv, 1, addr, regnum, 0);
297 else
298 return mdiobus_read_nested(priv->master_mii_bus, addr, regnum);
299 }
300
301 static int bcm_sf2_sw_mdio_write(struct mii_bus *bus, int addr, int regnum,
302 u16 val)
303 {
304 struct bcm_sf2_priv *priv = bus->priv;
305
306 /* Intercept writes to the Broadcom pseudo-PHY address, else,
307 * send them to our master MDIO bus controller
308 */
309 if (addr == BRCM_PSEUDO_PHY_ADDR && priv->indir_phy_mask & BIT(addr))
310 return bcm_sf2_sw_indir_rw(priv, 0, addr, regnum, val);
311 else
312 return mdiobus_write_nested(priv->master_mii_bus, addr,
313 regnum, val);
314 }
315
316 static irqreturn_t bcm_sf2_switch_0_isr(int irq, void *dev_id)
317 {
318 struct dsa_switch *ds = dev_id;
319 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
320
321 priv->irq0_stat = intrl2_0_readl(priv, INTRL2_CPU_STATUS) &
322 ~priv->irq0_mask;
323 intrl2_0_writel(priv, priv->irq0_stat, INTRL2_CPU_CLEAR);
324
325 return IRQ_HANDLED;
326 }
327
328 static irqreturn_t bcm_sf2_switch_1_isr(int irq, void *dev_id)
329 {
330 struct dsa_switch *ds = dev_id;
331 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
332
333 priv->irq1_stat = intrl2_1_readl(priv, INTRL2_CPU_STATUS) &
334 ~priv->irq1_mask;
335 intrl2_1_writel(priv, priv->irq1_stat, INTRL2_CPU_CLEAR);
336
337 if (priv->irq1_stat & P_LINK_UP_IRQ(P7_IRQ_OFF)) {
338 priv->port_sts[7].link = true;
339 dsa_port_phylink_mac_change(ds, 7, true);
340 }
341 if (priv->irq1_stat & P_LINK_DOWN_IRQ(P7_IRQ_OFF)) {
342 priv->port_sts[7].link = false;
343 dsa_port_phylink_mac_change(ds, 7, false);
344 }
345
346 return IRQ_HANDLED;
347 }
348
349 static int bcm_sf2_sw_rst(struct bcm_sf2_priv *priv)
350 {
351 unsigned int timeout = 1000;
352 u32 reg;
353 int ret;
354
355 /* The watchdog reset does not work on 7278, we need to hit the
356 * "external" reset line through the reset controller.
357 */
358 if (priv->type == BCM7278_DEVICE_ID && !IS_ERR(priv->rcdev)) {
359 ret = reset_control_assert(priv->rcdev);
360 if (ret)
361 return ret;
362
363 return reset_control_deassert(priv->rcdev);
364 }
365
366 reg = core_readl(priv, CORE_WATCHDOG_CTRL);
367 reg |= SOFTWARE_RESET | EN_CHIP_RST | EN_SW_RESET;
368 core_writel(priv, reg, CORE_WATCHDOG_CTRL);
369
370 do {
371 reg = core_readl(priv, CORE_WATCHDOG_CTRL);
372 if (!(reg & SOFTWARE_RESET))
373 break;
374
375 usleep_range(1000, 2000);
376 } while (timeout-- > 0);
377
378 if (timeout == 0)
379 return -ETIMEDOUT;
380
381 return 0;
382 }
383
384 static void bcm_sf2_intr_disable(struct bcm_sf2_priv *priv)
385 {
386 intrl2_0_mask_set(priv, 0xffffffff);
387 intrl2_0_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
388 intrl2_1_mask_set(priv, 0xffffffff);
389 intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
390 }
391
392 static void bcm_sf2_identify_ports(struct bcm_sf2_priv *priv,
393 struct device_node *dn)
394 {
395 struct device_node *port;
396 unsigned int port_num;
397 phy_interface_t mode;
398 int err;
399
400 priv->moca_port = -1;
401
402 for_each_available_child_of_node(dn, port) {
403 if (of_property_read_u32(port, "reg", &port_num))
404 continue;
405
406 /* Internal PHYs get assigned a specific 'phy-mode' property
407 * value: "internal" to help flag them before MDIO probing
408 * has completed, since they might be turned off at that
409 * time
410 */
411 err = of_get_phy_mode(port, &mode);
412 if (err)
413 continue;
414
415 if (mode == PHY_INTERFACE_MODE_INTERNAL)
416 priv->int_phy_mask |= 1 << port_num;
417
418 if (mode == PHY_INTERFACE_MODE_MOCA)
419 priv->moca_port = port_num;
420
421 if (of_property_read_bool(port, "brcm,use-bcm-hdr"))
422 priv->brcm_tag_mask |= 1 << port_num;
423 }
424 }
425
426 static int bcm_sf2_mdio_register(struct dsa_switch *ds)
427 {
428 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
429 struct device_node *dn;
430 static int index;
431 int err;
432
433 /* Find our integrated MDIO bus node */
434 dn = of_find_compatible_node(NULL, NULL, "brcm,unimac-mdio");
435 priv->master_mii_bus = of_mdio_find_bus(dn);
436 if (!priv->master_mii_bus)
437 return -EPROBE_DEFER;
438
439 get_device(&priv->master_mii_bus->dev);
440 priv->master_mii_dn = dn;
441
442 priv->slave_mii_bus = devm_mdiobus_alloc(ds->dev);
443 if (!priv->slave_mii_bus)
444 return -ENOMEM;
445
446 priv->slave_mii_bus->priv = priv;
447 priv->slave_mii_bus->name = "sf2 slave mii";
448 priv->slave_mii_bus->read = bcm_sf2_sw_mdio_read;
449 priv->slave_mii_bus->write = bcm_sf2_sw_mdio_write;
450 snprintf(priv->slave_mii_bus->id, MII_BUS_ID_SIZE, "sf2-%d",
451 index++);
452 priv->slave_mii_bus->dev.of_node = dn;
453
454 /* Include the pseudo-PHY address to divert reads towards our
455 * workaround. This is only required for 7445D0, since 7445E0
456 * disconnects the internal switch pseudo-PHY such that we can use the
457 * regular SWITCH_MDIO master controller instead.
458 *
459 * Here we flag the pseudo PHY as needing special treatment and would
460 * otherwise make all other PHY read/writes go to the master MDIO bus
461 * controller that comes with this switch backed by the "mdio-unimac"
462 * driver.
463 */
464 if (of_machine_is_compatible("brcm,bcm7445d0"))
465 priv->indir_phy_mask |= (1 << BRCM_PSEUDO_PHY_ADDR);
466 else
467 priv->indir_phy_mask = 0;
468
469 ds->phys_mii_mask = priv->indir_phy_mask;
470 ds->slave_mii_bus = priv->slave_mii_bus;
471 priv->slave_mii_bus->parent = ds->dev->parent;
472 priv->slave_mii_bus->phy_mask = ~priv->indir_phy_mask;
473
474 err = of_mdiobus_register(priv->slave_mii_bus, dn);
475 if (err && dn)
476 of_node_put(dn);
477
478 return err;
479 }
480
481 static void bcm_sf2_mdio_unregister(struct bcm_sf2_priv *priv)
482 {
483 mdiobus_unregister(priv->slave_mii_bus);
484 of_node_put(priv->master_mii_dn);
485 }
486
487 static u32 bcm_sf2_sw_get_phy_flags(struct dsa_switch *ds, int port)
488 {
489 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
490
491 /* The BCM7xxx PHY driver expects to find the integrated PHY revision
492 * in bits 15:8 and the patch level in bits 7:0 which is exactly what
493 * the REG_PHY_REVISION register layout is.
494 */
495
496 return priv->hw_params.gphy_rev;
497 }
498
499 static void bcm_sf2_sw_validate(struct dsa_switch *ds, int port,
500 unsigned long *supported,
501 struct phylink_link_state *state)
502 {
503 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
504 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
505
506 if (!phy_interface_mode_is_rgmii(state->interface) &&
507 state->interface != PHY_INTERFACE_MODE_MII &&
508 state->interface != PHY_INTERFACE_MODE_REVMII &&
509 state->interface != PHY_INTERFACE_MODE_GMII &&
510 state->interface != PHY_INTERFACE_MODE_INTERNAL &&
511 state->interface != PHY_INTERFACE_MODE_MOCA) {
512 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
513 if (port != core_readl(priv, CORE_IMP0_PRT_ID))
514 dev_err(ds->dev,
515 "Unsupported interface: %d for port %d\n",
516 state->interface, port);
517 return;
518 }
519
520 /* Allow all the expected bits */
521 phylink_set(mask, Autoneg);
522 phylink_set_port_modes(mask);
523 phylink_set(mask, Pause);
524 phylink_set(mask, Asym_Pause);
525
526 /* With the exclusion of MII and Reverse MII, we support Gigabit,
527 * including Half duplex
528 */
529 if (state->interface != PHY_INTERFACE_MODE_MII &&
530 state->interface != PHY_INTERFACE_MODE_REVMII) {
531 phylink_set(mask, 1000baseT_Full);
532 phylink_set(mask, 1000baseT_Half);
533 }
534
535 phylink_set(mask, 10baseT_Half);
536 phylink_set(mask, 10baseT_Full);
537 phylink_set(mask, 100baseT_Half);
538 phylink_set(mask, 100baseT_Full);
539
540 bitmap_and(supported, supported, mask,
541 __ETHTOOL_LINK_MODE_MASK_NBITS);
542 bitmap_and(state->advertising, state->advertising, mask,
543 __ETHTOOL_LINK_MODE_MASK_NBITS);
544 }
545
546 static void bcm_sf2_sw_mac_config(struct dsa_switch *ds, int port,
547 unsigned int mode,
548 const struct phylink_link_state *state)
549 {
550 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
551 u32 id_mode_dis = 0, port_mode;
552 u32 reg, offset;
553
554 if (port == core_readl(priv, CORE_IMP0_PRT_ID))
555 return;
556
557 if (priv->type == BCM7445_DEVICE_ID)
558 offset = CORE_STS_OVERRIDE_GMIIP_PORT(port);
559 else
560 offset = CORE_STS_OVERRIDE_GMIIP2_PORT(port);
561
562 switch (state->interface) {
563 case PHY_INTERFACE_MODE_RGMII:
564 id_mode_dis = 1;
565 /* fallthrough */
566 case PHY_INTERFACE_MODE_RGMII_TXID:
567 port_mode = EXT_GPHY;
568 break;
569 case PHY_INTERFACE_MODE_MII:
570 port_mode = EXT_EPHY;
571 break;
572 case PHY_INTERFACE_MODE_REVMII:
573 port_mode = EXT_REVMII;
574 break;
575 default:
576 /* all other PHYs: internal and MoCA */
577 goto force_link;
578 }
579
580 /* Clear id_mode_dis bit, and the existing port mode, let
581 * RGMII_MODE_EN bet set by mac_link_{up,down}
582 */
583 reg = reg_readl(priv, REG_RGMII_CNTRL_P(port));
584 reg &= ~ID_MODE_DIS;
585 reg &= ~(PORT_MODE_MASK << PORT_MODE_SHIFT);
586 reg &= ~(RX_PAUSE_EN | TX_PAUSE_EN);
587
588 reg |= port_mode;
589 if (id_mode_dis)
590 reg |= ID_MODE_DIS;
591
592 if (state->pause & MLO_PAUSE_TXRX_MASK) {
593 if (state->pause & MLO_PAUSE_TX)
594 reg |= TX_PAUSE_EN;
595 reg |= RX_PAUSE_EN;
596 }
597
598 reg_writel(priv, reg, REG_RGMII_CNTRL_P(port));
599
600 force_link:
601 /* Force link settings detected from the PHY */
602 reg = SW_OVERRIDE;
603 switch (state->speed) {
604 case SPEED_1000:
605 reg |= SPDSTS_1000 << SPEED_SHIFT;
606 break;
607 case SPEED_100:
608 reg |= SPDSTS_100 << SPEED_SHIFT;
609 break;
610 }
611
612 if (state->link)
613 reg |= LINK_STS;
614 if (state->duplex == DUPLEX_FULL)
615 reg |= DUPLX_MODE;
616
617 core_writel(priv, reg, offset);
618 }
619
620 static void bcm_sf2_sw_mac_link_set(struct dsa_switch *ds, int port,
621 phy_interface_t interface, bool link)
622 {
623 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
624 u32 reg;
625
626 if (!phy_interface_mode_is_rgmii(interface) &&
627 interface != PHY_INTERFACE_MODE_MII &&
628 interface != PHY_INTERFACE_MODE_REVMII)
629 return;
630
631 /* If the link is down, just disable the interface to conserve power */
632 reg = reg_readl(priv, REG_RGMII_CNTRL_P(port));
633 if (link)
634 reg |= RGMII_MODE_EN;
635 else
636 reg &= ~RGMII_MODE_EN;
637 reg_writel(priv, reg, REG_RGMII_CNTRL_P(port));
638 }
639
640 static void bcm_sf2_sw_mac_link_down(struct dsa_switch *ds, int port,
641 unsigned int mode,
642 phy_interface_t interface)
643 {
644 bcm_sf2_sw_mac_link_set(ds, port, interface, false);
645 }
646
647 static void bcm_sf2_sw_mac_link_up(struct dsa_switch *ds, int port,
648 unsigned int mode,
649 phy_interface_t interface,
650 struct phy_device *phydev)
651 {
652 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
653 struct ethtool_eee *p = &priv->dev->ports[port].eee;
654
655 bcm_sf2_sw_mac_link_set(ds, port, interface, true);
656
657 if (mode == MLO_AN_PHY && phydev)
658 p->eee_enabled = b53_eee_init(ds, port, phydev);
659 }
660
661 static void bcm_sf2_sw_fixed_state(struct dsa_switch *ds, int port,
662 struct phylink_link_state *status)
663 {
664 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
665
666 status->link = false;
667
668 /* MoCA port is special as we do not get link status from CORE_LNKSTS,
669 * which means that we need to force the link at the port override
670 * level to get the data to flow. We do use what the interrupt handler
671 * did determine before.
672 *
673 * For the other ports, we just force the link status, since this is
674 * a fixed PHY device.
675 */
676 if (port == priv->moca_port) {
677 status->link = priv->port_sts[port].link;
678 /* For MoCA interfaces, also force a link down notification
679 * since some version of the user-space daemon (mocad) use
680 * cmd->autoneg to force the link, which messes up the PHY
681 * state machine and make it go in PHY_FORCING state instead.
682 */
683 if (!status->link)
684 netif_carrier_off(dsa_to_port(ds, port)->slave);
685 status->duplex = DUPLEX_FULL;
686 } else {
687 status->link = true;
688 }
689 }
690
691 static void bcm_sf2_enable_acb(struct dsa_switch *ds)
692 {
693 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
694 u32 reg;
695
696 /* Enable ACB globally */
697 reg = acb_readl(priv, ACB_CONTROL);
698 reg |= (ACB_FLUSH_MASK << ACB_FLUSH_SHIFT);
699 acb_writel(priv, reg, ACB_CONTROL);
700 reg &= ~(ACB_FLUSH_MASK << ACB_FLUSH_SHIFT);
701 reg |= ACB_EN | ACB_ALGORITHM;
702 acb_writel(priv, reg, ACB_CONTROL);
703 }
704
705 static int bcm_sf2_sw_suspend(struct dsa_switch *ds)
706 {
707 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
708 unsigned int port;
709
710 bcm_sf2_intr_disable(priv);
711
712 /* Disable all ports physically present including the IMP
713 * port, the other ones have already been disabled during
714 * bcm_sf2_sw_setup
715 */
716 for (port = 0; port < ds->num_ports; port++) {
717 if (dsa_is_user_port(ds, port) || dsa_is_cpu_port(ds, port))
718 bcm_sf2_port_disable(ds, port);
719 }
720
721 return 0;
722 }
723
724 static int bcm_sf2_sw_resume(struct dsa_switch *ds)
725 {
726 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
727 int ret;
728
729 ret = bcm_sf2_sw_rst(priv);
730 if (ret) {
731 pr_err("%s: failed to software reset switch\n", __func__);
732 return ret;
733 }
734
735 ret = bcm_sf2_cfp_resume(ds);
736 if (ret)
737 return ret;
738
739 if (priv->hw_params.num_gphy == 1)
740 bcm_sf2_gphy_enable_set(ds, true);
741
742 ds->ops->setup(ds);
743
744 return 0;
745 }
746
747 static void bcm_sf2_sw_get_wol(struct dsa_switch *ds, int port,
748 struct ethtool_wolinfo *wol)
749 {
750 struct net_device *p = dsa_to_port(ds, port)->cpu_dp->master;
751 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
752 struct ethtool_wolinfo pwol = { };
753
754 /* Get the parent device WoL settings */
755 if (p->ethtool_ops->get_wol)
756 p->ethtool_ops->get_wol(p, &pwol);
757
758 /* Advertise the parent device supported settings */
759 wol->supported = pwol.supported;
760 memset(&wol->sopass, 0, sizeof(wol->sopass));
761
762 if (pwol.wolopts & WAKE_MAGICSECURE)
763 memcpy(&wol->sopass, pwol.sopass, sizeof(wol->sopass));
764
765 if (priv->wol_ports_mask & (1 << port))
766 wol->wolopts = pwol.wolopts;
767 else
768 wol->wolopts = 0;
769 }
770
771 static int bcm_sf2_sw_set_wol(struct dsa_switch *ds, int port,
772 struct ethtool_wolinfo *wol)
773 {
774 struct net_device *p = dsa_to_port(ds, port)->cpu_dp->master;
775 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
776 s8 cpu_port = dsa_to_port(ds, port)->cpu_dp->index;
777 struct ethtool_wolinfo pwol = { };
778
779 if (p->ethtool_ops->get_wol)
780 p->ethtool_ops->get_wol(p, &pwol);
781 if (wol->wolopts & ~pwol.supported)
782 return -EINVAL;
783
784 if (wol->wolopts)
785 priv->wol_ports_mask |= (1 << port);
786 else
787 priv->wol_ports_mask &= ~(1 << port);
788
789 /* If we have at least one port enabled, make sure the CPU port
790 * is also enabled. If the CPU port is the last one enabled, we disable
791 * it since this configuration does not make sense.
792 */
793 if (priv->wol_ports_mask && priv->wol_ports_mask != (1 << cpu_port))
794 priv->wol_ports_mask |= (1 << cpu_port);
795 else
796 priv->wol_ports_mask &= ~(1 << cpu_port);
797
798 return p->ethtool_ops->set_wol(p, wol);
799 }
800
801 static int bcm_sf2_sw_setup(struct dsa_switch *ds)
802 {
803 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
804 unsigned int port;
805
806 /* Enable all valid ports and disable those unused */
807 for (port = 0; port < priv->hw_params.num_ports; port++) {
808 /* IMP port receives special treatment */
809 if (dsa_is_user_port(ds, port))
810 bcm_sf2_port_setup(ds, port, NULL);
811 else if (dsa_is_cpu_port(ds, port))
812 bcm_sf2_imp_setup(ds, port);
813 else
814 bcm_sf2_port_disable(ds, port);
815 }
816
817 b53_configure_vlan(ds);
818 bcm_sf2_enable_acb(ds);
819
820 return 0;
821 }
822
823 /* The SWITCH_CORE register space is managed by b53 but operates on a page +
824 * register basis so we need to translate that into an address that the
825 * bus-glue understands.
826 */
827 #define SF2_PAGE_REG_MKADDR(page, reg) ((page) << 10 | (reg) << 2)
828
829 static int bcm_sf2_core_read8(struct b53_device *dev, u8 page, u8 reg,
830 u8 *val)
831 {
832 struct bcm_sf2_priv *priv = dev->priv;
833
834 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg));
835
836 return 0;
837 }
838
839 static int bcm_sf2_core_read16(struct b53_device *dev, u8 page, u8 reg,
840 u16 *val)
841 {
842 struct bcm_sf2_priv *priv = dev->priv;
843
844 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg));
845
846 return 0;
847 }
848
849 static int bcm_sf2_core_read32(struct b53_device *dev, u8 page, u8 reg,
850 u32 *val)
851 {
852 struct bcm_sf2_priv *priv = dev->priv;
853
854 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg));
855
856 return 0;
857 }
858
859 static int bcm_sf2_core_read64(struct b53_device *dev, u8 page, u8 reg,
860 u64 *val)
861 {
862 struct bcm_sf2_priv *priv = dev->priv;
863
864 *val = core_readq(priv, SF2_PAGE_REG_MKADDR(page, reg));
865
866 return 0;
867 }
868
869 static int bcm_sf2_core_write8(struct b53_device *dev, u8 page, u8 reg,
870 u8 value)
871 {
872 struct bcm_sf2_priv *priv = dev->priv;
873
874 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg));
875
876 return 0;
877 }
878
879 static int bcm_sf2_core_write16(struct b53_device *dev, u8 page, u8 reg,
880 u16 value)
881 {
882 struct bcm_sf2_priv *priv = dev->priv;
883
884 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg));
885
886 return 0;
887 }
888
889 static int bcm_sf2_core_write32(struct b53_device *dev, u8 page, u8 reg,
890 u32 value)
891 {
892 struct bcm_sf2_priv *priv = dev->priv;
893
894 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg));
895
896 return 0;
897 }
898
899 static int bcm_sf2_core_write64(struct b53_device *dev, u8 page, u8 reg,
900 u64 value)
901 {
902 struct bcm_sf2_priv *priv = dev->priv;
903
904 core_writeq(priv, value, SF2_PAGE_REG_MKADDR(page, reg));
905
906 return 0;
907 }
908
909 static const struct b53_io_ops bcm_sf2_io_ops = {
910 .read8 = bcm_sf2_core_read8,
911 .read16 = bcm_sf2_core_read16,
912 .read32 = bcm_sf2_core_read32,
913 .read48 = bcm_sf2_core_read64,
914 .read64 = bcm_sf2_core_read64,
915 .write8 = bcm_sf2_core_write8,
916 .write16 = bcm_sf2_core_write16,
917 .write32 = bcm_sf2_core_write32,
918 .write48 = bcm_sf2_core_write64,
919 .write64 = bcm_sf2_core_write64,
920 };
921
922 static void bcm_sf2_sw_get_strings(struct dsa_switch *ds, int port,
923 u32 stringset, uint8_t *data)
924 {
925 int cnt = b53_get_sset_count(ds, port, stringset);
926
927 b53_get_strings(ds, port, stringset, data);
928 bcm_sf2_cfp_get_strings(ds, port, stringset,
929 data + cnt * ETH_GSTRING_LEN);
930 }
931
932 static void bcm_sf2_sw_get_ethtool_stats(struct dsa_switch *ds, int port,
933 uint64_t *data)
934 {
935 int cnt = b53_get_sset_count(ds, port, ETH_SS_STATS);
936
937 b53_get_ethtool_stats(ds, port, data);
938 bcm_sf2_cfp_get_ethtool_stats(ds, port, data + cnt);
939 }
940
941 static int bcm_sf2_sw_get_sset_count(struct dsa_switch *ds, int port,
942 int sset)
943 {
944 int cnt = b53_get_sset_count(ds, port, sset);
945
946 if (cnt < 0)
947 return cnt;
948
949 cnt += bcm_sf2_cfp_get_sset_count(ds, port, sset);
950
951 return cnt;
952 }
953
954 static const struct dsa_switch_ops bcm_sf2_ops = {
955 .get_tag_protocol = b53_get_tag_protocol,
956 .setup = bcm_sf2_sw_setup,
957 .get_strings = bcm_sf2_sw_get_strings,
958 .get_ethtool_stats = bcm_sf2_sw_get_ethtool_stats,
959 .get_sset_count = bcm_sf2_sw_get_sset_count,
960 .get_ethtool_phy_stats = b53_get_ethtool_phy_stats,
961 .get_phy_flags = bcm_sf2_sw_get_phy_flags,
962 .phylink_validate = bcm_sf2_sw_validate,
963 .phylink_mac_config = bcm_sf2_sw_mac_config,
964 .phylink_mac_link_down = bcm_sf2_sw_mac_link_down,
965 .phylink_mac_link_up = bcm_sf2_sw_mac_link_up,
966 .phylink_fixed_state = bcm_sf2_sw_fixed_state,
967 .suspend = bcm_sf2_sw_suspend,
968 .resume = bcm_sf2_sw_resume,
969 .get_wol = bcm_sf2_sw_get_wol,
970 .set_wol = bcm_sf2_sw_set_wol,
971 .port_enable = bcm_sf2_port_setup,
972 .port_disable = bcm_sf2_port_disable,
973 .get_mac_eee = b53_get_mac_eee,
974 .set_mac_eee = b53_set_mac_eee,
975 .port_bridge_join = b53_br_join,
976 .port_bridge_leave = b53_br_leave,
977 .port_stp_state_set = b53_br_set_stp_state,
978 .port_fast_age = b53_br_fast_age,
979 .port_vlan_filtering = b53_vlan_filtering,
980 .port_vlan_prepare = b53_vlan_prepare,
981 .port_vlan_add = b53_vlan_add,
982 .port_vlan_del = b53_vlan_del,
983 .port_fdb_dump = b53_fdb_dump,
984 .port_fdb_add = b53_fdb_add,
985 .port_fdb_del = b53_fdb_del,
986 .get_rxnfc = bcm_sf2_get_rxnfc,
987 .set_rxnfc = bcm_sf2_set_rxnfc,
988 .port_mirror_add = b53_mirror_add,
989 .port_mirror_del = b53_mirror_del,
990 .port_mdb_prepare = b53_mdb_prepare,
991 .port_mdb_add = b53_mdb_add,
992 .port_mdb_del = b53_mdb_del,
993 };
994
995 struct bcm_sf2_of_data {
996 u32 type;
997 const u16 *reg_offsets;
998 unsigned int core_reg_align;
999 unsigned int num_cfp_rules;
1000 };
1001
1002 /* Register offsets for the SWITCH_REG_* block */
1003 static const u16 bcm_sf2_7445_reg_offsets[] = {
1004 [REG_SWITCH_CNTRL] = 0x00,
1005 [REG_SWITCH_STATUS] = 0x04,
1006 [REG_DIR_DATA_WRITE] = 0x08,
1007 [REG_DIR_DATA_READ] = 0x0C,
1008 [REG_SWITCH_REVISION] = 0x18,
1009 [REG_PHY_REVISION] = 0x1C,
1010 [REG_SPHY_CNTRL] = 0x2C,
1011 [REG_RGMII_0_CNTRL] = 0x34,
1012 [REG_RGMII_1_CNTRL] = 0x40,
1013 [REG_RGMII_2_CNTRL] = 0x4c,
1014 [REG_LED_0_CNTRL] = 0x90,
1015 [REG_LED_1_CNTRL] = 0x94,
1016 [REG_LED_2_CNTRL] = 0x98,
1017 };
1018
1019 static const struct bcm_sf2_of_data bcm_sf2_7445_data = {
1020 .type = BCM7445_DEVICE_ID,
1021 .core_reg_align = 0,
1022 .reg_offsets = bcm_sf2_7445_reg_offsets,
1023 .num_cfp_rules = 256,
1024 };
1025
1026 static const u16 bcm_sf2_7278_reg_offsets[] = {
1027 [REG_SWITCH_CNTRL] = 0x00,
1028 [REG_SWITCH_STATUS] = 0x04,
1029 [REG_DIR_DATA_WRITE] = 0x08,
1030 [REG_DIR_DATA_READ] = 0x0c,
1031 [REG_SWITCH_REVISION] = 0x10,
1032 [REG_PHY_REVISION] = 0x14,
1033 [REG_SPHY_CNTRL] = 0x24,
1034 [REG_RGMII_0_CNTRL] = 0xe0,
1035 [REG_RGMII_1_CNTRL] = 0xec,
1036 [REG_RGMII_2_CNTRL] = 0xf8,
1037 [REG_LED_0_CNTRL] = 0x40,
1038 [REG_LED_1_CNTRL] = 0x4c,
1039 [REG_LED_2_CNTRL] = 0x58,
1040 };
1041
1042 static const struct bcm_sf2_of_data bcm_sf2_7278_data = {
1043 .type = BCM7278_DEVICE_ID,
1044 .core_reg_align = 1,
1045 .reg_offsets = bcm_sf2_7278_reg_offsets,
1046 .num_cfp_rules = 128,
1047 };
1048
1049 static const struct of_device_id bcm_sf2_of_match[] = {
1050 { .compatible = "brcm,bcm7445-switch-v4.0",
1051 .data = &bcm_sf2_7445_data
1052 },
1053 { .compatible = "brcm,bcm7278-switch-v4.0",
1054 .data = &bcm_sf2_7278_data
1055 },
1056 { .compatible = "brcm,bcm7278-switch-v4.8",
1057 .data = &bcm_sf2_7278_data
1058 },
1059 { /* sentinel */ },
1060 };
1061 MODULE_DEVICE_TABLE(of, bcm_sf2_of_match);
1062
1063 static int bcm_sf2_sw_probe(struct platform_device *pdev)
1064 {
1065 const char *reg_names[BCM_SF2_REGS_NUM] = BCM_SF2_REGS_NAME;
1066 struct device_node *dn = pdev->dev.of_node;
1067 const struct of_device_id *of_id = NULL;
1068 const struct bcm_sf2_of_data *data;
1069 struct b53_platform_data *pdata;
1070 struct dsa_switch_ops *ops;
1071 struct bcm_sf2_priv *priv;
1072 struct b53_device *dev;
1073 struct dsa_switch *ds;
1074 void __iomem **base;
1075 unsigned int i;
1076 u32 reg, rev;
1077 int ret;
1078
1079 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
1080 if (!priv)
1081 return -ENOMEM;
1082
1083 ops = devm_kzalloc(&pdev->dev, sizeof(*ops), GFP_KERNEL);
1084 if (!ops)
1085 return -ENOMEM;
1086
1087 dev = b53_switch_alloc(&pdev->dev, &bcm_sf2_io_ops, priv);
1088 if (!dev)
1089 return -ENOMEM;
1090
1091 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1092 if (!pdata)
1093 return -ENOMEM;
1094
1095 of_id = of_match_node(bcm_sf2_of_match, dn);
1096 if (!of_id || !of_id->data)
1097 return -EINVAL;
1098
1099 data = of_id->data;
1100
1101 /* Set SWITCH_REG register offsets and SWITCH_CORE align factor */
1102 priv->type = data->type;
1103 priv->reg_offsets = data->reg_offsets;
1104 priv->core_reg_align = data->core_reg_align;
1105 priv->num_cfp_rules = data->num_cfp_rules;
1106
1107 priv->rcdev = devm_reset_control_get_optional_exclusive(&pdev->dev,
1108 "switch");
1109 if (PTR_ERR(priv->rcdev) == -EPROBE_DEFER)
1110 return PTR_ERR(priv->rcdev);
1111
1112 /* Auto-detection using standard registers will not work, so
1113 * provide an indication of what kind of device we are for
1114 * b53_common to work with
1115 */
1116 pdata->chip_id = priv->type;
1117 dev->pdata = pdata;
1118
1119 priv->dev = dev;
1120 ds = dev->ds;
1121 ds->ops = &bcm_sf2_ops;
1122
1123 /* Advertise the 8 egress queues */
1124 ds->num_tx_queues = SF2_NUM_EGRESS_QUEUES;
1125
1126 dev_set_drvdata(&pdev->dev, priv);
1127
1128 spin_lock_init(&priv->indir_lock);
1129 mutex_init(&priv->cfp.lock);
1130 INIT_LIST_HEAD(&priv->cfp.rules_list);
1131
1132 /* CFP rule #0 cannot be used for specific classifications, flag it as
1133 * permanently used
1134 */
1135 set_bit(0, priv->cfp.used);
1136 set_bit(0, priv->cfp.unique);
1137
1138 bcm_sf2_identify_ports(priv, dn->child);
1139
1140 priv->irq0 = irq_of_parse_and_map(dn, 0);
1141 priv->irq1 = irq_of_parse_and_map(dn, 1);
1142
1143 base = &priv->core;
1144 for (i = 0; i < BCM_SF2_REGS_NUM; i++) {
1145 *base = devm_platform_ioremap_resource(pdev, i);
1146 if (IS_ERR(*base)) {
1147 pr_err("unable to find register: %s\n", reg_names[i]);
1148 return PTR_ERR(*base);
1149 }
1150 base++;
1151 }
1152
1153 ret = bcm_sf2_sw_rst(priv);
1154 if (ret) {
1155 pr_err("unable to software reset switch: %d\n", ret);
1156 return ret;
1157 }
1158
1159 bcm_sf2_gphy_enable_set(priv->dev->ds, true);
1160
1161 ret = bcm_sf2_mdio_register(ds);
1162 if (ret) {
1163 pr_err("failed to register MDIO bus\n");
1164 return ret;
1165 }
1166
1167 bcm_sf2_gphy_enable_set(priv->dev->ds, false);
1168
1169 ret = bcm_sf2_cfp_rst(priv);
1170 if (ret) {
1171 pr_err("failed to reset CFP\n");
1172 goto out_mdio;
1173 }
1174
1175 /* Disable all interrupts and request them */
1176 bcm_sf2_intr_disable(priv);
1177
1178 ret = devm_request_irq(&pdev->dev, priv->irq0, bcm_sf2_switch_0_isr, 0,
1179 "switch_0", ds);
1180 if (ret < 0) {
1181 pr_err("failed to request switch_0 IRQ\n");
1182 goto out_mdio;
1183 }
1184
1185 ret = devm_request_irq(&pdev->dev, priv->irq1, bcm_sf2_switch_1_isr, 0,
1186 "switch_1", ds);
1187 if (ret < 0) {
1188 pr_err("failed to request switch_1 IRQ\n");
1189 goto out_mdio;
1190 }
1191
1192 /* Reset the MIB counters */
1193 reg = core_readl(priv, CORE_GMNCFGCFG);
1194 reg |= RST_MIB_CNT;
1195 core_writel(priv, reg, CORE_GMNCFGCFG);
1196 reg &= ~RST_MIB_CNT;
1197 core_writel(priv, reg, CORE_GMNCFGCFG);
1198
1199 /* Get the maximum number of ports for this switch */
1200 priv->hw_params.num_ports = core_readl(priv, CORE_IMP0_PRT_ID) + 1;
1201 if (priv->hw_params.num_ports > DSA_MAX_PORTS)
1202 priv->hw_params.num_ports = DSA_MAX_PORTS;
1203
1204 /* Assume a single GPHY setup if we can't read that property */
1205 if (of_property_read_u32(dn, "brcm,num-gphy",
1206 &priv->hw_params.num_gphy))
1207 priv->hw_params.num_gphy = 1;
1208
1209 rev = reg_readl(priv, REG_SWITCH_REVISION);
1210 priv->hw_params.top_rev = (rev >> SWITCH_TOP_REV_SHIFT) &
1211 SWITCH_TOP_REV_MASK;
1212 priv->hw_params.core_rev = (rev & SF2_REV_MASK);
1213
1214 rev = reg_readl(priv, REG_PHY_REVISION);
1215 priv->hw_params.gphy_rev = rev & PHY_REVISION_MASK;
1216
1217 ret = b53_switch_register(dev);
1218 if (ret)
1219 goto out_mdio;
1220
1221 dev_info(&pdev->dev,
1222 "Starfighter 2 top: %x.%02x, core: %x.%02x, IRQs: %d, %d\n",
1223 priv->hw_params.top_rev >> 8, priv->hw_params.top_rev & 0xff,
1224 priv->hw_params.core_rev >> 8, priv->hw_params.core_rev & 0xff,
1225 priv->irq0, priv->irq1);
1226
1227 return 0;
1228
1229 out_mdio:
1230 bcm_sf2_mdio_unregister(priv);
1231 return ret;
1232 }
1233
1234 static int bcm_sf2_sw_remove(struct platform_device *pdev)
1235 {
1236 struct bcm_sf2_priv *priv = platform_get_drvdata(pdev);
1237
1238 priv->wol_ports_mask = 0;
1239 /* Disable interrupts */
1240 bcm_sf2_intr_disable(priv);
1241 dsa_unregister_switch(priv->dev->ds);
1242 bcm_sf2_cfp_exit(priv->dev->ds);
1243 bcm_sf2_mdio_unregister(priv);
1244 if (priv->type == BCM7278_DEVICE_ID && !IS_ERR(priv->rcdev))
1245 reset_control_assert(priv->rcdev);
1246
1247 return 0;
1248 }
1249
1250 static void bcm_sf2_sw_shutdown(struct platform_device *pdev)
1251 {
1252 struct bcm_sf2_priv *priv = platform_get_drvdata(pdev);
1253
1254 /* For a kernel about to be kexec'd we want to keep the GPHY on for a
1255 * successful MDIO bus scan to occur. If we did turn off the GPHY
1256 * before (e.g: port_disable), this will also power it back on.
1257 *
1258 * Do not rely on kexec_in_progress, just power the PHY on.
1259 */
1260 if (priv->hw_params.num_gphy == 1)
1261 bcm_sf2_gphy_enable_set(priv->dev->ds, true);
1262 }
1263
1264 #ifdef CONFIG_PM_SLEEP
1265 static int bcm_sf2_suspend(struct device *dev)
1266 {
1267 struct bcm_sf2_priv *priv = dev_get_drvdata(dev);
1268
1269 return dsa_switch_suspend(priv->dev->ds);
1270 }
1271
1272 static int bcm_sf2_resume(struct device *dev)
1273 {
1274 struct bcm_sf2_priv *priv = dev_get_drvdata(dev);
1275
1276 return dsa_switch_resume(priv->dev->ds);
1277 }
1278 #endif /* CONFIG_PM_SLEEP */
1279
1280 static SIMPLE_DEV_PM_OPS(bcm_sf2_pm_ops,
1281 bcm_sf2_suspend, bcm_sf2_resume);
1282
1283
1284 static struct platform_driver bcm_sf2_driver = {
1285 .probe = bcm_sf2_sw_probe,
1286 .remove = bcm_sf2_sw_remove,
1287 .shutdown = bcm_sf2_sw_shutdown,
1288 .driver = {
1289 .name = "brcm-sf2",
1290 .of_match_table = bcm_sf2_of_match,
1291 .pm = &bcm_sf2_pm_ops,
1292 },
1293 };
1294 module_platform_driver(bcm_sf2_driver);
1295
1296 MODULE_AUTHOR("Broadcom Corporation");
1297 MODULE_DESCRIPTION("Driver for Broadcom Starfighter 2 ethernet switch chip");
1298 MODULE_LICENSE("GPL");
1299 MODULE_ALIAS("platform:brcm-sf2");
Linux with added FPC-III support