drivers/net/dsa/mv88e6xxx/port.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Marvell 88E6xxx Switch Port Registers support
   4  *
   5  * Copyright (c) 2008 Marvell Semiconductor
   6  *
   7  * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
   8  *      Vivien Didelot <vivien.didelot@savoirfairelinux.com>
   9  */
  10
  11 #include <linux/bitfield.h>
  12 #include <linux/if_bridge.h>
  13 #include <linux/phy.h>
  14 #include <linux/phylink.h>
  15
  16 #include "chip.h"
  17 #include "port.h"
  18 #include "serdes.h"
  19
  20 int mv88e6xxx_port_read(struct mv88e6xxx_chip *chip, int port, int reg,
  21                         u16 *val)
  22 {
  23         int addr = chip->info->port_base_addr + port;
  24
  25         return mv88e6xxx_read(chip, addr, reg, val);
  26 }
  27
  28 int mv88e6xxx_port_write(struct mv88e6xxx_chip *chip, int port, int reg,
  29                          u16 val)
  30 {
  31         int addr = chip->info->port_base_addr + port;
  32
  33         return mv88e6xxx_write(chip, addr, reg, val);
  34 }
  35
  36 /* Offset 0x00: MAC (or PCS or Physical) Status Register
  37  *
  38  * For most devices, this is read only. However the 6185 has the MyPause
  39  * bit read/write.
  40  */
  41 int mv88e6185_port_set_pause(struct mv88e6xxx_chip *chip, int port,
  42                              int pause)
  43 {
  44         u16 reg;
  45         int err;
  46
  47         err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, &reg);
  48         if (err)
  49                 return err;
  50
  51         if (pause)
  52                 reg |= MV88E6XXX_PORT_STS_MY_PAUSE;
  53         else
  54                 reg &= ~MV88E6XXX_PORT_STS_MY_PAUSE;
  55
  56         return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_STS, reg);
  57 }
  58
  59 /* Offset 0x01: MAC (or PCS or Physical) Control Register
  60  *
  61  * Link, Duplex and Flow Control have one force bit, one value bit.
  62  *
  63  * For port's MAC speed, ForceSpd (or SpdValue) bits 1:0 program the value.
  64  * Alternative values require the 200BASE (or AltSpeed) bit 12 set.
  65  * Newer chips need a ForcedSpd bit 13 set to consider the value.
  66  */
  67
  68 static int mv88e6xxx_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port,
  69                                           phy_interface_t mode)
  70 {
  71         u16 reg;
  72         int err;
  73
  74         err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, &reg);
  75         if (err)
  76                 return err;
  77
  78         reg &= ~(MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK |
  79                  MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK);
  80
  81         switch (mode) {
  82         case PHY_INTERFACE_MODE_RGMII_RXID:
  83                 reg |= MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK;
  84                 break;
  85         case PHY_INTERFACE_MODE_RGMII_TXID:
  86                 reg |= MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK;
  87                 break;
  88         case PHY_INTERFACE_MODE_RGMII_ID:
  89                 reg |= MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK |
  90                         MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK;
  91                 break;
  92         case PHY_INTERFACE_MODE_RGMII:
  93                 break;
  94         default:
  95                 return 0;
  96         }
  97
  98         err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg);
  99         if (err)
 100                 return err;
 101
 102         dev_dbg(chip->dev, "p%d: delay RXCLK %s, TXCLK %s\n", port,
 103                 reg & MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK ? "yes" : "no",
 104                 reg & MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK ? "yes" : "no");
 105
 106         return 0;
 107 }
 108
 109 int mv88e6352_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port,
 110                                    phy_interface_t mode)
 111 {
 112         if (port < 5)
 113                 return -EOPNOTSUPP;
 114
 115         return mv88e6xxx_port_set_rgmii_delay(chip, port, mode);
 116 }
 117
 118 int mv88e6390_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port,
 119                                    phy_interface_t mode)
 120 {
 121         if (port != 0)
 122                 return -EOPNOTSUPP;
 123
 124         return mv88e6xxx_port_set_rgmii_delay(chip, port, mode);
 125 }
 126
 127 int mv88e6xxx_port_set_link(struct mv88e6xxx_chip *chip, int port, int link)
 128 {
 129         u16 reg;
 130         int err;
 131
 132         err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, &reg);
 133         if (err)
 134                 return err;
 135
 136         reg &= ~(MV88E6XXX_PORT_MAC_CTL_FORCE_LINK |
 137                  MV88E6XXX_PORT_MAC_CTL_LINK_UP);
 138
 139         switch (link) {
 140         case LINK_FORCED_DOWN:
 141                 reg |= MV88E6XXX_PORT_MAC_CTL_FORCE_LINK;
 142                 break;
 143         case LINK_FORCED_UP:
 144                 reg |= MV88E6XXX_PORT_MAC_CTL_FORCE_LINK |
 145                         MV88E6XXX_PORT_MAC_CTL_LINK_UP;
 146                 break;
 147         case LINK_UNFORCED:
 148                 /* normal link detection */
 149                 break;
 150         default:
 151                 return -EINVAL;
 152         }
 153
 154         err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg);
 155         if (err)
 156                 return err;
 157
 158         dev_dbg(chip->dev, "p%d: %s link %s\n", port,
 159                 reg & MV88E6XXX_PORT_MAC_CTL_FORCE_LINK ? "Force" : "Unforce",
 160                 reg & MV88E6XXX_PORT_MAC_CTL_LINK_UP ? "up" : "down");
 161
 162         return 0;
 163 }
 164
 165 int mv88e6xxx_port_set_duplex(struct mv88e6xxx_chip *chip, int port, int dup)
 166 {
 167         u16 reg;
 168         int err;
 169
 170         err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, &reg);
 171         if (err)
 172                 return err;
 173
 174         reg &= ~(MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX |
 175                  MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL);
 176
 177         switch (dup) {
 178         case DUPLEX_HALF:
 179                 reg |= MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX;
 180                 break;
 181         case DUPLEX_FULL:
 182                 reg |= MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX |
 183                         MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL;
 184                 break;
 185         case DUPLEX_UNFORCED:
 186                 /* normal duplex detection */
 187                 break;
 188         default:
 189                 return -EOPNOTSUPP;
 190         }
 191
 192         err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg);
 193         if (err)
 194                 return err;
 195
 196         dev_dbg(chip->dev, "p%d: %s %s duplex\n", port,
 197                 reg & MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX ? "Force" : "Unforce",
 198                 reg & MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL ? "full" : "half");
 199
 200         return 0;
 201 }
 202
 203 static int mv88e6xxx_port_set_speed(struct mv88e6xxx_chip *chip, int port,
 204                                     int speed, bool alt_bit, bool force_bit)
 205 {
 206         u16 reg, ctrl;
 207         int err;
 208
 209         switch (speed) {
 210         case 10:
 211                 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_10;
 212                 break;
 213         case 100:
 214                 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_100;
 215                 break;
 216         case 200:
 217                 if (alt_bit)
 218                         ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_100 |
 219                                 MV88E6390_PORT_MAC_CTL_ALTSPEED;
 220                 else
 221                         ctrl = MV88E6065_PORT_MAC_CTL_SPEED_200;
 222                 break;
 223         case 1000:
 224                 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_1000;
 225                 break;
 226         case 2500:
 227                 if (alt_bit)
 228                         ctrl = MV88E6390_PORT_MAC_CTL_SPEED_10000 |
 229                                 MV88E6390_PORT_MAC_CTL_ALTSPEED;
 230                 else
 231                         ctrl = MV88E6390_PORT_MAC_CTL_SPEED_10000;
 232                 break;
 233         case 10000:
 234                 /* all bits set, fall through... */
 235         case SPEED_UNFORCED:
 236                 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_UNFORCED;
 237                 break;
 238         default:
 239                 return -EOPNOTSUPP;
 240         }
 241
 242         err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, &reg);
 243         if (err)
 244                 return err;
 245
 246         reg &= ~MV88E6XXX_PORT_MAC_CTL_SPEED_MASK;
 247         if (alt_bit)
 248                 reg &= ~MV88E6390_PORT_MAC_CTL_ALTSPEED;
 249         if (force_bit) {
 250                 reg &= ~MV88E6390_PORT_MAC_CTL_FORCE_SPEED;
 251                 if (speed != SPEED_UNFORCED)
 252                         ctrl |= MV88E6390_PORT_MAC_CTL_FORCE_SPEED;
 253         }
 254         reg |= ctrl;
 255
 256         err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg);
 257         if (err)
 258                 return err;
 259
 260         if (speed)
 261                 dev_dbg(chip->dev, "p%d: Speed set to %d Mbps\n", port, speed);
 262         else
 263                 dev_dbg(chip->dev, "p%d: Speed unforced\n", port);
 264
 265         return 0;
 266 }
 267
 268 /* Support 10, 100, 200 Mbps (e.g. 88E6065 family) */
 269 int mv88e6065_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed)
 270 {
 271         if (speed == SPEED_MAX)
 272                 speed = 200;
 273
 274         if (speed > 200)
 275                 return -EOPNOTSUPP;
 276
 277         /* Setting 200 Mbps on port 0 to 3 selects 100 Mbps */
 278         return mv88e6xxx_port_set_speed(chip, port, speed, false, false);
 279 }
 280
 281 /* Support 10, 100, 1000 Mbps (e.g. 88E6185 family) */
 282 int mv88e6185_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed)
 283 {
 284         if (speed == SPEED_MAX)
 285                 speed = 1000;
 286
 287         if (speed == 200 || speed > 1000)
 288                 return -EOPNOTSUPP;
 289
 290         return mv88e6xxx_port_set_speed(chip, port, speed, false, false);
 291 }
 292
 293 /* Support 10, 100 Mbps (e.g. 88E6250 family) */
 294 int mv88e6250_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed)
 295 {
 296         if (speed == SPEED_MAX)
 297                 speed = 100;
 298
 299         if (speed > 100)
 300                 return -EOPNOTSUPP;
 301
 302         return mv88e6xxx_port_set_speed(chip, port, speed, false, false);
 303 }
 304
 305 /* Support 10, 100, 200, 1000, 2500 Mbps (e.g. 88E6341) */
 306 int mv88e6341_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed)
 307 {
 308         if (speed == SPEED_MAX)
 309                 speed = port < 5 ? 1000 : 2500;
 310
 311         if (speed > 2500)
 312                 return -EOPNOTSUPP;
 313
 314         if (speed == 200 && port != 0)
 315                 return -EOPNOTSUPP;
 316
 317         if (speed == 2500 && port < 5)
 318                 return -EOPNOTSUPP;
 319
 320         return mv88e6xxx_port_set_speed(chip, port, speed, !port, true);
 321 }
 322
 323 phy_interface_t mv88e6341_port_max_speed_mode(int port)
 324 {
 325         if (port == 5)
 326                 return PHY_INTERFACE_MODE_2500BASEX;
 327
 328         return PHY_INTERFACE_MODE_NA;
 329 }
 330
 331 /* Support 10, 100, 200, 1000 Mbps (e.g. 88E6352 family) */
 332 int mv88e6352_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed)
 333 {
 334         if (speed == SPEED_MAX)
 335                 speed = 1000;
 336
 337         if (speed > 1000)
 338                 return -EOPNOTSUPP;
 339
 340         if (speed == 200 && port < 5)
 341                 return -EOPNOTSUPP;
 342
 343         return mv88e6xxx_port_set_speed(chip, port, speed, true, false);
 344 }
 345
 346 /* Support 10, 100, 200, 1000, 2500 Mbps (e.g. 88E6390) */
 347 int mv88e6390_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed)
 348 {
 349         if (speed == SPEED_MAX)
 350                 speed = port < 9 ? 1000 : 2500;
 351
 352         if (speed > 2500)
 353                 return -EOPNOTSUPP;
 354
 355         if (speed == 200 && port != 0)
 356                 return -EOPNOTSUPP;
 357
 358         if (speed == 2500 && port < 9)
 359                 return -EOPNOTSUPP;
 360
 361         return mv88e6xxx_port_set_speed(chip, port, speed, true, true);
 362 }
 363
 364 phy_interface_t mv88e6390_port_max_speed_mode(int port)
 365 {
 366         if (port == 9 || port == 10)
 367                 return PHY_INTERFACE_MODE_2500BASEX;
 368
 369         return PHY_INTERFACE_MODE_NA;
 370 }
 371
 372 /* Support 10, 100, 200, 1000, 2500, 10000 Mbps (e.g. 88E6190X) */
 373 int mv88e6390x_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed)
 374 {
 375         if (speed == SPEED_MAX)
 376                 speed = port < 9 ? 1000 : 10000;
 377
 378         if (speed == 200 && port != 0)
 379                 return -EOPNOTSUPP;
 380
 381         if (speed >= 2500 && port < 9)
 382                 return -EOPNOTSUPP;
 383
 384         return mv88e6xxx_port_set_speed(chip, port, speed, true, true);
 385 }
 386
 387 phy_interface_t mv88e6390x_port_max_speed_mode(int port)
 388 {
 389         if (port == 9 || port == 10)
 390                 return PHY_INTERFACE_MODE_XAUI;
 391
 392         return PHY_INTERFACE_MODE_NA;
 393 }
 394
 395 static int mv88e6xxx_port_set_cmode(struct mv88e6xxx_chip *chip, int port,
 396                                     phy_interface_t mode, bool force)
 397 {
 398         u8 lane;
 399         u16 cmode;
 400         u16 reg;
 401         int err;
 402
 403         /* Default to a slow mode, so freeing up SERDES interfaces for
 404          * other ports which might use them for SFPs.
 405          */
 406         if (mode == PHY_INTERFACE_MODE_NA)
 407                 mode = PHY_INTERFACE_MODE_1000BASEX;
 408
 409         switch (mode) {
 410         case PHY_INTERFACE_MODE_1000BASEX:
 411                 cmode = MV88E6XXX_PORT_STS_CMODE_1000BASEX;
 412                 break;
 413         case PHY_INTERFACE_MODE_SGMII:
 414                 cmode = MV88E6XXX_PORT_STS_CMODE_SGMII;
 415                 break;
 416         case PHY_INTERFACE_MODE_2500BASEX:
 417                 cmode = MV88E6XXX_PORT_STS_CMODE_2500BASEX;
 418                 break;
 419         case PHY_INTERFACE_MODE_XGMII:
 420         case PHY_INTERFACE_MODE_XAUI:
 421                 cmode = MV88E6XXX_PORT_STS_CMODE_XAUI;
 422                 break;
 423         case PHY_INTERFACE_MODE_RXAUI:
 424                 cmode = MV88E6XXX_PORT_STS_CMODE_RXAUI;
 425                 break;
 426         default:
 427                 cmode = 0;
 428         }
 429
 430         /* cmode doesn't change, nothing to do for us unless forced */
 431         if (cmode == chip->ports[port].cmode && !force)
 432                 return 0;
 433
 434         lane = mv88e6xxx_serdes_get_lane(chip, port);
 435         if (lane) {
 436                 if (chip->ports[port].serdes_irq) {
 437                         err = mv88e6xxx_serdes_irq_disable(chip, port, lane);
 438                         if (err)
 439                                 return err;
 440                 }
 441
 442                 err = mv88e6xxx_serdes_power_down(chip, port, lane);
 443                 if (err)
 444                         return err;
 445         }
 446
 447         chip->ports[port].cmode = 0;
 448
 449         if (cmode) {
 450                 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, &reg);
 451                 if (err)
 452                         return err;
 453
 454                 reg &= ~MV88E6XXX_PORT_STS_CMODE_MASK;
 455                 reg |= cmode;
 456
 457                 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_STS, reg);
 458                 if (err)
 459                         return err;
 460
 461                 chip->ports[port].cmode = cmode;
 462
 463                 lane = mv88e6xxx_serdes_get_lane(chip, port);
 464                 if (!lane)
 465                         return -ENODEV;
 466
 467                 err = mv88e6xxx_serdes_power_up(chip, port, lane);
 468                 if (err)
 469                         return err;
 470
 471                 if (chip->ports[port].serdes_irq) {
 472                         err = mv88e6xxx_serdes_irq_enable(chip, port, lane);
 473                         if (err)
 474                                 return err;
 475                 }
 476         }
 477
 478         return 0;
 479 }
 480
 481 int mv88e6390x_port_set_cmode(struct mv88e6xxx_chip *chip, int port,
 482                               phy_interface_t mode)
 483 {
 484         if (port != 9 && port != 10)
 485                 return -EOPNOTSUPP;
 486
 487         return mv88e6xxx_port_set_cmode(chip, port, mode, false);
 488 }
 489
 490 int mv88e6390_port_set_cmode(struct mv88e6xxx_chip *chip, int port,
 491                              phy_interface_t mode)
 492 {
 493         if (port != 9 && port != 10)
 494                 return -EOPNOTSUPP;
 495
 496         switch (mode) {
 497         case PHY_INTERFACE_MODE_NA:
 498                 return 0;
 499         case PHY_INTERFACE_MODE_XGMII:
 500         case PHY_INTERFACE_MODE_XAUI:
 501         case PHY_INTERFACE_MODE_RXAUI:
 502                 return -EINVAL;
 503         default:
 504                 break;
 505         }
 506
 507         return mv88e6xxx_port_set_cmode(chip, port, mode, false);
 508 }
 509
 510 static int mv88e6341_port_set_cmode_writable(struct mv88e6xxx_chip *chip,
 511                                              int port)
 512 {
 513         int err, addr;
 514         u16 reg, bits;
 515
 516         if (port != 5)
 517                 return -EOPNOTSUPP;
 518
 519         addr = chip->info->port_base_addr + port;
 520
 521         err = mv88e6xxx_port_hidden_read(chip, 0x7, addr, 0, &reg);
 522         if (err)
 523                 return err;
 524
 525         bits = MV88E6341_PORT_RESERVED_1A_FORCE_CMODE |
 526                MV88E6341_PORT_RESERVED_1A_SGMII_AN;
 527
 528         if ((reg & bits) == bits)
 529                 return 0;
 530
 531         reg |= bits;
 532         return mv88e6xxx_port_hidden_write(chip, 0x7, addr, 0, reg);
 533 }
 534
 535 int mv88e6341_port_set_cmode(struct mv88e6xxx_chip *chip, int port,
 536                              phy_interface_t mode)
 537 {
 538         int err;
 539
 540         if (port != 5)
 541                 return -EOPNOTSUPP;
 542
 543         switch (mode) {
 544         case PHY_INTERFACE_MODE_NA:
 545                 return 0;
 546         case PHY_INTERFACE_MODE_XGMII:
 547         case PHY_INTERFACE_MODE_XAUI:
 548         case PHY_INTERFACE_MODE_RXAUI:
 549                 return -EINVAL;
 550         default:
 551                 break;
 552         }
 553
 554         err = mv88e6341_port_set_cmode_writable(chip, port);
 555         if (err)
 556                 return err;
 557
 558         return mv88e6xxx_port_set_cmode(chip, port, mode, true);
 559 }
 560
 561 int mv88e6185_port_get_cmode(struct mv88e6xxx_chip *chip, int port, u8 *cmode)
 562 {
 563         int err;
 564         u16 reg;
 565
 566         err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, &reg);
 567         if (err)
 568                 return err;
 569
 570         *cmode = reg & MV88E6185_PORT_STS_CMODE_MASK;
 571
 572         return 0;
 573 }
 574
 575 int mv88e6352_port_get_cmode(struct mv88e6xxx_chip *chip, int port, u8 *cmode)
 576 {
 577         int err;
 578         u16 reg;
 579
 580         err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, &reg);
 581         if (err)
 582                 return err;
 583
 584         *cmode = reg & MV88E6XXX_PORT_STS_CMODE_MASK;
 585
 586         return 0;
 587 }
 588
 589 int mv88e6250_port_link_state(struct mv88e6xxx_chip *chip, int port,
 590                               struct phylink_link_state *state)
 591 {
 592         int err;
 593         u16 reg;
 594
 595         err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, &reg);
 596         if (err)
 597                 return err;
 598
 599         if (port < 5) {
 600                 switch (reg & MV88E6250_PORT_STS_PORTMODE_MASK) {
 601                 case MV88E6250_PORT_STS_PORTMODE_PHY_10_HALF:
 602                         state->speed = SPEED_10;
 603                         state->duplex = DUPLEX_HALF;
 604                         break;
 605                 case MV88E6250_PORT_STS_PORTMODE_PHY_100_HALF:
 606                         state->speed = SPEED_100;
 607                         state->duplex = DUPLEX_HALF;
 608                         break;
 609                 case MV88E6250_PORT_STS_PORTMODE_PHY_10_FULL:
 610                         state->speed = SPEED_10;
 611                         state->duplex = DUPLEX_FULL;
 612                         break;
 613                 case MV88E6250_PORT_STS_PORTMODE_PHY_100_FULL:
 614                         state->speed = SPEED_100;
 615                         state->duplex = DUPLEX_FULL;
 616                         break;
 617                 default:
 618                         state->speed = SPEED_UNKNOWN;
 619                         state->duplex = DUPLEX_UNKNOWN;
 620                         break;
 621                 }
 622         } else {
 623                 switch (reg & MV88E6250_PORT_STS_PORTMODE_MASK) {
 624                 case MV88E6250_PORT_STS_PORTMODE_MII_10_HALF:
 625                         state->speed = SPEED_10;
 626                         state->duplex = DUPLEX_HALF;
 627                         break;
 628                 case MV88E6250_PORT_STS_PORTMODE_MII_100_HALF:
 629                         state->speed = SPEED_100;
 630                         state->duplex = DUPLEX_HALF;
 631                         break;
 632                 case MV88E6250_PORT_STS_PORTMODE_MII_10_FULL:
 633                         state->speed = SPEED_10;
 634                         state->duplex = DUPLEX_FULL;
 635                         break;
 636                 case MV88E6250_PORT_STS_PORTMODE_MII_100_FULL:
 637                         state->speed = SPEED_100;
 638                         state->duplex = DUPLEX_FULL;
 639                         break;
 640                 default:
 641                         state->speed = SPEED_UNKNOWN;
 642                         state->duplex = DUPLEX_UNKNOWN;
 643                         break;
 644                 }
 645         }
 646
 647         state->link = !!(reg & MV88E6250_PORT_STS_LINK);
 648         state->an_enabled = 1;
 649         state->an_complete = state->link;
 650         state->interface = PHY_INTERFACE_MODE_NA;
 651
 652         return 0;
 653 }
 654
 655 int mv88e6352_port_link_state(struct mv88e6xxx_chip *chip, int port,
 656                               struct phylink_link_state *state)
 657 {
 658         int err;
 659         u16 reg;
 660
 661         switch (chip->ports[port].cmode) {
 662         case MV88E6XXX_PORT_STS_CMODE_RGMII:
 663                 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL,
 664                                           &reg);
 665                 if (err)
 666                         return err;
 667
 668                 if ((reg & MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK) &&
 669                     (reg & MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK))
 670                         state->interface = PHY_INTERFACE_MODE_RGMII_ID;
 671                 else if (reg & MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK)
 672                         state->interface = PHY_INTERFACE_MODE_RGMII_RXID;
 673                 else if (reg & MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK)
 674                         state->interface = PHY_INTERFACE_MODE_RGMII_TXID;
 675                 else
 676                         state->interface = PHY_INTERFACE_MODE_RGMII;
 677                 break;
 678         case MV88E6XXX_PORT_STS_CMODE_1000BASEX:
 679                 state->interface = PHY_INTERFACE_MODE_1000BASEX;
 680                 break;
 681         case MV88E6XXX_PORT_STS_CMODE_SGMII:
 682                 state->interface = PHY_INTERFACE_MODE_SGMII;
 683                 break;
 684         case MV88E6XXX_PORT_STS_CMODE_2500BASEX:
 685                 state->interface = PHY_INTERFACE_MODE_2500BASEX;
 686                 break;
 687         case MV88E6XXX_PORT_STS_CMODE_XAUI:
 688                 state->interface = PHY_INTERFACE_MODE_XAUI;
 689                 break;
 690         case MV88E6XXX_PORT_STS_CMODE_RXAUI:
 691                 state->interface = PHY_INTERFACE_MODE_RXAUI;
 692                 break;
 693         default:
 694                 /* we do not support other cmode values here */
 695                 state->interface = PHY_INTERFACE_MODE_NA;
 696         }
 697
 698         err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, &reg);
 699         if (err)
 700                 return err;
 701
 702         switch (reg & MV88E6XXX_PORT_STS_SPEED_MASK) {
 703         case MV88E6XXX_PORT_STS_SPEED_10:
 704                 state->speed = SPEED_10;
 705                 break;
 706         case MV88E6XXX_PORT_STS_SPEED_100:
 707                 state->speed = SPEED_100;
 708                 break;
 709         case MV88E6XXX_PORT_STS_SPEED_1000:
 710                 state->speed = SPEED_1000;
 711                 break;
 712         case MV88E6XXX_PORT_STS_SPEED_10000:
 713                 if ((reg & MV88E6XXX_PORT_STS_CMODE_MASK) ==
 714                     MV88E6XXX_PORT_STS_CMODE_2500BASEX)
 715                         state->speed = SPEED_2500;
 716                 else
 717                         state->speed = SPEED_10000;
 718                 break;
 719         }
 720
 721         state->duplex = reg & MV88E6XXX_PORT_STS_DUPLEX ?
 722                         DUPLEX_FULL : DUPLEX_HALF;
 723         state->link = !!(reg & MV88E6XXX_PORT_STS_LINK);
 724         state->an_enabled = 1;
 725         state->an_complete = state->link;
 726
 727         return 0;
 728 }
 729
 730 int mv88e6185_port_link_state(struct mv88e6xxx_chip *chip, int port,
 731                               struct phylink_link_state *state)
 732 {
 733         if (state->interface == PHY_INTERFACE_MODE_1000BASEX) {
 734                 u8 cmode = chip->ports[port].cmode;
 735
 736                 /* When a port is in "Cross-chip serdes" mode, it uses
 737                  * 1000Base-X full duplex mode, but there is no automatic
 738                  * link detection. Use the sync OK status for link (as it
 739                  * would do for 1000Base-X mode.)
 740                  */
 741                 if (cmode == MV88E6185_PORT_STS_CMODE_SERDES) {
 742                         u16 mac;
 743                         int err;
 744
 745                         err = mv88e6xxx_port_read(chip, port,
 746                                                   MV88E6XXX_PORT_MAC_CTL, &mac);
 747                         if (err)
 748                                 return err;
 749
 750                         state->link = !!(mac & MV88E6185_PORT_MAC_CTL_SYNC_OK);
 751                         state->an_enabled = 1;
 752                         state->an_complete =
 753                                 !!(mac & MV88E6185_PORT_MAC_CTL_AN_DONE);
 754                         state->duplex =
 755                                 state->link ? DUPLEX_FULL : DUPLEX_UNKNOWN;
 756                         state->speed =
 757                                 state->link ? SPEED_1000 : SPEED_UNKNOWN;
 758
 759                         return 0;
 760                 }
 761         }
 762
 763         return mv88e6352_port_link_state(chip, port, state);
 764 }
 765
 766 /* Offset 0x02: Jamming Control
 767  *
 768  * Do not limit the period of time that this port can be paused for by
 769  * the remote end or the period of time that this port can pause the
 770  * remote end.
 771  */
 772 int mv88e6097_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in,
 773                                u8 out)
 774 {
 775         return mv88e6xxx_port_write(chip, port, MV88E6097_PORT_JAM_CTL,
 776                                     out << 8 | in);
 777 }
 778
 779 int mv88e6390_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in,
 780                                u8 out)
 781 {
 782         int err;
 783
 784         err = mv88e6xxx_port_write(chip, port, MV88E6390_PORT_FLOW_CTL,
 785                                    MV88E6390_PORT_FLOW_CTL_UPDATE |
 786                                    MV88E6390_PORT_FLOW_CTL_LIMIT_IN | in);
 787         if (err)
 788                 return err;
 789
 790         return mv88e6xxx_port_write(chip, port, MV88E6390_PORT_FLOW_CTL,
 791                                     MV88E6390_PORT_FLOW_CTL_UPDATE |
 792                                     MV88E6390_PORT_FLOW_CTL_LIMIT_OUT | out);
 793 }
 794
 795 /* Offset 0x04: Port Control Register */
 796
 797 static const char * const mv88e6xxx_port_state_names[] = {
 798         [MV88E6XXX_PORT_CTL0_STATE_DISABLED] = "Disabled",
 799         [MV88E6XXX_PORT_CTL0_STATE_BLOCKING] = "Blocking/Listening",
 800         [MV88E6XXX_PORT_CTL0_STATE_LEARNING] = "Learning",
 801         [MV88E6XXX_PORT_CTL0_STATE_FORWARDING] = "Forwarding",
 802 };
 803
 804 int mv88e6xxx_port_set_state(struct mv88e6xxx_chip *chip, int port, u8 state)
 805 {
 806         u16 reg;
 807         int err;
 808
 809         err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, &reg);
 810         if (err)
 811                 return err;
 812
 813         reg &= ~MV88E6XXX_PORT_CTL0_STATE_MASK;
 814
 815         switch (state) {
 816         case BR_STATE_DISABLED:
 817                 state = MV88E6XXX_PORT_CTL0_STATE_DISABLED;
 818                 break;
 819         case BR_STATE_BLOCKING:
 820         case BR_STATE_LISTENING:
 821                 state = MV88E6XXX_PORT_CTL0_STATE_BLOCKING;
 822                 break;
 823         case BR_STATE_LEARNING:
 824                 state = MV88E6XXX_PORT_CTL0_STATE_LEARNING;
 825                 break;
 826         case BR_STATE_FORWARDING:
 827                 state = MV88E6XXX_PORT_CTL0_STATE_FORWARDING;
 828                 break;
 829         default:
 830                 return -EINVAL;
 831         }
 832
 833         reg |= state;
 834
 835         err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
 836         if (err)
 837                 return err;
 838
 839         dev_dbg(chip->dev, "p%d: PortState set to %s\n", port,
 840                 mv88e6xxx_port_state_names[state]);
 841
 842         return 0;
 843 }
 844
 845 int mv88e6xxx_port_set_egress_mode(struct mv88e6xxx_chip *chip, int port,
 846                                    enum mv88e6xxx_egress_mode mode)
 847 {
 848         int err;
 849         u16 reg;
 850
 851         err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, &reg);
 852         if (err)
 853                 return err;
 854
 855         reg &= ~MV88E6XXX_PORT_CTL0_EGRESS_MODE_MASK;
 856
 857         switch (mode) {
 858         case MV88E6XXX_EGRESS_MODE_UNMODIFIED:
 859                 reg |= MV88E6XXX_PORT_CTL0_EGRESS_MODE_UNMODIFIED;
 860                 break;
 861         case MV88E6XXX_EGRESS_MODE_UNTAGGED:
 862                 reg |= MV88E6XXX_PORT_CTL0_EGRESS_MODE_UNTAGGED;
 863                 break;
 864         case MV88E6XXX_EGRESS_MODE_TAGGED:
 865                 reg |= MV88E6XXX_PORT_CTL0_EGRESS_MODE_TAGGED;
 866                 break;
 867         case MV88E6XXX_EGRESS_MODE_ETHERTYPE:
 868                 reg |= MV88E6XXX_PORT_CTL0_EGRESS_MODE_ETHER_TYPE_DSA;
 869                 break;
 870         default:
 871                 return -EINVAL;
 872         }
 873
 874         return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
 875 }
 876
 877 int mv88e6085_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port,
 878                                   enum mv88e6xxx_frame_mode mode)
 879 {
 880         int err;
 881         u16 reg;
 882
 883         err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, &reg);
 884         if (err)
 885                 return err;
 886
 887         reg &= ~MV88E6XXX_PORT_CTL0_FRAME_MODE_MASK;
 888
 889         switch (mode) {
 890         case MV88E6XXX_FRAME_MODE_NORMAL:
 891                 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_NORMAL;
 892                 break;
 893         case MV88E6XXX_FRAME_MODE_DSA:
 894                 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_DSA;
 895                 break;
 896         default:
 897                 return -EINVAL;
 898         }
 899
 900         return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
 901 }
 902
 903 int mv88e6351_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port,
 904                                   enum mv88e6xxx_frame_mode mode)
 905 {
 906         int err;
 907         u16 reg;
 908
 909         err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, &reg);
 910         if (err)
 911                 return err;
 912
 913         reg &= ~MV88E6XXX_PORT_CTL0_FRAME_MODE_MASK;
 914
 915         switch (mode) {
 916         case MV88E6XXX_FRAME_MODE_NORMAL:
 917                 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_NORMAL;
 918                 break;
 919         case MV88E6XXX_FRAME_MODE_DSA:
 920                 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_DSA;
 921                 break;
 922         case MV88E6XXX_FRAME_MODE_PROVIDER:
 923                 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_PROVIDER;
 924                 break;
 925         case MV88E6XXX_FRAME_MODE_ETHERTYPE:
 926                 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_ETHER_TYPE_DSA;
 927                 break;
 928         default:
 929                 return -EINVAL;
 930         }
 931
 932         return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
 933 }
 934
 935 static int mv88e6185_port_set_forward_unknown(struct mv88e6xxx_chip *chip,
 936                                               int port, bool unicast)
 937 {
 938         int err;
 939         u16 reg;
 940
 941         err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, &reg);
 942         if (err)
 943                 return err;
 944
 945         if (unicast)
 946                 reg |= MV88E6185_PORT_CTL0_FORWARD_UNKNOWN;
 947         else
 948                 reg &= ~MV88E6185_PORT_CTL0_FORWARD_UNKNOWN;
 949
 950         return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
 951 }
 952
 953 int mv88e6352_port_set_egress_floods(struct mv88e6xxx_chip *chip, int port,
 954                                      bool unicast, bool multicast)
 955 {
 956         int err;
 957         u16 reg;
 958
 959         err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, &reg);
 960         if (err)
 961                 return err;
 962
 963         reg &= ~MV88E6352_PORT_CTL0_EGRESS_FLOODS_MASK;
 964
 965         if (unicast && multicast)
 966                 reg |= MV88E6352_PORT_CTL0_EGRESS_FLOODS_ALL_UNKNOWN_DA;
 967         else if (unicast)
 968                 reg |= MV88E6352_PORT_CTL0_EGRESS_FLOODS_NO_UNKNOWN_MC_DA;
 969         else if (multicast)
 970                 reg |= MV88E6352_PORT_CTL0_EGRESS_FLOODS_NO_UNKNOWN_UC_DA;
 971         else
 972                 reg |= MV88E6352_PORT_CTL0_EGRESS_FLOODS_NO_UNKNOWN_DA;
 973
 974         return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
 975 }
 976
 977 /* Offset 0x05: Port Control 1 */
 978
 979 int mv88e6xxx_port_set_message_port(struct mv88e6xxx_chip *chip, int port,
 980                                     bool message_port)
 981 {
 982         u16 val;
 983         int err;
 984
 985         err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL1, &val);
 986         if (err)
 987                 return err;
 988
 989         if (message_port)
 990                 val |= MV88E6XXX_PORT_CTL1_MESSAGE_PORT;
 991         else
 992                 val &= ~MV88E6XXX_PORT_CTL1_MESSAGE_PORT;
 993
 994         return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL1, val);
 995 }
 996
 997 /* Offset 0x06: Port Based VLAN Map */
 998
 999 int mv88e6xxx_port_set_vlan_map(struct mv88e6xxx_chip *chip, int port, u16 map)
1000 {
1001         const u16 mask = mv88e6xxx_port_mask(chip);
1002         u16 reg;
1003         int err;
1004
1005         err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_BASE_VLAN, &reg);
1006         if (err)
1007                 return err;
1008
1009         reg &= ~mask;
1010         reg |= map & mask;
1011
1012         err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_BASE_VLAN, reg);
1013         if (err)
1014                 return err;
1015
1016         dev_dbg(chip->dev, "p%d: VLANTable set to %.3x\n", port, map);
1017
1018         return 0;
1019 }
1020
1021 int mv88e6xxx_port_get_fid(struct mv88e6xxx_chip *chip, int port, u16 *fid)
1022 {
1023         const u16 upper_mask = (mv88e6xxx_num_databases(chip) - 1) >> 4;
1024         u16 reg;
1025         int err;
1026
1027         /* Port's default FID lower 4 bits are located in reg 0x06, offset 12 */
1028         err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_BASE_VLAN, &reg);
1029         if (err)
1030                 return err;
1031
1032         *fid = (reg & 0xf000) >> 12;
1033
1034         /* Port's default FID upper bits are located in reg 0x05, offset 0 */
1035         if (upper_mask) {
1036                 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL1,
1037                                           &reg);
1038                 if (err)
1039                         return err;
1040
1041                 *fid |= (reg & upper_mask) << 4;
1042         }
1043
1044         return 0;
1045 }
1046
1047 int mv88e6xxx_port_set_fid(struct mv88e6xxx_chip *chip, int port, u16 fid)
1048 {
1049         const u16 upper_mask = (mv88e6xxx_num_databases(chip) - 1) >> 4;
1050         u16 reg;
1051         int err;
1052
1053         if (fid >= mv88e6xxx_num_databases(chip))
1054                 return -EINVAL;
1055
1056         /* Port's default FID lower 4 bits are located in reg 0x06, offset 12 */
1057         err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_BASE_VLAN, &reg);
1058         if (err)
1059                 return err;
1060
1061         reg &= 0x0fff;
1062         reg |= (fid & 0x000f) << 12;
1063
1064         err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_BASE_VLAN, reg);
1065         if (err)
1066                 return err;
1067
1068         /* Port's default FID upper bits are located in reg 0x05, offset 0 */
1069         if (upper_mask) {
1070                 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL1,
1071                                           &reg);
1072                 if (err)
1073                         return err;
1074
1075                 reg &= ~upper_mask;
1076                 reg |= (fid >> 4) & upper_mask;
1077
1078                 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL1,
1079                                            reg);
1080                 if (err)
1081                         return err;
1082         }
1083
1084         dev_dbg(chip->dev, "p%d: FID set to %u\n", port, fid);
1085
1086         return 0;
1087 }
1088
1089 /* Offset 0x07: Default Port VLAN ID & Priority */
1090
1091 int mv88e6xxx_port_get_pvid(struct mv88e6xxx_chip *chip, int port, u16 *pvid)
1092 {
1093         u16 reg;
1094         int err;
1095
1096         err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN,
1097                                   &reg);
1098         if (err)
1099                 return err;
1100
1101         *pvid = reg & MV88E6XXX_PORT_DEFAULT_VLAN_MASK;
1102
1103         return 0;
1104 }
1105
1106 int mv88e6xxx_port_set_pvid(struct mv88e6xxx_chip *chip, int port, u16 pvid)
1107 {
1108         u16 reg;
1109         int err;
1110
1111         err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN,
1112                                   &reg);
1113         if (err)
1114                 return err;
1115
1116         reg &= ~MV88E6XXX_PORT_DEFAULT_VLAN_MASK;
1117         reg |= pvid & MV88E6XXX_PORT_DEFAULT_VLAN_MASK;
1118
1119         err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN,
1120                                    reg);
1121         if (err)
1122                 return err;
1123
1124         dev_dbg(chip->dev, "p%d: DefaultVID set to %u\n", port, pvid);
1125
1126         return 0;
1127 }
1128
1129 /* Offset 0x08: Port Control 2 Register */
1130
1131 static const char * const mv88e6xxx_port_8021q_mode_names[] = {
1132         [MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED] = "Disabled",
1133         [MV88E6XXX_PORT_CTL2_8021Q_MODE_FALLBACK] = "Fallback",
1134         [MV88E6XXX_PORT_CTL2_8021Q_MODE_CHECK] = "Check",
1135         [MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE] = "Secure",
1136 };
1137
1138 static int mv88e6185_port_set_default_forward(struct mv88e6xxx_chip *chip,
1139                                               int port, bool multicast)
1140 {
1141         int err;
1142         u16 reg;
1143
1144         err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, &reg);
1145         if (err)
1146                 return err;
1147
1148         if (multicast)
1149                 reg |= MV88E6XXX_PORT_CTL2_DEFAULT_FORWARD;
1150         else
1151                 reg &= ~MV88E6XXX_PORT_CTL2_DEFAULT_FORWARD;
1152
1153         return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg);
1154 }
1155
1156 int mv88e6185_port_set_egress_floods(struct mv88e6xxx_chip *chip, int port,
1157                                      bool unicast, bool multicast)
1158 {
1159         int err;
1160
1161         err = mv88e6185_port_set_forward_unknown(chip, port, unicast);
1162         if (err)
1163                 return err;
1164
1165         return mv88e6185_port_set_default_forward(chip, port, multicast);
1166 }
1167
1168 int mv88e6095_port_set_upstream_port(struct mv88e6xxx_chip *chip, int port,
1169                                      int upstream_port)
1170 {
1171         int err;
1172         u16 reg;
1173
1174         err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, &reg);
1175         if (err)
1176                 return err;
1177
1178         reg &= ~MV88E6095_PORT_CTL2_CPU_PORT_MASK;
1179         reg |= upstream_port;
1180
1181         return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg);
1182 }
1183
1184 int mv88e6xxx_port_set_mirror(struct mv88e6xxx_chip *chip, int port,
1185                               enum mv88e6xxx_egress_direction direction,
1186                               bool mirror)
1187 {
1188         bool *mirror_port;
1189         u16 reg;
1190         u16 bit;
1191         int err;
1192
1193         err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, &reg);
1194         if (err)
1195                 return err;
1196
1197         switch (direction) {
1198         case MV88E6XXX_EGRESS_DIR_INGRESS:
1199                 bit = MV88E6XXX_PORT_CTL2_INGRESS_MONITOR;
1200                 mirror_port = &chip->ports[port].mirror_ingress;
1201                 break;
1202         case MV88E6XXX_EGRESS_DIR_EGRESS:
1203                 bit = MV88E6XXX_PORT_CTL2_EGRESS_MONITOR;
1204                 mirror_port = &chip->ports[port].mirror_egress;
1205                 break;
1206         default:
1207                 return -EINVAL;
1208         }
1209
1210         reg &= ~bit;
1211         if (mirror)
1212                 reg |= bit;
1213
1214         err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg);
1215         if (!err)
1216                 *mirror_port = mirror;
1217
1218         return err;
1219 }
1220
1221 int mv88e6xxx_port_set_8021q_mode(struct mv88e6xxx_chip *chip, int port,
1222                                   u16 mode)
1223 {
1224         u16 reg;
1225         int err;
1226
1227         err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, &reg);
1228         if (err)
1229                 return err;
1230
1231         reg &= ~MV88E6XXX_PORT_CTL2_8021Q_MODE_MASK;
1232         reg |= mode & MV88E6XXX_PORT_CTL2_8021Q_MODE_MASK;
1233
1234         err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg);
1235         if (err)
1236                 return err;
1237
1238         dev_dbg(chip->dev, "p%d: 802.1QMode set to %s\n", port,
1239                 mv88e6xxx_port_8021q_mode_names[mode]);
1240
1241         return 0;
1242 }
1243
1244 int mv88e6xxx_port_set_map_da(struct mv88e6xxx_chip *chip, int port)
1245 {
1246         u16 reg;
1247         int err;
1248
1249         err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, &reg);
1250         if (err)
1251                 return err;
1252
1253         reg |= MV88E6XXX_PORT_CTL2_MAP_DA;
1254
1255         return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg);
1256 }
1257
1258 int mv88e6165_port_set_jumbo_size(struct mv88e6xxx_chip *chip, int port,
1259                                   size_t size)
1260 {
1261         u16 reg;
1262         int err;
1263
1264         err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, &reg);
1265         if (err)
1266                 return err;
1267
1268         reg &= ~MV88E6XXX_PORT_CTL2_JUMBO_MODE_MASK;
1269
1270         if (size <= 1522)
1271                 reg |= MV88E6XXX_PORT_CTL2_JUMBO_MODE_1522;
1272         else if (size <= 2048)
1273                 reg |= MV88E6XXX_PORT_CTL2_JUMBO_MODE_2048;
1274         else if (size <= 10240)
1275                 reg |= MV88E6XXX_PORT_CTL2_JUMBO_MODE_10240;
1276         else
1277                 return -ERANGE;
1278
1279         return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg);
1280 }
1281
1282 /* Offset 0x09: Port Rate Control */
1283
1284 int mv88e6095_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port)
1285 {
1286         return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL1,
1287                                     0x0000);
1288 }
1289
1290 int mv88e6097_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port)
1291 {
1292         return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL1,
1293                                     0x0001);
1294 }
1295
1296 /* Offset 0x0C: Port ATU Control */
1297
1298 int mv88e6xxx_port_disable_learn_limit(struct mv88e6xxx_chip *chip, int port)
1299 {
1300         return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ATU_CTL, 0);
1301 }
1302
1303 /* Offset 0x0D: (Priority) Override Register */
1304
1305 int mv88e6xxx_port_disable_pri_override(struct mv88e6xxx_chip *chip, int port)
1306 {
1307         return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_PRI_OVERRIDE, 0);
1308 }
1309
1310 /* Offset 0x0f: Port Ether type */
1311
1312 int mv88e6351_port_set_ether_type(struct mv88e6xxx_chip *chip, int port,
1313                                   u16 etype)
1314 {
1315         return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ETH_TYPE, etype);
1316 }
1317
1318 /* Offset 0x18: Port IEEE Priority Remapping Registers [0-3]
1319  * Offset 0x19: Port IEEE Priority Remapping Registers [4-7]
1320  */
1321
1322 int mv88e6095_port_tag_remap(struct mv88e6xxx_chip *chip, int port)
1323 {
1324         int err;
1325
1326         /* Use a direct priority mapping for all IEEE tagged frames */
1327         err = mv88e6xxx_port_write(chip, port,
1328                                    MV88E6095_PORT_IEEE_PRIO_REMAP_0123,
1329                                    0x3210);
1330         if (err)
1331                 return err;
1332
1333         return mv88e6xxx_port_write(chip, port,
1334                                     MV88E6095_PORT_IEEE_PRIO_REMAP_4567,
1335                                     0x7654);
1336 }
1337
1338 static int mv88e6xxx_port_ieeepmt_write(struct mv88e6xxx_chip *chip,
1339                                         int port, u16 table, u8 ptr, u16 data)
1340 {
1341         u16 reg;
1342
1343         reg = MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_UPDATE | table |
1344                 (ptr << __bf_shf(MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_PTR_MASK)) |
1345                 (data & MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_DATA_MASK);
1346
1347         return mv88e6xxx_port_write(chip, port,
1348                                     MV88E6390_PORT_IEEE_PRIO_MAP_TABLE, reg);
1349 }
1350
1351 int mv88e6390_port_tag_remap(struct mv88e6xxx_chip *chip, int port)
1352 {
1353         int err, i;
1354         u16 table;
1355
1356         for (i = 0; i <= 7; i++) {
1357                 table = MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_INGRESS_PCP;
1358                 err = mv88e6xxx_port_ieeepmt_write(chip, port, table, i,
1359                                                    (i | i << 4));
1360                 if (err)
1361                         return err;
1362
1363                 table = MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_GREEN_PCP;
1364                 err = mv88e6xxx_port_ieeepmt_write(chip, port, table, i, i);
1365                 if (err)
1366                         return err;
1367
1368                 table = MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_YELLOW_PCP;
1369                 err = mv88e6xxx_port_ieeepmt_write(chip, port, table, i, i);
1370                 if (err)
1371                         return err;
1372
1373                 table = MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_AVB_PCP;
1374                 err = mv88e6xxx_port_ieeepmt_write(chip, port, table, i, i);
1375                 if (err)
1376                         return err;
1377         }
1378
1379         return 0;
1380 }
1381
1382 /* Offset 0x0E: Policy Control Register */
1383
1384 int mv88e6352_port_set_policy(struct mv88e6xxx_chip *chip, int port,
1385                               enum mv88e6xxx_policy_mapping mapping,
1386                               enum mv88e6xxx_policy_action action)
1387 {
1388         u16 reg, mask, val;
1389         int shift;
1390         int err;
1391
1392         switch (mapping) {
1393         case MV88E6XXX_POLICY_MAPPING_DA:
1394                 shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_DA_MASK);
1395                 mask = MV88E6XXX_PORT_POLICY_CTL_DA_MASK;
1396                 break;
1397         case MV88E6XXX_POLICY_MAPPING_SA:
1398                 shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_SA_MASK);
1399                 mask = MV88E6XXX_PORT_POLICY_CTL_SA_MASK;
1400                 break;
1401         case MV88E6XXX_POLICY_MAPPING_VTU:
1402                 shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_VTU_MASK);
1403                 mask = MV88E6XXX_PORT_POLICY_CTL_VTU_MASK;
1404                 break;
1405         case MV88E6XXX_POLICY_MAPPING_ETYPE:
1406                 shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_ETYPE_MASK);
1407                 mask = MV88E6XXX_PORT_POLICY_CTL_ETYPE_MASK;
1408                 break;
1409         case MV88E6XXX_POLICY_MAPPING_PPPOE:
1410                 shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_PPPOE_MASK);
1411                 mask = MV88E6XXX_PORT_POLICY_CTL_PPPOE_MASK;
1412                 break;
1413         case MV88E6XXX_POLICY_MAPPING_VBAS:
1414                 shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_VBAS_MASK);
1415                 mask = MV88E6XXX_PORT_POLICY_CTL_VBAS_MASK;
1416                 break;
1417         case MV88E6XXX_POLICY_MAPPING_OPT82:
1418                 shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_OPT82_MASK);
1419                 mask = MV88E6XXX_PORT_POLICY_CTL_OPT82_MASK;
1420                 break;
1421         case MV88E6XXX_POLICY_MAPPING_UDP:
1422                 shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_UDP_MASK);
1423                 mask = MV88E6XXX_PORT_POLICY_CTL_UDP_MASK;
1424                 break;
1425         default:
1426                 return -EOPNOTSUPP;
1427         }
1428
1429         switch (action) {
1430         case MV88E6XXX_POLICY_ACTION_NORMAL:
1431                 val = MV88E6XXX_PORT_POLICY_CTL_NORMAL;
1432                 break;
1433         case MV88E6XXX_POLICY_ACTION_MIRROR:
1434                 val = MV88E6XXX_PORT_POLICY_CTL_MIRROR;
1435                 break;
1436         case MV88E6XXX_POLICY_ACTION_TRAP:
1437                 val = MV88E6XXX_PORT_POLICY_CTL_TRAP;
1438                 break;
1439         case MV88E6XXX_POLICY_ACTION_DISCARD:
1440                 val = MV88E6XXX_PORT_POLICY_CTL_DISCARD;
1441                 break;
1442         default:
1443                 return -EOPNOTSUPP;
1444         }
1445
1446         err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_POLICY_CTL, &reg);
1447         if (err)
1448                 return err;
1449
1450         reg &= ~mask;
1451         reg |= (val << shift) & mask;
1452
1453         return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_POLICY_CTL, reg);
1454 }