drivers/net/dsa/qca8k.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * Copyright (C) 2009 Felix Fietkau <nbd@nbd.name>
   4  * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
   5  * Copyright (c) 2015, The Linux Foundation. All rights reserved.
   6  */
   7
   8 #ifndef __QCA8K_H
   9 #define __QCA8K_H
  10
  11 #include <linux/delay.h>
  12 #include <linux/regmap.h>
  13 #include <linux/gpio.h>
  14
  15 #define QCA8K_NUM_PORTS                                 7
  16
  17 #define PHY_ID_QCA8337                                  0x004dd036
  18 #define QCA8K_ID_QCA8337                                0x13
  19
  20 #define QCA8K_NUM_FDB_RECORDS                           2048
  21
  22 #define QCA8K_CPU_PORT                                  0
  23
  24 /* Global control registers */
  25 #define QCA8K_REG_MASK_CTRL                             0x000
  26 #define   QCA8K_MASK_CTRL_ID_M                          0xff
  27 #define   QCA8K_MASK_CTRL_ID_S                          8
  28 #define QCA8K_REG_PORT0_PAD_CTRL                        0x004
  29 #define QCA8K_REG_PORT5_PAD_CTRL                        0x008
  30 #define QCA8K_REG_PORT6_PAD_CTRL                        0x00c
  31 #define   QCA8K_PORT_PAD_RGMII_EN                       BIT(26)
  32 #define   QCA8K_PORT_PAD_RGMII_TX_DELAY(x)              \
  33                                                 ((0x8 + (x & 0x3)) << 22)
  34 #define   QCA8K_PORT_PAD_RGMII_RX_DELAY(x)              \
  35                                                 ((0x10 + (x & 0x3)) << 20)
  36 #define   QCA8K_MAX_DELAY                               3
  37 #define   QCA8K_PORT_PAD_RGMII_RX_DELAY_EN              BIT(24)
  38 #define   QCA8K_PORT_PAD_SGMII_EN                       BIT(7)
  39 #define QCA8K_REG_MODULE_EN                             0x030
  40 #define   QCA8K_MODULE_EN_MIB                           BIT(0)
  41 #define QCA8K_REG_MIB                                   0x034
  42 #define   QCA8K_MIB_FLUSH                               BIT(24)
  43 #define   QCA8K_MIB_CPU_KEEP                            BIT(20)
  44 #define   QCA8K_MIB_BUSY                                BIT(17)
  45 #define QCA8K_MDIO_MASTER_CTRL                          0x3c
  46 #define   QCA8K_MDIO_MASTER_BUSY                        BIT(31)
  47 #define   QCA8K_MDIO_MASTER_EN                          BIT(30)
  48 #define   QCA8K_MDIO_MASTER_READ                        BIT(27)
  49 #define   QCA8K_MDIO_MASTER_WRITE                       0
  50 #define   QCA8K_MDIO_MASTER_SUP_PRE                     BIT(26)
  51 #define   QCA8K_MDIO_MASTER_PHY_ADDR(x)                 ((x) << 21)
  52 #define   QCA8K_MDIO_MASTER_REG_ADDR(x)                 ((x) << 16)
  53 #define   QCA8K_MDIO_MASTER_DATA(x)                     (x)
  54 #define   QCA8K_MDIO_MASTER_DATA_MASK                   GENMASK(15, 0)
  55 #define   QCA8K_MDIO_MASTER_MAX_PORTS                   5
  56 #define   QCA8K_MDIO_MASTER_MAX_REG                     32
  57 #define QCA8K_GOL_MAC_ADDR0                             0x60
  58 #define QCA8K_GOL_MAC_ADDR1                             0x64
  59 #define QCA8K_REG_PORT_STATUS(_i)                       (0x07c + (_i) * 4)
  60 #define   QCA8K_PORT_STATUS_SPEED                       GENMASK(1, 0)
  61 #define   QCA8K_PORT_STATUS_SPEED_10                    0
  62 #define   QCA8K_PORT_STATUS_SPEED_100                   0x1
  63 #define   QCA8K_PORT_STATUS_SPEED_1000                  0x2
  64 #define   QCA8K_PORT_STATUS_TXMAC                       BIT(2)
  65 #define   QCA8K_PORT_STATUS_RXMAC                       BIT(3)
  66 #define   QCA8K_PORT_STATUS_TXFLOW                      BIT(4)
  67 #define   QCA8K_PORT_STATUS_RXFLOW                      BIT(5)
  68 #define   QCA8K_PORT_STATUS_DUPLEX                      BIT(6)
  69 #define   QCA8K_PORT_STATUS_LINK_UP                     BIT(8)
  70 #define   QCA8K_PORT_STATUS_LINK_AUTO                   BIT(9)
  71 #define   QCA8K_PORT_STATUS_LINK_PAUSE                  BIT(10)
  72 #define QCA8K_REG_PORT_HDR_CTRL(_i)                     (0x9c + (_i * 4))
  73 #define   QCA8K_PORT_HDR_CTRL_RX_MASK                   GENMASK(3, 2)
  74 #define   QCA8K_PORT_HDR_CTRL_RX_S                      2
  75 #define   QCA8K_PORT_HDR_CTRL_TX_MASK                   GENMASK(1, 0)
  76 #define   QCA8K_PORT_HDR_CTRL_TX_S                      0
  77 #define   QCA8K_PORT_HDR_CTRL_ALL                       2
  78 #define   QCA8K_PORT_HDR_CTRL_MGMT                      1
  79 #define   QCA8K_PORT_HDR_CTRL_NONE                      0
  80
  81 /* EEE control registers */
  82 #define QCA8K_REG_EEE_CTRL                              0x100
  83 #define  QCA8K_REG_EEE_CTRL_LPI_EN(_i)                  ((_i + 1) * 2)
  84
  85 /* ACL registers */
  86 #define QCA8K_REG_PORT_VLAN_CTRL0(_i)                   (0x420 + (_i * 8))
  87 #define   QCA8K_PORT_VLAN_CVID(x)                       (x << 16)
  88 #define   QCA8K_PORT_VLAN_SVID(x)                       x
  89 #define QCA8K_REG_PORT_VLAN_CTRL1(_i)                   (0x424 + (_i * 8))
  90 #define QCA8K_REG_IPV4_PRI_BASE_ADDR                    0x470
  91 #define QCA8K_REG_IPV4_PRI_ADDR_MASK                    0x474
  92
  93 /* Lookup registers */
  94 #define QCA8K_REG_ATU_DATA0                             0x600
  95 #define   QCA8K_ATU_ADDR2_S                             24
  96 #define   QCA8K_ATU_ADDR3_S                             16
  97 #define   QCA8K_ATU_ADDR4_S                             8
  98 #define QCA8K_REG_ATU_DATA1                             0x604
  99 #define   QCA8K_ATU_PORT_M                              0x7f
 100 #define   QCA8K_ATU_PORT_S                              16
 101 #define   QCA8K_ATU_ADDR0_S                             8
 102 #define QCA8K_REG_ATU_DATA2                             0x608
 103 #define   QCA8K_ATU_VID_M                               0xfff
 104 #define   QCA8K_ATU_VID_S                               8
 105 #define   QCA8K_ATU_STATUS_M                            0xf
 106 #define   QCA8K_ATU_STATUS_STATIC                       0xf
 107 #define QCA8K_REG_ATU_FUNC                              0x60c
 108 #define   QCA8K_ATU_FUNC_BUSY                           BIT(31)
 109 #define   QCA8K_ATU_FUNC_PORT_EN                        BIT(14)
 110 #define   QCA8K_ATU_FUNC_MULTI_EN                       BIT(13)
 111 #define   QCA8K_ATU_FUNC_FULL                           BIT(12)
 112 #define   QCA8K_ATU_FUNC_PORT_M                         0xf
 113 #define   QCA8K_ATU_FUNC_PORT_S                         8
 114 #define QCA8K_REG_GLOBAL_FW_CTRL0                       0x620
 115 #define   QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN             BIT(10)
 116 #define QCA8K_REG_GLOBAL_FW_CTRL1                       0x624
 117 #define   QCA8K_GLOBAL_FW_CTRL1_IGMP_DP_S               24
 118 #define   QCA8K_GLOBAL_FW_CTRL1_BC_DP_S                 16
 119 #define   QCA8K_GLOBAL_FW_CTRL1_MC_DP_S                 8
 120 #define   QCA8K_GLOBAL_FW_CTRL1_UC_DP_S                 0
 121 #define QCA8K_PORT_LOOKUP_CTRL(_i)                      (0x660 + (_i) * 0xc)
 122 #define   QCA8K_PORT_LOOKUP_MEMBER                      GENMASK(6, 0)
 123 #define   QCA8K_PORT_LOOKUP_STATE_MASK                  GENMASK(18, 16)
 124 #define   QCA8K_PORT_LOOKUP_STATE_DISABLED              (0 << 16)
 125 #define   QCA8K_PORT_LOOKUP_STATE_BLOCKING              (1 << 16)
 126 #define   QCA8K_PORT_LOOKUP_STATE_LISTENING             (2 << 16)
 127 #define   QCA8K_PORT_LOOKUP_STATE_LEARNING              (3 << 16)
 128 #define   QCA8K_PORT_LOOKUP_STATE_FORWARD               (4 << 16)
 129 #define   QCA8K_PORT_LOOKUP_STATE                       GENMASK(18, 16)
 130 #define   QCA8K_PORT_LOOKUP_LEARN                       BIT(20)
 131
 132 /* Pkt edit registers */
 133 #define QCA8K_EGRESS_VLAN(x)                            (0x0c70 + (4 * (x / 2)))
 134
 135 /* L3 registers */
 136 #define QCA8K_HROUTER_CONTROL                           0xe00
 137 #define   QCA8K_HROUTER_CONTROL_GLB_LOCKTIME_M          GENMASK(17, 16)
 138 #define   QCA8K_HROUTER_CONTROL_GLB_LOCKTIME_S          16
 139 #define   QCA8K_HROUTER_CONTROL_ARP_AGE_MODE            1
 140 #define QCA8K_HROUTER_PBASED_CONTROL1                   0xe08
 141 #define QCA8K_HROUTER_PBASED_CONTROL2                   0xe0c
 142 #define QCA8K_HNAT_CONTROL                              0xe38
 143
 144 /* MIB registers */
 145 #define QCA8K_PORT_MIB_COUNTER(_i)                      (0x1000 + (_i) * 0x100)
 146
 147 /* QCA specific MII registers */
 148 #define MII_ATH_MMD_ADDR                                0x0d
 149 #define MII_ATH_MMD_DATA                                0x0e
 150
 151 enum {
 152         QCA8K_PORT_SPEED_10M = 0,
 153         QCA8K_PORT_SPEED_100M = 1,
 154         QCA8K_PORT_SPEED_1000M = 2,
 155         QCA8K_PORT_SPEED_ERR = 3,
 156 };
 157
 158 enum qca8k_fdb_cmd {
 159         QCA8K_FDB_FLUSH = 1,
 160         QCA8K_FDB_LOAD = 2,
 161         QCA8K_FDB_PURGE = 3,
 162         QCA8K_FDB_NEXT = 6,
 163         QCA8K_FDB_SEARCH = 7,
 164 };
 165
 166 struct ar8xxx_port_status {
 167         int enabled;
 168 };
 169
 170 struct qca8k_priv {
 171         struct regmap *regmap;
 172         struct mii_bus *bus;
 173         struct ar8xxx_port_status port_sts[QCA8K_NUM_PORTS];
 174         struct dsa_switch *ds;
 175         struct mutex reg_mutex;
 176         struct device *dev;
 177         struct dsa_switch_ops ops;
 178         struct gpio_desc *reset_gpio;
 179 };
 180
 181 struct qca8k_mib_desc {
 182         unsigned int size;
 183         unsigned int offset;
 184         const char *name;
 185 };
 186
 187 struct qca8k_fdb {
 188         u16 vid;
 189         u8 port_mask;
 190         u8 aging;
 191         u8 mac[6];
 192 };
 193
 194 #endif /* __QCA8K_H */