drivers/net/ethernet/amazon/ena/ena_netdev.h

   1 /*
   2  * Copyright 2015 Amazon.com, Inc. or its affiliates.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #ifndef ENA_H
  34 #define ENA_H
  35
  36 #include <linux/bitops.h>
  37 #include <linux/dim.h>
  38 #include <linux/etherdevice.h>
  39 #include <linux/if_vlan.h>
  40 #include <linux/inetdevice.h>
  41 #include <linux/interrupt.h>
  42 #include <linux/netdevice.h>
  43 #include <linux/skbuff.h>
  44
  45 #include "ena_com.h"
  46 #include "ena_eth_com.h"
  47
  48 #define DRV_MODULE_VER_MAJOR    2
  49 #define DRV_MODULE_VER_MINOR    1
  50 #define DRV_MODULE_VER_SUBMINOR 0
  51
  52 #define DRV_MODULE_NAME         "ena"
  53 #ifndef DRV_MODULE_VERSION
  54 #define DRV_MODULE_VERSION \
  55         __stringify(DRV_MODULE_VER_MAJOR) "."   \
  56         __stringify(DRV_MODULE_VER_MINOR) "."   \
  57         __stringify(DRV_MODULE_VER_SUBMINOR) "K"
  58 #endif
  59
  60 #define DEVICE_NAME     "Elastic Network Adapter (ENA)"
  61
  62 /* 1 for AENQ + ADMIN */
  63 #define ENA_ADMIN_MSIX_VEC              1
  64 #define ENA_MAX_MSIX_VEC(io_queues)     (ENA_ADMIN_MSIX_VEC + (io_queues))
  65
  66 /* The ENA buffer length fields is 16 bit long. So when PAGE_SIZE == 64kB the
  67  * driver passes 0.
  68  * Since the max packet size the ENA handles is ~9kB limit the buffer length to
  69  * 16kB.
  70  */
  71 #if PAGE_SIZE > SZ_16K
  72 #define ENA_PAGE_SIZE SZ_16K
  73 #else
  74 #define ENA_PAGE_SIZE PAGE_SIZE
  75 #endif
  76
  77 #define ENA_MIN_MSIX_VEC                2
  78
  79 #define ENA_REG_BAR                     0
  80 #define ENA_MEM_BAR                     2
  81 #define ENA_BAR_MASK (BIT(ENA_REG_BAR) | BIT(ENA_MEM_BAR))
  82
  83 #define ENA_DEFAULT_RING_SIZE   (1024)
  84 #define ENA_MIN_RING_SIZE       (256)
  85
  86 #define ENA_MIN_NUM_IO_QUEUES   (1)
  87
  88 #define ENA_TX_WAKEUP_THRESH            (MAX_SKB_FRAGS + 2)
  89 #define ENA_DEFAULT_RX_COPYBREAK        (256 - NET_IP_ALIGN)
  90
  91 /* limit the buffer size to 600 bytes to handle MTU changes from very
  92  * small to very large, in which case the number of buffers per packet
  93  * could exceed ENA_PKT_MAX_BUFS
  94  */
  95 #define ENA_DEFAULT_MIN_RX_BUFF_ALLOC_SIZE 600
  96
  97 #define ENA_MIN_MTU             128
  98
  99 #define ENA_NAME_MAX_LEN        20
 100 #define ENA_IRQNAME_SIZE        40
 101
 102 #define ENA_PKT_MAX_BUFS        19
 103
 104 #define ENA_RX_RSS_TABLE_LOG_SIZE  7
 105 #define ENA_RX_RSS_TABLE_SIZE   (1 << ENA_RX_RSS_TABLE_LOG_SIZE)
 106
 107 #define ENA_HASH_KEY_SIZE       40
 108
 109 /* The number of tx packet completions that will be handled each NAPI poll
 110  * cycle is ring_size / ENA_TX_POLL_BUDGET_DIVIDER.
 111  */
 112 #define ENA_TX_POLL_BUDGET_DIVIDER      4
 113
 114 /* Refill Rx queue when number of required descriptors is above
 115  * QUEUE_SIZE / ENA_RX_REFILL_THRESH_DIVIDER or ENA_RX_REFILL_THRESH_PACKET
 116  */
 117 #define ENA_RX_REFILL_THRESH_DIVIDER    8
 118 #define ENA_RX_REFILL_THRESH_PACKET     256
 119
 120 /* Number of queues to check for missing queues per timer service */
 121 #define ENA_MONITORED_TX_QUEUES 4
 122 /* Max timeout packets before device reset */
 123 #define MAX_NUM_OF_TIMEOUTED_PACKETS 128
 124
 125 #define ENA_TX_RING_IDX_NEXT(idx, ring_size) (((idx) + 1) & ((ring_size) - 1))
 126
 127 #define ENA_RX_RING_IDX_NEXT(idx, ring_size) (((idx) + 1) & ((ring_size) - 1))
 128 #define ENA_RX_RING_IDX_ADD(idx, n, ring_size) \
 129         (((idx) + (n)) & ((ring_size) - 1))
 130
 131 #define ENA_IO_TXQ_IDX(q)       (2 * (q))
 132 #define ENA_IO_RXQ_IDX(q)       (2 * (q) + 1)
 133
 134 #define ENA_MGMNT_IRQ_IDX               0
 135 #define ENA_IO_IRQ_FIRST_IDX            1
 136 #define ENA_IO_IRQ_IDX(q)               (ENA_IO_IRQ_FIRST_IDX + (q))
 137
 138 /* ENA device should send keep alive msg every 1 sec.
 139  * We wait for 6 sec just to be on the safe side.
 140  */
 141 #define ENA_DEVICE_KALIVE_TIMEOUT       (6 * HZ)
 142 #define ENA_MAX_NO_INTERRUPT_ITERATIONS 3
 143
 144 #define ENA_MMIO_DISABLE_REG_READ       BIT(0)
 145
 146 /* The max MTU size is configured to be the ethernet frame size without
 147  * the overhead of the ethernet header, which can have a VLAN header, and
 148  * a frame check sequence (FCS).
 149  * The buffer size we share with the device is defined to be ENA_PAGE_SIZE
 150  */
 151
 152 #define ENA_XDP_MAX_MTU (ENA_PAGE_SIZE - ETH_HLEN - ETH_FCS_LEN - \
 153                                 VLAN_HLEN - XDP_PACKET_HEADROOM)
 154
 155 #define ENA_IS_XDP_INDEX(adapter, index) (((index) >= (adapter)->xdp_first_ring) && \
 156         ((index) < (adapter)->xdp_first_ring + (adapter)->xdp_num_queues))
 157
 158 struct ena_irq {
 159         irq_handler_t handler;
 160         void *data;
 161         int cpu;
 162         u32 vector;
 163         cpumask_t affinity_hint_mask;
 164         char name[ENA_IRQNAME_SIZE];
 165 };
 166
 167 struct ena_napi {
 168         struct napi_struct napi ____cacheline_aligned;
 169         struct ena_ring *tx_ring;
 170         struct ena_ring *rx_ring;
 171         struct ena_ring *xdp_ring;
 172         bool first_interrupt;
 173         u32 qid;
 174         struct dim dim;
 175 };
 176
 177 struct ena_calc_queue_size_ctx {
 178         struct ena_com_dev_get_features_ctx *get_feat_ctx;
 179         struct ena_com_dev *ena_dev;
 180         struct pci_dev *pdev;
 181         u32 tx_queue_size;
 182         u32 rx_queue_size;
 183         u32 max_tx_queue_size;
 184         u32 max_rx_queue_size;
 185         u16 max_tx_sgl_size;
 186         u16 max_rx_sgl_size;
 187 };
 188
 189 struct ena_tx_buffer {
 190         struct sk_buff *skb;
 191         /* num of ena desc for this specific skb
 192          * (includes data desc and metadata desc)
 193          */
 194         u32 tx_descs;
 195         /* num of buffers used by this skb */
 196         u32 num_of_bufs;
 197
 198         /* XDP buffer structure which is used for sending packets in
 199          * the xdp queues
 200          */
 201         struct xdp_frame *xdpf;
 202         /* The rx page for the rx buffer that was received in rx and
 203          * re transmitted on xdp tx queues as a result of XDP_TX action.
 204          * We need to free the page once we finished cleaning the buffer in
 205          * clean_xdp_irq()
 206          */
 207         struct page *xdp_rx_page;
 208
 209         /* Indicate if bufs[0] map the linear data of the skb. */
 210         u8 map_linear_data;
 211
 212         /* Used for detect missing tx packets to limit the number of prints */
 213         u32 print_once;
 214         /* Save the last jiffies to detect missing tx packets
 215          *
 216          * sets to non zero value on ena_start_xmit and set to zero on
 217          * napi and timer_Service_routine.
 218          *
 219          * while this value is not protected by lock,
 220          * a given packet is not expected to be handled by ena_start_xmit
 221          * and by napi/timer_service at the same time.
 222          */
 223         unsigned long last_jiffies;
 224         struct ena_com_buf bufs[ENA_PKT_MAX_BUFS];
 225 } ____cacheline_aligned;
 226
 227 struct ena_rx_buffer {
 228         struct sk_buff *skb;
 229         struct page *page;
 230         u32 page_offset;
 231         struct ena_com_buf ena_buf;
 232 } ____cacheline_aligned;
 233
 234 struct ena_stats_tx {
 235         u64 cnt;
 236         u64 bytes;
 237         u64 queue_stop;
 238         u64 prepare_ctx_err;
 239         u64 queue_wakeup;
 240         u64 dma_mapping_err;
 241         u64 linearize;
 242         u64 linearize_failed;
 243         u64 napi_comp;
 244         u64 tx_poll;
 245         u64 doorbells;
 246         u64 bad_req_id;
 247         u64 llq_buffer_copy;
 248         u64 missed_tx;
 249 };
 250
 251 struct ena_stats_rx {
 252         u64 cnt;
 253         u64 bytes;
 254         u64 rx_copybreak_pkt;
 255         u64 csum_good;
 256         u64 refil_partial;
 257         u64 bad_csum;
 258         u64 page_alloc_fail;
 259         u64 skb_alloc_fail;
 260         u64 dma_mapping_err;
 261         u64 bad_desc_num;
 262         u64 bad_req_id;
 263         u64 empty_rx_ring;
 264         u64 csum_unchecked;
 265 };
 266
 267 struct ena_ring {
 268         /* Holds the empty requests for TX/RX
 269          * out of order completions
 270          */
 271         u16 *free_ids;
 272
 273         union {
 274                 struct ena_tx_buffer *tx_buffer_info;
 275                 struct ena_rx_buffer *rx_buffer_info;
 276         };
 277
 278         /* cache ptr to avoid using the adapter */
 279         struct device *dev;
 280         struct pci_dev *pdev;
 281         struct napi_struct *napi;
 282         struct net_device *netdev;
 283         struct ena_com_dev *ena_dev;
 284         struct ena_adapter *adapter;
 285         struct ena_com_io_cq *ena_com_io_cq;
 286         struct ena_com_io_sq *ena_com_io_sq;
 287         struct bpf_prog *xdp_bpf_prog;
 288         struct xdp_rxq_info xdp_rxq;
 289
 290         u16 next_to_use;
 291         u16 next_to_clean;
 292         u16 rx_copybreak;
 293         u16 rx_headroom;
 294         u16 qid;
 295         u16 mtu;
 296         u16 sgl_size;
 297
 298         /* The maximum header length the device can handle */
 299         u8 tx_max_header_size;
 300
 301         bool first_interrupt;
 302         u16 no_interrupt_event_cnt;
 303
 304         /* cpu for TPH */
 305         int cpu;
 306          /* number of tx/rx_buffer_info's entries */
 307         int ring_size;
 308
 309         enum ena_admin_placement_policy_type tx_mem_queue_type;
 310
 311         struct ena_com_rx_buf_info ena_bufs[ENA_PKT_MAX_BUFS];
 312         u32  smoothed_interval;
 313         u32  per_napi_packets;
 314         u16 non_empty_napi_events;
 315         struct u64_stats_sync syncp;
 316         union {
 317                 struct ena_stats_tx tx_stats;
 318                 struct ena_stats_rx rx_stats;
 319         };
 320
 321         u8 *push_buf_intermediate_buf;
 322         int empty_rx_queue;
 323 } ____cacheline_aligned;
 324
 325 struct ena_stats_dev {
 326         u64 tx_timeout;
 327         u64 suspend;
 328         u64 resume;
 329         u64 wd_expired;
 330         u64 interface_up;
 331         u64 interface_down;
 332         u64 admin_q_pause;
 333         u64 rx_drops;
 334 };
 335
 336 enum ena_flags_t {
 337         ENA_FLAG_DEVICE_RUNNING,
 338         ENA_FLAG_DEV_UP,
 339         ENA_FLAG_LINK_UP,
 340         ENA_FLAG_MSIX_ENABLED,
 341         ENA_FLAG_TRIGGER_RESET,
 342         ENA_FLAG_ONGOING_RESET
 343 };
 344
 345 /* adapter specific private data structure */
 346 struct ena_adapter {
 347         struct ena_com_dev *ena_dev;
 348         /* OS defined structs */
 349         struct net_device *netdev;
 350         struct pci_dev *pdev;
 351
 352         /* rx packets that shorter that this len will be copied to the skb
 353          * header
 354          */
 355         u32 rx_copybreak;
 356         u32 max_mtu;
 357
 358         u32 num_io_queues;
 359         u32 max_num_io_queues;
 360
 361         int msix_vecs;
 362
 363         u32 missing_tx_completion_threshold;
 364
 365         u32 requested_tx_ring_size;
 366         u32 requested_rx_ring_size;
 367
 368         u32 max_tx_ring_size;
 369         u32 max_rx_ring_size;
 370
 371         u32 msg_enable;
 372
 373         u16 max_tx_sgl_size;
 374         u16 max_rx_sgl_size;
 375
 376         u8 mac_addr[ETH_ALEN];
 377
 378         unsigned long keep_alive_timeout;
 379         unsigned long missing_tx_completion_to;
 380
 381         char name[ENA_NAME_MAX_LEN];
 382
 383         unsigned long flags;
 384         /* TX */
 385         struct ena_ring tx_ring[ENA_MAX_NUM_IO_QUEUES]
 386                 ____cacheline_aligned_in_smp;
 387
 388         /* RX */
 389         struct ena_ring rx_ring[ENA_MAX_NUM_IO_QUEUES]
 390                 ____cacheline_aligned_in_smp;
 391
 392         struct ena_napi ena_napi[ENA_MAX_NUM_IO_QUEUES];
 393
 394         struct ena_irq irq_tbl[ENA_MAX_MSIX_VEC(ENA_MAX_NUM_IO_QUEUES)];
 395
 396         /* timer service */
 397         struct work_struct reset_task;
 398         struct timer_list timer_service;
 399
 400         bool wd_state;
 401         bool dev_up_before_reset;
 402         unsigned long last_keep_alive_jiffies;
 403
 404         struct u64_stats_sync syncp;
 405         struct ena_stats_dev dev_stats;
 406
 407         /* last queue index that was checked for uncompleted tx packets */
 408         u32 last_monitored_tx_qid;
 409
 410         enum ena_regs_reset_reason_types reset_reason;
 411
 412         struct bpf_prog *xdp_bpf_prog;
 413         u32 xdp_first_ring;
 414         u32 xdp_num_queues;
 415 };
 416
 417 void ena_set_ethtool_ops(struct net_device *netdev);
 418
 419 void ena_dump_stats_to_dmesg(struct ena_adapter *adapter);
 420
 421 void ena_dump_stats_to_buf(struct ena_adapter *adapter, u8 *buf);
 422
 423 int ena_update_queue_sizes(struct ena_adapter *adapter,
 424                            u32 new_tx_size,
 425                            u32 new_rx_size);
 426
 427 int ena_update_queue_count(struct ena_adapter *adapter, u32 new_channel_count);
 428
 429 int ena_get_sset_count(struct net_device *netdev, int sset);
 430
 431 enum ena_xdp_errors_t {
 432         ENA_XDP_ALLOWED = 0,
 433         ENA_XDP_CURRENT_MTU_TOO_LARGE,
 434         ENA_XDP_NO_ENOUGH_QUEUES,
 435 };
 436
 437 static inline bool ena_xdp_queues_present(struct ena_adapter *adapter)
 438 {
 439         return adapter->xdp_first_ring != 0;
 440 }
 441
 442 static inline bool ena_xdp_present(struct ena_adapter *adapter)
 443 {
 444         return !!adapter->xdp_bpf_prog;
 445 }
 446
 447 static inline bool ena_xdp_present_ring(struct ena_ring *ring)
 448 {
 449         return !!ring->xdp_bpf_prog;
 450 }
 451
 452 static inline int ena_xdp_legal_queue_count(struct ena_adapter *adapter,
 453                                             u32 queues)
 454 {
 455         return 2 * queues <= adapter->max_num_io_queues;
 456 }
 457
 458 static inline enum ena_xdp_errors_t ena_xdp_allowed(struct ena_adapter *adapter)
 459 {
 460         enum ena_xdp_errors_t rc = ENA_XDP_ALLOWED;
 461
 462         if (adapter->netdev->mtu > ENA_XDP_MAX_MTU)
 463                 rc = ENA_XDP_CURRENT_MTU_TOO_LARGE;
 464         else if (!ena_xdp_legal_queue_count(adapter, adapter->num_io_queues))
 465                 rc = ENA_XDP_NO_ENOUGH_QUEUES;
 466
 467         return rc;
 468 }
 469
 470 #endif /* !(ENA_H) */