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treewide: remove redundant IS_ERR() before error code check
[linux/fpc-iii.git] / drivers / net / ethernet / brocade / bna / bfa_ioc.c
blobe17bfc87da908fbae4750df7bb7ff53957832461
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Linux network driver for QLogic BR-series Converged Network Adapter.
4 */
5 /*
6 * Copyright (c) 2005-2014 Brocade Communications Systems, Inc.
7 * Copyright (c) 2014-2015 QLogic Corporation
8 * All rights reserved
9 * www.qlogic.com
10 */
11
12 #include "bfa_ioc.h"
13 #include "bfi_reg.h"
14 #include "bfa_defs.h"
15
16 /* IOC local definitions */
17
18 /* Asic specific macros : see bfa_hw_cb.c and bfa_hw_ct.c for details. */
19
20 #define bfa_ioc_firmware_lock(__ioc) \
21 ((__ioc)->ioc_hwif->ioc_firmware_lock(__ioc))
22 #define bfa_ioc_firmware_unlock(__ioc) \
23 ((__ioc)->ioc_hwif->ioc_firmware_unlock(__ioc))
24 #define bfa_ioc_reg_init(__ioc) ((__ioc)->ioc_hwif->ioc_reg_init(__ioc))
25 #define bfa_ioc_map_port(__ioc) ((__ioc)->ioc_hwif->ioc_map_port(__ioc))
26 #define bfa_ioc_notify_fail(__ioc) \
27 ((__ioc)->ioc_hwif->ioc_notify_fail(__ioc))
28 #define bfa_ioc_sync_start(__ioc) \
29 ((__ioc)->ioc_hwif->ioc_sync_start(__ioc))
30 #define bfa_ioc_sync_join(__ioc) \
31 ((__ioc)->ioc_hwif->ioc_sync_join(__ioc))
32 #define bfa_ioc_sync_leave(__ioc) \
33 ((__ioc)->ioc_hwif->ioc_sync_leave(__ioc))
34 #define bfa_ioc_sync_ack(__ioc) \
35 ((__ioc)->ioc_hwif->ioc_sync_ack(__ioc))
36 #define bfa_ioc_sync_complete(__ioc) \
37 ((__ioc)->ioc_hwif->ioc_sync_complete(__ioc))
38 #define bfa_ioc_set_cur_ioc_fwstate(__ioc, __fwstate) \
39 ((__ioc)->ioc_hwif->ioc_set_fwstate(__ioc, __fwstate))
40 #define bfa_ioc_get_cur_ioc_fwstate(__ioc) \
41 ((__ioc)->ioc_hwif->ioc_get_fwstate(__ioc))
42 #define bfa_ioc_set_alt_ioc_fwstate(__ioc, __fwstate) \
43 ((__ioc)->ioc_hwif->ioc_set_alt_fwstate(__ioc, __fwstate))
44
45 static bool bfa_nw_auto_recover = true;
46
47 /*
48 * forward declarations
49 */
50 static void bfa_ioc_hw_sem_init(struct bfa_ioc *ioc);
51 static void bfa_ioc_hw_sem_get(struct bfa_ioc *ioc);
52 static void bfa_ioc_hw_sem_get_cancel(struct bfa_ioc *ioc);
53 static void bfa_ioc_hwinit(struct bfa_ioc *ioc, bool force);
54 static void bfa_ioc_poll_fwinit(struct bfa_ioc *ioc);
55 static void bfa_ioc_send_enable(struct bfa_ioc *ioc);
56 static void bfa_ioc_send_disable(struct bfa_ioc *ioc);
57 static void bfa_ioc_send_getattr(struct bfa_ioc *ioc);
58 static void bfa_ioc_hb_monitor(struct bfa_ioc *ioc);
59 static void bfa_ioc_hb_stop(struct bfa_ioc *ioc);
60 static void bfa_ioc_reset(struct bfa_ioc *ioc, bool force);
61 static void bfa_ioc_mbox_poll(struct bfa_ioc *ioc);
62 static void bfa_ioc_mbox_flush(struct bfa_ioc *ioc);
63 static void bfa_ioc_recover(struct bfa_ioc *ioc);
64 static void bfa_ioc_event_notify(struct bfa_ioc *, enum bfa_ioc_event);
65 static void bfa_ioc_disable_comp(struct bfa_ioc *ioc);
66 static void bfa_ioc_lpu_stop(struct bfa_ioc *ioc);
67 static void bfa_nw_ioc_debug_save_ftrc(struct bfa_ioc *ioc);
68 static void bfa_ioc_fail_notify(struct bfa_ioc *ioc);
69 static void bfa_ioc_pf_enabled(struct bfa_ioc *ioc);
70 static void bfa_ioc_pf_disabled(struct bfa_ioc *ioc);
71 static void bfa_ioc_pf_failed(struct bfa_ioc *ioc);
72 static void bfa_ioc_pf_hwfailed(struct bfa_ioc *ioc);
73 static void bfa_ioc_pf_fwmismatch(struct bfa_ioc *ioc);
74 static enum bfa_status bfa_ioc_boot(struct bfa_ioc *ioc,
75 enum bfi_fwboot_type boot_type, u32 boot_param);
76 static u32 bfa_ioc_smem_pgnum(struct bfa_ioc *ioc, u32 fmaddr);
77 static void bfa_ioc_get_adapter_serial_num(struct bfa_ioc *ioc,
78 char *serial_num);
79 static void bfa_ioc_get_adapter_fw_ver(struct bfa_ioc *ioc,
80 char *fw_ver);
81 static void bfa_ioc_get_pci_chip_rev(struct bfa_ioc *ioc,
82 char *chip_rev);
83 static void bfa_ioc_get_adapter_optrom_ver(struct bfa_ioc *ioc,
84 char *optrom_ver);
85 static void bfa_ioc_get_adapter_manufacturer(struct bfa_ioc *ioc,
86 char *manufacturer);
87 static void bfa_ioc_get_adapter_model(struct bfa_ioc *ioc, char *model);
88 static u64 bfa_ioc_get_pwwn(struct bfa_ioc *ioc);
89
90 /* IOC state machine definitions/declarations */
91 enum ioc_event {
92 IOC_E_RESET = 1, /*!< IOC reset request */
93 IOC_E_ENABLE = 2, /*!< IOC enable request */
94 IOC_E_DISABLE = 3, /*!< IOC disable request */
95 IOC_E_DETACH = 4, /*!< driver detach cleanup */
96 IOC_E_ENABLED = 5, /*!< f/w enabled */
97 IOC_E_FWRSP_GETATTR = 6, /*!< IOC get attribute response */
98 IOC_E_DISABLED = 7, /*!< f/w disabled */
99 IOC_E_PFFAILED = 8, /*!< failure notice by iocpf sm */
100 IOC_E_HBFAIL = 9, /*!< heartbeat failure */
101 IOC_E_HWERROR = 10, /*!< hardware error interrupt */
102 IOC_E_TIMEOUT = 11, /*!< timeout */
103 IOC_E_HWFAILED = 12, /*!< PCI mapping failure notice */
104 };
105
106 bfa_fsm_state_decl(bfa_ioc, uninit, struct bfa_ioc, enum ioc_event);
107 bfa_fsm_state_decl(bfa_ioc, reset, struct bfa_ioc, enum ioc_event);
108 bfa_fsm_state_decl(bfa_ioc, enabling, struct bfa_ioc, enum ioc_event);
109 bfa_fsm_state_decl(bfa_ioc, getattr, struct bfa_ioc, enum ioc_event);
110 bfa_fsm_state_decl(bfa_ioc, op, struct bfa_ioc, enum ioc_event);
111 bfa_fsm_state_decl(bfa_ioc, fail_retry, struct bfa_ioc, enum ioc_event);
112 bfa_fsm_state_decl(bfa_ioc, fail, struct bfa_ioc, enum ioc_event);
113 bfa_fsm_state_decl(bfa_ioc, disabling, struct bfa_ioc, enum ioc_event);
114 bfa_fsm_state_decl(bfa_ioc, disabled, struct bfa_ioc, enum ioc_event);
115 bfa_fsm_state_decl(bfa_ioc, hwfail, struct bfa_ioc, enum ioc_event);
116
117 static struct bfa_sm_table ioc_sm_table[] = {
118 {BFA_SM(bfa_ioc_sm_uninit), BFA_IOC_UNINIT},
119 {BFA_SM(bfa_ioc_sm_reset), BFA_IOC_RESET},
120 {BFA_SM(bfa_ioc_sm_enabling), BFA_IOC_ENABLING},
121 {BFA_SM(bfa_ioc_sm_getattr), BFA_IOC_GETATTR},
122 {BFA_SM(bfa_ioc_sm_op), BFA_IOC_OPERATIONAL},
123 {BFA_SM(bfa_ioc_sm_fail_retry), BFA_IOC_INITFAIL},
124 {BFA_SM(bfa_ioc_sm_fail), BFA_IOC_FAIL},
125 {BFA_SM(bfa_ioc_sm_disabling), BFA_IOC_DISABLING},
126 {BFA_SM(bfa_ioc_sm_disabled), BFA_IOC_DISABLED},
127 {BFA_SM(bfa_ioc_sm_hwfail), BFA_IOC_HWFAIL},
128 };
129
130 /*
131 * Forward declareations for iocpf state machine
132 */
133 static void bfa_iocpf_enable(struct bfa_ioc *ioc);
134 static void bfa_iocpf_disable(struct bfa_ioc *ioc);
135 static void bfa_iocpf_fail(struct bfa_ioc *ioc);
136 static void bfa_iocpf_initfail(struct bfa_ioc *ioc);
137 static void bfa_iocpf_getattrfail(struct bfa_ioc *ioc);
138 static void bfa_iocpf_stop(struct bfa_ioc *ioc);
139
140 /* IOCPF state machine events */
141 enum iocpf_event {
142 IOCPF_E_ENABLE = 1, /*!< IOCPF enable request */
143 IOCPF_E_DISABLE = 2, /*!< IOCPF disable request */
144 IOCPF_E_STOP = 3, /*!< stop on driver detach */
145 IOCPF_E_FWREADY = 4, /*!< f/w initialization done */
146 IOCPF_E_FWRSP_ENABLE = 5, /*!< enable f/w response */
147 IOCPF_E_FWRSP_DISABLE = 6, /*!< disable f/w response */
148 IOCPF_E_FAIL = 7, /*!< failure notice by ioc sm */
149 IOCPF_E_INITFAIL = 8, /*!< init fail notice by ioc sm */
150 IOCPF_E_GETATTRFAIL = 9, /*!< init fail notice by ioc sm */
151 IOCPF_E_SEMLOCKED = 10, /*!< h/w semaphore is locked */
152 IOCPF_E_TIMEOUT = 11, /*!< f/w response timeout */
153 IOCPF_E_SEM_ERROR = 12, /*!< h/w sem mapping error */
154 };
155
156 /* IOCPF states */
157 enum bfa_iocpf_state {
158 BFA_IOCPF_RESET = 1, /*!< IOC is in reset state */
159 BFA_IOCPF_SEMWAIT = 2, /*!< Waiting for IOC h/w semaphore */
160 BFA_IOCPF_HWINIT = 3, /*!< IOC h/w is being initialized */
161 BFA_IOCPF_READY = 4, /*!< IOCPF is initialized */
162 BFA_IOCPF_INITFAIL = 5, /*!< IOCPF failed */
163 BFA_IOCPF_FAIL = 6, /*!< IOCPF failed */
164 BFA_IOCPF_DISABLING = 7, /*!< IOCPF is being disabled */
165 BFA_IOCPF_DISABLED = 8, /*!< IOCPF is disabled */
166 BFA_IOCPF_FWMISMATCH = 9, /*!< IOC f/w different from drivers */
167 };
168
169 bfa_fsm_state_decl(bfa_iocpf, reset, struct bfa_iocpf, enum iocpf_event);
170 bfa_fsm_state_decl(bfa_iocpf, fwcheck, struct bfa_iocpf, enum iocpf_event);
171 bfa_fsm_state_decl(bfa_iocpf, mismatch, struct bfa_iocpf, enum iocpf_event);
172 bfa_fsm_state_decl(bfa_iocpf, semwait, struct bfa_iocpf, enum iocpf_event);
173 bfa_fsm_state_decl(bfa_iocpf, hwinit, struct bfa_iocpf, enum iocpf_event);
174 bfa_fsm_state_decl(bfa_iocpf, enabling, struct bfa_iocpf, enum iocpf_event);
175 bfa_fsm_state_decl(bfa_iocpf, ready, struct bfa_iocpf, enum iocpf_event);
176 bfa_fsm_state_decl(bfa_iocpf, initfail_sync, struct bfa_iocpf,
177 enum iocpf_event);
178 bfa_fsm_state_decl(bfa_iocpf, initfail, struct bfa_iocpf, enum iocpf_event);
179 bfa_fsm_state_decl(bfa_iocpf, fail_sync, struct bfa_iocpf, enum iocpf_event);
180 bfa_fsm_state_decl(bfa_iocpf, fail, struct bfa_iocpf, enum iocpf_event);
181 bfa_fsm_state_decl(bfa_iocpf, disabling, struct bfa_iocpf, enum iocpf_event);
182 bfa_fsm_state_decl(bfa_iocpf, disabling_sync, struct bfa_iocpf,
183 enum iocpf_event);
184 bfa_fsm_state_decl(bfa_iocpf, disabled, struct bfa_iocpf, enum iocpf_event);
185
186 static struct bfa_sm_table iocpf_sm_table[] = {
187 {BFA_SM(bfa_iocpf_sm_reset), BFA_IOCPF_RESET},
188 {BFA_SM(bfa_iocpf_sm_fwcheck), BFA_IOCPF_FWMISMATCH},
189 {BFA_SM(bfa_iocpf_sm_mismatch), BFA_IOCPF_FWMISMATCH},
190 {BFA_SM(bfa_iocpf_sm_semwait), BFA_IOCPF_SEMWAIT},
191 {BFA_SM(bfa_iocpf_sm_hwinit), BFA_IOCPF_HWINIT},
192 {BFA_SM(bfa_iocpf_sm_enabling), BFA_IOCPF_HWINIT},
193 {BFA_SM(bfa_iocpf_sm_ready), BFA_IOCPF_READY},
194 {BFA_SM(bfa_iocpf_sm_initfail_sync), BFA_IOCPF_INITFAIL},
195 {BFA_SM(bfa_iocpf_sm_initfail), BFA_IOCPF_INITFAIL},
196 {BFA_SM(bfa_iocpf_sm_fail_sync), BFA_IOCPF_FAIL},
197 {BFA_SM(bfa_iocpf_sm_fail), BFA_IOCPF_FAIL},
198 {BFA_SM(bfa_iocpf_sm_disabling), BFA_IOCPF_DISABLING},
199 {BFA_SM(bfa_iocpf_sm_disabling_sync), BFA_IOCPF_DISABLING},
200 {BFA_SM(bfa_iocpf_sm_disabled), BFA_IOCPF_DISABLED},
201 };
202
203 /* IOC State Machine */
204
205 /* Beginning state. IOC uninit state. */
206 static void
207 bfa_ioc_sm_uninit_entry(struct bfa_ioc *ioc)
208 {
209 }
210
211 /* IOC is in uninit state. */
212 static void
213 bfa_ioc_sm_uninit(struct bfa_ioc *ioc, enum ioc_event event)
214 {
215 switch (event) {
216 case IOC_E_RESET:
217 bfa_fsm_set_state(ioc, bfa_ioc_sm_reset);
218 break;
219
220 default:
221 bfa_sm_fault(event);
222 }
223 }
224
225 /* Reset entry actions -- initialize state machine */
226 static void
227 bfa_ioc_sm_reset_entry(struct bfa_ioc *ioc)
228 {
229 bfa_fsm_set_state(&ioc->iocpf, bfa_iocpf_sm_reset);
230 }
231
232 /* IOC is in reset state. */
233 static void
234 bfa_ioc_sm_reset(struct bfa_ioc *ioc, enum ioc_event event)
235 {
236 switch (event) {
237 case IOC_E_ENABLE:
238 bfa_fsm_set_state(ioc, bfa_ioc_sm_enabling);
239 break;
240
241 case IOC_E_DISABLE:
242 bfa_ioc_disable_comp(ioc);
243 break;
244
245 case IOC_E_DETACH:
246 bfa_fsm_set_state(ioc, bfa_ioc_sm_uninit);
247 break;
248
249 default:
250 bfa_sm_fault(event);
251 }
252 }
253
254 static void
255 bfa_ioc_sm_enabling_entry(struct bfa_ioc *ioc)
256 {
257 bfa_iocpf_enable(ioc);
258 }
259
260 /* Host IOC function is being enabled, awaiting response from firmware.
261 * Semaphore is acquired.
262 */
263 static void
264 bfa_ioc_sm_enabling(struct bfa_ioc *ioc, enum ioc_event event)
265 {
266 switch (event) {
267 case IOC_E_ENABLED:
268 bfa_fsm_set_state(ioc, bfa_ioc_sm_getattr);
269 break;
270
271 case IOC_E_PFFAILED:
272 /* !!! fall through !!! */
273 case IOC_E_HWERROR:
274 ioc->cbfn->enable_cbfn(ioc->bfa, BFA_STATUS_IOC_FAILURE);
275 bfa_fsm_set_state(ioc, bfa_ioc_sm_fail);
276 if (event != IOC_E_PFFAILED)
277 bfa_iocpf_initfail(ioc);
278 break;
279
280 case IOC_E_HWFAILED:
281 ioc->cbfn->enable_cbfn(ioc->bfa, BFA_STATUS_IOC_FAILURE);
282 bfa_fsm_set_state(ioc, bfa_ioc_sm_hwfail);
283 break;
284
285 case IOC_E_DISABLE:
286 bfa_fsm_set_state(ioc, bfa_ioc_sm_disabling);
287 break;
288
289 case IOC_E_DETACH:
290 bfa_fsm_set_state(ioc, bfa_ioc_sm_uninit);
291 bfa_iocpf_stop(ioc);
292 break;
293
294 case IOC_E_ENABLE:
295 break;
296
297 default:
298 bfa_sm_fault(event);
299 }
300 }
301
302 /* Semaphore should be acquired for version check. */
303 static void
304 bfa_ioc_sm_getattr_entry(struct bfa_ioc *ioc)
305 {
306 mod_timer(&ioc->ioc_timer, jiffies +
307 msecs_to_jiffies(BFA_IOC_TOV));
308 bfa_ioc_send_getattr(ioc);
309 }
310
311 /* IOC configuration in progress. Timer is active. */
312 static void
313 bfa_ioc_sm_getattr(struct bfa_ioc *ioc, enum ioc_event event)
314 {
315 switch (event) {
316 case IOC_E_FWRSP_GETATTR:
317 del_timer(&ioc->ioc_timer);
318 bfa_fsm_set_state(ioc, bfa_ioc_sm_op);
319 break;
320
321 case IOC_E_PFFAILED:
322 case IOC_E_HWERROR:
323 del_timer(&ioc->ioc_timer);
324 /* fall through */
325 case IOC_E_TIMEOUT:
326 ioc->cbfn->enable_cbfn(ioc->bfa, BFA_STATUS_IOC_FAILURE);
327 bfa_fsm_set_state(ioc, bfa_ioc_sm_fail);
328 if (event != IOC_E_PFFAILED)
329 bfa_iocpf_getattrfail(ioc);
330 break;
331
332 case IOC_E_DISABLE:
333 del_timer(&ioc->ioc_timer);
334 bfa_fsm_set_state(ioc, bfa_ioc_sm_disabling);
335 break;
336
337 case IOC_E_ENABLE:
338 break;
339
340 default:
341 bfa_sm_fault(event);
342 }
343 }
344
345 static void
346 bfa_ioc_sm_op_entry(struct bfa_ioc *ioc)
347 {
348 ioc->cbfn->enable_cbfn(ioc->bfa, BFA_STATUS_OK);
349 bfa_ioc_event_notify(ioc, BFA_IOC_E_ENABLED);
350 bfa_ioc_hb_monitor(ioc);
351 }
352
353 static void
354 bfa_ioc_sm_op(struct bfa_ioc *ioc, enum ioc_event event)
355 {
356 switch (event) {
357 case IOC_E_ENABLE:
358 break;
359
360 case IOC_E_DISABLE:
361 bfa_ioc_hb_stop(ioc);
362 bfa_fsm_set_state(ioc, bfa_ioc_sm_disabling);
363 break;
364
365 case IOC_E_PFFAILED:
366 case IOC_E_HWERROR:
367 bfa_ioc_hb_stop(ioc);
368 /* !!! fall through !!! */
369 case IOC_E_HBFAIL:
370 if (ioc->iocpf.auto_recover)
371 bfa_fsm_set_state(ioc, bfa_ioc_sm_fail_retry);
372 else
373 bfa_fsm_set_state(ioc, bfa_ioc_sm_fail);
374
375 bfa_ioc_fail_notify(ioc);
376
377 if (event != IOC_E_PFFAILED)
378 bfa_iocpf_fail(ioc);
379 break;
380
381 default:
382 bfa_sm_fault(event);
383 }
384 }
385
386 static void
387 bfa_ioc_sm_disabling_entry(struct bfa_ioc *ioc)
388 {
389 bfa_iocpf_disable(ioc);
390 }
391
392 /* IOC is being disabled */
393 static void
394 bfa_ioc_sm_disabling(struct bfa_ioc *ioc, enum ioc_event event)
395 {
396 switch (event) {
397 case IOC_E_DISABLED:
398 bfa_fsm_set_state(ioc, bfa_ioc_sm_disabled);
399 break;
400
401 case IOC_E_HWERROR:
402 /*
403 * No state change. Will move to disabled state
404 * after iocpf sm completes failure processing and
405 * moves to disabled state.
406 */
407 bfa_iocpf_fail(ioc);
408 break;
409
410 case IOC_E_HWFAILED:
411 bfa_fsm_set_state(ioc, bfa_ioc_sm_hwfail);
412 bfa_ioc_disable_comp(ioc);
413 break;
414
415 default:
416 bfa_sm_fault(event);
417 }
418 }
419
420 /* IOC disable completion entry. */
421 static void
422 bfa_ioc_sm_disabled_entry(struct bfa_ioc *ioc)
423 {
424 bfa_ioc_disable_comp(ioc);
425 }
426
427 static void
428 bfa_ioc_sm_disabled(struct bfa_ioc *ioc, enum ioc_event event)
429 {
430 switch (event) {
431 case IOC_E_ENABLE:
432 bfa_fsm_set_state(ioc, bfa_ioc_sm_enabling);
433 break;
434
435 case IOC_E_DISABLE:
436 ioc->cbfn->disable_cbfn(ioc->bfa);
437 break;
438
439 case IOC_E_DETACH:
440 bfa_fsm_set_state(ioc, bfa_ioc_sm_uninit);
441 bfa_iocpf_stop(ioc);
442 break;
443
444 default:
445 bfa_sm_fault(event);
446 }
447 }
448
449 static void
450 bfa_ioc_sm_fail_retry_entry(struct bfa_ioc *ioc)
451 {
452 }
453
454 /* Hardware initialization retry. */
455 static void
456 bfa_ioc_sm_fail_retry(struct bfa_ioc *ioc, enum ioc_event event)
457 {
458 switch (event) {
459 case IOC_E_ENABLED:
460 bfa_fsm_set_state(ioc, bfa_ioc_sm_getattr);
461 break;
462
463 case IOC_E_PFFAILED:
464 case IOC_E_HWERROR:
465 /**
466 * Initialization retry failed.
467 */
468 ioc->cbfn->enable_cbfn(ioc->bfa, BFA_STATUS_IOC_FAILURE);
469 bfa_fsm_set_state(ioc, bfa_ioc_sm_fail);
470 if (event != IOC_E_PFFAILED)
471 bfa_iocpf_initfail(ioc);
472 break;
473
474 case IOC_E_HWFAILED:
475 ioc->cbfn->enable_cbfn(ioc->bfa, BFA_STATUS_IOC_FAILURE);
476 bfa_fsm_set_state(ioc, bfa_ioc_sm_hwfail);
477 break;
478
479 case IOC_E_ENABLE:
480 break;
481
482 case IOC_E_DISABLE:
483 bfa_fsm_set_state(ioc, bfa_ioc_sm_disabling);
484 break;
485
486 case IOC_E_DETACH:
487 bfa_fsm_set_state(ioc, bfa_ioc_sm_uninit);
488 bfa_iocpf_stop(ioc);
489 break;
490
491 default:
492 bfa_sm_fault(event);
493 }
494 }
495
496 static void
497 bfa_ioc_sm_fail_entry(struct bfa_ioc *ioc)
498 {
499 }
500
501 /* IOC failure. */
502 static void
503 bfa_ioc_sm_fail(struct bfa_ioc *ioc, enum ioc_event event)
504 {
505 switch (event) {
506 case IOC_E_ENABLE:
507 ioc->cbfn->enable_cbfn(ioc->bfa, BFA_STATUS_IOC_FAILURE);
508 break;
509
510 case IOC_E_DISABLE:
511 bfa_fsm_set_state(ioc, bfa_ioc_sm_disabling);
512 break;
513
514 case IOC_E_DETACH:
515 bfa_fsm_set_state(ioc, bfa_ioc_sm_uninit);
516 bfa_iocpf_stop(ioc);
517 break;
518
519 case IOC_E_HWERROR:
520 /* HB failure notification, ignore. */
521 break;
522
523 default:
524 bfa_sm_fault(event);
525 }
526 }
527
528 static void
529 bfa_ioc_sm_hwfail_entry(struct bfa_ioc *ioc)
530 {
531 }
532
533 /* IOC failure. */
534 static void
535 bfa_ioc_sm_hwfail(struct bfa_ioc *ioc, enum ioc_event event)
536 {
537 switch (event) {
538
539 case IOC_E_ENABLE:
540 ioc->cbfn->enable_cbfn(ioc->bfa, BFA_STATUS_IOC_FAILURE);
541 break;
542
543 case IOC_E_DISABLE:
544 ioc->cbfn->disable_cbfn(ioc->bfa);
545 break;
546
547 case IOC_E_DETACH:
548 bfa_fsm_set_state(ioc, bfa_ioc_sm_uninit);
549 break;
550
551 default:
552 bfa_sm_fault(event);
553 }
554 }
555
556 /* IOCPF State Machine */
557
558 /* Reset entry actions -- initialize state machine */
559 static void
560 bfa_iocpf_sm_reset_entry(struct bfa_iocpf *iocpf)
561 {
562 iocpf->fw_mismatch_notified = false;
563 iocpf->auto_recover = bfa_nw_auto_recover;
564 }
565
566 /* Beginning state. IOC is in reset state. */
567 static void
568 bfa_iocpf_sm_reset(struct bfa_iocpf *iocpf, enum iocpf_event event)
569 {
570 switch (event) {
571 case IOCPF_E_ENABLE:
572 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_fwcheck);
573 break;
574
575 case IOCPF_E_STOP:
576 break;
577
578 default:
579 bfa_sm_fault(event);
580 }
581 }
582
583 /* Semaphore should be acquired for version check. */
584 static void
585 bfa_iocpf_sm_fwcheck_entry(struct bfa_iocpf *iocpf)
586 {
587 bfa_ioc_hw_sem_init(iocpf->ioc);
588 bfa_ioc_hw_sem_get(iocpf->ioc);
589 }
590
591 /* Awaiting h/w semaphore to continue with version check. */
592 static void
593 bfa_iocpf_sm_fwcheck(struct bfa_iocpf *iocpf, enum iocpf_event event)
594 {
595 struct bfa_ioc *ioc = iocpf->ioc;
596
597 switch (event) {
598 case IOCPF_E_SEMLOCKED:
599 if (bfa_ioc_firmware_lock(ioc)) {
600 if (bfa_ioc_sync_start(ioc)) {
601 bfa_ioc_sync_join(ioc);
602 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_hwinit);
603 } else {
604 bfa_ioc_firmware_unlock(ioc);
605 bfa_nw_ioc_hw_sem_release(ioc);
606 mod_timer(&ioc->sem_timer, jiffies +
607 msecs_to_jiffies(BFA_IOC_HWSEM_TOV));
608 }
609 } else {
610 bfa_nw_ioc_hw_sem_release(ioc);
611 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_mismatch);
612 }
613 break;
614
615 case IOCPF_E_SEM_ERROR:
616 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_fail);
617 bfa_ioc_pf_hwfailed(ioc);
618 break;
619
620 case IOCPF_E_DISABLE:
621 bfa_ioc_hw_sem_get_cancel(ioc);
622 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_reset);
623 bfa_ioc_pf_disabled(ioc);
624 break;
625
626 case IOCPF_E_STOP:
627 bfa_ioc_hw_sem_get_cancel(ioc);
628 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_reset);
629 break;
630
631 default:
632 bfa_sm_fault(event);
633 }
634 }
635
636 /* Notify enable completion callback */
637 static void
638 bfa_iocpf_sm_mismatch_entry(struct bfa_iocpf *iocpf)
639 {
640 /* Call only the first time sm enters fwmismatch state. */
641 if (!iocpf->fw_mismatch_notified)
642 bfa_ioc_pf_fwmismatch(iocpf->ioc);
643
644 iocpf->fw_mismatch_notified = true;
645 mod_timer(&(iocpf->ioc)->iocpf_timer, jiffies +
646 msecs_to_jiffies(BFA_IOC_TOV));
647 }
648
649 /* Awaiting firmware version match. */
650 static void
651 bfa_iocpf_sm_mismatch(struct bfa_iocpf *iocpf, enum iocpf_event event)
652 {
653 struct bfa_ioc *ioc = iocpf->ioc;
654
655 switch (event) {
656 case IOCPF_E_TIMEOUT:
657 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_fwcheck);
658 break;
659
660 case IOCPF_E_DISABLE:
661 del_timer(&ioc->iocpf_timer);
662 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_reset);
663 bfa_ioc_pf_disabled(ioc);
664 break;
665
666 case IOCPF_E_STOP:
667 del_timer(&ioc->iocpf_timer);
668 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_reset);
669 break;
670
671 default:
672 bfa_sm_fault(event);
673 }
674 }
675
676 /* Request for semaphore. */
677 static void
678 bfa_iocpf_sm_semwait_entry(struct bfa_iocpf *iocpf)
679 {
680 bfa_ioc_hw_sem_get(iocpf->ioc);
681 }
682
683 /* Awaiting semaphore for h/w initialzation. */
684 static void
685 bfa_iocpf_sm_semwait(struct bfa_iocpf *iocpf, enum iocpf_event event)
686 {
687 struct bfa_ioc *ioc = iocpf->ioc;
688
689 switch (event) {
690 case IOCPF_E_SEMLOCKED:
691 if (bfa_ioc_sync_complete(ioc)) {
692 bfa_ioc_sync_join(ioc);
693 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_hwinit);
694 } else {
695 bfa_nw_ioc_hw_sem_release(ioc);
696 mod_timer(&ioc->sem_timer, jiffies +
697 msecs_to_jiffies(BFA_IOC_HWSEM_TOV));
698 }
699 break;
700
701 case IOCPF_E_SEM_ERROR:
702 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_fail);
703 bfa_ioc_pf_hwfailed(ioc);
704 break;
705
706 case IOCPF_E_DISABLE:
707 bfa_ioc_hw_sem_get_cancel(ioc);
708 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_disabling_sync);
709 break;
710
711 default:
712 bfa_sm_fault(event);
713 }
714 }
715
716 static void
717 bfa_iocpf_sm_hwinit_entry(struct bfa_iocpf *iocpf)
718 {
719 iocpf->poll_time = 0;
720 bfa_ioc_reset(iocpf->ioc, false);
721 }
722
723 /* Hardware is being initialized. Interrupts are enabled.
724 * Holding hardware semaphore lock.
725 */
726 static void
727 bfa_iocpf_sm_hwinit(struct bfa_iocpf *iocpf, enum iocpf_event event)
728 {
729 struct bfa_ioc *ioc = iocpf->ioc;
730
731 switch (event) {
732 case IOCPF_E_FWREADY:
733 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_enabling);
734 break;
735
736 case IOCPF_E_TIMEOUT:
737 bfa_nw_ioc_hw_sem_release(ioc);
738 bfa_ioc_pf_failed(ioc);
739 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_initfail_sync);
740 break;
741
742 case IOCPF_E_DISABLE:
743 del_timer(&ioc->iocpf_timer);
744 bfa_ioc_sync_leave(ioc);
745 bfa_nw_ioc_hw_sem_release(ioc);
746 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_disabled);
747 break;
748
749 default:
750 bfa_sm_fault(event);
751 }
752 }
753
754 static void
755 bfa_iocpf_sm_enabling_entry(struct bfa_iocpf *iocpf)
756 {
757 mod_timer(&(iocpf->ioc)->iocpf_timer, jiffies +
758 msecs_to_jiffies(BFA_IOC_TOV));
759 /**
760 * Enable Interrupts before sending fw IOC ENABLE cmd.
761 */
762 iocpf->ioc->cbfn->reset_cbfn(iocpf->ioc->bfa);
763 bfa_ioc_send_enable(iocpf->ioc);
764 }
765
766 /* Host IOC function is being enabled, awaiting response from firmware.
767 * Semaphore is acquired.
768 */
769 static void
770 bfa_iocpf_sm_enabling(struct bfa_iocpf *iocpf, enum iocpf_event event)
771 {
772 struct bfa_ioc *ioc = iocpf->ioc;
773
774 switch (event) {
775 case IOCPF_E_FWRSP_ENABLE:
776 del_timer(&ioc->iocpf_timer);
777 bfa_nw_ioc_hw_sem_release(ioc);
778 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_ready);
779 break;
780
781 case IOCPF_E_INITFAIL:
782 del_timer(&ioc->iocpf_timer);
783 /* fall through */
784
785 case IOCPF_E_TIMEOUT:
786 bfa_nw_ioc_hw_sem_release(ioc);
787 if (event == IOCPF_E_TIMEOUT)
788 bfa_ioc_pf_failed(ioc);
789 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_initfail_sync);
790 break;
791
792 case IOCPF_E_DISABLE:
793 del_timer(&ioc->iocpf_timer);
794 bfa_nw_ioc_hw_sem_release(ioc);
795 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_disabling);
796 break;
797
798 default:
799 bfa_sm_fault(event);
800 }
801 }
802
803 static void
804 bfa_iocpf_sm_ready_entry(struct bfa_iocpf *iocpf)
805 {
806 bfa_ioc_pf_enabled(iocpf->ioc);
807 }
808
809 static void
810 bfa_iocpf_sm_ready(struct bfa_iocpf *iocpf, enum iocpf_event event)
811 {
812 switch (event) {
813 case IOCPF_E_DISABLE:
814 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_disabling);
815 break;
816
817 case IOCPF_E_GETATTRFAIL:
818 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_initfail_sync);
819 break;
820
821 case IOCPF_E_FAIL:
822 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_fail_sync);
823 break;
824
825 default:
826 bfa_sm_fault(event);
827 }
828 }
829
830 static void
831 bfa_iocpf_sm_disabling_entry(struct bfa_iocpf *iocpf)
832 {
833 mod_timer(&(iocpf->ioc)->iocpf_timer, jiffies +
834 msecs_to_jiffies(BFA_IOC_TOV));
835 bfa_ioc_send_disable(iocpf->ioc);
836 }
837
838 /* IOC is being disabled */
839 static void
840 bfa_iocpf_sm_disabling(struct bfa_iocpf *iocpf, enum iocpf_event event)
841 {
842 struct bfa_ioc *ioc = iocpf->ioc;
843
844 switch (event) {
845 case IOCPF_E_FWRSP_DISABLE:
846 del_timer(&ioc->iocpf_timer);
847 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_disabling_sync);
848 break;
849
850 case IOCPF_E_FAIL:
851 del_timer(&ioc->iocpf_timer);
852 /* fall through*/
853
854 case IOCPF_E_TIMEOUT:
855 bfa_ioc_set_cur_ioc_fwstate(ioc, BFI_IOC_FAIL);
856 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_disabling_sync);
857 break;
858
859 case IOCPF_E_FWRSP_ENABLE:
860 break;
861
862 default:
863 bfa_sm_fault(event);
864 }
865 }
866
867 static void
868 bfa_iocpf_sm_disabling_sync_entry(struct bfa_iocpf *iocpf)
869 {
870 bfa_ioc_hw_sem_get(iocpf->ioc);
871 }
872
873 /* IOC hb ack request is being removed. */
874 static void
875 bfa_iocpf_sm_disabling_sync(struct bfa_iocpf *iocpf, enum iocpf_event event)
876 {
877 struct bfa_ioc *ioc = iocpf->ioc;
878
879 switch (event) {
880 case IOCPF_E_SEMLOCKED:
881 bfa_ioc_sync_leave(ioc);
882 bfa_nw_ioc_hw_sem_release(ioc);
883 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_disabled);
884 break;
885
886 case IOCPF_E_SEM_ERROR:
887 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_fail);
888 bfa_ioc_pf_hwfailed(ioc);
889 break;
890
891 case IOCPF_E_FAIL:
892 break;
893
894 default:
895 bfa_sm_fault(event);
896 }
897 }
898
899 /* IOC disable completion entry. */
900 static void
901 bfa_iocpf_sm_disabled_entry(struct bfa_iocpf *iocpf)
902 {
903 bfa_ioc_mbox_flush(iocpf->ioc);
904 bfa_ioc_pf_disabled(iocpf->ioc);
905 }
906
907 static void
908 bfa_iocpf_sm_disabled(struct bfa_iocpf *iocpf, enum iocpf_event event)
909 {
910 struct bfa_ioc *ioc = iocpf->ioc;
911
912 switch (event) {
913 case IOCPF_E_ENABLE:
914 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_semwait);
915 break;
916
917 case IOCPF_E_STOP:
918 bfa_ioc_firmware_unlock(ioc);
919 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_reset);
920 break;
921
922 default:
923 bfa_sm_fault(event);
924 }
925 }
926
927 static void
928 bfa_iocpf_sm_initfail_sync_entry(struct bfa_iocpf *iocpf)
929 {
930 bfa_nw_ioc_debug_save_ftrc(iocpf->ioc);
931 bfa_ioc_hw_sem_get(iocpf->ioc);
932 }
933
934 /* Hardware initialization failed. */
935 static void
936 bfa_iocpf_sm_initfail_sync(struct bfa_iocpf *iocpf, enum iocpf_event event)
937 {
938 struct bfa_ioc *ioc = iocpf->ioc;
939
940 switch (event) {
941 case IOCPF_E_SEMLOCKED:
942 bfa_ioc_notify_fail(ioc);
943 bfa_ioc_sync_leave(ioc);
944 bfa_ioc_set_cur_ioc_fwstate(ioc, BFI_IOC_FAIL);
945 bfa_nw_ioc_hw_sem_release(ioc);
946 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_initfail);
947 break;
948
949 case IOCPF_E_SEM_ERROR:
950 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_fail);
951 bfa_ioc_pf_hwfailed(ioc);
952 break;
953
954 case IOCPF_E_DISABLE:
955 bfa_ioc_hw_sem_get_cancel(ioc);
956 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_disabling_sync);
957 break;
958
959 case IOCPF_E_STOP:
960 bfa_ioc_hw_sem_get_cancel(ioc);
961 bfa_ioc_firmware_unlock(ioc);
962 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_reset);
963 break;
964
965 case IOCPF_E_FAIL:
966 break;
967
968 default:
969 bfa_sm_fault(event);
970 }
971 }
972
973 static void
974 bfa_iocpf_sm_initfail_entry(struct bfa_iocpf *iocpf)
975 {
976 }
977
978 /* Hardware initialization failed. */
979 static void
980 bfa_iocpf_sm_initfail(struct bfa_iocpf *iocpf, enum iocpf_event event)
981 {
982 struct bfa_ioc *ioc = iocpf->ioc;
983
984 switch (event) {
985 case IOCPF_E_DISABLE:
986 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_disabled);
987 break;
988
989 case IOCPF_E_STOP:
990 bfa_ioc_firmware_unlock(ioc);
991 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_reset);
992 break;
993
994 default:
995 bfa_sm_fault(event);
996 }
997 }
998
999 static void
1000 bfa_iocpf_sm_fail_sync_entry(struct bfa_iocpf *iocpf)
1001 {
1002 /**
1003 * Mark IOC as failed in hardware and stop firmware.
1004 */
1005 bfa_ioc_lpu_stop(iocpf->ioc);
1006
1007 /**
1008 * Flush any queued up mailbox requests.
1009 */
1010 bfa_ioc_mbox_flush(iocpf->ioc);
1011 bfa_ioc_hw_sem_get(iocpf->ioc);
1012 }
1013
1014 /* IOC is in failed state. */
1015 static void
1016 bfa_iocpf_sm_fail_sync(struct bfa_iocpf *iocpf, enum iocpf_event event)
1017 {
1018 struct bfa_ioc *ioc = iocpf->ioc;
1019
1020 switch (event) {
1021 case IOCPF_E_SEMLOCKED:
1022 bfa_ioc_sync_ack(ioc);
1023 bfa_ioc_notify_fail(ioc);
1024 if (!iocpf->auto_recover) {
1025 bfa_ioc_sync_leave(ioc);
1026 bfa_ioc_set_cur_ioc_fwstate(ioc, BFI_IOC_FAIL);
1027 bfa_nw_ioc_hw_sem_release(ioc);
1028 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_fail);
1029 } else {
1030 if (bfa_ioc_sync_complete(ioc))
1031 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_hwinit);
1032 else {
1033 bfa_nw_ioc_hw_sem_release(ioc);
1034 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_semwait);
1035 }
1036 }
1037 break;
1038
1039 case IOCPF_E_SEM_ERROR:
1040 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_fail);
1041 bfa_ioc_pf_hwfailed(ioc);
1042 break;
1043
1044 case IOCPF_E_DISABLE:
1045 bfa_ioc_hw_sem_get_cancel(ioc);
1046 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_disabling_sync);
1047 break;
1048
1049 case IOCPF_E_FAIL:
1050 break;
1051
1052 default:
1053 bfa_sm_fault(event);
1054 }
1055 }
1056
1057 static void
1058 bfa_iocpf_sm_fail_entry(struct bfa_iocpf *iocpf)
1059 {
1060 }
1061
1062 /* IOC is in failed state. */
1063 static void
1064 bfa_iocpf_sm_fail(struct bfa_iocpf *iocpf, enum iocpf_event event)
1065 {
1066 switch (event) {
1067 case IOCPF_E_DISABLE:
1068 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_disabled);
1069 break;
1070
1071 default:
1072 bfa_sm_fault(event);
1073 }
1074 }
1075
1076 /* BFA IOC private functions */
1077
1078 /* Notify common modules registered for notification. */
1079 static void
1080 bfa_ioc_event_notify(struct bfa_ioc *ioc, enum bfa_ioc_event event)
1081 {
1082 struct bfa_ioc_notify *notify;
1083
1084 list_for_each_entry(notify, &ioc->notify_q, qe)
1085 notify->cbfn(notify->cbarg, event);
1086 }
1087
1088 static void
1089 bfa_ioc_disable_comp(struct bfa_ioc *ioc)
1090 {
1091 ioc->cbfn->disable_cbfn(ioc->bfa);
1092 bfa_ioc_event_notify(ioc, BFA_IOC_E_DISABLED);
1093 }
1094
1095 bool
1096 bfa_nw_ioc_sem_get(void __iomem *sem_reg)
1097 {
1098 u32 r32;
1099 int cnt = 0;
1100 #define BFA_SEM_SPINCNT 3000
1101
1102 r32 = readl(sem_reg);
1103
1104 while ((r32 & 1) && (cnt < BFA_SEM_SPINCNT)) {
1105 cnt++;
1106 udelay(2);
1107 r32 = readl(sem_reg);
1108 }
1109
1110 if (!(r32 & 1))
1111 return true;
1112
1113 return false;
1114 }
1115
1116 void
1117 bfa_nw_ioc_sem_release(void __iomem *sem_reg)
1118 {
1119 readl(sem_reg);
1120 writel(1, sem_reg);
1121 }
1122
1123 /* Clear fwver hdr */
1124 static void
1125 bfa_ioc_fwver_clear(struct bfa_ioc *ioc)
1126 {
1127 u32 pgnum, loff = 0;
1128 int i;
1129
1130 pgnum = PSS_SMEM_PGNUM(ioc->ioc_regs.smem_pg0, loff);
1131 writel(pgnum, ioc->ioc_regs.host_page_num_fn);
1132
1133 for (i = 0; i < (sizeof(struct bfi_ioc_image_hdr) / sizeof(u32)); i++) {
1134 writel(0, ioc->ioc_regs.smem_page_start + loff);
1135 loff += sizeof(u32);
1136 }
1137 }
1138
1139
1140 static void
1141 bfa_ioc_hw_sem_init(struct bfa_ioc *ioc)
1142 {
1143 struct bfi_ioc_image_hdr fwhdr;
1144 u32 fwstate, r32;
1145
1146 /* Spin on init semaphore to serialize. */
1147 r32 = readl(ioc->ioc_regs.ioc_init_sem_reg);
1148 while (r32 & 0x1) {
1149 udelay(20);
1150 r32 = readl(ioc->ioc_regs.ioc_init_sem_reg);
1151 }
1152
1153 fwstate = bfa_ioc_get_cur_ioc_fwstate(ioc);
1154 if (fwstate == BFI_IOC_UNINIT) {
1155 writel(1, ioc->ioc_regs.ioc_init_sem_reg);
1156 return;
1157 }
1158
1159 bfa_nw_ioc_fwver_get(ioc, &fwhdr);
1160
1161 if (swab32(fwhdr.exec) == BFI_FWBOOT_TYPE_NORMAL) {
1162 writel(1, ioc->ioc_regs.ioc_init_sem_reg);
1163 return;
1164 }
1165
1166 bfa_ioc_fwver_clear(ioc);
1167 bfa_ioc_set_cur_ioc_fwstate(ioc, BFI_IOC_UNINIT);
1168 bfa_ioc_set_alt_ioc_fwstate(ioc, BFI_IOC_UNINIT);
1169
1170 /*
1171 * Try to lock and then unlock the semaphore.
1172 */
1173 readl(ioc->ioc_regs.ioc_sem_reg);
1174 writel(1, ioc->ioc_regs.ioc_sem_reg);
1175
1176 /* Unlock init semaphore */
1177 writel(1, ioc->ioc_regs.ioc_init_sem_reg);
1178 }
1179
1180 static void
1181 bfa_ioc_hw_sem_get(struct bfa_ioc *ioc)
1182 {
1183 u32 r32;
1184
1185 /**
1186 * First read to the semaphore register will return 0, subsequent reads
1187 * will return 1. Semaphore is released by writing 1 to the register
1188 */
1189 r32 = readl(ioc->ioc_regs.ioc_sem_reg);
1190 if (r32 == ~0) {
1191 bfa_fsm_send_event(&ioc->iocpf, IOCPF_E_SEM_ERROR);
1192 return;
1193 }
1194 if (!(r32 & 1)) {
1195 bfa_fsm_send_event(&ioc->iocpf, IOCPF_E_SEMLOCKED);
1196 return;
1197 }
1198
1199 mod_timer(&ioc->sem_timer, jiffies +
1200 msecs_to_jiffies(BFA_IOC_HWSEM_TOV));
1201 }
1202
1203 void
1204 bfa_nw_ioc_hw_sem_release(struct bfa_ioc *ioc)
1205 {
1206 writel(1, ioc->ioc_regs.ioc_sem_reg);
1207 }
1208
1209 static void
1210 bfa_ioc_hw_sem_get_cancel(struct bfa_ioc *ioc)
1211 {
1212 del_timer(&ioc->sem_timer);
1213 }
1214
1215 /* Initialize LPU local memory (aka secondary memory / SRAM) */
1216 static void
1217 bfa_ioc_lmem_init(struct bfa_ioc *ioc)
1218 {
1219 u32 pss_ctl;
1220 int i;
1221 #define PSS_LMEM_INIT_TIME 10000
1222
1223 pss_ctl = readl(ioc->ioc_regs.pss_ctl_reg);
1224 pss_ctl &= ~__PSS_LMEM_RESET;
1225 pss_ctl |= __PSS_LMEM_INIT_EN;
1226
1227 /*
1228 * i2c workaround 12.5khz clock
1229 */
1230 pss_ctl |= __PSS_I2C_CLK_DIV(3UL);
1231 writel(pss_ctl, ioc->ioc_regs.pss_ctl_reg);
1232
1233 /**
1234 * wait for memory initialization to be complete
1235 */
1236 i = 0;
1237 do {
1238 pss_ctl = readl(ioc->ioc_regs.pss_ctl_reg);
1239 i++;
1240 } while (!(pss_ctl & __PSS_LMEM_INIT_DONE) && (i < PSS_LMEM_INIT_TIME));
1241
1242 /**
1243 * If memory initialization is not successful, IOC timeout will catch
1244 * such failures.
1245 */
1246 BUG_ON(!(pss_ctl & __PSS_LMEM_INIT_DONE));
1247
1248 pss_ctl &= ~(__PSS_LMEM_INIT_DONE | __PSS_LMEM_INIT_EN);
1249 writel(pss_ctl, ioc->ioc_regs.pss_ctl_reg);
1250 }
1251
1252 static void
1253 bfa_ioc_lpu_start(struct bfa_ioc *ioc)
1254 {
1255 u32 pss_ctl;
1256
1257 /**
1258 * Take processor out of reset.
1259 */
1260 pss_ctl = readl(ioc->ioc_regs.pss_ctl_reg);
1261 pss_ctl &= ~__PSS_LPU0_RESET;
1262
1263 writel(pss_ctl, ioc->ioc_regs.pss_ctl_reg);
1264 }
1265
1266 static void
1267 bfa_ioc_lpu_stop(struct bfa_ioc *ioc)
1268 {
1269 u32 pss_ctl;
1270
1271 /**
1272 * Put processors in reset.
1273 */
1274 pss_ctl = readl(ioc->ioc_regs.pss_ctl_reg);
1275 pss_ctl |= (__PSS_LPU0_RESET | __PSS_LPU1_RESET);
1276
1277 writel(pss_ctl, ioc->ioc_regs.pss_ctl_reg);
1278 }
1279
1280 /* Get driver and firmware versions. */
1281 void
1282 bfa_nw_ioc_fwver_get(struct bfa_ioc *ioc, struct bfi_ioc_image_hdr *fwhdr)
1283 {
1284 u32 pgnum;
1285 u32 loff = 0;
1286 int i;
1287 u32 *fwsig = (u32 *) fwhdr;
1288
1289 pgnum = bfa_ioc_smem_pgnum(ioc, loff);
1290 writel(pgnum, ioc->ioc_regs.host_page_num_fn);
1291
1292 for (i = 0; i < (sizeof(struct bfi_ioc_image_hdr) / sizeof(u32));
1293 i++) {
1294 fwsig[i] =
1295 swab32(readl(loff + ioc->ioc_regs.smem_page_start));
1296 loff += sizeof(u32);
1297 }
1298 }
1299
1300 static bool
1301 bfa_ioc_fwver_md5_check(struct bfi_ioc_image_hdr *fwhdr_1,
1302 struct bfi_ioc_image_hdr *fwhdr_2)
1303 {
1304 int i;
1305
1306 for (i = 0; i < BFI_IOC_MD5SUM_SZ; i++) {
1307 if (fwhdr_1->md5sum[i] != fwhdr_2->md5sum[i])
1308 return false;
1309 }
1310
1311 return true;
1312 }
1313
1314 /* Returns TRUE if major minor and maintenance are same.
1315 * If patch version are same, check for MD5 Checksum to be same.
1316 */
1317 static bool
1318 bfa_ioc_fw_ver_compatible(struct bfi_ioc_image_hdr *drv_fwhdr,
1319 struct bfi_ioc_image_hdr *fwhdr_to_cmp)
1320 {
1321 if (drv_fwhdr->signature != fwhdr_to_cmp->signature)
1322 return false;
1323 if (drv_fwhdr->fwver.major != fwhdr_to_cmp->fwver.major)
1324 return false;
1325 if (drv_fwhdr->fwver.minor != fwhdr_to_cmp->fwver.minor)
1326 return false;
1327 if (drv_fwhdr->fwver.maint != fwhdr_to_cmp->fwver.maint)
1328 return false;
1329 if (drv_fwhdr->fwver.patch == fwhdr_to_cmp->fwver.patch &&
1330 drv_fwhdr->fwver.phase == fwhdr_to_cmp->fwver.phase &&
1331 drv_fwhdr->fwver.build == fwhdr_to_cmp->fwver.build)
1332 return bfa_ioc_fwver_md5_check(drv_fwhdr, fwhdr_to_cmp);
1333
1334 return true;
1335 }
1336
1337 static bool
1338 bfa_ioc_flash_fwver_valid(struct bfi_ioc_image_hdr *flash_fwhdr)
1339 {
1340 if (flash_fwhdr->fwver.major == 0 || flash_fwhdr->fwver.major == 0xFF)
1341 return false;
1342
1343 return true;
1344 }
1345
1346 static bool
1347 fwhdr_is_ga(struct bfi_ioc_image_hdr *fwhdr)
1348 {
1349 if (fwhdr->fwver.phase == 0 &&
1350 fwhdr->fwver.build == 0)
1351 return false;
1352
1353 return true;
1354 }
1355
1356 /* Returns TRUE if both are compatible and patch of fwhdr_to_cmp is better. */
1357 static enum bfi_ioc_img_ver_cmp
1358 bfa_ioc_fw_ver_patch_cmp(struct bfi_ioc_image_hdr *base_fwhdr,
1359 struct bfi_ioc_image_hdr *fwhdr_to_cmp)
1360 {
1361 if (!bfa_ioc_fw_ver_compatible(base_fwhdr, fwhdr_to_cmp))
1362 return BFI_IOC_IMG_VER_INCOMP;
1363
1364 if (fwhdr_to_cmp->fwver.patch > base_fwhdr->fwver.patch)
1365 return BFI_IOC_IMG_VER_BETTER;
1366 else if (fwhdr_to_cmp->fwver.patch < base_fwhdr->fwver.patch)
1367 return BFI_IOC_IMG_VER_OLD;
1368
1369 /* GA takes priority over internal builds of the same patch stream.
1370 * At this point major minor maint and patch numbers are same.
1371 */
1372 if (fwhdr_is_ga(base_fwhdr))
1373 if (fwhdr_is_ga(fwhdr_to_cmp))
1374 return BFI_IOC_IMG_VER_SAME;
1375 else
1376 return BFI_IOC_IMG_VER_OLD;
1377 else
1378 if (fwhdr_is_ga(fwhdr_to_cmp))
1379 return BFI_IOC_IMG_VER_BETTER;
1380
1381 if (fwhdr_to_cmp->fwver.phase > base_fwhdr->fwver.phase)
1382 return BFI_IOC_IMG_VER_BETTER;
1383 else if (fwhdr_to_cmp->fwver.phase < base_fwhdr->fwver.phase)
1384 return BFI_IOC_IMG_VER_OLD;
1385
1386 if (fwhdr_to_cmp->fwver.build > base_fwhdr->fwver.build)
1387 return BFI_IOC_IMG_VER_BETTER;
1388 else if (fwhdr_to_cmp->fwver.build < base_fwhdr->fwver.build)
1389 return BFI_IOC_IMG_VER_OLD;
1390
1391 /* All Version Numbers are equal.
1392 * Md5 check to be done as a part of compatibility check.
1393 */
1394 return BFI_IOC_IMG_VER_SAME;
1395 }
1396
1397 /* register definitions */
1398 #define FLI_CMD_REG 0x0001d000
1399 #define FLI_WRDATA_REG 0x0001d00c
1400 #define FLI_RDDATA_REG 0x0001d010
1401 #define FLI_ADDR_REG 0x0001d004
1402 #define FLI_DEV_STATUS_REG 0x0001d014
1403
1404 #define BFA_FLASH_FIFO_SIZE 128 /* fifo size */
1405 #define BFA_FLASH_CHECK_MAX 10000 /* max # of status check */
1406 #define BFA_FLASH_BLOCKING_OP_MAX 1000000 /* max # of blocking op check */
1407 #define BFA_FLASH_WIP_MASK 0x01 /* write in progress bit mask */
1408
1409 #define NFC_STATE_RUNNING 0x20000001
1410 #define NFC_STATE_PAUSED 0x00004560
1411 #define NFC_VER_VALID 0x147
1412
1413 enum bfa_flash_cmd {
1414 BFA_FLASH_FAST_READ = 0x0b, /* fast read */
1415 BFA_FLASH_WRITE_ENABLE = 0x06, /* write enable */
1416 BFA_FLASH_SECTOR_ERASE = 0xd8, /* sector erase */
1417 BFA_FLASH_WRITE = 0x02, /* write */
1418 BFA_FLASH_READ_STATUS = 0x05, /* read status */
1419 };
1420
1421 /* hardware error definition */
1422 enum bfa_flash_err {
1423 BFA_FLASH_NOT_PRESENT = -1, /*!< flash not present */
1424 BFA_FLASH_UNINIT = -2, /*!< flash not initialized */
1425 BFA_FLASH_BAD = -3, /*!< flash bad */
1426 BFA_FLASH_BUSY = -4, /*!< flash busy */
1427 BFA_FLASH_ERR_CMD_ACT = -5, /*!< command active never cleared */
1428 BFA_FLASH_ERR_FIFO_CNT = -6, /*!< fifo count never cleared */
1429 BFA_FLASH_ERR_WIP = -7, /*!< write-in-progress never cleared */
1430 BFA_FLASH_ERR_TIMEOUT = -8, /*!< fli timeout */
1431 BFA_FLASH_ERR_LEN = -9, /*!< invalid length */
1432 };
1433
1434 /* flash command register data structure */
1435 union bfa_flash_cmd_reg {
1436 struct {
1437 #ifdef __BIG_ENDIAN
1438 u32 act:1;
1439 u32 rsv:1;
1440 u32 write_cnt:9;
1441 u32 read_cnt:9;
1442 u32 addr_cnt:4;
1443 u32 cmd:8;
1444 #else
1445 u32 cmd:8;
1446 u32 addr_cnt:4;
1447 u32 read_cnt:9;
1448 u32 write_cnt:9;
1449 u32 rsv:1;
1450 u32 act:1;
1451 #endif
1452 } r;
1453 u32 i;
1454 };
1455
1456 /* flash device status register data structure */
1457 union bfa_flash_dev_status_reg {
1458 struct {
1459 #ifdef __BIG_ENDIAN
1460 u32 rsv:21;
1461 u32 fifo_cnt:6;
1462 u32 busy:1;
1463 u32 init_status:1;
1464 u32 present:1;
1465 u32 bad:1;
1466 u32 good:1;
1467 #else
1468 u32 good:1;
1469 u32 bad:1;
1470 u32 present:1;
1471 u32 init_status:1;
1472 u32 busy:1;
1473 u32 fifo_cnt:6;
1474 u32 rsv:21;
1475 #endif
1476 } r;
1477 u32 i;
1478 };
1479
1480 /* flash address register data structure */
1481 union bfa_flash_addr_reg {
1482 struct {
1483 #ifdef __BIG_ENDIAN
1484 u32 addr:24;
1485 u32 dummy:8;
1486 #else
1487 u32 dummy:8;
1488 u32 addr:24;
1489 #endif
1490 } r;
1491 u32 i;
1492 };
1493
1494 /* Flash raw private functions */
1495 static void
1496 bfa_flash_set_cmd(void __iomem *pci_bar, u8 wr_cnt,
1497 u8 rd_cnt, u8 ad_cnt, u8 op)
1498 {
1499 union bfa_flash_cmd_reg cmd;
1500
1501 cmd.i = 0;
1502 cmd.r.act = 1;
1503 cmd.r.write_cnt = wr_cnt;
1504 cmd.r.read_cnt = rd_cnt;
1505 cmd.r.addr_cnt = ad_cnt;
1506 cmd.r.cmd = op;
1507 writel(cmd.i, (pci_bar + FLI_CMD_REG));
1508 }
1509
1510 static void
1511 bfa_flash_set_addr(void __iomem *pci_bar, u32 address)
1512 {
1513 union bfa_flash_addr_reg addr;
1514
1515 addr.r.addr = address & 0x00ffffff;
1516 addr.r.dummy = 0;
1517 writel(addr.i, (pci_bar + FLI_ADDR_REG));
1518 }
1519
1520 static int
1521 bfa_flash_cmd_act_check(void __iomem *pci_bar)
1522 {
1523 union bfa_flash_cmd_reg cmd;
1524
1525 cmd.i = readl(pci_bar + FLI_CMD_REG);
1526
1527 if (cmd.r.act)
1528 return BFA_FLASH_ERR_CMD_ACT;
1529
1530 return 0;
1531 }
1532
1533 /* Flush FLI data fifo. */
1534 static int
1535 bfa_flash_fifo_flush(void __iomem *pci_bar)
1536 {
1537 u32 i;
1538 u32 t;
1539 union bfa_flash_dev_status_reg dev_status;
1540
1541 dev_status.i = readl(pci_bar + FLI_DEV_STATUS_REG);
1542
1543 if (!dev_status.r.fifo_cnt)
1544 return 0;
1545
1546 /* fifo counter in terms of words */
1547 for (i = 0; i < dev_status.r.fifo_cnt; i++)
1548 t = readl(pci_bar + FLI_RDDATA_REG);
1549
1550 /* Check the device status. It may take some time. */
1551 for (i = 0; i < BFA_FLASH_CHECK_MAX; i++) {
1552 dev_status.i = readl(pci_bar + FLI_DEV_STATUS_REG);
1553 if (!dev_status.r.fifo_cnt)
1554 break;
1555 }
1556
1557 if (dev_status.r.fifo_cnt)
1558 return BFA_FLASH_ERR_FIFO_CNT;
1559
1560 return 0;
1561 }
1562
1563 /* Read flash status. */
1564 static int
1565 bfa_flash_status_read(void __iomem *pci_bar)
1566 {
1567 union bfa_flash_dev_status_reg dev_status;
1568 int status;
1569 u32 ret_status;
1570 int i;
1571
1572 status = bfa_flash_fifo_flush(pci_bar);
1573 if (status < 0)
1574 return status;
1575
1576 bfa_flash_set_cmd(pci_bar, 0, 4, 0, BFA_FLASH_READ_STATUS);
1577
1578 for (i = 0; i < BFA_FLASH_CHECK_MAX; i++) {
1579 status = bfa_flash_cmd_act_check(pci_bar);
1580 if (!status)
1581 break;
1582 }
1583
1584 if (status)
1585 return status;
1586
1587 dev_status.i = readl(pci_bar + FLI_DEV_STATUS_REG);
1588 if (!dev_status.r.fifo_cnt)
1589 return BFA_FLASH_BUSY;
1590
1591 ret_status = readl(pci_bar + FLI_RDDATA_REG);
1592 ret_status >>= 24;
1593
1594 status = bfa_flash_fifo_flush(pci_bar);
1595 if (status < 0)
1596 return status;
1597
1598 return ret_status;
1599 }
1600
1601 /* Start flash read operation. */
1602 static int
1603 bfa_flash_read_start(void __iomem *pci_bar, u32 offset, u32 len,
1604 char *buf)
1605 {
1606 int status;
1607
1608 /* len must be mutiple of 4 and not exceeding fifo size */
1609 if (len == 0 || len > BFA_FLASH_FIFO_SIZE || (len & 0x03) != 0)
1610 return BFA_FLASH_ERR_LEN;
1611
1612 /* check status */
1613 status = bfa_flash_status_read(pci_bar);
1614 if (status == BFA_FLASH_BUSY)
1615 status = bfa_flash_status_read(pci_bar);
1616
1617 if (status < 0)
1618 return status;
1619
1620 /* check if write-in-progress bit is cleared */
1621 if (status & BFA_FLASH_WIP_MASK)
1622 return BFA_FLASH_ERR_WIP;
1623
1624 bfa_flash_set_addr(pci_bar, offset);
1625
1626 bfa_flash_set_cmd(pci_bar, 0, (u8)len, 4, BFA_FLASH_FAST_READ);
1627
1628 return 0;
1629 }
1630
1631 /* Check flash read operation. */
1632 static u32
1633 bfa_flash_read_check(void __iomem *pci_bar)
1634 {
1635 if (bfa_flash_cmd_act_check(pci_bar))
1636 return 1;
1637
1638 return 0;
1639 }
1640
1641 /* End flash read operation. */
1642 static void
1643 bfa_flash_read_end(void __iomem *pci_bar, u32 len, char *buf)
1644 {
1645 u32 i;
1646
1647 /* read data fifo up to 32 words */
1648 for (i = 0; i < len; i += 4) {
1649 u32 w = readl(pci_bar + FLI_RDDATA_REG);
1650 *((u32 *)(buf + i)) = swab32(w);
1651 }
1652
1653 bfa_flash_fifo_flush(pci_bar);
1654 }
1655
1656 /* Perform flash raw read. */
1657
1658 #define FLASH_BLOCKING_OP_MAX 500
1659 #define FLASH_SEM_LOCK_REG 0x18820
1660
1661 static int
1662 bfa_raw_sem_get(void __iomem *bar)
1663 {
1664 int locked;
1665
1666 locked = readl(bar + FLASH_SEM_LOCK_REG);
1667
1668 return !locked;
1669 }
1670
1671 static enum bfa_status
1672 bfa_flash_sem_get(void __iomem *bar)
1673 {
1674 u32 n = FLASH_BLOCKING_OP_MAX;
1675
1676 while (!bfa_raw_sem_get(bar)) {
1677 if (--n <= 0)
1678 return BFA_STATUS_BADFLASH;
1679 mdelay(10);
1680 }
1681 return BFA_STATUS_OK;
1682 }
1683
1684 static void
1685 bfa_flash_sem_put(void __iomem *bar)
1686 {
1687 writel(0, (bar + FLASH_SEM_LOCK_REG));
1688 }
1689
1690 static enum bfa_status
1691 bfa_flash_raw_read(void __iomem *pci_bar, u32 offset, char *buf,
1692 u32 len)
1693 {
1694 u32 n;
1695 int status;
1696 u32 off, l, s, residue, fifo_sz;
1697
1698 residue = len;
1699 off = 0;
1700 fifo_sz = BFA_FLASH_FIFO_SIZE;
1701 status = bfa_flash_sem_get(pci_bar);
1702 if (status != BFA_STATUS_OK)
1703 return status;
1704
1705 while (residue) {
1706 s = offset + off;
1707 n = s / fifo_sz;
1708 l = (n + 1) * fifo_sz - s;
1709 if (l > residue)
1710 l = residue;
1711
1712 status = bfa_flash_read_start(pci_bar, offset + off, l,
1713 &buf[off]);
1714 if (status < 0) {
1715 bfa_flash_sem_put(pci_bar);
1716 return BFA_STATUS_FAILED;
1717 }
1718
1719 n = BFA_FLASH_BLOCKING_OP_MAX;
1720 while (bfa_flash_read_check(pci_bar)) {
1721 if (--n <= 0) {
1722 bfa_flash_sem_put(pci_bar);
1723 return BFA_STATUS_FAILED;
1724 }
1725 }
1726
1727 bfa_flash_read_end(pci_bar, l, &buf[off]);
1728
1729 residue -= l;
1730 off += l;
1731 }
1732 bfa_flash_sem_put(pci_bar);
1733
1734 return BFA_STATUS_OK;
1735 }
1736
1737 #define BFA_FLASH_PART_FWIMG_ADDR 0x100000 /* fw image address */
1738
1739 static enum bfa_status
1740 bfa_nw_ioc_flash_img_get_chnk(struct bfa_ioc *ioc, u32 off,
1741 u32 *fwimg)
1742 {
1743 return bfa_flash_raw_read(ioc->pcidev.pci_bar_kva,
1744 BFA_FLASH_PART_FWIMG_ADDR + (off * sizeof(u32)),
1745 (char *)fwimg, BFI_FLASH_CHUNK_SZ);
1746 }
1747
1748 static enum bfi_ioc_img_ver_cmp
1749 bfa_ioc_flash_fwver_cmp(struct bfa_ioc *ioc,
1750 struct bfi_ioc_image_hdr *base_fwhdr)
1751 {
1752 struct bfi_ioc_image_hdr *flash_fwhdr;
1753 enum bfa_status status;
1754 u32 fwimg[BFI_FLASH_CHUNK_SZ_WORDS];
1755
1756 status = bfa_nw_ioc_flash_img_get_chnk(ioc, 0, fwimg);
1757 if (status != BFA_STATUS_OK)
1758 return BFI_IOC_IMG_VER_INCOMP;
1759
1760 flash_fwhdr = (struct bfi_ioc_image_hdr *)fwimg;
1761 if (bfa_ioc_flash_fwver_valid(flash_fwhdr))
1762 return bfa_ioc_fw_ver_patch_cmp(base_fwhdr, flash_fwhdr);
1763 else
1764 return BFI_IOC_IMG_VER_INCOMP;
1765 }
1766
1767 /**
1768 * Returns TRUE if driver is willing to work with current smem f/w version.
1769 */
1770 bool
1771 bfa_nw_ioc_fwver_cmp(struct bfa_ioc *ioc, struct bfi_ioc_image_hdr *fwhdr)
1772 {
1773 struct bfi_ioc_image_hdr *drv_fwhdr;
1774 enum bfi_ioc_img_ver_cmp smem_flash_cmp, drv_smem_cmp;
1775
1776 drv_fwhdr = (struct bfi_ioc_image_hdr *)
1777 bfa_cb_image_get_chunk(bfa_ioc_asic_gen(ioc), 0);
1778
1779 /* If smem is incompatible or old, driver should not work with it. */
1780 drv_smem_cmp = bfa_ioc_fw_ver_patch_cmp(drv_fwhdr, fwhdr);
1781 if (drv_smem_cmp == BFI_IOC_IMG_VER_INCOMP ||
1782 drv_smem_cmp == BFI_IOC_IMG_VER_OLD) {
1783 return false;
1784 }
1785
1786 /* IF Flash has a better F/W than smem do not work with smem.
1787 * If smem f/w == flash f/w, as smem f/w not old | incmp, work with it.
1788 * If Flash is old or incomp work with smem iff smem f/w == drv f/w.
1789 */
1790 smem_flash_cmp = bfa_ioc_flash_fwver_cmp(ioc, fwhdr);
1791
1792 if (smem_flash_cmp == BFI_IOC_IMG_VER_BETTER)
1793 return false;
1794 else if (smem_flash_cmp == BFI_IOC_IMG_VER_SAME)
1795 return true;
1796 else
1797 return (drv_smem_cmp == BFI_IOC_IMG_VER_SAME) ?
1798 true : false;
1799 }
1800
1801 /* Return true if current running version is valid. Firmware signature and
1802 * execution context (driver/bios) must match.
1803 */
1804 static bool
1805 bfa_ioc_fwver_valid(struct bfa_ioc *ioc, u32 boot_env)
1806 {
1807 struct bfi_ioc_image_hdr fwhdr;
1808
1809 bfa_nw_ioc_fwver_get(ioc, &fwhdr);
1810 if (swab32(fwhdr.bootenv) != boot_env)
1811 return false;
1812
1813 return bfa_nw_ioc_fwver_cmp(ioc, &fwhdr);
1814 }
1815
1816 /* Conditionally flush any pending message from firmware at start. */
1817 static void
1818 bfa_ioc_msgflush(struct bfa_ioc *ioc)
1819 {
1820 u32 r32;
1821
1822 r32 = readl(ioc->ioc_regs.lpu_mbox_cmd);
1823 if (r32)
1824 writel(1, ioc->ioc_regs.lpu_mbox_cmd);
1825 }
1826
1827 static void
1828 bfa_ioc_hwinit(struct bfa_ioc *ioc, bool force)
1829 {
1830 enum bfi_ioc_state ioc_fwstate;
1831 bool fwvalid;
1832 u32 boot_env;
1833
1834 ioc_fwstate = bfa_ioc_get_cur_ioc_fwstate(ioc);
1835
1836 if (force)
1837 ioc_fwstate = BFI_IOC_UNINIT;
1838
1839 boot_env = BFI_FWBOOT_ENV_OS;
1840
1841 /**
1842 * check if firmware is valid
1843 */
1844 fwvalid = (ioc_fwstate == BFI_IOC_UNINIT) ?
1845 false : bfa_ioc_fwver_valid(ioc, boot_env);
1846
1847 if (!fwvalid) {
1848 if (bfa_ioc_boot(ioc, BFI_FWBOOT_TYPE_NORMAL, boot_env) ==
1849 BFA_STATUS_OK)
1850 bfa_ioc_poll_fwinit(ioc);
1851
1852 return;
1853 }
1854
1855 /**
1856 * If hardware initialization is in progress (initialized by other IOC),
1857 * just wait for an initialization completion interrupt.
1858 */
1859 if (ioc_fwstate == BFI_IOC_INITING) {
1860 bfa_ioc_poll_fwinit(ioc);
1861 return;
1862 }
1863
1864 /**
1865 * If IOC function is disabled and firmware version is same,
1866 * just re-enable IOC.
1867 */
1868 if (ioc_fwstate == BFI_IOC_DISABLED || ioc_fwstate == BFI_IOC_OP) {
1869 /**
1870 * When using MSI-X any pending firmware ready event should
1871 * be flushed. Otherwise MSI-X interrupts are not delivered.
1872 */
1873 bfa_ioc_msgflush(ioc);
1874 bfa_fsm_send_event(&ioc->iocpf, IOCPF_E_FWREADY);
1875 return;
1876 }
1877
1878 /**
1879 * Initialize the h/w for any other states.
1880 */
1881 if (bfa_ioc_boot(ioc, BFI_FWBOOT_TYPE_NORMAL, boot_env) ==
1882 BFA_STATUS_OK)
1883 bfa_ioc_poll_fwinit(ioc);
1884 }
1885
1886 void
1887 bfa_nw_ioc_timeout(struct bfa_ioc *ioc)
1888 {
1889 bfa_fsm_send_event(ioc, IOC_E_TIMEOUT);
1890 }
1891
1892 static void
1893 bfa_ioc_mbox_send(struct bfa_ioc *ioc, void *ioc_msg, int len)
1894 {
1895 u32 *msgp = (u32 *) ioc_msg;
1896 u32 i;
1897
1898 BUG_ON(!(len <= BFI_IOC_MSGLEN_MAX));
1899
1900 /*
1901 * first write msg to mailbox registers
1902 */
1903 for (i = 0; i < len / sizeof(u32); i++)
1904 writel(cpu_to_le32(msgp[i]),
1905 ioc->ioc_regs.hfn_mbox + i * sizeof(u32));
1906
1907 for (; i < BFI_IOC_MSGLEN_MAX / sizeof(u32); i++)
1908 writel(0, ioc->ioc_regs.hfn_mbox + i * sizeof(u32));
1909
1910 /*
1911 * write 1 to mailbox CMD to trigger LPU event
1912 */
1913 writel(1, ioc->ioc_regs.hfn_mbox_cmd);
1914 (void) readl(ioc->ioc_regs.hfn_mbox_cmd);
1915 }
1916
1917 static void
1918 bfa_ioc_send_enable(struct bfa_ioc *ioc)
1919 {
1920 struct bfi_ioc_ctrl_req enable_req;
1921
1922 bfi_h2i_set(enable_req.mh, BFI_MC_IOC, BFI_IOC_H2I_ENABLE_REQ,
1923 bfa_ioc_portid(ioc));
1924 enable_req.clscode = htons(ioc->clscode);
1925 enable_req.rsvd = htons(0);
1926 /* overflow in 2106 */
1927 enable_req.tv_sec = ntohl(ktime_get_real_seconds());
1928 bfa_ioc_mbox_send(ioc, &enable_req, sizeof(struct bfi_ioc_ctrl_req));
1929 }
1930
1931 static void
1932 bfa_ioc_send_disable(struct bfa_ioc *ioc)
1933 {
1934 struct bfi_ioc_ctrl_req disable_req;
1935
1936 bfi_h2i_set(disable_req.mh, BFI_MC_IOC, BFI_IOC_H2I_DISABLE_REQ,
1937 bfa_ioc_portid(ioc));
1938 disable_req.clscode = htons(ioc->clscode);
1939 disable_req.rsvd = htons(0);
1940 /* overflow in 2106 */
1941 disable_req.tv_sec = ntohl(ktime_get_real_seconds());
1942 bfa_ioc_mbox_send(ioc, &disable_req, sizeof(struct bfi_ioc_ctrl_req));
1943 }
1944
1945 static void
1946 bfa_ioc_send_getattr(struct bfa_ioc *ioc)
1947 {
1948 struct bfi_ioc_getattr_req attr_req;
1949
1950 bfi_h2i_set(attr_req.mh, BFI_MC_IOC, BFI_IOC_H2I_GETATTR_REQ,
1951 bfa_ioc_portid(ioc));
1952 bfa_dma_be_addr_set(attr_req.attr_addr, ioc->attr_dma.pa);
1953 bfa_ioc_mbox_send(ioc, &attr_req, sizeof(attr_req));
1954 }
1955
1956 void
1957 bfa_nw_ioc_hb_check(struct bfa_ioc *ioc)
1958 {
1959 u32 hb_count;
1960
1961 hb_count = readl(ioc->ioc_regs.heartbeat);
1962 if (ioc->hb_count == hb_count) {
1963 bfa_ioc_recover(ioc);
1964 return;
1965 } else {
1966 ioc->hb_count = hb_count;
1967 }
1968
1969 bfa_ioc_mbox_poll(ioc);
1970 mod_timer(&ioc->hb_timer, jiffies +
1971 msecs_to_jiffies(BFA_IOC_HB_TOV));
1972 }
1973
1974 static void
1975 bfa_ioc_hb_monitor(struct bfa_ioc *ioc)
1976 {
1977 ioc->hb_count = readl(ioc->ioc_regs.heartbeat);
1978 mod_timer(&ioc->hb_timer, jiffies +
1979 msecs_to_jiffies(BFA_IOC_HB_TOV));
1980 }
1981
1982 static void
1983 bfa_ioc_hb_stop(struct bfa_ioc *ioc)
1984 {
1985 del_timer(&ioc->hb_timer);
1986 }
1987
1988 /* Initiate a full firmware download. */
1989 static enum bfa_status
1990 bfa_ioc_download_fw(struct bfa_ioc *ioc, u32 boot_type,
1991 u32 boot_env)
1992 {
1993 u32 *fwimg;
1994 u32 pgnum;
1995 u32 loff = 0;
1996 u32 chunkno = 0;
1997 u32 i;
1998 u32 asicmode;
1999 u32 fwimg_size;
2000 u32 fwimg_buf[BFI_FLASH_CHUNK_SZ_WORDS];
2001 enum bfa_status status;
2002
2003 if (boot_env == BFI_FWBOOT_ENV_OS &&
2004 boot_type == BFI_FWBOOT_TYPE_FLASH) {
2005 fwimg_size = BFI_FLASH_IMAGE_SZ/sizeof(u32);
2006
2007 status = bfa_nw_ioc_flash_img_get_chnk(ioc,
2008 BFA_IOC_FLASH_CHUNK_ADDR(chunkno), fwimg_buf);
2009 if (status != BFA_STATUS_OK)
2010 return status;
2011
2012 fwimg = fwimg_buf;
2013 } else {
2014 fwimg_size = bfa_cb_image_get_size(bfa_ioc_asic_gen(ioc));
2015 fwimg = bfa_cb_image_get_chunk(bfa_ioc_asic_gen(ioc),
2016 BFA_IOC_FLASH_CHUNK_ADDR(chunkno));
2017 }
2018
2019 pgnum = bfa_ioc_smem_pgnum(ioc, loff);
2020
2021 writel(pgnum, ioc->ioc_regs.host_page_num_fn);
2022
2023 for (i = 0; i < fwimg_size; i++) {
2024 if (BFA_IOC_FLASH_CHUNK_NO(i) != chunkno) {
2025 chunkno = BFA_IOC_FLASH_CHUNK_NO(i);
2026 if (boot_env == BFI_FWBOOT_ENV_OS &&
2027 boot_type == BFI_FWBOOT_TYPE_FLASH) {
2028 status = bfa_nw_ioc_flash_img_get_chnk(ioc,
2029 BFA_IOC_FLASH_CHUNK_ADDR(chunkno),
2030 fwimg_buf);
2031 if (status != BFA_STATUS_OK)
2032 return status;
2033
2034 fwimg = fwimg_buf;
2035 } else {
2036 fwimg = bfa_cb_image_get_chunk(
2037 bfa_ioc_asic_gen(ioc),
2038 BFA_IOC_FLASH_CHUNK_ADDR(chunkno));
2039 }
2040 }
2041
2042 /**
2043 * write smem
2044 */
2045 writel(swab32(fwimg[BFA_IOC_FLASH_OFFSET_IN_CHUNK(i)]),
2046 ioc->ioc_regs.smem_page_start + loff);
2047
2048 loff += sizeof(u32);
2049
2050 /**
2051 * handle page offset wrap around
2052 */
2053 loff = PSS_SMEM_PGOFF(loff);
2054 if (loff == 0) {
2055 pgnum++;
2056 writel(pgnum,
2057 ioc->ioc_regs.host_page_num_fn);
2058 }
2059 }
2060
2061 writel(bfa_ioc_smem_pgnum(ioc, 0),
2062 ioc->ioc_regs.host_page_num_fn);
2063
2064 /*
2065 * Set boot type, env and device mode at the end.
2066 */
2067 if (boot_env == BFI_FWBOOT_ENV_OS &&
2068 boot_type == BFI_FWBOOT_TYPE_FLASH) {
2069 boot_type = BFI_FWBOOT_TYPE_NORMAL;
2070 }
2071 asicmode = BFI_FWBOOT_DEVMODE(ioc->asic_gen, ioc->asic_mode,
2072 ioc->port0_mode, ioc->port1_mode);
2073 writel(asicmode, ((ioc->ioc_regs.smem_page_start)
2074 + BFI_FWBOOT_DEVMODE_OFF));
2075 writel(boot_type, ((ioc->ioc_regs.smem_page_start)
2076 + (BFI_FWBOOT_TYPE_OFF)));
2077 writel(boot_env, ((ioc->ioc_regs.smem_page_start)
2078 + (BFI_FWBOOT_ENV_OFF)));
2079 return BFA_STATUS_OK;
2080 }
2081
2082 static void
2083 bfa_ioc_reset(struct bfa_ioc *ioc, bool force)
2084 {
2085 bfa_ioc_hwinit(ioc, force);
2086 }
2087
2088 /* BFA ioc enable reply by firmware */
2089 static void
2090 bfa_ioc_enable_reply(struct bfa_ioc *ioc, enum bfa_mode port_mode,
2091 u8 cap_bm)
2092 {
2093 struct bfa_iocpf *iocpf = &ioc->iocpf;
2094
2095 ioc->port_mode = ioc->port_mode_cfg = port_mode;
2096 ioc->ad_cap_bm = cap_bm;
2097 bfa_fsm_send_event(iocpf, IOCPF_E_FWRSP_ENABLE);
2098 }
2099
2100 /* Update BFA configuration from firmware configuration. */
2101 static void
2102 bfa_ioc_getattr_reply(struct bfa_ioc *ioc)
2103 {
2104 struct bfi_ioc_attr *attr = ioc->attr;
2105
2106 attr->adapter_prop = ntohl(attr->adapter_prop);
2107 attr->card_type = ntohl(attr->card_type);
2108 attr->maxfrsize = ntohs(attr->maxfrsize);
2109
2110 bfa_fsm_send_event(ioc, IOC_E_FWRSP_GETATTR);
2111 }
2112
2113 /* Attach time initialization of mbox logic. */
2114 static void
2115 bfa_ioc_mbox_attach(struct bfa_ioc *ioc)
2116 {
2117 struct bfa_ioc_mbox_mod *mod = &ioc->mbox_mod;
2118 int mc;
2119
2120 INIT_LIST_HEAD(&mod->cmd_q);
2121 for (mc = 0; mc < BFI_MC_MAX; mc++) {
2122 mod->mbhdlr[mc].cbfn = NULL;
2123 mod->mbhdlr[mc].cbarg = ioc->bfa;
2124 }
2125 }
2126
2127 /* Mbox poll timer -- restarts any pending mailbox requests. */
2128 static void
2129 bfa_ioc_mbox_poll(struct bfa_ioc *ioc)
2130 {
2131 struct bfa_ioc_mbox_mod *mod = &ioc->mbox_mod;
2132 struct bfa_mbox_cmd *cmd;
2133 bfa_mbox_cmd_cbfn_t cbfn;
2134 void *cbarg;
2135 u32 stat;
2136
2137 /**
2138 * If no command pending, do nothing
2139 */
2140 if (list_empty(&mod->cmd_q))
2141 return;
2142
2143 /**
2144 * If previous command is not yet fetched by firmware, do nothing
2145 */
2146 stat = readl(ioc->ioc_regs.hfn_mbox_cmd);
2147 if (stat)
2148 return;
2149
2150 /**
2151 * Enqueue command to firmware.
2152 */
2153 cmd = list_first_entry(&mod->cmd_q, struct bfa_mbox_cmd, qe);
2154 list_del(&cmd->qe);
2155 bfa_ioc_mbox_send(ioc, cmd->msg, sizeof(cmd->msg));
2156
2157 /**
2158 * Give a callback to the client, indicating that the command is sent
2159 */
2160 if (cmd->cbfn) {
2161 cbfn = cmd->cbfn;
2162 cbarg = cmd->cbarg;
2163 cmd->cbfn = NULL;
2164 cbfn(cbarg);
2165 }
2166 }
2167
2168 /* Cleanup any pending requests. */
2169 static void
2170 bfa_ioc_mbox_flush(struct bfa_ioc *ioc)
2171 {
2172 struct bfa_ioc_mbox_mod *mod = &ioc->mbox_mod;
2173 struct bfa_mbox_cmd *cmd;
2174
2175 while (!list_empty(&mod->cmd_q)) {
2176 cmd = list_first_entry(&mod->cmd_q, struct bfa_mbox_cmd, qe);
2177 list_del(&cmd->qe);
2178 }
2179 }
2180
2181 /**
2182 * bfa_nw_ioc_smem_read - Read data from SMEM to host through PCI memmap
2183 *
2184 * @ioc: memory for IOC
2185 * @tbuf: app memory to store data from smem
2186 * @soff: smem offset
2187 * @sz: size of smem in bytes
2188 */
2189 static int
2190 bfa_nw_ioc_smem_read(struct bfa_ioc *ioc, void *tbuf, u32 soff, u32 sz)
2191 {
2192 u32 pgnum, loff, r32;
2193 int i, len;
2194 u32 *buf = tbuf;
2195
2196 pgnum = PSS_SMEM_PGNUM(ioc->ioc_regs.smem_pg0, soff);
2197 loff = PSS_SMEM_PGOFF(soff);
2198
2199 /*
2200 * Hold semaphore to serialize pll init and fwtrc.
2201 */
2202 if (!bfa_nw_ioc_sem_get(ioc->ioc_regs.ioc_init_sem_reg))
2203 return 1;
2204
2205 writel(pgnum, ioc->ioc_regs.host_page_num_fn);
2206
2207 len = sz/sizeof(u32);
2208 for (i = 0; i < len; i++) {
2209 r32 = swab32(readl(loff + ioc->ioc_regs.smem_page_start));
2210 buf[i] = be32_to_cpu(r32);
2211 loff += sizeof(u32);
2212
2213 /**
2214 * handle page offset wrap around
2215 */
2216 loff = PSS_SMEM_PGOFF(loff);
2217 if (loff == 0) {
2218 pgnum++;
2219 writel(pgnum, ioc->ioc_regs.host_page_num_fn);
2220 }
2221 }
2222
2223 writel(PSS_SMEM_PGNUM(ioc->ioc_regs.smem_pg0, 0),
2224 ioc->ioc_regs.host_page_num_fn);
2225
2226 /*
2227 * release semaphore
2228 */
2229 readl(ioc->ioc_regs.ioc_init_sem_reg);
2230 writel(1, ioc->ioc_regs.ioc_init_sem_reg);
2231 return 0;
2232 }
2233
2234 /* Retrieve saved firmware trace from a prior IOC failure. */
2235 int
2236 bfa_nw_ioc_debug_fwtrc(struct bfa_ioc *ioc, void *trcdata, int *trclen)
2237 {
2238 u32 loff = BFI_IOC_TRC_OFF + BNA_DBG_FWTRC_LEN * ioc->port_id;
2239 int tlen, status = 0;
2240
2241 tlen = *trclen;
2242 if (tlen > BNA_DBG_FWTRC_LEN)
2243 tlen = BNA_DBG_FWTRC_LEN;
2244
2245 status = bfa_nw_ioc_smem_read(ioc, trcdata, loff, tlen);
2246 *trclen = tlen;
2247 return status;
2248 }
2249
2250 /* Save firmware trace if configured. */
2251 static void
2252 bfa_nw_ioc_debug_save_ftrc(struct bfa_ioc *ioc)
2253 {
2254 int tlen;
2255
2256 if (ioc->dbg_fwsave_once) {
2257 ioc->dbg_fwsave_once = false;
2258 if (ioc->dbg_fwsave_len) {
2259 tlen = ioc->dbg_fwsave_len;
2260 bfa_nw_ioc_debug_fwtrc(ioc, ioc->dbg_fwsave, &tlen);
2261 }
2262 }
2263 }
2264
2265 /* Retrieve saved firmware trace from a prior IOC failure. */
2266 int
2267 bfa_nw_ioc_debug_fwsave(struct bfa_ioc *ioc, void *trcdata, int *trclen)
2268 {
2269 int tlen;
2270
2271 if (ioc->dbg_fwsave_len == 0)
2272 return BFA_STATUS_ENOFSAVE;
2273
2274 tlen = *trclen;
2275 if (tlen > ioc->dbg_fwsave_len)
2276 tlen = ioc->dbg_fwsave_len;
2277
2278 memcpy(trcdata, ioc->dbg_fwsave, tlen);
2279 *trclen = tlen;
2280 return BFA_STATUS_OK;
2281 }
2282
2283 static void
2284 bfa_ioc_fail_notify(struct bfa_ioc *ioc)
2285 {
2286 /**
2287 * Notify driver and common modules registered for notification.
2288 */
2289 ioc->cbfn->hbfail_cbfn(ioc->bfa);
2290 bfa_ioc_event_notify(ioc, BFA_IOC_E_FAILED);
2291 bfa_nw_ioc_debug_save_ftrc(ioc);
2292 }
2293
2294 /* IOCPF to IOC interface */
2295 static void
2296 bfa_ioc_pf_enabled(struct bfa_ioc *ioc)
2297 {
2298 bfa_fsm_send_event(ioc, IOC_E_ENABLED);
2299 }
2300
2301 static void
2302 bfa_ioc_pf_disabled(struct bfa_ioc *ioc)
2303 {
2304 bfa_fsm_send_event(ioc, IOC_E_DISABLED);
2305 }
2306
2307 static void
2308 bfa_ioc_pf_failed(struct bfa_ioc *ioc)
2309 {
2310 bfa_fsm_send_event(ioc, IOC_E_PFFAILED);
2311 }
2312
2313 static void
2314 bfa_ioc_pf_hwfailed(struct bfa_ioc *ioc)
2315 {
2316 bfa_fsm_send_event(ioc, IOC_E_HWFAILED);
2317 }
2318
2319 static void
2320 bfa_ioc_pf_fwmismatch(struct bfa_ioc *ioc)
2321 {
2322 /**
2323 * Provide enable completion callback and AEN notification.
2324 */
2325 ioc->cbfn->enable_cbfn(ioc->bfa, BFA_STATUS_IOC_FAILURE);
2326 }
2327
2328 /* IOC public */
2329 static enum bfa_status
2330 bfa_ioc_pll_init(struct bfa_ioc *ioc)
2331 {
2332 /*
2333 * Hold semaphore so that nobody can access the chip during init.
2334 */
2335 bfa_nw_ioc_sem_get(ioc->ioc_regs.ioc_init_sem_reg);
2336
2337 bfa_ioc_pll_init_asic(ioc);
2338
2339 ioc->pllinit = true;
2340
2341 /* Initialize LMEM */
2342 bfa_ioc_lmem_init(ioc);
2343
2344 /*
2345 * release semaphore.
2346 */
2347 bfa_nw_ioc_sem_release(ioc->ioc_regs.ioc_init_sem_reg);
2348
2349 return BFA_STATUS_OK;
2350 }
2351
2352 /* Interface used by diag module to do firmware boot with memory test
2353 * as the entry vector.
2354 */
2355 static enum bfa_status
2356 bfa_ioc_boot(struct bfa_ioc *ioc, enum bfi_fwboot_type boot_type,
2357 u32 boot_env)
2358 {
2359 struct bfi_ioc_image_hdr *drv_fwhdr;
2360 enum bfa_status status;
2361 bfa_ioc_stats(ioc, ioc_boots);
2362
2363 if (bfa_ioc_pll_init(ioc) != BFA_STATUS_OK)
2364 return BFA_STATUS_FAILED;
2365 if (boot_env == BFI_FWBOOT_ENV_OS &&
2366 boot_type == BFI_FWBOOT_TYPE_NORMAL) {
2367 drv_fwhdr = (struct bfi_ioc_image_hdr *)
2368 bfa_cb_image_get_chunk(bfa_ioc_asic_gen(ioc), 0);
2369 /* Work with Flash iff flash f/w is better than driver f/w.
2370 * Otherwise push drivers firmware.
2371 */
2372 if (bfa_ioc_flash_fwver_cmp(ioc, drv_fwhdr) ==
2373 BFI_IOC_IMG_VER_BETTER)
2374 boot_type = BFI_FWBOOT_TYPE_FLASH;
2375 }
2376
2377 /**
2378 * Initialize IOC state of all functions on a chip reset.
2379 */
2380 if (boot_type == BFI_FWBOOT_TYPE_MEMTEST) {
2381 bfa_ioc_set_cur_ioc_fwstate(ioc, BFI_IOC_MEMTEST);
2382 bfa_ioc_set_alt_ioc_fwstate(ioc, BFI_IOC_MEMTEST);
2383 } else {
2384 bfa_ioc_set_cur_ioc_fwstate(ioc, BFI_IOC_INITING);
2385 bfa_ioc_set_alt_ioc_fwstate(ioc, BFI_IOC_INITING);
2386 }
2387
2388 bfa_ioc_msgflush(ioc);
2389 status = bfa_ioc_download_fw(ioc, boot_type, boot_env);
2390 if (status == BFA_STATUS_OK)
2391 bfa_ioc_lpu_start(ioc);
2392 else
2393 bfa_fsm_send_event(&ioc->iocpf, IOCPF_E_TIMEOUT);
2394
2395 return status;
2396 }
2397
2398 /* Enable/disable IOC failure auto recovery. */
2399 void
2400 bfa_nw_ioc_auto_recover(bool auto_recover)
2401 {
2402 bfa_nw_auto_recover = auto_recover;
2403 }
2404
2405 static bool
2406 bfa_ioc_msgget(struct bfa_ioc *ioc, void *mbmsg)
2407 {
2408 u32 *msgp = mbmsg;
2409 u32 r32;
2410 int i;
2411
2412 r32 = readl(ioc->ioc_regs.lpu_mbox_cmd);
2413 if ((r32 & 1) == 0)
2414 return false;
2415
2416 /**
2417 * read the MBOX msg
2418 */
2419 for (i = 0; i < (sizeof(union bfi_ioc_i2h_msg_u) / sizeof(u32));
2420 i++) {
2421 r32 = readl(ioc->ioc_regs.lpu_mbox +
2422 i * sizeof(u32));
2423 msgp[i] = htonl(r32);
2424 }
2425
2426 /**
2427 * turn off mailbox interrupt by clearing mailbox status
2428 */
2429 writel(1, ioc->ioc_regs.lpu_mbox_cmd);
2430 readl(ioc->ioc_regs.lpu_mbox_cmd);
2431
2432 return true;
2433 }
2434
2435 static void
2436 bfa_ioc_isr(struct bfa_ioc *ioc, struct bfi_mbmsg *m)
2437 {
2438 union bfi_ioc_i2h_msg_u *msg;
2439 struct bfa_iocpf *iocpf = &ioc->iocpf;
2440
2441 msg = (union bfi_ioc_i2h_msg_u *) m;
2442
2443 bfa_ioc_stats(ioc, ioc_isrs);
2444
2445 switch (msg->mh.msg_id) {
2446 case BFI_IOC_I2H_HBEAT:
2447 break;
2448
2449 case BFI_IOC_I2H_ENABLE_REPLY:
2450 bfa_ioc_enable_reply(ioc,
2451 (enum bfa_mode)msg->fw_event.port_mode,
2452 msg->fw_event.cap_bm);
2453 break;
2454
2455 case BFI_IOC_I2H_DISABLE_REPLY:
2456 bfa_fsm_send_event(iocpf, IOCPF_E_FWRSP_DISABLE);
2457 break;
2458
2459 case BFI_IOC_I2H_GETATTR_REPLY:
2460 bfa_ioc_getattr_reply(ioc);
2461 break;
2462
2463 default:
2464 BUG_ON(1);
2465 }
2466 }
2467
2468 /**
2469 * bfa_nw_ioc_attach - IOC attach time initialization and setup.
2470 *
2471 * @ioc: memory for IOC
2472 * @bfa: driver instance structure
2473 */
2474 void
2475 bfa_nw_ioc_attach(struct bfa_ioc *ioc, void *bfa, struct bfa_ioc_cbfn *cbfn)
2476 {
2477 ioc->bfa = bfa;
2478 ioc->cbfn = cbfn;
2479 ioc->fcmode = false;
2480 ioc->pllinit = false;
2481 ioc->dbg_fwsave_once = true;
2482 ioc->iocpf.ioc = ioc;
2483
2484 bfa_ioc_mbox_attach(ioc);
2485 INIT_LIST_HEAD(&ioc->notify_q);
2486
2487 bfa_fsm_set_state(ioc, bfa_ioc_sm_uninit);
2488 bfa_fsm_send_event(ioc, IOC_E_RESET);
2489 }
2490
2491 /* Driver detach time IOC cleanup. */
2492 void
2493 bfa_nw_ioc_detach(struct bfa_ioc *ioc)
2494 {
2495 bfa_fsm_send_event(ioc, IOC_E_DETACH);
2496
2497 /* Done with detach, empty the notify_q. */
2498 INIT_LIST_HEAD(&ioc->notify_q);
2499 }
2500
2501 /**
2502 * bfa_nw_ioc_pci_init - Setup IOC PCI properties.
2503 *
2504 * @pcidev: PCI device information for this IOC
2505 */
2506 void
2507 bfa_nw_ioc_pci_init(struct bfa_ioc *ioc, struct bfa_pcidev *pcidev,
2508 enum bfi_pcifn_class clscode)
2509 {
2510 ioc->clscode = clscode;
2511 ioc->pcidev = *pcidev;
2512
2513 /**
2514 * Initialize IOC and device personality
2515 */
2516 ioc->port0_mode = ioc->port1_mode = BFI_PORT_MODE_FC;
2517 ioc->asic_mode = BFI_ASIC_MODE_FC;
2518
2519 switch (pcidev->device_id) {
2520 case PCI_DEVICE_ID_BROCADE_CT:
2521 ioc->asic_gen = BFI_ASIC_GEN_CT;
2522 ioc->port0_mode = ioc->port1_mode = BFI_PORT_MODE_ETH;
2523 ioc->asic_mode = BFI_ASIC_MODE_ETH;
2524 ioc->port_mode = ioc->port_mode_cfg = BFA_MODE_CNA;
2525 ioc->ad_cap_bm = BFA_CM_CNA;
2526 break;
2527
2528 case BFA_PCI_DEVICE_ID_CT2:
2529 ioc->asic_gen = BFI_ASIC_GEN_CT2;
2530 if (clscode == BFI_PCIFN_CLASS_FC &&
2531 pcidev->ssid == BFA_PCI_CT2_SSID_FC) {
2532 ioc->asic_mode = BFI_ASIC_MODE_FC16;
2533 ioc->fcmode = true;
2534 ioc->port_mode = ioc->port_mode_cfg = BFA_MODE_HBA;
2535 ioc->ad_cap_bm = BFA_CM_HBA;
2536 } else {
2537 ioc->port0_mode = ioc->port1_mode = BFI_PORT_MODE_ETH;
2538 ioc->asic_mode = BFI_ASIC_MODE_ETH;
2539 if (pcidev->ssid == BFA_PCI_CT2_SSID_FCoE) {
2540 ioc->port_mode =
2541 ioc->port_mode_cfg = BFA_MODE_CNA;
2542 ioc->ad_cap_bm = BFA_CM_CNA;
2543 } else {
2544 ioc->port_mode =
2545 ioc->port_mode_cfg = BFA_MODE_NIC;
2546 ioc->ad_cap_bm = BFA_CM_NIC;
2547 }
2548 }
2549 break;
2550
2551 default:
2552 BUG_ON(1);
2553 }
2554
2555 /**
2556 * Set asic specific interfaces.
2557 */
2558 if (ioc->asic_gen == BFI_ASIC_GEN_CT)
2559 bfa_nw_ioc_set_ct_hwif(ioc);
2560 else {
2561 WARN_ON(ioc->asic_gen != BFI_ASIC_GEN_CT2);
2562 bfa_nw_ioc_set_ct2_hwif(ioc);
2563 bfa_nw_ioc_ct2_poweron(ioc);
2564 }
2565
2566 bfa_ioc_map_port(ioc);
2567 bfa_ioc_reg_init(ioc);
2568 }
2569
2570 /**
2571 * bfa_nw_ioc_mem_claim - Initialize IOC dma memory
2572 *
2573 * @dm_kva: kernel virtual address of IOC dma memory
2574 * @dm_pa: physical address of IOC dma memory
2575 */
2576 void
2577 bfa_nw_ioc_mem_claim(struct bfa_ioc *ioc, u8 *dm_kva, u64 dm_pa)
2578 {
2579 /**
2580 * dma memory for firmware attribute
2581 */
2582 ioc->attr_dma.kva = dm_kva;
2583 ioc->attr_dma.pa = dm_pa;
2584 ioc->attr = (struct bfi_ioc_attr *) dm_kva;
2585 }
2586
2587 /* Return size of dma memory required. */
2588 u32
2589 bfa_nw_ioc_meminfo(void)
2590 {
2591 return roundup(sizeof(struct bfi_ioc_attr), BFA_DMA_ALIGN_SZ);
2592 }
2593
2594 void
2595 bfa_nw_ioc_enable(struct bfa_ioc *ioc)
2596 {
2597 bfa_ioc_stats(ioc, ioc_enables);
2598 ioc->dbg_fwsave_once = true;
2599
2600 bfa_fsm_send_event(ioc, IOC_E_ENABLE);
2601 }
2602
2603 void
2604 bfa_nw_ioc_disable(struct bfa_ioc *ioc)
2605 {
2606 bfa_ioc_stats(ioc, ioc_disables);
2607 bfa_fsm_send_event(ioc, IOC_E_DISABLE);
2608 }
2609
2610 /* Initialize memory for saving firmware trace. */
2611 void
2612 bfa_nw_ioc_debug_memclaim(struct bfa_ioc *ioc, void *dbg_fwsave)
2613 {
2614 ioc->dbg_fwsave = dbg_fwsave;
2615 ioc->dbg_fwsave_len = ioc->iocpf.auto_recover ? BNA_DBG_FWTRC_LEN : 0;
2616 }
2617
2618 static u32
2619 bfa_ioc_smem_pgnum(struct bfa_ioc *ioc, u32 fmaddr)
2620 {
2621 return PSS_SMEM_PGNUM(ioc->ioc_regs.smem_pg0, fmaddr);
2622 }
2623
2624 /* Register mailbox message handler function, to be called by common modules */
2625 void
2626 bfa_nw_ioc_mbox_regisr(struct bfa_ioc *ioc, enum bfi_mclass mc,
2627 bfa_ioc_mbox_mcfunc_t cbfn, void *cbarg)
2628 {
2629 struct bfa_ioc_mbox_mod *mod = &ioc->mbox_mod;
2630
2631 mod->mbhdlr[mc].cbfn = cbfn;
2632 mod->mbhdlr[mc].cbarg = cbarg;
2633 }
2634
2635 /**
2636 * bfa_nw_ioc_mbox_queue - Queue a mailbox command request to firmware.
2637 *
2638 * @ioc: IOC instance
2639 * @cmd: Mailbox command
2640 *
2641 * Waits if mailbox is busy. Responsibility of caller to serialize
2642 */
2643 bool
2644 bfa_nw_ioc_mbox_queue(struct bfa_ioc *ioc, struct bfa_mbox_cmd *cmd,
2645 bfa_mbox_cmd_cbfn_t cbfn, void *cbarg)
2646 {
2647 struct bfa_ioc_mbox_mod *mod = &ioc->mbox_mod;
2648 u32 stat;
2649
2650 cmd->cbfn = cbfn;
2651 cmd->cbarg = cbarg;
2652
2653 /**
2654 * If a previous command is pending, queue new command
2655 */
2656 if (!list_empty(&mod->cmd_q)) {
2657 list_add_tail(&cmd->qe, &mod->cmd_q);
2658 return true;
2659 }
2660
2661 /**
2662 * If mailbox is busy, queue command for poll timer
2663 */
2664 stat = readl(ioc->ioc_regs.hfn_mbox_cmd);
2665 if (stat) {
2666 list_add_tail(&cmd->qe, &mod->cmd_q);
2667 return true;
2668 }
2669
2670 /**
2671 * mailbox is free -- queue command to firmware
2672 */
2673 bfa_ioc_mbox_send(ioc, cmd->msg, sizeof(cmd->msg));
2674
2675 return false;
2676 }
2677
2678 /* Handle mailbox interrupts */
2679 void
2680 bfa_nw_ioc_mbox_isr(struct bfa_ioc *ioc)
2681 {
2682 struct bfa_ioc_mbox_mod *mod = &ioc->mbox_mod;
2683 struct bfi_mbmsg m;
2684 int mc;
2685
2686 if (bfa_ioc_msgget(ioc, &m)) {
2687 /**
2688 * Treat IOC message class as special.
2689 */
2690 mc = m.mh.msg_class;
2691 if (mc == BFI_MC_IOC) {
2692 bfa_ioc_isr(ioc, &m);
2693 return;
2694 }
2695
2696 if ((mc >= BFI_MC_MAX) || (mod->mbhdlr[mc].cbfn == NULL))
2697 return;
2698
2699 mod->mbhdlr[mc].cbfn(mod->mbhdlr[mc].cbarg, &m);
2700 }
2701
2702 bfa_ioc_lpu_read_stat(ioc);
2703
2704 /**
2705 * Try to send pending mailbox commands
2706 */
2707 bfa_ioc_mbox_poll(ioc);
2708 }
2709
2710 void
2711 bfa_nw_ioc_error_isr(struct bfa_ioc *ioc)
2712 {
2713 bfa_ioc_stats(ioc, ioc_hbfails);
2714 bfa_ioc_stats_hb_count(ioc, ioc->hb_count);
2715 bfa_fsm_send_event(ioc, IOC_E_HWERROR);
2716 }
2717
2718 /* return true if IOC is disabled */
2719 bool
2720 bfa_nw_ioc_is_disabled(struct bfa_ioc *ioc)
2721 {
2722 return bfa_fsm_cmp_state(ioc, bfa_ioc_sm_disabling) ||
2723 bfa_fsm_cmp_state(ioc, bfa_ioc_sm_disabled);
2724 }
2725
2726 /* return true if IOC is operational */
2727 bool
2728 bfa_nw_ioc_is_operational(struct bfa_ioc *ioc)
2729 {
2730 return bfa_fsm_cmp_state(ioc, bfa_ioc_sm_op);
2731 }
2732
2733 /* Add to IOC heartbeat failure notification queue. To be used by common
2734 * modules such as cee, port, diag.
2735 */
2736 void
2737 bfa_nw_ioc_notify_register(struct bfa_ioc *ioc,
2738 struct bfa_ioc_notify *notify)
2739 {
2740 list_add_tail(&notify->qe, &ioc->notify_q);
2741 }
2742
2743 #define BFA_MFG_NAME "QLogic"
2744 static void
2745 bfa_ioc_get_adapter_attr(struct bfa_ioc *ioc,
2746 struct bfa_adapter_attr *ad_attr)
2747 {
2748 struct bfi_ioc_attr *ioc_attr;
2749
2750 ioc_attr = ioc->attr;
2751
2752 bfa_ioc_get_adapter_serial_num(ioc, ad_attr->serial_num);
2753 bfa_ioc_get_adapter_fw_ver(ioc, ad_attr->fw_ver);
2754 bfa_ioc_get_adapter_optrom_ver(ioc, ad_attr->optrom_ver);
2755 bfa_ioc_get_adapter_manufacturer(ioc, ad_attr->manufacturer);
2756 memcpy(&ad_attr->vpd, &ioc_attr->vpd,
2757 sizeof(struct bfa_mfg_vpd));
2758
2759 ad_attr->nports = bfa_ioc_get_nports(ioc);
2760 ad_attr->max_speed = bfa_ioc_speed_sup(ioc);
2761
2762 bfa_ioc_get_adapter_model(ioc, ad_attr->model);
2763 /* For now, model descr uses same model string */
2764 bfa_ioc_get_adapter_model(ioc, ad_attr->model_descr);
2765
2766 ad_attr->card_type = ioc_attr->card_type;
2767 ad_attr->is_mezz = bfa_mfg_is_mezz(ioc_attr->card_type);
2768
2769 if (BFI_ADAPTER_IS_SPECIAL(ioc_attr->adapter_prop))
2770 ad_attr->prototype = 1;
2771 else
2772 ad_attr->prototype = 0;
2773
2774 ad_attr->pwwn = bfa_ioc_get_pwwn(ioc);
2775 bfa_nw_ioc_get_mac(ioc, ad_attr->mac);
2776
2777 ad_attr->pcie_gen = ioc_attr->pcie_gen;
2778 ad_attr->pcie_lanes = ioc_attr->pcie_lanes;
2779 ad_attr->pcie_lanes_orig = ioc_attr->pcie_lanes_orig;
2780 ad_attr->asic_rev = ioc_attr->asic_rev;
2781
2782 bfa_ioc_get_pci_chip_rev(ioc, ad_attr->hw_ver);
2783 }
2784
2785 static enum bfa_ioc_type
2786 bfa_ioc_get_type(struct bfa_ioc *ioc)
2787 {
2788 if (ioc->clscode == BFI_PCIFN_CLASS_ETH)
2789 return BFA_IOC_TYPE_LL;
2790
2791 BUG_ON(!(ioc->clscode == BFI_PCIFN_CLASS_FC));
2792
2793 return (ioc->attr->port_mode == BFI_PORT_MODE_FC)
2794 ? BFA_IOC_TYPE_FC : BFA_IOC_TYPE_FCoE;
2795 }
2796
2797 static void
2798 bfa_ioc_get_adapter_serial_num(struct bfa_ioc *ioc, char *serial_num)
2799 {
2800 memcpy(serial_num,
2801 (void *)ioc->attr->brcd_serialnum,
2802 BFA_ADAPTER_SERIAL_NUM_LEN);
2803 }
2804
2805 static void
2806 bfa_ioc_get_adapter_fw_ver(struct bfa_ioc *ioc, char *fw_ver)
2807 {
2808 memcpy(fw_ver, ioc->attr->fw_version, BFA_VERSION_LEN);
2809 }
2810
2811 static void
2812 bfa_ioc_get_pci_chip_rev(struct bfa_ioc *ioc, char *chip_rev)
2813 {
2814 BUG_ON(!(chip_rev));
2815
2816 memset(chip_rev, 0, BFA_IOC_CHIP_REV_LEN);
2817
2818 chip_rev[0] = 'R';
2819 chip_rev[1] = 'e';
2820 chip_rev[2] = 'v';
2821 chip_rev[3] = '-';
2822 chip_rev[4] = ioc->attr->asic_rev;
2823 chip_rev[5] = '\0';
2824 }
2825
2826 static void
2827 bfa_ioc_get_adapter_optrom_ver(struct bfa_ioc *ioc, char *optrom_ver)
2828 {
2829 memcpy(optrom_ver, ioc->attr->optrom_version,
2830 BFA_VERSION_LEN);
2831 }
2832
2833 static void
2834 bfa_ioc_get_adapter_manufacturer(struct bfa_ioc *ioc, char *manufacturer)
2835 {
2836 strncpy(manufacturer, BFA_MFG_NAME, BFA_ADAPTER_MFG_NAME_LEN);
2837 }
2838
2839 static void
2840 bfa_ioc_get_adapter_model(struct bfa_ioc *ioc, char *model)
2841 {
2842 struct bfi_ioc_attr *ioc_attr;
2843
2844 BUG_ON(!(model));
2845 memset(model, 0, BFA_ADAPTER_MODEL_NAME_LEN);
2846
2847 ioc_attr = ioc->attr;
2848
2849 snprintf(model, BFA_ADAPTER_MODEL_NAME_LEN, "%s-%u",
2850 BFA_MFG_NAME, ioc_attr->card_type);
2851 }
2852
2853 static enum bfa_ioc_state
2854 bfa_ioc_get_state(struct bfa_ioc *ioc)
2855 {
2856 enum bfa_iocpf_state iocpf_st;
2857 enum bfa_ioc_state ioc_st = bfa_sm_to_state(ioc_sm_table, ioc->fsm);
2858
2859 if (ioc_st == BFA_IOC_ENABLING ||
2860 ioc_st == BFA_IOC_FAIL || ioc_st == BFA_IOC_INITFAIL) {
2861
2862 iocpf_st = bfa_sm_to_state(iocpf_sm_table, ioc->iocpf.fsm);
2863
2864 switch (iocpf_st) {
2865 case BFA_IOCPF_SEMWAIT:
2866 ioc_st = BFA_IOC_SEMWAIT;
2867 break;
2868
2869 case BFA_IOCPF_HWINIT:
2870 ioc_st = BFA_IOC_HWINIT;
2871 break;
2872
2873 case BFA_IOCPF_FWMISMATCH:
2874 ioc_st = BFA_IOC_FWMISMATCH;
2875 break;
2876
2877 case BFA_IOCPF_FAIL:
2878 ioc_st = BFA_IOC_FAIL;
2879 break;
2880
2881 case BFA_IOCPF_INITFAIL:
2882 ioc_st = BFA_IOC_INITFAIL;
2883 break;
2884
2885 default:
2886 break;
2887 }
2888 }
2889 return ioc_st;
2890 }
2891
2892 void
2893 bfa_nw_ioc_get_attr(struct bfa_ioc *ioc, struct bfa_ioc_attr *ioc_attr)
2894 {
2895 memset((void *)ioc_attr, 0, sizeof(struct bfa_ioc_attr));
2896
2897 ioc_attr->state = bfa_ioc_get_state(ioc);
2898 ioc_attr->port_id = bfa_ioc_portid(ioc);
2899 ioc_attr->port_mode = ioc->port_mode;
2900
2901 ioc_attr->port_mode_cfg = ioc->port_mode_cfg;
2902 ioc_attr->cap_bm = ioc->ad_cap_bm;
2903
2904 ioc_attr->ioc_type = bfa_ioc_get_type(ioc);
2905
2906 bfa_ioc_get_adapter_attr(ioc, &ioc_attr->adapter_attr);
2907
2908 ioc_attr->pci_attr.device_id = bfa_ioc_devid(ioc);
2909 ioc_attr->pci_attr.pcifn = bfa_ioc_pcifn(ioc);
2910 ioc_attr->def_fn = bfa_ioc_is_default(ioc);
2911 bfa_ioc_get_pci_chip_rev(ioc, ioc_attr->pci_attr.chip_rev);
2912 }
2913
2914 /* WWN public */
2915 static u64
2916 bfa_ioc_get_pwwn(struct bfa_ioc *ioc)
2917 {
2918 return ioc->attr->pwwn;
2919 }
2920
2921 void
2922 bfa_nw_ioc_get_mac(struct bfa_ioc *ioc, u8 *mac)
2923 {
2924 ether_addr_copy(mac, ioc->attr->mac);
2925 }
2926
2927 /* Firmware failure detected. Start recovery actions. */
2928 static void
2929 bfa_ioc_recover(struct bfa_ioc *ioc)
2930 {
2931 pr_crit("Heart Beat of IOC has failed\n");
2932 bfa_ioc_stats(ioc, ioc_hbfails);
2933 bfa_ioc_stats_hb_count(ioc, ioc->hb_count);
2934 bfa_fsm_send_event(ioc, IOC_E_HBFAIL);
2935 }
2936
2937 /* BFA IOC PF private functions */
2938
2939 static void
2940 bfa_iocpf_enable(struct bfa_ioc *ioc)
2941 {
2942 bfa_fsm_send_event(&ioc->iocpf, IOCPF_E_ENABLE);
2943 }
2944
2945 static void
2946 bfa_iocpf_disable(struct bfa_ioc *ioc)
2947 {
2948 bfa_fsm_send_event(&ioc->iocpf, IOCPF_E_DISABLE);
2949 }
2950
2951 static void
2952 bfa_iocpf_fail(struct bfa_ioc *ioc)
2953 {
2954 bfa_fsm_send_event(&ioc->iocpf, IOCPF_E_FAIL);
2955 }
2956
2957 static void
2958 bfa_iocpf_initfail(struct bfa_ioc *ioc)
2959 {
2960 bfa_fsm_send_event(&ioc->iocpf, IOCPF_E_INITFAIL);
2961 }
2962
2963 static void
2964 bfa_iocpf_getattrfail(struct bfa_ioc *ioc)
2965 {
2966 bfa_fsm_send_event(&ioc->iocpf, IOCPF_E_GETATTRFAIL);
2967 }
2968
2969 static void
2970 bfa_iocpf_stop(struct bfa_ioc *ioc)
2971 {
2972 bfa_fsm_send_event(&ioc->iocpf, IOCPF_E_STOP);
2973 }
2974
2975 void
2976 bfa_nw_iocpf_timeout(struct bfa_ioc *ioc)
2977 {
2978 enum bfa_iocpf_state iocpf_st;
2979
2980 iocpf_st = bfa_sm_to_state(iocpf_sm_table, ioc->iocpf.fsm);
2981
2982 if (iocpf_st == BFA_IOCPF_HWINIT)
2983 bfa_ioc_poll_fwinit(ioc);
2984 else
2985 bfa_fsm_send_event(&ioc->iocpf, IOCPF_E_TIMEOUT);
2986 }
2987
2988 void
2989 bfa_nw_iocpf_sem_timeout(struct bfa_ioc *ioc)
2990 {
2991 bfa_ioc_hw_sem_get(ioc);
2992 }
2993
2994 static void
2995 bfa_ioc_poll_fwinit(struct bfa_ioc *ioc)
2996 {
2997 u32 fwstate = bfa_ioc_get_cur_ioc_fwstate(ioc);
2998
2999 if (fwstate == BFI_IOC_DISABLED) {
3000 bfa_fsm_send_event(&ioc->iocpf, IOCPF_E_FWREADY);
3001 return;
3002 }
3003
3004 if (ioc->iocpf.poll_time >= BFA_IOC_TOV) {
3005 bfa_fsm_send_event(&ioc->iocpf, IOCPF_E_TIMEOUT);
3006 } else {
3007 ioc->iocpf.poll_time += BFA_IOC_POLL_TOV;
3008 mod_timer(&ioc->iocpf_timer, jiffies +
3009 msecs_to_jiffies(BFA_IOC_POLL_TOV));
3010 }
3011 }
3012
3013 /*
3014 * Flash module specific
3015 */
3016
3017 /*
3018 * FLASH DMA buffer should be big enough to hold both MFG block and
3019 * asic block(64k) at the same time and also should be 2k aligned to
3020 * avoid write segement to cross sector boundary.
3021 */
3022 #define BFA_FLASH_SEG_SZ 2048
3023 #define BFA_FLASH_DMA_BUF_SZ \
3024 roundup(0x010000 + sizeof(struct bfa_mfg_block), BFA_FLASH_SEG_SZ)
3025
3026 static void
3027 bfa_flash_cb(struct bfa_flash *flash)
3028 {
3029 flash->op_busy = 0;
3030 if (flash->cbfn)
3031 flash->cbfn(flash->cbarg, flash->status);
3032 }
3033
3034 static void
3035 bfa_flash_notify(void *cbarg, enum bfa_ioc_event event)
3036 {
3037 struct bfa_flash *flash = cbarg;
3038
3039 switch (event) {
3040 case BFA_IOC_E_DISABLED:
3041 case BFA_IOC_E_FAILED:
3042 if (flash->op_busy) {
3043 flash->status = BFA_STATUS_IOC_FAILURE;
3044 flash->cbfn(flash->cbarg, flash->status);
3045 flash->op_busy = 0;
3046 }
3047 break;
3048 default:
3049 break;
3050 }
3051 }
3052
3053 /*
3054 * Send flash write request.
3055 */
3056 static void
3057 bfa_flash_write_send(struct bfa_flash *flash)
3058 {
3059 struct bfi_flash_write_req *msg =
3060 (struct bfi_flash_write_req *) flash->mb.msg;
3061 u32 len;
3062
3063 msg->type = be32_to_cpu(flash->type);
3064 msg->instance = flash->instance;
3065 msg->offset = be32_to_cpu(flash->addr_off + flash->offset);
3066 len = (flash->residue < BFA_FLASH_DMA_BUF_SZ) ?
3067 flash->residue : BFA_FLASH_DMA_BUF_SZ;
3068 msg->length = be32_to_cpu(len);
3069
3070 /* indicate if it's the last msg of the whole write operation */
3071 msg->last = (len == flash->residue) ? 1 : 0;
3072
3073 bfi_h2i_set(msg->mh, BFI_MC_FLASH, BFI_FLASH_H2I_WRITE_REQ,
3074 bfa_ioc_portid(flash->ioc));
3075 bfa_alen_set(&msg->alen, len, flash->dbuf_pa);
3076 memcpy(flash->dbuf_kva, flash->ubuf + flash->offset, len);
3077 bfa_nw_ioc_mbox_queue(flash->ioc, &flash->mb, NULL, NULL);
3078
3079 flash->residue -= len;
3080 flash->offset += len;
3081 }
3082
3083 /**
3084 * bfa_flash_read_send - Send flash read request.
3085 *
3086 * @cbarg: callback argument
3087 */
3088 static void
3089 bfa_flash_read_send(void *cbarg)
3090 {
3091 struct bfa_flash *flash = cbarg;
3092 struct bfi_flash_read_req *msg =
3093 (struct bfi_flash_read_req *) flash->mb.msg;
3094 u32 len;
3095
3096 msg->type = be32_to_cpu(flash->type);
3097 msg->instance = flash->instance;
3098 msg->offset = be32_to_cpu(flash->addr_off + flash->offset);
3099 len = (flash->residue < BFA_FLASH_DMA_BUF_SZ) ?
3100 flash->residue : BFA_FLASH_DMA_BUF_SZ;
3101 msg->length = be32_to_cpu(len);
3102 bfi_h2i_set(msg->mh, BFI_MC_FLASH, BFI_FLASH_H2I_READ_REQ,
3103 bfa_ioc_portid(flash->ioc));
3104 bfa_alen_set(&msg->alen, len, flash->dbuf_pa);
3105 bfa_nw_ioc_mbox_queue(flash->ioc, &flash->mb, NULL, NULL);
3106 }
3107
3108 /**
3109 * bfa_flash_intr - Process flash response messages upon receiving interrupts.
3110 *
3111 * @flasharg: flash structure
3112 * @msg: message structure
3113 */
3114 static void
3115 bfa_flash_intr(void *flasharg, struct bfi_mbmsg *msg)
3116 {
3117 struct bfa_flash *flash = flasharg;
3118 u32 status;
3119
3120 union {
3121 struct bfi_flash_query_rsp *query;
3122 struct bfi_flash_write_rsp *write;
3123 struct bfi_flash_read_rsp *read;
3124 struct bfi_mbmsg *msg;
3125 } m;
3126
3127 m.msg = msg;
3128
3129 /* receiving response after ioc failure */
3130 if (!flash->op_busy && msg->mh.msg_id != BFI_FLASH_I2H_EVENT)
3131 return;
3132
3133 switch (msg->mh.msg_id) {
3134 case BFI_FLASH_I2H_QUERY_RSP:
3135 status = be32_to_cpu(m.query->status);
3136 if (status == BFA_STATUS_OK) {
3137 u32 i;
3138 struct bfa_flash_attr *attr, *f;
3139
3140 attr = (struct bfa_flash_attr *) flash->ubuf;
3141 f = (struct bfa_flash_attr *) flash->dbuf_kva;
3142 attr->status = be32_to_cpu(f->status);
3143 attr->npart = be32_to_cpu(f->npart);
3144 for (i = 0; i < attr->npart; i++) {
3145 attr->part[i].part_type =
3146 be32_to_cpu(f->part[i].part_type);
3147 attr->part[i].part_instance =
3148 be32_to_cpu(f->part[i].part_instance);
3149 attr->part[i].part_off =
3150 be32_to_cpu(f->part[i].part_off);
3151 attr->part[i].part_size =
3152 be32_to_cpu(f->part[i].part_size);
3153 attr->part[i].part_len =
3154 be32_to_cpu(f->part[i].part_len);
3155 attr->part[i].part_status =
3156 be32_to_cpu(f->part[i].part_status);
3157 }
3158 }
3159 flash->status = status;
3160 bfa_flash_cb(flash);
3161 break;
3162 case BFI_FLASH_I2H_WRITE_RSP:
3163 status = be32_to_cpu(m.write->status);
3164 if (status != BFA_STATUS_OK || flash->residue == 0) {
3165 flash->status = status;
3166 bfa_flash_cb(flash);
3167 } else
3168 bfa_flash_write_send(flash);
3169 break;
3170 case BFI_FLASH_I2H_READ_RSP:
3171 status = be32_to_cpu(m.read->status);
3172 if (status != BFA_STATUS_OK) {
3173 flash->status = status;
3174 bfa_flash_cb(flash);
3175 } else {
3176 u32 len = be32_to_cpu(m.read->length);
3177 memcpy(flash->ubuf + flash->offset,
3178 flash->dbuf_kva, len);
3179 flash->residue -= len;
3180 flash->offset += len;
3181 if (flash->residue == 0) {
3182 flash->status = status;
3183 bfa_flash_cb(flash);
3184 } else
3185 bfa_flash_read_send(flash);
3186 }
3187 break;
3188 case BFI_FLASH_I2H_BOOT_VER_RSP:
3189 case BFI_FLASH_I2H_EVENT:
3190 break;
3191 default:
3192 WARN_ON(1);
3193 }
3194 }
3195
3196 /*
3197 * Flash memory info API.
3198 */
3199 u32
3200 bfa_nw_flash_meminfo(void)
3201 {
3202 return roundup(BFA_FLASH_DMA_BUF_SZ, BFA_DMA_ALIGN_SZ);
3203 }
3204
3205 /**
3206 * bfa_nw_flash_attach - Flash attach API.
3207 *
3208 * @flash: flash structure
3209 * @ioc: ioc structure
3210 * @dev: device structure
3211 */
3212 void
3213 bfa_nw_flash_attach(struct bfa_flash *flash, struct bfa_ioc *ioc, void *dev)
3214 {
3215 flash->ioc = ioc;
3216 flash->cbfn = NULL;
3217 flash->cbarg = NULL;
3218 flash->op_busy = 0;
3219
3220 bfa_nw_ioc_mbox_regisr(flash->ioc, BFI_MC_FLASH, bfa_flash_intr, flash);
3221 bfa_ioc_notify_init(&flash->ioc_notify, bfa_flash_notify, flash);
3222 list_add_tail(&flash->ioc_notify.qe, &flash->ioc->notify_q);
3223 }
3224
3225 /**
3226 * bfa_nw_flash_memclaim - Claim memory for flash
3227 *
3228 * @flash: flash structure
3229 * @dm_kva: pointer to virtual memory address
3230 * @dm_pa: physical memory address
3231 */
3232 void
3233 bfa_nw_flash_memclaim(struct bfa_flash *flash, u8 *dm_kva, u64 dm_pa)
3234 {
3235 flash->dbuf_kva = dm_kva;
3236 flash->dbuf_pa = dm_pa;
3237 memset(flash->dbuf_kva, 0, BFA_FLASH_DMA_BUF_SZ);
3238 dm_kva += roundup(BFA_FLASH_DMA_BUF_SZ, BFA_DMA_ALIGN_SZ);
3239 dm_pa += roundup(BFA_FLASH_DMA_BUF_SZ, BFA_DMA_ALIGN_SZ);
3240 }
3241
3242 /**
3243 * bfa_nw_flash_get_attr - Get flash attribute.
3244 *
3245 * @flash: flash structure
3246 * @attr: flash attribute structure
3247 * @cbfn: callback function
3248 * @cbarg: callback argument
3249 *
3250 * Return status.
3251 */
3252 enum bfa_status
3253 bfa_nw_flash_get_attr(struct bfa_flash *flash, struct bfa_flash_attr *attr,
3254 bfa_cb_flash cbfn, void *cbarg)
3255 {
3256 struct bfi_flash_query_req *msg =
3257 (struct bfi_flash_query_req *) flash->mb.msg;
3258
3259 if (!bfa_nw_ioc_is_operational(flash->ioc))
3260 return BFA_STATUS_IOC_NON_OP;
3261
3262 if (flash->op_busy)
3263 return BFA_STATUS_DEVBUSY;
3264
3265 flash->op_busy = 1;
3266 flash->cbfn = cbfn;
3267 flash->cbarg = cbarg;
3268 flash->ubuf = (u8 *) attr;
3269
3270 bfi_h2i_set(msg->mh, BFI_MC_FLASH, BFI_FLASH_H2I_QUERY_REQ,
3271 bfa_ioc_portid(flash->ioc));
3272 bfa_alen_set(&msg->alen, sizeof(struct bfa_flash_attr), flash->dbuf_pa);
3273 bfa_nw_ioc_mbox_queue(flash->ioc, &flash->mb, NULL, NULL);
3274
3275 return BFA_STATUS_OK;
3276 }
3277
3278 /**
3279 * bfa_nw_flash_update_part - Update flash partition.
3280 *
3281 * @flash: flash structure
3282 * @type: flash partition type
3283 * @instance: flash partition instance
3284 * @buf: update data buffer
3285 * @len: data buffer length
3286 * @offset: offset relative to the partition starting address
3287 * @cbfn: callback function
3288 * @cbarg: callback argument
3289 *
3290 * Return status.
3291 */
3292 enum bfa_status
3293 bfa_nw_flash_update_part(struct bfa_flash *flash, u32 type, u8 instance,
3294 void *buf, u32 len, u32 offset,
3295 bfa_cb_flash cbfn, void *cbarg)
3296 {
3297 if (!bfa_nw_ioc_is_operational(flash->ioc))
3298 return BFA_STATUS_IOC_NON_OP;
3299
3300 /*
3301 * 'len' must be in word (4-byte) boundary
3302 */
3303 if (!len || (len & 0x03))
3304 return BFA_STATUS_FLASH_BAD_LEN;
3305
3306 if (type == BFA_FLASH_PART_MFG)
3307 return BFA_STATUS_EINVAL;
3308
3309 if (flash->op_busy)
3310 return BFA_STATUS_DEVBUSY;
3311
3312 flash->op_busy = 1;
3313 flash->cbfn = cbfn;
3314 flash->cbarg = cbarg;
3315 flash->type = type;
3316 flash->instance = instance;
3317 flash->residue = len;
3318 flash->offset = 0;
3319 flash->addr_off = offset;
3320 flash->ubuf = buf;
3321
3322 bfa_flash_write_send(flash);
3323
3324 return BFA_STATUS_OK;
3325 }
3326
3327 /**
3328 * bfa_nw_flash_read_part - Read flash partition.
3329 *
3330 * @flash: flash structure
3331 * @type: flash partition type
3332 * @instance: flash partition instance
3333 * @buf: read data buffer
3334 * @len: data buffer length
3335 * @offset: offset relative to the partition starting address
3336 * @cbfn: callback function
3337 * @cbarg: callback argument
3338 *
3339 * Return status.
3340 */
3341 enum bfa_status
3342 bfa_nw_flash_read_part(struct bfa_flash *flash, u32 type, u8 instance,
3343 void *buf, u32 len, u32 offset,
3344 bfa_cb_flash cbfn, void *cbarg)
3345 {
3346 if (!bfa_nw_ioc_is_operational(flash->ioc))
3347 return BFA_STATUS_IOC_NON_OP;
3348
3349 /*
3350 * 'len' must be in word (4-byte) boundary
3351 */
3352 if (!len || (len & 0x03))
3353 return BFA_STATUS_FLASH_BAD_LEN;
3354
3355 if (flash->op_busy)
3356 return BFA_STATUS_DEVBUSY;
3357
3358 flash->op_busy = 1;
3359 flash->cbfn = cbfn;
3360 flash->cbarg = cbarg;
3361 flash->type = type;
3362 flash->instance = instance;
3363 flash->residue = len;
3364 flash->offset = 0;
3365 flash->addr_off = offset;
3366 flash->ubuf = buf;
3367
3368 bfa_flash_read_send(flash);
3369
3370 return BFA_STATUS_OK;
3371 }
Linux with added FPC-III support