drivers/net/ethernet/chelsio/cxgb3/adapter.h

   1 /*
   2  * Copyright (c) 2003-2008 Chelsio, Inc. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 /* This file should not be included directly.  Include common.h instead. */
  34
  35 #ifndef __T3_ADAPTER_H__
  36 #define __T3_ADAPTER_H__
  37
  38 #include <linux/pci.h>
  39 #include <linux/spinlock.h>
  40 #include <linux/interrupt.h>
  41 #include <linux/timer.h>
  42 #include <linux/cache.h>
  43 #include <linux/mutex.h>
  44 #include <linux/bitops.h>
  45 #include "t3cdev.h"
  46 #include <asm/io.h>
  47
  48 struct adapter;
  49 struct sge_qset;
  50 struct port_info;
  51
  52 enum mac_idx_types {
  53         LAN_MAC_IDX     = 0,
  54         SAN_MAC_IDX,
  55
  56         MAX_MAC_IDX
  57 };
  58
  59 struct iscsi_config {
  60         __u8    mac_addr[ETH_ALEN];
  61         __u32   flags;
  62         int (*send)(struct port_info *pi, struct sk_buff **skb);
  63         int (*recv)(struct port_info *pi, struct sk_buff *skb);
  64 };
  65
  66 struct port_info {
  67         struct adapter *adapter;
  68         struct sge_qset *qs;
  69         u8 port_id;
  70         u8 nqsets;
  71         u8 first_qset;
  72         struct cphy phy;
  73         struct cmac mac;
  74         struct link_config link_config;
  75         int activity;
  76         __be32 iscsi_ipv4addr;
  77         struct iscsi_config iscsic;
  78
  79         int link_fault; /* link fault was detected */
  80 };
  81
  82 enum {                          /* adapter flags */
  83         FULL_INIT_DONE = (1 << 0),
  84         USING_MSI = (1 << 1),
  85         USING_MSIX = (1 << 2),
  86         QUEUES_BOUND = (1 << 3),
  87         TP_PARITY_INIT = (1 << 4),
  88         NAPI_INIT = (1 << 5),
  89 };
  90
  91 struct fl_pg_chunk {
  92         struct page *page;
  93         void *va;
  94         unsigned int offset;
  95         unsigned long *p_cnt;
  96         dma_addr_t mapping;
  97 };
  98
  99 struct rx_desc;
 100 struct rx_sw_desc;
 101
 102 struct sge_fl {                     /* SGE per free-buffer list state */
 103         unsigned int buf_size;      /* size of each Rx buffer */
 104         unsigned int credits;       /* # of available Rx buffers */
 105         unsigned int pend_cred;     /* new buffers since last FL DB ring */
 106         unsigned int size;          /* capacity of free list */
 107         unsigned int cidx;          /* consumer index */
 108         unsigned int pidx;          /* producer index */
 109         unsigned int gen;           /* free list generation */
 110         struct fl_pg_chunk pg_chunk;/* page chunk cache */
 111         unsigned int use_pages;     /* whether FL uses pages or sk_buffs */
 112         unsigned int order;         /* order of page allocations */
 113         unsigned int alloc_size;    /* size of allocated buffer */
 114         struct rx_desc *desc;       /* address of HW Rx descriptor ring */
 115         struct rx_sw_desc *sdesc;   /* address of SW Rx descriptor ring */
 116         dma_addr_t   phys_addr;     /* physical address of HW ring start */
 117         unsigned int cntxt_id;      /* SGE context id for the free list */
 118         unsigned long empty;        /* # of times queue ran out of buffers */
 119         unsigned long alloc_failed; /* # of times buffer allocation failed */
 120 };
 121
 122 /*
 123  * Bundle size for grouping offload RX packets for delivery to the stack.
 124  * Don't make this too big as we do prefetch on each packet in a bundle.
 125  */
 126 # define RX_BUNDLE_SIZE 8
 127
 128 struct rsp_desc;
 129
 130 struct sge_rspq {               /* state for an SGE response queue */
 131         unsigned int credits;   /* # of pending response credits */
 132         unsigned int size;      /* capacity of response queue */
 133         unsigned int cidx;      /* consumer index */
 134         unsigned int gen;       /* current generation bit */
 135         unsigned int polling;   /* is the queue serviced through NAPI? */
 136         unsigned int holdoff_tmr;       /* interrupt holdoff timer in 100ns */
 137         unsigned int next_holdoff;      /* holdoff time for next interrupt */
 138         unsigned int rx_recycle_buf; /* whether recycling occurred
 139                                         within current sop-eop */
 140         struct rsp_desc *desc;  /* address of HW response ring */
 141         dma_addr_t phys_addr;   /* physical address of the ring */
 142         unsigned int cntxt_id;  /* SGE context id for the response q */
 143         spinlock_t lock;        /* guards response processing */
 144         struct sk_buff_head rx_queue; /* offload packet receive queue */
 145         struct sk_buff *pg_skb; /* used to build frag list in napi handler */
 146
 147         unsigned long offload_pkts;
 148         unsigned long offload_bundles;
 149         unsigned long eth_pkts; /* # of ethernet packets */
 150         unsigned long pure_rsps;        /* # of pure (non-data) responses */
 151         unsigned long imm_data; /* responses with immediate data */
 152         unsigned long rx_drops; /* # of packets dropped due to no mem */
 153         unsigned long async_notif; /* # of asynchronous notification events */
 154         unsigned long empty;    /* # of times queue ran out of credits */
 155         unsigned long nomem;    /* # of responses deferred due to no mem */
 156         unsigned long unhandled_irqs;   /* # of spurious intrs */
 157         unsigned long starved;
 158         unsigned long restarted;
 159 };
 160
 161 struct tx_desc;
 162 struct tx_sw_desc;
 163
 164 struct sge_txq {                /* state for an SGE Tx queue */
 165         unsigned long flags;    /* HW DMA fetch status */
 166         unsigned int in_use;    /* # of in-use Tx descriptors */
 167         unsigned int size;      /* # of descriptors */
 168         unsigned int processed; /* total # of descs HW has processed */
 169         unsigned int cleaned;   /* total # of descs SW has reclaimed */
 170         unsigned int stop_thres;        /* SW TX queue suspend threshold */
 171         unsigned int cidx;      /* consumer index */
 172         unsigned int pidx;      /* producer index */
 173         unsigned int gen;       /* current value of generation bit */
 174         unsigned int unacked;   /* Tx descriptors used since last COMPL */
 175         struct tx_desc *desc;   /* address of HW Tx descriptor ring */
 176         struct tx_sw_desc *sdesc;       /* address of SW Tx descriptor ring */
 177         spinlock_t lock;        /* guards enqueueing of new packets */
 178         unsigned int token;     /* WR token */
 179         dma_addr_t phys_addr;   /* physical address of the ring */
 180         struct sk_buff_head sendq;      /* List of backpressured offload packets */
 181         struct tasklet_struct qresume_tsk;      /* restarts the queue */
 182         unsigned int cntxt_id;  /* SGE context id for the Tx q */
 183         unsigned long stops;    /* # of times q has been stopped */
 184         unsigned long restarts; /* # of queue restarts */
 185 };
 186
 187 enum {                          /* per port SGE statistics */
 188         SGE_PSTAT_TSO,          /* # of TSO requests */
 189         SGE_PSTAT_RX_CSUM_GOOD, /* # of successful RX csum offloads */
 190         SGE_PSTAT_TX_CSUM,      /* # of TX checksum offloads */
 191         SGE_PSTAT_VLANEX,       /* # of VLAN tag extractions */
 192         SGE_PSTAT_VLANINS,      /* # of VLAN tag insertions */
 193
 194         SGE_PSTAT_MAX           /* must be last */
 195 };
 196
 197 struct napi_gro_fraginfo;
 198
 199 struct sge_qset {               /* an SGE queue set */
 200         struct adapter *adap;
 201         struct napi_struct napi;
 202         struct sge_rspq rspq;
 203         struct sge_fl fl[SGE_RXQ_PER_SET];
 204         struct sge_txq txq[SGE_TXQ_PER_SET];
 205         int nomem;
 206         void *lro_va;
 207         struct net_device *netdev;
 208         struct netdev_queue *tx_q;      /* associated netdev TX queue */
 209         unsigned long txq_stopped;      /* which Tx queues are stopped */
 210         struct timer_list tx_reclaim_timer;     /* reclaims TX buffers */
 211         struct timer_list rx_reclaim_timer;     /* reclaims RX buffers */
 212         unsigned long port_stats[SGE_PSTAT_MAX];
 213 } ____cacheline_aligned;
 214
 215 struct sge {
 216         struct sge_qset qs[SGE_QSETS];
 217         spinlock_t reg_lock;    /* guards non-atomic SGE registers (eg context) */
 218 };
 219
 220 struct adapter {
 221         struct t3cdev tdev;
 222         struct list_head adapter_list;
 223         void __iomem *regs;
 224         struct pci_dev *pdev;
 225         unsigned long registered_device_map;
 226         unsigned long open_device_map;
 227         unsigned long flags;
 228
 229         const char *name;
 230         int msg_enable;
 231         unsigned int mmio_len;
 232
 233         struct adapter_params params;
 234         unsigned int slow_intr_mask;
 235         unsigned long irq_stats[IRQ_NUM_STATS];
 236
 237         int msix_nvectors;
 238         struct {
 239                 unsigned short vec;
 240                 char desc[22];
 241         } msix_info[SGE_QSETS + 1];
 242
 243         /* T3 modules */
 244         struct sge sge;
 245         struct mc7 pmrx;
 246         struct mc7 pmtx;
 247         struct mc7 cm;
 248         struct mc5 mc5;
 249
 250         struct net_device *port[MAX_NPORTS];
 251         unsigned int check_task_cnt;
 252         struct delayed_work adap_check_task;
 253         struct work_struct ext_intr_handler_task;
 254         struct work_struct fatal_error_handler_task;
 255         struct work_struct link_fault_handler_task;
 256
 257         struct work_struct db_full_task;
 258         struct work_struct db_empty_task;
 259         struct work_struct db_drop_task;
 260
 261         struct dentry *debugfs_root;
 262
 263         struct mutex mdio_lock;
 264         spinlock_t stats_lock;
 265         spinlock_t work_lock;
 266
 267         struct sk_buff *nofail_skb;
 268 };
 269
 270 static inline u32 t3_read_reg(struct adapter *adapter, u32 reg_addr)
 271 {
 272         u32 val = readl(adapter->regs + reg_addr);
 273
 274         CH_DBG(adapter, MMIO, "read register 0x%x value 0x%x\n", reg_addr, val);
 275         return val;
 276 }
 277
 278 static inline void t3_write_reg(struct adapter *adapter, u32 reg_addr, u32 val)
 279 {
 280         CH_DBG(adapter, MMIO, "setting register 0x%x to 0x%x\n", reg_addr, val);
 281         writel(val, adapter->regs + reg_addr);
 282 }
 283
 284 static inline struct port_info *adap2pinfo(struct adapter *adap, int idx)
 285 {
 286         return netdev_priv(adap->port[idx]);
 287 }
 288
 289 static inline int phy2portid(struct cphy *phy)
 290 {
 291         struct adapter *adap = phy->adapter;
 292         struct port_info *port0 = adap2pinfo(adap, 0);
 293
 294         return &port0->phy == phy ? 0 : 1;
 295 }
 296
 297 #define OFFLOAD_DEVMAP_BIT 15
 298
 299 #define tdev2adap(d) container_of(d, struct adapter, tdev)
 300
 301 static inline int offload_running(struct adapter *adapter)
 302 {
 303         return test_bit(OFFLOAD_DEVMAP_BIT, &adapter->open_device_map);
 304 }
 305
 306 int t3_offload_tx(struct t3cdev *tdev, struct sk_buff *skb);
 307
 308 void t3_os_ext_intr_handler(struct adapter *adapter);
 309 void t3_os_link_changed(struct adapter *adapter, int port_id, int link_status,
 310                         int speed, int duplex, int fc);
 311 void t3_os_phymod_changed(struct adapter *adap, int port_id);
 312 void t3_os_link_fault(struct adapter *adapter, int port_id, int state);
 313 void t3_os_link_fault_handler(struct adapter *adapter, int port_id);
 314
 315 void t3_sge_start(struct adapter *adap);
 316 void t3_sge_stop(struct adapter *adap);
 317 void t3_start_sge_timers(struct adapter *adap);
 318 void t3_stop_sge_timers(struct adapter *adap);
 319 void t3_free_sge_resources(struct adapter *adap);
 320 void t3_sge_err_intr_handler(struct adapter *adapter);
 321 irq_handler_t t3_intr_handler(struct adapter *adap, int polling);
 322 netdev_tx_t t3_eth_xmit(struct sk_buff *skb, struct net_device *dev);
 323 int t3_mgmt_tx(struct adapter *adap, struct sk_buff *skb);
 324 void t3_update_qset_coalesce(struct sge_qset *qs, const struct qset_params *p);
 325 int t3_sge_alloc_qset(struct adapter *adapter, unsigned int id, int nports,
 326                       int irq_vec_idx, const struct qset_params *p,
 327                       int ntxq, struct net_device *dev,
 328                       struct netdev_queue *netdevq);
 329 extern struct workqueue_struct *cxgb3_wq;
 330
 331 int t3_get_edc_fw(struct cphy *phy, int edc_idx, int size);
 332
 333 #endif                          /* __T3_ADAPTER_H__ */