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treewide: remove redundant IS_ERR() before error code check
[linux/fpc-iii.git] / drivers / net / ethernet / chelsio / cxgb4 / cxgb4_main.c
blob649842a8aa285e45eb929493fee2e40603339258
1 /*
2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
3 *
4 * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
36
37 #include <linux/bitmap.h>
38 #include <linux/crc32.h>
39 #include <linux/ctype.h>
40 #include <linux/debugfs.h>
41 #include <linux/err.h>
42 #include <linux/etherdevice.h>
43 #include <linux/firmware.h>
44 #include <linux/if.h>
45 #include <linux/if_vlan.h>
46 #include <linux/init.h>
47 #include <linux/log2.h>
48 #include <linux/mdio.h>
49 #include <linux/module.h>
50 #include <linux/moduleparam.h>
51 #include <linux/mutex.h>
52 #include <linux/netdevice.h>
53 #include <linux/pci.h>
54 #include <linux/aer.h>
55 #include <linux/rtnetlink.h>
56 #include <linux/sched.h>
57 #include <linux/seq_file.h>
58 #include <linux/sockios.h>
59 #include <linux/vmalloc.h>
60 #include <linux/workqueue.h>
61 #include <net/neighbour.h>
62 #include <net/netevent.h>
63 #include <net/addrconf.h>
64 #include <net/bonding.h>
65 #include <linux/uaccess.h>
66 #include <linux/crash_dump.h>
67 #include <net/udp_tunnel.h>
68 #include <net/xfrm.h>
69
70 #include "cxgb4.h"
71 #include "cxgb4_filter.h"
72 #include "t4_regs.h"
73 #include "t4_values.h"
74 #include "t4_msg.h"
75 #include "t4fw_api.h"
76 #include "t4fw_version.h"
77 #include "cxgb4_dcb.h"
78 #include "srq.h"
79 #include "cxgb4_debugfs.h"
80 #include "clip_tbl.h"
81 #include "l2t.h"
82 #include "smt.h"
83 #include "sched.h"
84 #include "cxgb4_tc_u32.h"
85 #include "cxgb4_tc_flower.h"
86 #include "cxgb4_tc_mqprio.h"
87 #include "cxgb4_tc_matchall.h"
88 #include "cxgb4_ptp.h"
89 #include "cxgb4_cudbg.h"
90
91 char cxgb4_driver_name[] = KBUILD_MODNAME;
92
93 #ifdef DRV_VERSION
94 #undef DRV_VERSION
95 #endif
96 #define DRV_VERSION "2.0.0-ko"
97 const char cxgb4_driver_version[] = DRV_VERSION;
98 #define DRV_DESC "Chelsio T4/T5/T6 Network Driver"
99
100 #define DFLT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK | \
101 NETIF_MSG_TIMER | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP |\
102 NETIF_MSG_RX_ERR | NETIF_MSG_TX_ERR)
103
104 /* Macros needed to support the PCI Device ID Table ...
105 */
106 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN \
107 static const struct pci_device_id cxgb4_pci_tbl[] = {
108 #define CXGB4_UNIFIED_PF 0x4
109
110 #define CH_PCI_DEVICE_ID_FUNCTION CXGB4_UNIFIED_PF
111
112 /* Include PCI Device IDs for both PF4 and PF0-3 so our PCI probe() routine is
113 * called for both.
114 */
115 #define CH_PCI_DEVICE_ID_FUNCTION2 0x0
116
117 #define CH_PCI_ID_TABLE_ENTRY(devid) \
118 {PCI_VDEVICE(CHELSIO, (devid)), CXGB4_UNIFIED_PF}
119
120 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_END \
121 { 0, } \
122 }
123
124 #include "t4_pci_id_tbl.h"
125
126 #define FW4_FNAME "cxgb4/t4fw.bin"
127 #define FW5_FNAME "cxgb4/t5fw.bin"
128 #define FW6_FNAME "cxgb4/t6fw.bin"
129 #define FW4_CFNAME "cxgb4/t4-config.txt"
130 #define FW5_CFNAME "cxgb4/t5-config.txt"
131 #define FW6_CFNAME "cxgb4/t6-config.txt"
132 #define PHY_AQ1202_FIRMWARE "cxgb4/aq1202_fw.cld"
133 #define PHY_BCM84834_FIRMWARE "cxgb4/bcm8483.bin"
134 #define PHY_AQ1202_DEVICEID 0x4409
135 #define PHY_BCM84834_DEVICEID 0x4486
136
137 MODULE_DESCRIPTION(DRV_DESC);
138 MODULE_AUTHOR("Chelsio Communications");
139 MODULE_LICENSE("Dual BSD/GPL");
140 MODULE_VERSION(DRV_VERSION);
141 MODULE_DEVICE_TABLE(pci, cxgb4_pci_tbl);
142 MODULE_FIRMWARE(FW4_FNAME);
143 MODULE_FIRMWARE(FW5_FNAME);
144 MODULE_FIRMWARE(FW6_FNAME);
145
146 /*
147 * The driver uses the best interrupt scheme available on a platform in the
148 * order MSI-X, MSI, legacy INTx interrupts. This parameter determines which
149 * of these schemes the driver may consider as follows:
150 *
151 * msi = 2: choose from among all three options
152 * msi = 1: only consider MSI and INTx interrupts
153 * msi = 0: force INTx interrupts
154 */
155 static int msi = 2;
156
157 module_param(msi, int, 0644);
158 MODULE_PARM_DESC(msi, "whether to use INTx (0), MSI (1) or MSI-X (2)");
159
160 /*
161 * Normally we tell the chip to deliver Ingress Packets into our DMA buffers
162 * offset by 2 bytes in order to have the IP headers line up on 4-byte
163 * boundaries. This is a requirement for many architectures which will throw
164 * a machine check fault if an attempt is made to access one of the 4-byte IP
165 * header fields on a non-4-byte boundary. And it's a major performance issue
166 * even on some architectures which allow it like some implementations of the
167 * x86 ISA. However, some architectures don't mind this and for some very
168 * edge-case performance sensitive applications (like forwarding large volumes
169 * of small packets), setting this DMA offset to 0 will decrease the number of
170 * PCI-E Bus transfers enough to measurably affect performance.
171 */
172 static int rx_dma_offset = 2;
173
174 /* TX Queue select used to determine what algorithm to use for selecting TX
175 * queue. Select between the kernel provided function (select_queue=0) or user
176 * cxgb_select_queue function (select_queue=1)
177 *
178 * Default: select_queue=0
179 */
180 static int select_queue;
181 module_param(select_queue, int, 0644);
182 MODULE_PARM_DESC(select_queue,
183 "Select between kernel provided method of selecting or driver method of selecting TX queue. Default is kernel method.");
184
185 static struct dentry *cxgb4_debugfs_root;
186
187 LIST_HEAD(adapter_list);
188 DEFINE_MUTEX(uld_mutex);
189
190 static int cfg_queues(struct adapter *adap);
191
192 static void link_report(struct net_device *dev)
193 {
194 if (!netif_carrier_ok(dev))
195 netdev_info(dev, "link down\n");
196 else {
197 static const char *fc[] = { "no", "Rx", "Tx", "Tx/Rx" };
198
199 const char *s;
200 const struct port_info *p = netdev_priv(dev);
201
202 switch (p->link_cfg.speed) {
203 case 100:
204 s = "100Mbps";
205 break;
206 case 1000:
207 s = "1Gbps";
208 break;
209 case 10000:
210 s = "10Gbps";
211 break;
212 case 25000:
213 s = "25Gbps";
214 break;
215 case 40000:
216 s = "40Gbps";
217 break;
218 case 50000:
219 s = "50Gbps";
220 break;
221 case 100000:
222 s = "100Gbps";
223 break;
224 default:
225 pr_info("%s: unsupported speed: %d\n",
226 dev->name, p->link_cfg.speed);
227 return;
228 }
229
230 netdev_info(dev, "link up, %s, full-duplex, %s PAUSE\n", s,
231 fc[p->link_cfg.fc]);
232 }
233 }
234
235 #ifdef CONFIG_CHELSIO_T4_DCB
236 /* Set up/tear down Data Center Bridging Priority mapping for a net device. */
237 static void dcb_tx_queue_prio_enable(struct net_device *dev, int enable)
238 {
239 struct port_info *pi = netdev_priv(dev);
240 struct adapter *adap = pi->adapter;
241 struct sge_eth_txq *txq = &adap->sge.ethtxq[pi->first_qset];
242 int i;
243
244 /* We use a simple mapping of Port TX Queue Index to DCB
245 * Priority when we're enabling DCB.
246 */
247 for (i = 0; i < pi->nqsets; i++, txq++) {
248 u32 name, value;
249 int err;
250
251 name = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DMAQ) |
252 FW_PARAMS_PARAM_X_V(
253 FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH) |
254 FW_PARAMS_PARAM_YZ_V(txq->q.cntxt_id));
255 value = enable ? i : 0xffffffff;
256
257 /* Since we can be called while atomic (from "interrupt
258 * level") we need to issue the Set Parameters Commannd
259 * without sleeping (timeout < 0).
260 */
261 err = t4_set_params_timeout(adap, adap->mbox, adap->pf, 0, 1,
262 &name, &value,
263 -FW_CMD_MAX_TIMEOUT);
264
265 if (err)
266 dev_err(adap->pdev_dev,
267 "Can't %s DCB Priority on port %d, TX Queue %d: err=%d\n",
268 enable ? "set" : "unset", pi->port_id, i, -err);
269 else
270 txq->dcb_prio = enable ? value : 0;
271 }
272 }
273
274 int cxgb4_dcb_enabled(const struct net_device *dev)
275 {
276 struct port_info *pi = netdev_priv(dev);
277
278 if (!pi->dcb.enabled)
279 return 0;
280
281 return ((pi->dcb.state == CXGB4_DCB_STATE_FW_ALLSYNCED) ||
282 (pi->dcb.state == CXGB4_DCB_STATE_HOST));
283 }
284 #endif /* CONFIG_CHELSIO_T4_DCB */
285
286 void t4_os_link_changed(struct adapter *adapter, int port_id, int link_stat)
287 {
288 struct net_device *dev = adapter->port[port_id];
289
290 /* Skip changes from disabled ports. */
291 if (netif_running(dev) && link_stat != netif_carrier_ok(dev)) {
292 if (link_stat)
293 netif_carrier_on(dev);
294 else {
295 #ifdef CONFIG_CHELSIO_T4_DCB
296 if (cxgb4_dcb_enabled(dev)) {
297 cxgb4_dcb_reset(dev);
298 dcb_tx_queue_prio_enable(dev, false);
299 }
300 #endif /* CONFIG_CHELSIO_T4_DCB */
301 netif_carrier_off(dev);
302 }
303
304 link_report(dev);
305 }
306 }
307
308 void t4_os_portmod_changed(struct adapter *adap, int port_id)
309 {
310 static const char *mod_str[] = {
311 NULL, "LR", "SR", "ER", "passive DA", "active DA", "LRM"
312 };
313
314 struct net_device *dev = adap->port[port_id];
315 struct port_info *pi = netdev_priv(dev);
316
317 if (pi->mod_type == FW_PORT_MOD_TYPE_NONE)
318 netdev_info(dev, "port module unplugged\n");
319 else if (pi->mod_type < ARRAY_SIZE(mod_str))
320 netdev_info(dev, "%s module inserted\n", mod_str[pi->mod_type]);
321 else if (pi->mod_type == FW_PORT_MOD_TYPE_NOTSUPPORTED)
322 netdev_info(dev, "%s: unsupported port module inserted\n",
323 dev->name);
324 else if (pi->mod_type == FW_PORT_MOD_TYPE_UNKNOWN)
325 netdev_info(dev, "%s: unknown port module inserted\n",
326 dev->name);
327 else if (pi->mod_type == FW_PORT_MOD_TYPE_ERROR)
328 netdev_info(dev, "%s: transceiver module error\n", dev->name);
329 else
330 netdev_info(dev, "%s: unknown module type %d inserted\n",
331 dev->name, pi->mod_type);
332
333 /* If the interface is running, then we'll need any "sticky" Link
334 * Parameters redone with a new Transceiver Module.
335 */
336 pi->link_cfg.redo_l1cfg = netif_running(dev);
337 }
338
339 int dbfifo_int_thresh = 10; /* 10 == 640 entry threshold */
340 module_param(dbfifo_int_thresh, int, 0644);
341 MODULE_PARM_DESC(dbfifo_int_thresh, "doorbell fifo interrupt threshold");
342
343 /*
344 * usecs to sleep while draining the dbfifo
345 */
346 static int dbfifo_drain_delay = 1000;
347 module_param(dbfifo_drain_delay, int, 0644);
348 MODULE_PARM_DESC(dbfifo_drain_delay,
349 "usecs to sleep while draining the dbfifo");
350
351 static inline int cxgb4_set_addr_hash(struct port_info *pi)
352 {
353 struct adapter *adap = pi->adapter;
354 u64 vec = 0;
355 bool ucast = false;
356 struct hash_mac_addr *entry;
357
358 /* Calculate the hash vector for the updated list and program it */
359 list_for_each_entry(entry, &adap->mac_hlist, list) {
360 ucast |= is_unicast_ether_addr(entry->addr);
361 vec |= (1ULL << hash_mac_addr(entry->addr));
362 }
363 return t4_set_addr_hash(adap, adap->mbox, pi->viid, ucast,
364 vec, false);
365 }
366
367 static int cxgb4_mac_sync(struct net_device *netdev, const u8 *mac_addr)
368 {
369 struct port_info *pi = netdev_priv(netdev);
370 struct adapter *adap = pi->adapter;
371 int ret;
372 u64 mhash = 0;
373 u64 uhash = 0;
374 /* idx stores the index of allocated filters,
375 * its size should be modified based on the number of
376 * MAC addresses that we allocate filters for
377 */
378
379 u16 idx[1] = {};
380 bool free = false;
381 bool ucast = is_unicast_ether_addr(mac_addr);
382 const u8 *maclist[1] = {mac_addr};
383 struct hash_mac_addr *new_entry;
384
385 ret = cxgb4_alloc_mac_filt(adap, pi->viid, free, 1, maclist,
386 idx, ucast ? &uhash : &mhash, false);
387 if (ret < 0)
388 goto out;
389 /* if hash != 0, then add the addr to hash addr list
390 * so on the end we will calculate the hash for the
391 * list and program it
392 */
393 if (uhash || mhash) {
394 new_entry = kzalloc(sizeof(*new_entry), GFP_ATOMIC);
395 if (!new_entry)
396 return -ENOMEM;
397 ether_addr_copy(new_entry->addr, mac_addr);
398 list_add_tail(&new_entry->list, &adap->mac_hlist);
399 ret = cxgb4_set_addr_hash(pi);
400 }
401 out:
402 return ret < 0 ? ret : 0;
403 }
404
405 static int cxgb4_mac_unsync(struct net_device *netdev, const u8 *mac_addr)
406 {
407 struct port_info *pi = netdev_priv(netdev);
408 struct adapter *adap = pi->adapter;
409 int ret;
410 const u8 *maclist[1] = {mac_addr};
411 struct hash_mac_addr *entry, *tmp;
412
413 /* If the MAC address to be removed is in the hash addr
414 * list, delete it from the list and update hash vector
415 */
416 list_for_each_entry_safe(entry, tmp, &adap->mac_hlist, list) {
417 if (ether_addr_equal(entry->addr, mac_addr)) {
418 list_del(&entry->list);
419 kfree(entry);
420 return cxgb4_set_addr_hash(pi);
421 }
422 }
423
424 ret = cxgb4_free_mac_filt(adap, pi->viid, 1, maclist, false);
425 return ret < 0 ? -EINVAL : 0;
426 }
427
428 /*
429 * Set Rx properties of a port, such as promiscruity, address filters, and MTU.
430 * If @mtu is -1 it is left unchanged.
431 */
432 static int set_rxmode(struct net_device *dev, int mtu, bool sleep_ok)
433 {
434 struct port_info *pi = netdev_priv(dev);
435 struct adapter *adapter = pi->adapter;
436
437 __dev_uc_sync(dev, cxgb4_mac_sync, cxgb4_mac_unsync);
438 __dev_mc_sync(dev, cxgb4_mac_sync, cxgb4_mac_unsync);
439
440 return t4_set_rxmode(adapter, adapter->mbox, pi->viid, mtu,
441 (dev->flags & IFF_PROMISC) ? 1 : 0,
442 (dev->flags & IFF_ALLMULTI) ? 1 : 0, 1, -1,
443 sleep_ok);
444 }
445
446 /**
447 * cxgb4_change_mac - Update match filter for a MAC address.
448 * @pi: the port_info
449 * @viid: the VI id
450 * @tcam_idx: TCAM index of existing filter for old value of MAC address,
451 * or -1
452 * @addr: the new MAC address value
453 * @persist: whether a new MAC allocation should be persistent
454 * @add_smt: if true also add the address to the HW SMT
455 *
456 * Modifies an MPS filter and sets it to the new MAC address if
457 * @tcam_idx >= 0, or adds the MAC address to a new filter if
458 * @tcam_idx < 0. In the latter case the address is added persistently
459 * if @persist is %true.
460 * Addresses are programmed to hash region, if tcam runs out of entries.
461 *
462 */
463 int cxgb4_change_mac(struct port_info *pi, unsigned int viid,
464 int *tcam_idx, const u8 *addr, bool persist,
465 u8 *smt_idx)
466 {
467 struct adapter *adapter = pi->adapter;
468 struct hash_mac_addr *entry, *new_entry;
469 int ret;
470
471 ret = t4_change_mac(adapter, adapter->mbox, viid,
472 *tcam_idx, addr, persist, smt_idx);
473 /* We ran out of TCAM entries. try programming hash region. */
474 if (ret == -ENOMEM) {
475 /* If the MAC address to be updated is in the hash addr
476 * list, update it from the list
477 */
478 list_for_each_entry(entry, &adapter->mac_hlist, list) {
479 if (entry->iface_mac) {
480 ether_addr_copy(entry->addr, addr);
481 goto set_hash;
482 }
483 }
484 new_entry = kzalloc(sizeof(*new_entry), GFP_KERNEL);
485 if (!new_entry)
486 return -ENOMEM;
487 ether_addr_copy(new_entry->addr, addr);
488 new_entry->iface_mac = true;
489 list_add_tail(&new_entry->list, &adapter->mac_hlist);
490 set_hash:
491 ret = cxgb4_set_addr_hash(pi);
492 } else if (ret >= 0) {
493 *tcam_idx = ret;
494 ret = 0;
495 }
496
497 return ret;
498 }
499
500 /*
501 * link_start - enable a port
502 * @dev: the port to enable
503 *
504 * Performs the MAC and PHY actions needed to enable a port.
505 */
506 static int link_start(struct net_device *dev)
507 {
508 int ret;
509 struct port_info *pi = netdev_priv(dev);
510 unsigned int mb = pi->adapter->pf;
511
512 /*
513 * We do not set address filters and promiscuity here, the stack does
514 * that step explicitly.
515 */
516 ret = t4_set_rxmode(pi->adapter, mb, pi->viid, dev->mtu, -1, -1, -1,
517 !!(dev->features & NETIF_F_HW_VLAN_CTAG_RX), true);
518 if (ret == 0)
519 ret = cxgb4_update_mac_filt(pi, pi->viid, &pi->xact_addr_filt,
520 dev->dev_addr, true, &pi->smt_idx);
521 if (ret == 0)
522 ret = t4_link_l1cfg(pi->adapter, mb, pi->tx_chan,
523 &pi->link_cfg);
524 if (ret == 0) {
525 local_bh_disable();
526 ret = t4_enable_pi_params(pi->adapter, mb, pi, true,
527 true, CXGB4_DCB_ENABLED);
528 local_bh_enable();
529 }
530
531 return ret;
532 }
533
534 #ifdef CONFIG_CHELSIO_T4_DCB
535 /* Handle a Data Center Bridging update message from the firmware. */
536 static void dcb_rpl(struct adapter *adap, const struct fw_port_cmd *pcmd)
537 {
538 int port = FW_PORT_CMD_PORTID_G(ntohl(pcmd->op_to_portid));
539 struct net_device *dev = adap->port[adap->chan_map[port]];
540 int old_dcb_enabled = cxgb4_dcb_enabled(dev);
541 int new_dcb_enabled;
542
543 cxgb4_dcb_handle_fw_update(adap, pcmd);
544 new_dcb_enabled = cxgb4_dcb_enabled(dev);
545
546 /* If the DCB has become enabled or disabled on the port then we're
547 * going to need to set up/tear down DCB Priority parameters for the
548 * TX Queues associated with the port.
549 */
550 if (new_dcb_enabled != old_dcb_enabled)
551 dcb_tx_queue_prio_enable(dev, new_dcb_enabled);
552 }
553 #endif /* CONFIG_CHELSIO_T4_DCB */
554
555 /* Response queue handler for the FW event queue.
556 */
557 static int fwevtq_handler(struct sge_rspq *q, const __be64 *rsp,
558 const struct pkt_gl *gl)
559 {
560 u8 opcode = ((const struct rss_header *)rsp)->opcode;
561
562 rsp++; /* skip RSS header */
563
564 /* FW can send EGR_UPDATEs encapsulated in a CPL_FW4_MSG.
565 */
566 if (unlikely(opcode == CPL_FW4_MSG &&
567 ((const struct cpl_fw4_msg *)rsp)->type == FW_TYPE_RSSCPL)) {
568 rsp++;
569 opcode = ((const struct rss_header *)rsp)->opcode;
570 rsp++;
571 if (opcode != CPL_SGE_EGR_UPDATE) {
572 dev_err(q->adap->pdev_dev, "unexpected FW4/CPL %#x on FW event queue\n"
573 , opcode);
574 goto out;
575 }
576 }
577
578 if (likely(opcode == CPL_SGE_EGR_UPDATE)) {
579 const struct cpl_sge_egr_update *p = (void *)rsp;
580 unsigned int qid = EGR_QID_G(ntohl(p->opcode_qid));
581 struct sge_txq *txq;
582
583 txq = q->adap->sge.egr_map[qid - q->adap->sge.egr_start];
584 txq->restarts++;
585 if (txq->q_type == CXGB4_TXQ_ETH) {
586 struct sge_eth_txq *eq;
587
588 eq = container_of(txq, struct sge_eth_txq, q);
589 t4_sge_eth_txq_egress_update(q->adap, eq, -1);
590 } else {
591 struct sge_uld_txq *oq;
592
593 oq = container_of(txq, struct sge_uld_txq, q);
594 tasklet_schedule(&oq->qresume_tsk);
595 }
596 } else if (opcode == CPL_FW6_MSG || opcode == CPL_FW4_MSG) {
597 const struct cpl_fw6_msg *p = (void *)rsp;
598
599 #ifdef CONFIG_CHELSIO_T4_DCB
600 const struct fw_port_cmd *pcmd = (const void *)p->data;
601 unsigned int cmd = FW_CMD_OP_G(ntohl(pcmd->op_to_portid));
602 unsigned int action =
603 FW_PORT_CMD_ACTION_G(ntohl(pcmd->action_to_len16));
604
605 if (cmd == FW_PORT_CMD &&
606 (action == FW_PORT_ACTION_GET_PORT_INFO ||
607 action == FW_PORT_ACTION_GET_PORT_INFO32)) {
608 int port = FW_PORT_CMD_PORTID_G(
609 be32_to_cpu(pcmd->op_to_portid));
610 struct net_device *dev;
611 int dcbxdis, state_input;
612
613 dev = q->adap->port[q->adap->chan_map[port]];
614 dcbxdis = (action == FW_PORT_ACTION_GET_PORT_INFO
615 ? !!(pcmd->u.info.dcbxdis_pkd & FW_PORT_CMD_DCBXDIS_F)
616 : !!(be32_to_cpu(pcmd->u.info32.lstatus32_to_cbllen32)
617 & FW_PORT_CMD_DCBXDIS32_F));
618 state_input = (dcbxdis
619 ? CXGB4_DCB_INPUT_FW_DISABLED
620 : CXGB4_DCB_INPUT_FW_ENABLED);
621
622 cxgb4_dcb_state_fsm(dev, state_input);
623 }
624
625 if (cmd == FW_PORT_CMD &&
626 action == FW_PORT_ACTION_L2_DCB_CFG)
627 dcb_rpl(q->adap, pcmd);
628 else
629 #endif
630 if (p->type == 0)
631 t4_handle_fw_rpl(q->adap, p->data);
632 } else if (opcode == CPL_L2T_WRITE_RPL) {
633 const struct cpl_l2t_write_rpl *p = (void *)rsp;
634
635 do_l2t_write_rpl(q->adap, p);
636 } else if (opcode == CPL_SMT_WRITE_RPL) {
637 const struct cpl_smt_write_rpl *p = (void *)rsp;
638
639 do_smt_write_rpl(q->adap, p);
640 } else if (opcode == CPL_SET_TCB_RPL) {
641 const struct cpl_set_tcb_rpl *p = (void *)rsp;
642
643 filter_rpl(q->adap, p);
644 } else if (opcode == CPL_ACT_OPEN_RPL) {
645 const struct cpl_act_open_rpl *p = (void *)rsp;
646
647 hash_filter_rpl(q->adap, p);
648 } else if (opcode == CPL_ABORT_RPL_RSS) {
649 const struct cpl_abort_rpl_rss *p = (void *)rsp;
650
651 hash_del_filter_rpl(q->adap, p);
652 } else if (opcode == CPL_SRQ_TABLE_RPL) {
653 const struct cpl_srq_table_rpl *p = (void *)rsp;
654
655 do_srq_table_rpl(q->adap, p);
656 } else
657 dev_err(q->adap->pdev_dev,
658 "unexpected CPL %#x on FW event queue\n", opcode);
659 out:
660 return 0;
661 }
662
663 static void disable_msi(struct adapter *adapter)
664 {
665 if (adapter->flags & CXGB4_USING_MSIX) {
666 pci_disable_msix(adapter->pdev);
667 adapter->flags &= ~CXGB4_USING_MSIX;
668 } else if (adapter->flags & CXGB4_USING_MSI) {
669 pci_disable_msi(adapter->pdev);
670 adapter->flags &= ~CXGB4_USING_MSI;
671 }
672 }
673
674 /*
675 * Interrupt handler for non-data events used with MSI-X.
676 */
677 static irqreturn_t t4_nondata_intr(int irq, void *cookie)
678 {
679 struct adapter *adap = cookie;
680 u32 v = t4_read_reg(adap, MYPF_REG(PL_PF_INT_CAUSE_A));
681
682 if (v & PFSW_F) {
683 adap->swintr = 1;
684 t4_write_reg(adap, MYPF_REG(PL_PF_INT_CAUSE_A), v);
685 }
686 if (adap->flags & CXGB4_MASTER_PF)
687 t4_slow_intr_handler(adap);
688 return IRQ_HANDLED;
689 }
690
691 int cxgb4_set_msix_aff(struct adapter *adap, unsigned short vec,
692 cpumask_var_t *aff_mask, int idx)
693 {
694 int rv;
695
696 if (!zalloc_cpumask_var(aff_mask, GFP_KERNEL)) {
697 dev_err(adap->pdev_dev, "alloc_cpumask_var failed\n");
698 return -ENOMEM;
699 }
700
701 cpumask_set_cpu(cpumask_local_spread(idx, dev_to_node(adap->pdev_dev)),
702 *aff_mask);
703
704 rv = irq_set_affinity_hint(vec, *aff_mask);
705 if (rv)
706 dev_warn(adap->pdev_dev,
707 "irq_set_affinity_hint %u failed %d\n",
708 vec, rv);
709
710 return 0;
711 }
712
713 void cxgb4_clear_msix_aff(unsigned short vec, cpumask_var_t aff_mask)
714 {
715 irq_set_affinity_hint(vec, NULL);
716 free_cpumask_var(aff_mask);
717 }
718
719 static int request_msix_queue_irqs(struct adapter *adap)
720 {
721 struct sge *s = &adap->sge;
722 struct msix_info *minfo;
723 int err, ethqidx;
724
725 if (s->fwevtq_msix_idx < 0)
726 return -ENOMEM;
727
728 err = request_irq(adap->msix_info[s->fwevtq_msix_idx].vec,
729 t4_sge_intr_msix, 0,
730 adap->msix_info[s->fwevtq_msix_idx].desc,
731 &s->fw_evtq);
732 if (err)
733 return err;
734
735 for_each_ethrxq(s, ethqidx) {
736 minfo = s->ethrxq[ethqidx].msix;
737 err = request_irq(minfo->vec,
738 t4_sge_intr_msix, 0,
739 minfo->desc,
740 &s->ethrxq[ethqidx].rspq);
741 if (err)
742 goto unwind;
743
744 cxgb4_set_msix_aff(adap, minfo->vec,
745 &minfo->aff_mask, ethqidx);
746 }
747 return 0;
748
749 unwind:
750 while (--ethqidx >= 0) {
751 minfo = s->ethrxq[ethqidx].msix;
752 cxgb4_clear_msix_aff(minfo->vec, minfo->aff_mask);
753 free_irq(minfo->vec, &s->ethrxq[ethqidx].rspq);
754 }
755 free_irq(adap->msix_info[s->fwevtq_msix_idx].vec, &s->fw_evtq);
756 return err;
757 }
758
759 static void free_msix_queue_irqs(struct adapter *adap)
760 {
761 struct sge *s = &adap->sge;
762 struct msix_info *minfo;
763 int i;
764
765 free_irq(adap->msix_info[s->fwevtq_msix_idx].vec, &s->fw_evtq);
766 for_each_ethrxq(s, i) {
767 minfo = s->ethrxq[i].msix;
768 cxgb4_clear_msix_aff(minfo->vec, minfo->aff_mask);
769 free_irq(minfo->vec, &s->ethrxq[i].rspq);
770 }
771 }
772
773 static int setup_ppod_edram(struct adapter *adap)
774 {
775 unsigned int param, val;
776 int ret;
777
778 /* Driver sends FW_PARAMS_PARAM_DEV_PPOD_EDRAM read command to check
779 * if firmware supports ppod edram feature or not. If firmware
780 * returns 1, then driver can enable this feature by sending
781 * FW_PARAMS_PARAM_DEV_PPOD_EDRAM write command with value 1 to
782 * enable ppod edram feature.
783 */
784 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
785 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PPOD_EDRAM));
786
787 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, &param, &val);
788 if (ret < 0) {
789 dev_warn(adap->pdev_dev,
790 "querying PPOD_EDRAM support failed: %d\n",
791 ret);
792 return -1;
793 }
794
795 if (val != 1)
796 return -1;
797
798 ret = t4_set_params(adap, adap->mbox, adap->pf, 0, 1, &param, &val);
799 if (ret < 0) {
800 dev_err(adap->pdev_dev,
801 "setting PPOD_EDRAM failed: %d\n", ret);
802 return -1;
803 }
804 return 0;
805 }
806
807 static void adap_config_hpfilter(struct adapter *adapter)
808 {
809 u32 param, val = 0;
810 int ret;
811
812 /* Enable HP filter region. Older fw will fail this request and
813 * it is fine.
814 */
815 param = FW_PARAM_DEV(HPFILTER_REGION_SUPPORT);
816 ret = t4_set_params(adapter, adapter->mbox, adapter->pf, 0,
817 1, &param, &val);
818
819 /* An error means FW doesn't know about HP filter support,
820 * it's not a problem, don't return an error.
821 */
822 if (ret < 0)
823 dev_err(adapter->pdev_dev,
824 "HP filter region isn't supported by FW\n");
825 }
826
827 /**
828 * cxgb4_write_rss - write the RSS table for a given port
829 * @pi: the port
830 * @queues: array of queue indices for RSS
831 *
832 * Sets up the portion of the HW RSS table for the port's VI to distribute
833 * packets to the Rx queues in @queues.
834 * Should never be called before setting up sge eth rx queues
835 */
836 int cxgb4_write_rss(const struct port_info *pi, const u16 *queues)
837 {
838 u16 *rss;
839 int i, err;
840 struct adapter *adapter = pi->adapter;
841 const struct sge_eth_rxq *rxq;
842
843 rxq = &adapter->sge.ethrxq[pi->first_qset];
844 rss = kmalloc_array(pi->rss_size, sizeof(u16), GFP_KERNEL);
845 if (!rss)
846 return -ENOMEM;
847
848 /* map the queue indices to queue ids */
849 for (i = 0; i < pi->rss_size; i++, queues++)
850 rss[i] = rxq[*queues].rspq.abs_id;
851
852 err = t4_config_rss_range(adapter, adapter->pf, pi->viid, 0,
853 pi->rss_size, rss, pi->rss_size);
854 /* If Tunnel All Lookup isn't specified in the global RSS
855 * Configuration, then we need to specify a default Ingress
856 * Queue for any ingress packets which aren't hashed. We'll
857 * use our first ingress queue ...
858 */
859 if (!err)
860 err = t4_config_vi_rss(adapter, adapter->mbox, pi->viid,
861 FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_F |
862 FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_F |
863 FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_F |
864 FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_F |
865 FW_RSS_VI_CONFIG_CMD_UDPEN_F,
866 rss[0]);
867 kfree(rss);
868 return err;
869 }
870
871 /**
872 * setup_rss - configure RSS
873 * @adap: the adapter
874 *
875 * Sets up RSS for each port.
876 */
877 static int setup_rss(struct adapter *adap)
878 {
879 int i, j, err;
880
881 for_each_port(adap, i) {
882 const struct port_info *pi = adap2pinfo(adap, i);
883
884 /* Fill default values with equal distribution */
885 for (j = 0; j < pi->rss_size; j++)
886 pi->rss[j] = j % pi->nqsets;
887
888 err = cxgb4_write_rss(pi, pi->rss);
889 if (err)
890 return err;
891 }
892 return 0;
893 }
894
895 /*
896 * Return the channel of the ingress queue with the given qid.
897 */
898 static unsigned int rxq_to_chan(const struct sge *p, unsigned int qid)
899 {
900 qid -= p->ingr_start;
901 return netdev2pinfo(p->ingr_map[qid]->netdev)->tx_chan;
902 }
903
904 void cxgb4_quiesce_rx(struct sge_rspq *q)
905 {
906 if (q->handler)
907 napi_disable(&q->napi);
908 }
909
910 /*
911 * Wait until all NAPI handlers are descheduled.
912 */
913 static void quiesce_rx(struct adapter *adap)
914 {
915 int i;
916
917 for (i = 0; i < adap->sge.ingr_sz; i++) {
918 struct sge_rspq *q = adap->sge.ingr_map[i];
919
920 if (!q)
921 continue;
922
923 cxgb4_quiesce_rx(q);
924 }
925 }
926
927 /* Disable interrupt and napi handler */
928 static void disable_interrupts(struct adapter *adap)
929 {
930 struct sge *s = &adap->sge;
931
932 if (adap->flags & CXGB4_FULL_INIT_DONE) {
933 t4_intr_disable(adap);
934 if (adap->flags & CXGB4_USING_MSIX) {
935 free_msix_queue_irqs(adap);
936 free_irq(adap->msix_info[s->nd_msix_idx].vec,
937 adap);
938 } else {
939 free_irq(adap->pdev->irq, adap);
940 }
941 quiesce_rx(adap);
942 }
943 }
944
945 void cxgb4_enable_rx(struct adapter *adap, struct sge_rspq *q)
946 {
947 if (q->handler)
948 napi_enable(&q->napi);
949
950 /* 0-increment GTS to start the timer and enable interrupts */
951 t4_write_reg(adap, MYPF_REG(SGE_PF_GTS_A),
952 SEINTARM_V(q->intr_params) |
953 INGRESSQID_V(q->cntxt_id));
954 }
955
956 /*
957 * Enable NAPI scheduling and interrupt generation for all Rx queues.
958 */
959 static void enable_rx(struct adapter *adap)
960 {
961 int i;
962
963 for (i = 0; i < adap->sge.ingr_sz; i++) {
964 struct sge_rspq *q = adap->sge.ingr_map[i];
965
966 if (!q)
967 continue;
968
969 cxgb4_enable_rx(adap, q);
970 }
971 }
972
973 static int setup_non_data_intr(struct adapter *adap)
974 {
975 int msix;
976
977 adap->sge.nd_msix_idx = -1;
978 if (!(adap->flags & CXGB4_USING_MSIX))
979 return 0;
980
981 /* Request MSI-X vector for non-data interrupt */
982 msix = cxgb4_get_msix_idx_from_bmap(adap);
983 if (msix < 0)
984 return -ENOMEM;
985
986 snprintf(adap->msix_info[msix].desc,
987 sizeof(adap->msix_info[msix].desc),
988 "%s", adap->port[0]->name);
989
990 adap->sge.nd_msix_idx = msix;
991 return 0;
992 }
993
994 static int setup_fw_sge_queues(struct adapter *adap)
995 {
996 struct sge *s = &adap->sge;
997 int msix, err = 0;
998
999 bitmap_zero(s->starving_fl, s->egr_sz);
1000 bitmap_zero(s->txq_maperr, s->egr_sz);
1001
1002 if (adap->flags & CXGB4_USING_MSIX) {
1003 s->fwevtq_msix_idx = -1;
1004 msix = cxgb4_get_msix_idx_from_bmap(adap);
1005 if (msix < 0)
1006 return -ENOMEM;
1007
1008 snprintf(adap->msix_info[msix].desc,
1009 sizeof(adap->msix_info[msix].desc),
1010 "%s-FWeventq", adap->port[0]->name);
1011 } else {
1012 err = t4_sge_alloc_rxq(adap, &s->intrq, false, adap->port[0], 0,
1013 NULL, NULL, NULL, -1);
1014 if (err)
1015 return err;
1016 msix = -((int)s->intrq.abs_id + 1);
1017 }
1018
1019 err = t4_sge_alloc_rxq(adap, &s->fw_evtq, true, adap->port[0],
1020 msix, NULL, fwevtq_handler, NULL, -1);
1021 if (err && msix >= 0)
1022 cxgb4_free_msix_idx_in_bmap(adap, msix);
1023
1024 s->fwevtq_msix_idx = msix;
1025 return err;
1026 }
1027
1028 /**
1029 * setup_sge_queues - configure SGE Tx/Rx/response queues
1030 * @adap: the adapter
1031 *
1032 * Determines how many sets of SGE queues to use and initializes them.
1033 * We support multiple queue sets per port if we have MSI-X, otherwise
1034 * just one queue set per port.
1035 */
1036 static int setup_sge_queues(struct adapter *adap)
1037 {
1038 struct sge_uld_rxq_info *rxq_info = NULL;
1039 struct sge *s = &adap->sge;
1040 unsigned int cmplqid = 0;
1041 int err, i, j, msix = 0;
1042
1043 if (is_uld(adap))
1044 rxq_info = s->uld_rxq_info[CXGB4_ULD_RDMA];
1045
1046 if (!(adap->flags & CXGB4_USING_MSIX))
1047 msix = -((int)s->intrq.abs_id + 1);
1048
1049 for_each_port(adap, i) {
1050 struct net_device *dev = adap->port[i];
1051 struct port_info *pi = netdev_priv(dev);
1052 struct sge_eth_rxq *q = &s->ethrxq[pi->first_qset];
1053 struct sge_eth_txq *t = &s->ethtxq[pi->first_qset];
1054
1055 for (j = 0; j < pi->nqsets; j++, q++) {
1056 if (msix >= 0) {
1057 msix = cxgb4_get_msix_idx_from_bmap(adap);
1058 if (msix < 0) {
1059 err = msix;
1060 goto freeout;
1061 }
1062
1063 snprintf(adap->msix_info[msix].desc,
1064 sizeof(adap->msix_info[msix].desc),
1065 "%s-Rx%d", dev->name, j);
1066 q->msix = &adap->msix_info[msix];
1067 }
1068
1069 err = t4_sge_alloc_rxq(adap, &q->rspq, false, dev,
1070 msix, &q->fl,
1071 t4_ethrx_handler,
1072 NULL,
1073 t4_get_tp_ch_map(adap,
1074 pi->tx_chan));
1075 if (err)
1076 goto freeout;
1077 q->rspq.idx = j;
1078 memset(&q->stats, 0, sizeof(q->stats));
1079 }
1080
1081 q = &s->ethrxq[pi->first_qset];
1082 for (j = 0; j < pi->nqsets; j++, t++, q++) {
1083 err = t4_sge_alloc_eth_txq(adap, t, dev,
1084 netdev_get_tx_queue(dev, j),
1085 q->rspq.cntxt_id,
1086 !!(adap->flags & CXGB4_SGE_DBQ_TIMER));
1087 if (err)
1088 goto freeout;
1089 }
1090 }
1091
1092 for_each_port(adap, i) {
1093 /* Note that cmplqid below is 0 if we don't
1094 * have RDMA queues, and that's the right value.
1095 */
1096 if (rxq_info)
1097 cmplqid = rxq_info->uldrxq[i].rspq.cntxt_id;
1098
1099 err = t4_sge_alloc_ctrl_txq(adap, &s->ctrlq[i], adap->port[i],
1100 s->fw_evtq.cntxt_id, cmplqid);
1101 if (err)
1102 goto freeout;
1103 }
1104
1105 if (!is_t4(adap->params.chip)) {
1106 err = t4_sge_alloc_eth_txq(adap, &s->ptptxq, adap->port[0],
1107 netdev_get_tx_queue(adap->port[0], 0)
1108 , s->fw_evtq.cntxt_id, false);
1109 if (err)
1110 goto freeout;
1111 }
1112
1113 t4_write_reg(adap, is_t4(adap->params.chip) ?
1114 MPS_TRC_RSS_CONTROL_A :
1115 MPS_T5_TRC_RSS_CONTROL_A,
1116 RSSCONTROL_V(netdev2pinfo(adap->port[0])->tx_chan) |
1117 QUEUENUMBER_V(s->ethrxq[0].rspq.abs_id));
1118 return 0;
1119 freeout:
1120 dev_err(adap->pdev_dev, "Can't allocate queues, err=%d\n", -err);
1121 t4_free_sge_resources(adap);
1122 return err;
1123 }
1124
1125 static u16 cxgb_select_queue(struct net_device *dev, struct sk_buff *skb,
1126 struct net_device *sb_dev)
1127 {
1128 int txq;
1129
1130 #ifdef CONFIG_CHELSIO_T4_DCB
1131 /* If a Data Center Bridging has been successfully negotiated on this
1132 * link then we'll use the skb's priority to map it to a TX Queue.
1133 * The skb's priority is determined via the VLAN Tag Priority Code
1134 * Point field.
1135 */
1136 if (cxgb4_dcb_enabled(dev) && !is_kdump_kernel()) {
1137 u16 vlan_tci;
1138 int err;
1139
1140 err = vlan_get_tag(skb, &vlan_tci);
1141 if (unlikely(err)) {
1142 if (net_ratelimit())
1143 netdev_warn(dev,
1144 "TX Packet without VLAN Tag on DCB Link\n");
1145 txq = 0;
1146 } else {
1147 txq = (vlan_tci & VLAN_PRIO_MASK) >> VLAN_PRIO_SHIFT;
1148 #ifdef CONFIG_CHELSIO_T4_FCOE
1149 if (skb->protocol == htons(ETH_P_FCOE))
1150 txq = skb->priority & 0x7;
1151 #endif /* CONFIG_CHELSIO_T4_FCOE */
1152 }
1153 return txq;
1154 }
1155 #endif /* CONFIG_CHELSIO_T4_DCB */
1156
1157 if (dev->num_tc) {
1158 struct port_info *pi = netdev2pinfo(dev);
1159 u8 ver, proto;
1160
1161 ver = ip_hdr(skb)->version;
1162 proto = (ver == 6) ? ipv6_hdr(skb)->nexthdr :
1163 ip_hdr(skb)->protocol;
1164
1165 /* Send unsupported traffic pattern to normal NIC queues. */
1166 txq = netdev_pick_tx(dev, skb, sb_dev);
1167 if (xfrm_offload(skb) || is_ptp_enabled(skb, dev) ||
1168 skb->encapsulation ||
1169 (proto != IPPROTO_TCP && proto != IPPROTO_UDP))
1170 txq = txq % pi->nqsets;
1171
1172 return txq;
1173 }
1174
1175 if (select_queue) {
1176 txq = (skb_rx_queue_recorded(skb)
1177 ? skb_get_rx_queue(skb)
1178 : smp_processor_id());
1179
1180 while (unlikely(txq >= dev->real_num_tx_queues))
1181 txq -= dev->real_num_tx_queues;
1182
1183 return txq;
1184 }
1185
1186 return netdev_pick_tx(dev, skb, NULL) % dev->real_num_tx_queues;
1187 }
1188
1189 static int closest_timer(const struct sge *s, int time)
1190 {
1191 int i, delta, match = 0, min_delta = INT_MAX;
1192
1193 for (i = 0; i < ARRAY_SIZE(s->timer_val); i++) {
1194 delta = time - s->timer_val[i];
1195 if (delta < 0)
1196 delta = -delta;
1197 if (delta < min_delta) {
1198 min_delta = delta;
1199 match = i;
1200 }
1201 }
1202 return match;
1203 }
1204
1205 static int closest_thres(const struct sge *s, int thres)
1206 {
1207 int i, delta, match = 0, min_delta = INT_MAX;
1208
1209 for (i = 0; i < ARRAY_SIZE(s->counter_val); i++) {
1210 delta = thres - s->counter_val[i];
1211 if (delta < 0)
1212 delta = -delta;
1213 if (delta < min_delta) {
1214 min_delta = delta;
1215 match = i;
1216 }
1217 }
1218 return match;
1219 }
1220
1221 /**
1222 * cxgb4_set_rspq_intr_params - set a queue's interrupt holdoff parameters
1223 * @q: the Rx queue
1224 * @us: the hold-off time in us, or 0 to disable timer
1225 * @cnt: the hold-off packet count, or 0 to disable counter
1226 *
1227 * Sets an Rx queue's interrupt hold-off time and packet count. At least
1228 * one of the two needs to be enabled for the queue to generate interrupts.
1229 */
1230 int cxgb4_set_rspq_intr_params(struct sge_rspq *q,
1231 unsigned int us, unsigned int cnt)
1232 {
1233 struct adapter *adap = q->adap;
1234
1235 if ((us | cnt) == 0)
1236 cnt = 1;
1237
1238 if (cnt) {
1239 int err;
1240 u32 v, new_idx;
1241
1242 new_idx = closest_thres(&adap->sge, cnt);
1243 if (q->desc && q->pktcnt_idx != new_idx) {
1244 /* the queue has already been created, update it */
1245 v = FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DMAQ) |
1246 FW_PARAMS_PARAM_X_V(
1247 FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH) |
1248 FW_PARAMS_PARAM_YZ_V(q->cntxt_id);
1249 err = t4_set_params(adap, adap->mbox, adap->pf, 0, 1,
1250 &v, &new_idx);
1251 if (err)
1252 return err;
1253 }
1254 q->pktcnt_idx = new_idx;
1255 }
1256
1257 us = us == 0 ? 6 : closest_timer(&adap->sge, us);
1258 q->intr_params = QINTR_TIMER_IDX_V(us) | QINTR_CNT_EN_V(cnt > 0);
1259 return 0;
1260 }
1261
1262 static int cxgb_set_features(struct net_device *dev, netdev_features_t features)
1263 {
1264 const struct port_info *pi = netdev_priv(dev);
1265 netdev_features_t changed = dev->features ^ features;
1266 int err;
1267
1268 if (!(changed & NETIF_F_HW_VLAN_CTAG_RX))
1269 return 0;
1270
1271 err = t4_set_rxmode(pi->adapter, pi->adapter->pf, pi->viid, -1,
1272 -1, -1, -1,
1273 !!(features & NETIF_F_HW_VLAN_CTAG_RX), true);
1274 if (unlikely(err))
1275 dev->features = features ^ NETIF_F_HW_VLAN_CTAG_RX;
1276 return err;
1277 }
1278
1279 static int setup_debugfs(struct adapter *adap)
1280 {
1281 if (IS_ERR_OR_NULL(adap->debugfs_root))
1282 return -1;
1283
1284 #ifdef CONFIG_DEBUG_FS
1285 t4_setup_debugfs(adap);
1286 #endif
1287 return 0;
1288 }
1289
1290 /*
1291 * upper-layer driver support
1292 */
1293
1294 /*
1295 * Allocate an active-open TID and set it to the supplied value.
1296 */
1297 int cxgb4_alloc_atid(struct tid_info *t, void *data)
1298 {
1299 int atid = -1;
1300
1301 spin_lock_bh(&t->atid_lock);
1302 if (t->afree) {
1303 union aopen_entry *p = t->afree;
1304
1305 atid = (p - t->atid_tab) + t->atid_base;
1306 t->afree = p->next;
1307 p->data = data;
1308 t->atids_in_use++;
1309 }
1310 spin_unlock_bh(&t->atid_lock);
1311 return atid;
1312 }
1313 EXPORT_SYMBOL(cxgb4_alloc_atid);
1314
1315 /*
1316 * Release an active-open TID.
1317 */
1318 void cxgb4_free_atid(struct tid_info *t, unsigned int atid)
1319 {
1320 union aopen_entry *p = &t->atid_tab[atid - t->atid_base];
1321
1322 spin_lock_bh(&t->atid_lock);
1323 p->next = t->afree;
1324 t->afree = p;
1325 t->atids_in_use--;
1326 spin_unlock_bh(&t->atid_lock);
1327 }
1328 EXPORT_SYMBOL(cxgb4_free_atid);
1329
1330 /*
1331 * Allocate a server TID and set it to the supplied value.
1332 */
1333 int cxgb4_alloc_stid(struct tid_info *t, int family, void *data)
1334 {
1335 int stid;
1336
1337 spin_lock_bh(&t->stid_lock);
1338 if (family == PF_INET) {
1339 stid = find_first_zero_bit(t->stid_bmap, t->nstids);
1340 if (stid < t->nstids)
1341 __set_bit(stid, t->stid_bmap);
1342 else
1343 stid = -1;
1344 } else {
1345 stid = bitmap_find_free_region(t->stid_bmap, t->nstids, 1);
1346 if (stid < 0)
1347 stid = -1;
1348 }
1349 if (stid >= 0) {
1350 t->stid_tab[stid].data = data;
1351 stid += t->stid_base;
1352 /* IPv6 requires max of 520 bits or 16 cells in TCAM
1353 * This is equivalent to 4 TIDs. With CLIP enabled it
1354 * needs 2 TIDs.
1355 */
1356 if (family == PF_INET6) {
1357 t->stids_in_use += 2;
1358 t->v6_stids_in_use += 2;
1359 } else {
1360 t->stids_in_use++;
1361 }
1362 }
1363 spin_unlock_bh(&t->stid_lock);
1364 return stid;
1365 }
1366 EXPORT_SYMBOL(cxgb4_alloc_stid);
1367
1368 /* Allocate a server filter TID and set it to the supplied value.
1369 */
1370 int cxgb4_alloc_sftid(struct tid_info *t, int family, void *data)
1371 {
1372 int stid;
1373
1374 spin_lock_bh(&t->stid_lock);
1375 if (family == PF_INET) {
1376 stid = find_next_zero_bit(t->stid_bmap,
1377 t->nstids + t->nsftids, t->nstids);
1378 if (stid < (t->nstids + t->nsftids))
1379 __set_bit(stid, t->stid_bmap);
1380 else
1381 stid = -1;
1382 } else {
1383 stid = -1;
1384 }
1385 if (stid >= 0) {
1386 t->stid_tab[stid].data = data;
1387 stid -= t->nstids;
1388 stid += t->sftid_base;
1389 t->sftids_in_use++;
1390 }
1391 spin_unlock_bh(&t->stid_lock);
1392 return stid;
1393 }
1394 EXPORT_SYMBOL(cxgb4_alloc_sftid);
1395
1396 /* Release a server TID.
1397 */
1398 void cxgb4_free_stid(struct tid_info *t, unsigned int stid, int family)
1399 {
1400 /* Is it a server filter TID? */
1401 if (t->nsftids && (stid >= t->sftid_base)) {
1402 stid -= t->sftid_base;
1403 stid += t->nstids;
1404 } else {
1405 stid -= t->stid_base;
1406 }
1407
1408 spin_lock_bh(&t->stid_lock);
1409 if (family == PF_INET)
1410 __clear_bit(stid, t->stid_bmap);
1411 else
1412 bitmap_release_region(t->stid_bmap, stid, 1);
1413 t->stid_tab[stid].data = NULL;
1414 if (stid < t->nstids) {
1415 if (family == PF_INET6) {
1416 t->stids_in_use -= 2;
1417 t->v6_stids_in_use -= 2;
1418 } else {
1419 t->stids_in_use--;
1420 }
1421 } else {
1422 t->sftids_in_use--;
1423 }
1424
1425 spin_unlock_bh(&t->stid_lock);
1426 }
1427 EXPORT_SYMBOL(cxgb4_free_stid);
1428
1429 /*
1430 * Populate a TID_RELEASE WR. Caller must properly size the skb.
1431 */
1432 static void mk_tid_release(struct sk_buff *skb, unsigned int chan,
1433 unsigned int tid)
1434 {
1435 struct cpl_tid_release *req;
1436
1437 set_wr_txq(skb, CPL_PRIORITY_SETUP, chan);
1438 req = __skb_put(skb, sizeof(*req));
1439 INIT_TP_WR(req, tid);
1440 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_TID_RELEASE, tid));
1441 }
1442
1443 /*
1444 * Queue a TID release request and if necessary schedule a work queue to
1445 * process it.
1446 */
1447 static void cxgb4_queue_tid_release(struct tid_info *t, unsigned int chan,
1448 unsigned int tid)
1449 {
1450 struct adapter *adap = container_of(t, struct adapter, tids);
1451 void **p = &t->tid_tab[tid - t->tid_base];
1452
1453 spin_lock_bh(&adap->tid_release_lock);
1454 *p = adap->tid_release_head;
1455 /* Low 2 bits encode the Tx channel number */
1456 adap->tid_release_head = (void **)((uintptr_t)p | chan);
1457 if (!adap->tid_release_task_busy) {
1458 adap->tid_release_task_busy = true;
1459 queue_work(adap->workq, &adap->tid_release_task);
1460 }
1461 spin_unlock_bh(&adap->tid_release_lock);
1462 }
1463
1464 /*
1465 * Process the list of pending TID release requests.
1466 */
1467 static void process_tid_release_list(struct work_struct *work)
1468 {
1469 struct sk_buff *skb;
1470 struct adapter *adap;
1471
1472 adap = container_of(work, struct adapter, tid_release_task);
1473
1474 spin_lock_bh(&adap->tid_release_lock);
1475 while (adap->tid_release_head) {
1476 void **p = adap->tid_release_head;
1477 unsigned int chan = (uintptr_t)p & 3;
1478 p = (void *)p - chan;
1479
1480 adap->tid_release_head = *p;
1481 *p = NULL;
1482 spin_unlock_bh(&adap->tid_release_lock);
1483
1484 while (!(skb = alloc_skb(sizeof(struct cpl_tid_release),
1485 GFP_KERNEL)))
1486 schedule_timeout_uninterruptible(1);
1487
1488 mk_tid_release(skb, chan, p - adap->tids.tid_tab);
1489 t4_ofld_send(adap, skb);
1490 spin_lock_bh(&adap->tid_release_lock);
1491 }
1492 adap->tid_release_task_busy = false;
1493 spin_unlock_bh(&adap->tid_release_lock);
1494 }
1495
1496 /*
1497 * Release a TID and inform HW. If we are unable to allocate the release
1498 * message we defer to a work queue.
1499 */
1500 void cxgb4_remove_tid(struct tid_info *t, unsigned int chan, unsigned int tid,
1501 unsigned short family)
1502 {
1503 struct adapter *adap = container_of(t, struct adapter, tids);
1504 struct sk_buff *skb;
1505
1506 WARN_ON(tid_out_of_range(&adap->tids, tid));
1507
1508 if (t->tid_tab[tid - adap->tids.tid_base]) {
1509 t->tid_tab[tid - adap->tids.tid_base] = NULL;
1510 atomic_dec(&t->conns_in_use);
1511 if (t->hash_base && (tid >= t->hash_base)) {
1512 if (family == AF_INET6)
1513 atomic_sub(2, &t->hash_tids_in_use);
1514 else
1515 atomic_dec(&t->hash_tids_in_use);
1516 } else {
1517 if (family == AF_INET6)
1518 atomic_sub(2, &t->tids_in_use);
1519 else
1520 atomic_dec(&t->tids_in_use);
1521 }
1522 }
1523
1524 skb = alloc_skb(sizeof(struct cpl_tid_release), GFP_ATOMIC);
1525 if (likely(skb)) {
1526 mk_tid_release(skb, chan, tid);
1527 t4_ofld_send(adap, skb);
1528 } else
1529 cxgb4_queue_tid_release(t, chan, tid);
1530 }
1531 EXPORT_SYMBOL(cxgb4_remove_tid);
1532
1533 /*
1534 * Allocate and initialize the TID tables. Returns 0 on success.
1535 */
1536 static int tid_init(struct tid_info *t)
1537 {
1538 struct adapter *adap = container_of(t, struct adapter, tids);
1539 unsigned int max_ftids = t->nftids + t->nsftids;
1540 unsigned int natids = t->natids;
1541 unsigned int hpftid_bmap_size;
1542 unsigned int eotid_bmap_size;
1543 unsigned int stid_bmap_size;
1544 unsigned int ftid_bmap_size;
1545 size_t size;
1546
1547 stid_bmap_size = BITS_TO_LONGS(t->nstids + t->nsftids);
1548 ftid_bmap_size = BITS_TO_LONGS(t->nftids);
1549 hpftid_bmap_size = BITS_TO_LONGS(t->nhpftids);
1550 eotid_bmap_size = BITS_TO_LONGS(t->neotids);
1551 size = t->ntids * sizeof(*t->tid_tab) +
1552 natids * sizeof(*t->atid_tab) +
1553 t->nstids * sizeof(*t->stid_tab) +
1554 t->nsftids * sizeof(*t->stid_tab) +
1555 stid_bmap_size * sizeof(long) +
1556 t->nhpftids * sizeof(*t->hpftid_tab) +
1557 hpftid_bmap_size * sizeof(long) +
1558 max_ftids * sizeof(*t->ftid_tab) +
1559 ftid_bmap_size * sizeof(long) +
1560 t->neotids * sizeof(*t->eotid_tab) +
1561 eotid_bmap_size * sizeof(long);
1562
1563 t->tid_tab = kvzalloc(size, GFP_KERNEL);
1564 if (!t->tid_tab)
1565 return -ENOMEM;
1566
1567 t->atid_tab = (union aopen_entry *)&t->tid_tab[t->ntids];
1568 t->stid_tab = (struct serv_entry *)&t->atid_tab[natids];
1569 t->stid_bmap = (unsigned long *)&t->stid_tab[t->nstids + t->nsftids];
1570 t->hpftid_tab = (struct filter_entry *)&t->stid_bmap[stid_bmap_size];
1571 t->hpftid_bmap = (unsigned long *)&t->hpftid_tab[t->nhpftids];
1572 t->ftid_tab = (struct filter_entry *)&t->hpftid_bmap[hpftid_bmap_size];
1573 t->ftid_bmap = (unsigned long *)&t->ftid_tab[max_ftids];
1574 t->eotid_tab = (struct eotid_entry *)&t->ftid_bmap[ftid_bmap_size];
1575 t->eotid_bmap = (unsigned long *)&t->eotid_tab[t->neotids];
1576 spin_lock_init(&t->stid_lock);
1577 spin_lock_init(&t->atid_lock);
1578 spin_lock_init(&t->ftid_lock);
1579
1580 t->stids_in_use = 0;
1581 t->v6_stids_in_use = 0;
1582 t->sftids_in_use = 0;
1583 t->afree = NULL;
1584 t->atids_in_use = 0;
1585 atomic_set(&t->tids_in_use, 0);
1586 atomic_set(&t->conns_in_use, 0);
1587 atomic_set(&t->hash_tids_in_use, 0);
1588
1589 /* Setup the free list for atid_tab and clear the stid bitmap. */
1590 if (natids) {
1591 while (--natids)
1592 t->atid_tab[natids - 1].next = &t->atid_tab[natids];
1593 t->afree = t->atid_tab;
1594 }
1595
1596 if (is_offload(adap)) {
1597 bitmap_zero(t->stid_bmap, t->nstids + t->nsftids);
1598 /* Reserve stid 0 for T4/T5 adapters */
1599 if (!t->stid_base &&
1600 CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
1601 __set_bit(0, t->stid_bmap);
1602
1603 if (t->neotids)
1604 bitmap_zero(t->eotid_bmap, t->neotids);
1605 }
1606
1607 if (t->nhpftids)
1608 bitmap_zero(t->hpftid_bmap, t->nhpftids);
1609 bitmap_zero(t->ftid_bmap, t->nftids);
1610 return 0;
1611 }
1612
1613 /**
1614 * cxgb4_create_server - create an IP server
1615 * @dev: the device
1616 * @stid: the server TID
1617 * @sip: local IP address to bind server to
1618 * @sport: the server's TCP port
1619 * @queue: queue to direct messages from this server to
1620 *
1621 * Create an IP server for the given port and address.
1622 * Returns <0 on error and one of the %NET_XMIT_* values on success.
1623 */
1624 int cxgb4_create_server(const struct net_device *dev, unsigned int stid,
1625 __be32 sip, __be16 sport, __be16 vlan,
1626 unsigned int queue)
1627 {
1628 unsigned int chan;
1629 struct sk_buff *skb;
1630 struct adapter *adap;
1631 struct cpl_pass_open_req *req;
1632 int ret;
1633
1634 skb = alloc_skb(sizeof(*req), GFP_KERNEL);
1635 if (!skb)
1636 return -ENOMEM;
1637
1638 adap = netdev2adap(dev);
1639 req = __skb_put(skb, sizeof(*req));
1640 INIT_TP_WR(req, 0);
1641 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_PASS_OPEN_REQ, stid));
1642 req->local_port = sport;
1643 req->peer_port = htons(0);
1644 req->local_ip = sip;
1645 req->peer_ip = htonl(0);
1646 chan = rxq_to_chan(&adap->sge, queue);
1647 req->opt0 = cpu_to_be64(TX_CHAN_V(chan));
1648 req->opt1 = cpu_to_be64(CONN_POLICY_V(CPL_CONN_POLICY_ASK) |
1649 SYN_RSS_ENABLE_F | SYN_RSS_QUEUE_V(queue));
1650 ret = t4_mgmt_tx(adap, skb);
1651 return net_xmit_eval(ret);
1652 }
1653 EXPORT_SYMBOL(cxgb4_create_server);
1654
1655 /* cxgb4_create_server6 - create an IPv6 server
1656 * @dev: the device
1657 * @stid: the server TID
1658 * @sip: local IPv6 address to bind server to
1659 * @sport: the server's TCP port
1660 * @queue: queue to direct messages from this server to
1661 *
1662 * Create an IPv6 server for the given port and address.
1663 * Returns <0 on error and one of the %NET_XMIT_* values on success.
1664 */
1665 int cxgb4_create_server6(const struct net_device *dev, unsigned int stid,
1666 const struct in6_addr *sip, __be16 sport,
1667 unsigned int queue)
1668 {
1669 unsigned int chan;
1670 struct sk_buff *skb;
1671 struct adapter *adap;
1672 struct cpl_pass_open_req6 *req;
1673 int ret;
1674
1675 skb = alloc_skb(sizeof(*req), GFP_KERNEL);
1676 if (!skb)
1677 return -ENOMEM;
1678
1679 adap = netdev2adap(dev);
1680 req = __skb_put(skb, sizeof(*req));
1681 INIT_TP_WR(req, 0);
1682 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_PASS_OPEN_REQ6, stid));
1683 req->local_port = sport;
1684 req->peer_port = htons(0);
1685 req->local_ip_hi = *(__be64 *)(sip->s6_addr);
1686 req->local_ip_lo = *(__be64 *)(sip->s6_addr + 8);
1687 req->peer_ip_hi = cpu_to_be64(0);
1688 req->peer_ip_lo = cpu_to_be64(0);
1689 chan = rxq_to_chan(&adap->sge, queue);
1690 req->opt0 = cpu_to_be64(TX_CHAN_V(chan));
1691 req->opt1 = cpu_to_be64(CONN_POLICY_V(CPL_CONN_POLICY_ASK) |
1692 SYN_RSS_ENABLE_F | SYN_RSS_QUEUE_V(queue));
1693 ret = t4_mgmt_tx(adap, skb);
1694 return net_xmit_eval(ret);
1695 }
1696 EXPORT_SYMBOL(cxgb4_create_server6);
1697
1698 int cxgb4_remove_server(const struct net_device *dev, unsigned int stid,
1699 unsigned int queue, bool ipv6)
1700 {
1701 struct sk_buff *skb;
1702 struct adapter *adap;
1703 struct cpl_close_listsvr_req *req;
1704 int ret;
1705
1706 adap = netdev2adap(dev);
1707
1708 skb = alloc_skb(sizeof(*req), GFP_KERNEL);
1709 if (!skb)
1710 return -ENOMEM;
1711
1712 req = __skb_put(skb, sizeof(*req));
1713 INIT_TP_WR(req, 0);
1714 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_CLOSE_LISTSRV_REQ, stid));
1715 req->reply_ctrl = htons(NO_REPLY_V(0) | (ipv6 ? LISTSVR_IPV6_V(1) :
1716 LISTSVR_IPV6_V(0)) | QUEUENO_V(queue));
1717 ret = t4_mgmt_tx(adap, skb);
1718 return net_xmit_eval(ret);
1719 }
1720 EXPORT_SYMBOL(cxgb4_remove_server);
1721
1722 /**
1723 * cxgb4_best_mtu - find the entry in the MTU table closest to an MTU
1724 * @mtus: the HW MTU table
1725 * @mtu: the target MTU
1726 * @idx: index of selected entry in the MTU table
1727 *
1728 * Returns the index and the value in the HW MTU table that is closest to
1729 * but does not exceed @mtu, unless @mtu is smaller than any value in the
1730 * table, in which case that smallest available value is selected.
1731 */
1732 unsigned int cxgb4_best_mtu(const unsigned short *mtus, unsigned short mtu,
1733 unsigned int *idx)
1734 {
1735 unsigned int i = 0;
1736
1737 while (i < NMTUS - 1 && mtus[i + 1] <= mtu)
1738 ++i;
1739 if (idx)
1740 *idx = i;
1741 return mtus[i];
1742 }
1743 EXPORT_SYMBOL(cxgb4_best_mtu);
1744
1745 /**
1746 * cxgb4_best_aligned_mtu - find best MTU, [hopefully] data size aligned
1747 * @mtus: the HW MTU table
1748 * @header_size: Header Size
1749 * @data_size_max: maximum Data Segment Size
1750 * @data_size_align: desired Data Segment Size Alignment (2^N)
1751 * @mtu_idxp: HW MTU Table Index return value pointer (possibly NULL)
1752 *
1753 * Similar to cxgb4_best_mtu() but instead of searching the Hardware
1754 * MTU Table based solely on a Maximum MTU parameter, we break that
1755 * parameter up into a Header Size and Maximum Data Segment Size, and
1756 * provide a desired Data Segment Size Alignment. If we find an MTU in
1757 * the Hardware MTU Table which will result in a Data Segment Size with
1758 * the requested alignment _and_ that MTU isn't "too far" from the
1759 * closest MTU, then we'll return that rather than the closest MTU.
1760 */
1761 unsigned int cxgb4_best_aligned_mtu(const unsigned short *mtus,
1762 unsigned short header_size,
1763 unsigned short data_size_max,
1764 unsigned short data_size_align,
1765 unsigned int *mtu_idxp)
1766 {
1767 unsigned short max_mtu = header_size + data_size_max;
1768 unsigned short data_size_align_mask = data_size_align - 1;
1769 int mtu_idx, aligned_mtu_idx;
1770
1771 /* Scan the MTU Table till we find an MTU which is larger than our
1772 * Maximum MTU or we reach the end of the table. Along the way,
1773 * record the last MTU found, if any, which will result in a Data
1774 * Segment Length matching the requested alignment.
1775 */
1776 for (mtu_idx = 0, aligned_mtu_idx = -1; mtu_idx < NMTUS; mtu_idx++) {
1777 unsigned short data_size = mtus[mtu_idx] - header_size;
1778
1779 /* If this MTU minus the Header Size would result in a
1780 * Data Segment Size of the desired alignment, remember it.
1781 */
1782 if ((data_size & data_size_align_mask) == 0)
1783 aligned_mtu_idx = mtu_idx;
1784
1785 /* If we're not at the end of the Hardware MTU Table and the
1786 * next element is larger than our Maximum MTU, drop out of
1787 * the loop.
1788 */
1789 if (mtu_idx+1 < NMTUS && mtus[mtu_idx+1] > max_mtu)
1790 break;
1791 }
1792
1793 /* If we fell out of the loop because we ran to the end of the table,
1794 * then we just have to use the last [largest] entry.
1795 */
1796 if (mtu_idx == NMTUS)
1797 mtu_idx--;
1798
1799 /* If we found an MTU which resulted in the requested Data Segment
1800 * Length alignment and that's "not far" from the largest MTU which is
1801 * less than or equal to the maximum MTU, then use that.
1802 */
1803 if (aligned_mtu_idx >= 0 &&
1804 mtu_idx - aligned_mtu_idx <= 1)
1805 mtu_idx = aligned_mtu_idx;
1806
1807 /* If the caller has passed in an MTU Index pointer, pass the
1808 * MTU Index back. Return the MTU value.
1809 */
1810 if (mtu_idxp)
1811 *mtu_idxp = mtu_idx;
1812 return mtus[mtu_idx];
1813 }
1814 EXPORT_SYMBOL(cxgb4_best_aligned_mtu);
1815
1816 /**
1817 * cxgb4_port_chan - get the HW channel of a port
1818 * @dev: the net device for the port
1819 *
1820 * Return the HW Tx channel of the given port.
1821 */
1822 unsigned int cxgb4_port_chan(const struct net_device *dev)
1823 {
1824 return netdev2pinfo(dev)->tx_chan;
1825 }
1826 EXPORT_SYMBOL(cxgb4_port_chan);
1827
1828 /**
1829 * cxgb4_port_e2cchan - get the HW c-channel of a port
1830 * @dev: the net device for the port
1831 *
1832 * Return the HW RX c-channel of the given port.
1833 */
1834 unsigned int cxgb4_port_e2cchan(const struct net_device *dev)
1835 {
1836 return netdev2pinfo(dev)->rx_cchan;
1837 }
1838 EXPORT_SYMBOL(cxgb4_port_e2cchan);
1839
1840 unsigned int cxgb4_dbfifo_count(const struct net_device *dev, int lpfifo)
1841 {
1842 struct adapter *adap = netdev2adap(dev);
1843 u32 v1, v2, lp_count, hp_count;
1844
1845 v1 = t4_read_reg(adap, SGE_DBFIFO_STATUS_A);
1846 v2 = t4_read_reg(adap, SGE_DBFIFO_STATUS2_A);
1847 if (is_t4(adap->params.chip)) {
1848 lp_count = LP_COUNT_G(v1);
1849 hp_count = HP_COUNT_G(v1);
1850 } else {
1851 lp_count = LP_COUNT_T5_G(v1);
1852 hp_count = HP_COUNT_T5_G(v2);
1853 }
1854 return lpfifo ? lp_count : hp_count;
1855 }
1856 EXPORT_SYMBOL(cxgb4_dbfifo_count);
1857
1858 /**
1859 * cxgb4_port_viid - get the VI id of a port
1860 * @dev: the net device for the port
1861 *
1862 * Return the VI id of the given port.
1863 */
1864 unsigned int cxgb4_port_viid(const struct net_device *dev)
1865 {
1866 return netdev2pinfo(dev)->viid;
1867 }
1868 EXPORT_SYMBOL(cxgb4_port_viid);
1869
1870 /**
1871 * cxgb4_port_idx - get the index of a port
1872 * @dev: the net device for the port
1873 *
1874 * Return the index of the given port.
1875 */
1876 unsigned int cxgb4_port_idx(const struct net_device *dev)
1877 {
1878 return netdev2pinfo(dev)->port_id;
1879 }
1880 EXPORT_SYMBOL(cxgb4_port_idx);
1881
1882 void cxgb4_get_tcp_stats(struct pci_dev *pdev, struct tp_tcp_stats *v4,
1883 struct tp_tcp_stats *v6)
1884 {
1885 struct adapter *adap = pci_get_drvdata(pdev);
1886
1887 spin_lock(&adap->stats_lock);
1888 t4_tp_get_tcp_stats(adap, v4, v6, false);
1889 spin_unlock(&adap->stats_lock);
1890 }
1891 EXPORT_SYMBOL(cxgb4_get_tcp_stats);
1892
1893 void cxgb4_iscsi_init(struct net_device *dev, unsigned int tag_mask,
1894 const unsigned int *pgsz_order)
1895 {
1896 struct adapter *adap = netdev2adap(dev);
1897
1898 t4_write_reg(adap, ULP_RX_ISCSI_TAGMASK_A, tag_mask);
1899 t4_write_reg(adap, ULP_RX_ISCSI_PSZ_A, HPZ0_V(pgsz_order[0]) |
1900 HPZ1_V(pgsz_order[1]) | HPZ2_V(pgsz_order[2]) |
1901 HPZ3_V(pgsz_order[3]));
1902 }
1903 EXPORT_SYMBOL(cxgb4_iscsi_init);
1904
1905 int cxgb4_flush_eq_cache(struct net_device *dev)
1906 {
1907 struct adapter *adap = netdev2adap(dev);
1908
1909 return t4_sge_ctxt_flush(adap, adap->mbox, CTXT_EGRESS);
1910 }
1911 EXPORT_SYMBOL(cxgb4_flush_eq_cache);
1912
1913 static int read_eq_indices(struct adapter *adap, u16 qid, u16 *pidx, u16 *cidx)
1914 {
1915 u32 addr = t4_read_reg(adap, SGE_DBQ_CTXT_BADDR_A) + 24 * qid + 8;
1916 __be64 indices;
1917 int ret;
1918
1919 spin_lock(&adap->win0_lock);
1920 ret = t4_memory_rw(adap, 0, MEM_EDC0, addr,
1921 sizeof(indices), (__be32 *)&indices,
1922 T4_MEMORY_READ);
1923 spin_unlock(&adap->win0_lock);
1924 if (!ret) {
1925 *cidx = (be64_to_cpu(indices) >> 25) & 0xffff;
1926 *pidx = (be64_to_cpu(indices) >> 9) & 0xffff;
1927 }
1928 return ret;
1929 }
1930
1931 int cxgb4_sync_txq_pidx(struct net_device *dev, u16 qid, u16 pidx,
1932 u16 size)
1933 {
1934 struct adapter *adap = netdev2adap(dev);
1935 u16 hw_pidx, hw_cidx;
1936 int ret;
1937
1938 ret = read_eq_indices(adap, qid, &hw_pidx, &hw_cidx);
1939 if (ret)
1940 goto out;
1941
1942 if (pidx != hw_pidx) {
1943 u16 delta;
1944 u32 val;
1945
1946 if (pidx >= hw_pidx)
1947 delta = pidx - hw_pidx;
1948 else
1949 delta = size - hw_pidx + pidx;
1950
1951 if (is_t4(adap->params.chip))
1952 val = PIDX_V(delta);
1953 else
1954 val = PIDX_T5_V(delta);
1955 wmb();
1956 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A),
1957 QID_V(qid) | val);
1958 }
1959 out:
1960 return ret;
1961 }
1962 EXPORT_SYMBOL(cxgb4_sync_txq_pidx);
1963
1964 int cxgb4_read_tpte(struct net_device *dev, u32 stag, __be32 *tpte)
1965 {
1966 u32 edc0_size, edc1_size, mc0_size, mc1_size, size;
1967 u32 edc0_end, edc1_end, mc0_end, mc1_end;
1968 u32 offset, memtype, memaddr;
1969 struct adapter *adap;
1970 u32 hma_size = 0;
1971 int ret;
1972
1973 adap = netdev2adap(dev);
1974
1975 offset = ((stag >> 8) * 32) + adap->vres.stag.start;
1976
1977 /* Figure out where the offset lands in the Memory Type/Address scheme.
1978 * This code assumes that the memory is laid out starting at offset 0
1979 * with no breaks as: EDC0, EDC1, MC0, MC1. All cards have both EDC0
1980 * and EDC1. Some cards will have neither MC0 nor MC1, most cards have
1981 * MC0, and some have both MC0 and MC1.
1982 */
1983 size = t4_read_reg(adap, MA_EDRAM0_BAR_A);
1984 edc0_size = EDRAM0_SIZE_G(size) << 20;
1985 size = t4_read_reg(adap, MA_EDRAM1_BAR_A);
1986 edc1_size = EDRAM1_SIZE_G(size) << 20;
1987 size = t4_read_reg(adap, MA_EXT_MEMORY0_BAR_A);
1988 mc0_size = EXT_MEM0_SIZE_G(size) << 20;
1989
1990 if (t4_read_reg(adap, MA_TARGET_MEM_ENABLE_A) & HMA_MUX_F) {
1991 size = t4_read_reg(adap, MA_EXT_MEMORY1_BAR_A);
1992 hma_size = EXT_MEM1_SIZE_G(size) << 20;
1993 }
1994 edc0_end = edc0_size;
1995 edc1_end = edc0_end + edc1_size;
1996 mc0_end = edc1_end + mc0_size;
1997
1998 if (offset < edc0_end) {
1999 memtype = MEM_EDC0;
2000 memaddr = offset;
2001 } else if (offset < edc1_end) {
2002 memtype = MEM_EDC1;
2003 memaddr = offset - edc0_end;
2004 } else {
2005 if (hma_size && (offset < (edc1_end + hma_size))) {
2006 memtype = MEM_HMA;
2007 memaddr = offset - edc1_end;
2008 } else if (offset < mc0_end) {
2009 memtype = MEM_MC0;
2010 memaddr = offset - edc1_end;
2011 } else if (is_t5(adap->params.chip)) {
2012 size = t4_read_reg(adap, MA_EXT_MEMORY1_BAR_A);
2013 mc1_size = EXT_MEM1_SIZE_G(size) << 20;
2014 mc1_end = mc0_end + mc1_size;
2015 if (offset < mc1_end) {
2016 memtype = MEM_MC1;
2017 memaddr = offset - mc0_end;
2018 } else {
2019 /* offset beyond the end of any memory */
2020 goto err;
2021 }
2022 } else {
2023 /* T4/T6 only has a single memory channel */
2024 goto err;
2025 }
2026 }
2027
2028 spin_lock(&adap->win0_lock);
2029 ret = t4_memory_rw(adap, 0, memtype, memaddr, 32, tpte, T4_MEMORY_READ);
2030 spin_unlock(&adap->win0_lock);
2031 return ret;
2032
2033 err:
2034 dev_err(adap->pdev_dev, "stag %#x, offset %#x out of range\n",
2035 stag, offset);
2036 return -EINVAL;
2037 }
2038 EXPORT_SYMBOL(cxgb4_read_tpte);
2039
2040 u64 cxgb4_read_sge_timestamp(struct net_device *dev)
2041 {
2042 u32 hi, lo;
2043 struct adapter *adap;
2044
2045 adap = netdev2adap(dev);
2046 lo = t4_read_reg(adap, SGE_TIMESTAMP_LO_A);
2047 hi = TSVAL_G(t4_read_reg(adap, SGE_TIMESTAMP_HI_A));
2048
2049 return ((u64)hi << 32) | (u64)lo;
2050 }
2051 EXPORT_SYMBOL(cxgb4_read_sge_timestamp);
2052
2053 int cxgb4_bar2_sge_qregs(struct net_device *dev,
2054 unsigned int qid,
2055 enum cxgb4_bar2_qtype qtype,
2056 int user,
2057 u64 *pbar2_qoffset,
2058 unsigned int *pbar2_qid)
2059 {
2060 return t4_bar2_sge_qregs(netdev2adap(dev),
2061 qid,
2062 (qtype == CXGB4_BAR2_QTYPE_EGRESS
2063 ? T4_BAR2_QTYPE_EGRESS
2064 : T4_BAR2_QTYPE_INGRESS),
2065 user,
2066 pbar2_qoffset,
2067 pbar2_qid);
2068 }
2069 EXPORT_SYMBOL(cxgb4_bar2_sge_qregs);
2070
2071 static struct pci_driver cxgb4_driver;
2072
2073 static void check_neigh_update(struct neighbour *neigh)
2074 {
2075 const struct device *parent;
2076 const struct net_device *netdev = neigh->dev;
2077
2078 if (is_vlan_dev(netdev))
2079 netdev = vlan_dev_real_dev(netdev);
2080 parent = netdev->dev.parent;
2081 if (parent && parent->driver == &cxgb4_driver.driver)
2082 t4_l2t_update(dev_get_drvdata(parent), neigh);
2083 }
2084
2085 static int netevent_cb(struct notifier_block *nb, unsigned long event,
2086 void *data)
2087 {
2088 switch (event) {
2089 case NETEVENT_NEIGH_UPDATE:
2090 check_neigh_update(data);
2091 break;
2092 case NETEVENT_REDIRECT:
2093 default:
2094 break;
2095 }
2096 return 0;
2097 }
2098
2099 static bool netevent_registered;
2100 static struct notifier_block cxgb4_netevent_nb = {
2101 .notifier_call = netevent_cb
2102 };
2103
2104 static void drain_db_fifo(struct adapter *adap, int usecs)
2105 {
2106 u32 v1, v2, lp_count, hp_count;
2107
2108 do {
2109 v1 = t4_read_reg(adap, SGE_DBFIFO_STATUS_A);
2110 v2 = t4_read_reg(adap, SGE_DBFIFO_STATUS2_A);
2111 if (is_t4(adap->params.chip)) {
2112 lp_count = LP_COUNT_G(v1);
2113 hp_count = HP_COUNT_G(v1);
2114 } else {
2115 lp_count = LP_COUNT_T5_G(v1);
2116 hp_count = HP_COUNT_T5_G(v2);
2117 }
2118
2119 if (lp_count == 0 && hp_count == 0)
2120 break;
2121 set_current_state(TASK_UNINTERRUPTIBLE);
2122 schedule_timeout(usecs_to_jiffies(usecs));
2123 } while (1);
2124 }
2125
2126 static void disable_txq_db(struct sge_txq *q)
2127 {
2128 unsigned long flags;
2129
2130 spin_lock_irqsave(&q->db_lock, flags);
2131 q->db_disabled = 1;
2132 spin_unlock_irqrestore(&q->db_lock, flags);
2133 }
2134
2135 static void enable_txq_db(struct adapter *adap, struct sge_txq *q)
2136 {
2137 spin_lock_irq(&q->db_lock);
2138 if (q->db_pidx_inc) {
2139 /* Make sure that all writes to the TX descriptors
2140 * are committed before we tell HW about them.
2141 */
2142 wmb();
2143 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A),
2144 QID_V(q->cntxt_id) | PIDX_V(q->db_pidx_inc));
2145 q->db_pidx_inc = 0;
2146 }
2147 q->db_disabled = 0;
2148 spin_unlock_irq(&q->db_lock);
2149 }
2150
2151 static void disable_dbs(struct adapter *adap)
2152 {
2153 int i;
2154
2155 for_each_ethrxq(&adap->sge, i)
2156 disable_txq_db(&adap->sge.ethtxq[i].q);
2157 if (is_offload(adap)) {
2158 struct sge_uld_txq_info *txq_info =
2159 adap->sge.uld_txq_info[CXGB4_TX_OFLD];
2160
2161 if (txq_info) {
2162 for_each_ofldtxq(&adap->sge, i) {
2163 struct sge_uld_txq *txq = &txq_info->uldtxq[i];
2164
2165 disable_txq_db(&txq->q);
2166 }
2167 }
2168 }
2169 for_each_port(adap, i)
2170 disable_txq_db(&adap->sge.ctrlq[i].q);
2171 }
2172
2173 static void enable_dbs(struct adapter *adap)
2174 {
2175 int i;
2176
2177 for_each_ethrxq(&adap->sge, i)
2178 enable_txq_db(adap, &adap->sge.ethtxq[i].q);
2179 if (is_offload(adap)) {
2180 struct sge_uld_txq_info *txq_info =
2181 adap->sge.uld_txq_info[CXGB4_TX_OFLD];
2182
2183 if (txq_info) {
2184 for_each_ofldtxq(&adap->sge, i) {
2185 struct sge_uld_txq *txq = &txq_info->uldtxq[i];
2186
2187 enable_txq_db(adap, &txq->q);
2188 }
2189 }
2190 }
2191 for_each_port(adap, i)
2192 enable_txq_db(adap, &adap->sge.ctrlq[i].q);
2193 }
2194
2195 static void notify_rdma_uld(struct adapter *adap, enum cxgb4_control cmd)
2196 {
2197 enum cxgb4_uld type = CXGB4_ULD_RDMA;
2198
2199 if (adap->uld && adap->uld[type].handle)
2200 adap->uld[type].control(adap->uld[type].handle, cmd);
2201 }
2202
2203 static void process_db_full(struct work_struct *work)
2204 {
2205 struct adapter *adap;
2206
2207 adap = container_of(work, struct adapter, db_full_task);
2208
2209 drain_db_fifo(adap, dbfifo_drain_delay);
2210 enable_dbs(adap);
2211 notify_rdma_uld(adap, CXGB4_CONTROL_DB_EMPTY);
2212 if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
2213 t4_set_reg_field(adap, SGE_INT_ENABLE3_A,
2214 DBFIFO_HP_INT_F | DBFIFO_LP_INT_F,
2215 DBFIFO_HP_INT_F | DBFIFO_LP_INT_F);
2216 else
2217 t4_set_reg_field(adap, SGE_INT_ENABLE3_A,
2218 DBFIFO_LP_INT_F, DBFIFO_LP_INT_F);
2219 }
2220
2221 static void sync_txq_pidx(struct adapter *adap, struct sge_txq *q)
2222 {
2223 u16 hw_pidx, hw_cidx;
2224 int ret;
2225
2226 spin_lock_irq(&q->db_lock);
2227 ret = read_eq_indices(adap, (u16)q->cntxt_id, &hw_pidx, &hw_cidx);
2228 if (ret)
2229 goto out;
2230 if (q->db_pidx != hw_pidx) {
2231 u16 delta;
2232 u32 val;
2233
2234 if (q->db_pidx >= hw_pidx)
2235 delta = q->db_pidx - hw_pidx;
2236 else
2237 delta = q->size - hw_pidx + q->db_pidx;
2238
2239 if (is_t4(adap->params.chip))
2240 val = PIDX_V(delta);
2241 else
2242 val = PIDX_T5_V(delta);
2243 wmb();
2244 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A),
2245 QID_V(q->cntxt_id) | val);
2246 }
2247 out:
2248 q->db_disabled = 0;
2249 q->db_pidx_inc = 0;
2250 spin_unlock_irq(&q->db_lock);
2251 if (ret)
2252 CH_WARN(adap, "DB drop recovery failed.\n");
2253 }
2254
2255 static void recover_all_queues(struct adapter *adap)
2256 {
2257 int i;
2258
2259 for_each_ethrxq(&adap->sge, i)
2260 sync_txq_pidx(adap, &adap->sge.ethtxq[i].q);
2261 if (is_offload(adap)) {
2262 struct sge_uld_txq_info *txq_info =
2263 adap->sge.uld_txq_info[CXGB4_TX_OFLD];
2264 if (txq_info) {
2265 for_each_ofldtxq(&adap->sge, i) {
2266 struct sge_uld_txq *txq = &txq_info->uldtxq[i];
2267
2268 sync_txq_pidx(adap, &txq->q);
2269 }
2270 }
2271 }
2272 for_each_port(adap, i)
2273 sync_txq_pidx(adap, &adap->sge.ctrlq[i].q);
2274 }
2275
2276 static void process_db_drop(struct work_struct *work)
2277 {
2278 struct adapter *adap;
2279
2280 adap = container_of(work, struct adapter, db_drop_task);
2281
2282 if (is_t4(adap->params.chip)) {
2283 drain_db_fifo(adap, dbfifo_drain_delay);
2284 notify_rdma_uld(adap, CXGB4_CONTROL_DB_DROP);
2285 drain_db_fifo(adap, dbfifo_drain_delay);
2286 recover_all_queues(adap);
2287 drain_db_fifo(adap, dbfifo_drain_delay);
2288 enable_dbs(adap);
2289 notify_rdma_uld(adap, CXGB4_CONTROL_DB_EMPTY);
2290 } else if (is_t5(adap->params.chip)) {
2291 u32 dropped_db = t4_read_reg(adap, 0x010ac);
2292 u16 qid = (dropped_db >> 15) & 0x1ffff;
2293 u16 pidx_inc = dropped_db & 0x1fff;
2294 u64 bar2_qoffset;
2295 unsigned int bar2_qid;
2296 int ret;
2297
2298 ret = t4_bar2_sge_qregs(adap, qid, T4_BAR2_QTYPE_EGRESS,
2299 0, &bar2_qoffset, &bar2_qid);
2300 if (ret)
2301 dev_err(adap->pdev_dev, "doorbell drop recovery: "
2302 "qid=%d, pidx_inc=%d\n", qid, pidx_inc);
2303 else
2304 writel(PIDX_T5_V(pidx_inc) | QID_V(bar2_qid),
2305 adap->bar2 + bar2_qoffset + SGE_UDB_KDOORBELL);
2306
2307 /* Re-enable BAR2 WC */
2308 t4_set_reg_field(adap, 0x10b0, 1<<15, 1<<15);
2309 }
2310
2311 if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
2312 t4_set_reg_field(adap, SGE_DOORBELL_CONTROL_A, DROPPED_DB_F, 0);
2313 }
2314
2315 void t4_db_full(struct adapter *adap)
2316 {
2317 if (is_t4(adap->params.chip)) {
2318 disable_dbs(adap);
2319 notify_rdma_uld(adap, CXGB4_CONTROL_DB_FULL);
2320 t4_set_reg_field(adap, SGE_INT_ENABLE3_A,
2321 DBFIFO_HP_INT_F | DBFIFO_LP_INT_F, 0);
2322 queue_work(adap->workq, &adap->db_full_task);
2323 }
2324 }
2325
2326 void t4_db_dropped(struct adapter *adap)
2327 {
2328 if (is_t4(adap->params.chip)) {
2329 disable_dbs(adap);
2330 notify_rdma_uld(adap, CXGB4_CONTROL_DB_FULL);
2331 }
2332 queue_work(adap->workq, &adap->db_drop_task);
2333 }
2334
2335 void t4_register_netevent_notifier(void)
2336 {
2337 if (!netevent_registered) {
2338 register_netevent_notifier(&cxgb4_netevent_nb);
2339 netevent_registered = true;
2340 }
2341 }
2342
2343 static void detach_ulds(struct adapter *adap)
2344 {
2345 unsigned int i;
2346
2347 mutex_lock(&uld_mutex);
2348 list_del(&adap->list_node);
2349
2350 for (i = 0; i < CXGB4_ULD_MAX; i++)
2351 if (adap->uld && adap->uld[i].handle)
2352 adap->uld[i].state_change(adap->uld[i].handle,
2353 CXGB4_STATE_DETACH);
2354
2355 if (netevent_registered && list_empty(&adapter_list)) {
2356 unregister_netevent_notifier(&cxgb4_netevent_nb);
2357 netevent_registered = false;
2358 }
2359 mutex_unlock(&uld_mutex);
2360 }
2361
2362 static void notify_ulds(struct adapter *adap, enum cxgb4_state new_state)
2363 {
2364 unsigned int i;
2365
2366 mutex_lock(&uld_mutex);
2367 for (i = 0; i < CXGB4_ULD_MAX; i++)
2368 if (adap->uld && adap->uld[i].handle)
2369 adap->uld[i].state_change(adap->uld[i].handle,
2370 new_state);
2371 mutex_unlock(&uld_mutex);
2372 }
2373
2374 #if IS_ENABLED(CONFIG_IPV6)
2375 static int cxgb4_inet6addr_handler(struct notifier_block *this,
2376 unsigned long event, void *data)
2377 {
2378 struct inet6_ifaddr *ifa = data;
2379 struct net_device *event_dev = ifa->idev->dev;
2380 const struct device *parent = NULL;
2381 #if IS_ENABLED(CONFIG_BONDING)
2382 struct adapter *adap;
2383 #endif
2384 if (is_vlan_dev(event_dev))
2385 event_dev = vlan_dev_real_dev(event_dev);
2386 #if IS_ENABLED(CONFIG_BONDING)
2387 if (event_dev->flags & IFF_MASTER) {
2388 list_for_each_entry(adap, &adapter_list, list_node) {
2389 switch (event) {
2390 case NETDEV_UP:
2391 cxgb4_clip_get(adap->port[0],
2392 (const u32 *)ifa, 1);
2393 break;
2394 case NETDEV_DOWN:
2395 cxgb4_clip_release(adap->port[0],
2396 (const u32 *)ifa, 1);
2397 break;
2398 default:
2399 break;
2400 }
2401 }
2402 return NOTIFY_OK;
2403 }
2404 #endif
2405
2406 if (event_dev)
2407 parent = event_dev->dev.parent;
2408
2409 if (parent && parent->driver == &cxgb4_driver.driver) {
2410 switch (event) {
2411 case NETDEV_UP:
2412 cxgb4_clip_get(event_dev, (const u32 *)ifa, 1);
2413 break;
2414 case NETDEV_DOWN:
2415 cxgb4_clip_release(event_dev, (const u32 *)ifa, 1);
2416 break;
2417 default:
2418 break;
2419 }
2420 }
2421 return NOTIFY_OK;
2422 }
2423
2424 static bool inet6addr_registered;
2425 static struct notifier_block cxgb4_inet6addr_notifier = {
2426 .notifier_call = cxgb4_inet6addr_handler
2427 };
2428
2429 static void update_clip(const struct adapter *adap)
2430 {
2431 int i;
2432 struct net_device *dev;
2433 int ret;
2434
2435 rcu_read_lock();
2436
2437 for (i = 0; i < MAX_NPORTS; i++) {
2438 dev = adap->port[i];
2439 ret = 0;
2440
2441 if (dev)
2442 ret = cxgb4_update_root_dev_clip(dev);
2443
2444 if (ret < 0)
2445 break;
2446 }
2447 rcu_read_unlock();
2448 }
2449 #endif /* IS_ENABLED(CONFIG_IPV6) */
2450
2451 /**
2452 * cxgb_up - enable the adapter
2453 * @adap: adapter being enabled
2454 *
2455 * Called when the first port is enabled, this function performs the
2456 * actions necessary to make an adapter operational, such as completing
2457 * the initialization of HW modules, and enabling interrupts.
2458 *
2459 * Must be called with the rtnl lock held.
2460 */
2461 static int cxgb_up(struct adapter *adap)
2462 {
2463 struct sge *s = &adap->sge;
2464 int err;
2465
2466 mutex_lock(&uld_mutex);
2467 err = setup_sge_queues(adap);
2468 if (err)
2469 goto rel_lock;
2470 err = setup_rss(adap);
2471 if (err)
2472 goto freeq;
2473
2474 if (adap->flags & CXGB4_USING_MSIX) {
2475 if (s->nd_msix_idx < 0) {
2476 err = -ENOMEM;
2477 goto irq_err;
2478 }
2479
2480 err = request_irq(adap->msix_info[s->nd_msix_idx].vec,
2481 t4_nondata_intr, 0,
2482 adap->msix_info[s->nd_msix_idx].desc, adap);
2483 if (err)
2484 goto irq_err;
2485
2486 err = request_msix_queue_irqs(adap);
2487 if (err)
2488 goto irq_err_free_nd_msix;
2489 } else {
2490 err = request_irq(adap->pdev->irq, t4_intr_handler(adap),
2491 (adap->flags & CXGB4_USING_MSI) ? 0
2492 : IRQF_SHARED,
2493 adap->port[0]->name, adap);
2494 if (err)
2495 goto irq_err;
2496 }
2497
2498 enable_rx(adap);
2499 t4_sge_start(adap);
2500 t4_intr_enable(adap);
2501 adap->flags |= CXGB4_FULL_INIT_DONE;
2502 mutex_unlock(&uld_mutex);
2503
2504 notify_ulds(adap, CXGB4_STATE_UP);
2505 #if IS_ENABLED(CONFIG_IPV6)
2506 update_clip(adap);
2507 #endif
2508 return err;
2509
2510 irq_err_free_nd_msix:
2511 free_irq(adap->msix_info[s->nd_msix_idx].vec, adap);
2512 irq_err:
2513 dev_err(adap->pdev_dev, "request_irq failed, err %d\n", err);
2514 freeq:
2515 t4_free_sge_resources(adap);
2516 rel_lock:
2517 mutex_unlock(&uld_mutex);
2518 return err;
2519 }
2520
2521 static void cxgb_down(struct adapter *adapter)
2522 {
2523 cancel_work_sync(&adapter->tid_release_task);
2524 cancel_work_sync(&adapter->db_full_task);
2525 cancel_work_sync(&adapter->db_drop_task);
2526 adapter->tid_release_task_busy = false;
2527 adapter->tid_release_head = NULL;
2528
2529 t4_sge_stop(adapter);
2530 t4_free_sge_resources(adapter);
2531
2532 adapter->flags &= ~CXGB4_FULL_INIT_DONE;
2533 }
2534
2535 /*
2536 * net_device operations
2537 */
2538 int cxgb_open(struct net_device *dev)
2539 {
2540 struct port_info *pi = netdev_priv(dev);
2541 struct adapter *adapter = pi->adapter;
2542 int err;
2543
2544 netif_carrier_off(dev);
2545
2546 if (!(adapter->flags & CXGB4_FULL_INIT_DONE)) {
2547 err = cxgb_up(adapter);
2548 if (err < 0)
2549 return err;
2550 }
2551
2552 /* It's possible that the basic port information could have
2553 * changed since we first read it.
2554 */
2555 err = t4_update_port_info(pi);
2556 if (err < 0)
2557 return err;
2558
2559 err = link_start(dev);
2560 if (!err)
2561 netif_tx_start_all_queues(dev);
2562 return err;
2563 }
2564
2565 int cxgb_close(struct net_device *dev)
2566 {
2567 struct port_info *pi = netdev_priv(dev);
2568 struct adapter *adapter = pi->adapter;
2569 int ret;
2570
2571 netif_tx_stop_all_queues(dev);
2572 netif_carrier_off(dev);
2573 ret = t4_enable_pi_params(adapter, adapter->pf, pi,
2574 false, false, false);
2575 #ifdef CONFIG_CHELSIO_T4_DCB
2576 cxgb4_dcb_reset(dev);
2577 dcb_tx_queue_prio_enable(dev, false);
2578 #endif
2579 return ret;
2580 }
2581
2582 int cxgb4_create_server_filter(const struct net_device *dev, unsigned int stid,
2583 __be32 sip, __be16 sport, __be16 vlan,
2584 unsigned int queue, unsigned char port, unsigned char mask)
2585 {
2586 int ret;
2587 struct filter_entry *f;
2588 struct adapter *adap;
2589 int i;
2590 u8 *val;
2591
2592 adap = netdev2adap(dev);
2593
2594 /* Adjust stid to correct filter index */
2595 stid -= adap->tids.sftid_base;
2596 stid += adap->tids.nftids;
2597
2598 /* Check to make sure the filter requested is writable ...
2599 */
2600 f = &adap->tids.ftid_tab[stid];
2601 ret = writable_filter(f);
2602 if (ret)
2603 return ret;
2604
2605 /* Clear out any old resources being used by the filter before
2606 * we start constructing the new filter.
2607 */
2608 if (f->valid)
2609 clear_filter(adap, f);
2610
2611 /* Clear out filter specifications */
2612 memset(&f->fs, 0, sizeof(struct ch_filter_specification));
2613 f->fs.val.lport = cpu_to_be16(sport);
2614 f->fs.mask.lport = ~0;
2615 val = (u8 *)&sip;
2616 if ((val[0] | val[1] | val[2] | val[3]) != 0) {
2617 for (i = 0; i < 4; i++) {
2618 f->fs.val.lip[i] = val[i];
2619 f->fs.mask.lip[i] = ~0;
2620 }
2621 if (adap->params.tp.vlan_pri_map & PORT_F) {
2622 f->fs.val.iport = port;
2623 f->fs.mask.iport = mask;
2624 }
2625 }
2626
2627 if (adap->params.tp.vlan_pri_map & PROTOCOL_F) {
2628 f->fs.val.proto = IPPROTO_TCP;
2629 f->fs.mask.proto = ~0;
2630 }
2631
2632 f->fs.dirsteer = 1;
2633 f->fs.iq = queue;
2634 /* Mark filter as locked */
2635 f->locked = 1;
2636 f->fs.rpttid = 1;
2637
2638 /* Save the actual tid. We need this to get the corresponding
2639 * filter entry structure in filter_rpl.
2640 */
2641 f->tid = stid + adap->tids.ftid_base;
2642 ret = set_filter_wr(adap, stid);
2643 if (ret) {
2644 clear_filter(adap, f);
2645 return ret;
2646 }
2647
2648 return 0;
2649 }
2650 EXPORT_SYMBOL(cxgb4_create_server_filter);
2651
2652 int cxgb4_remove_server_filter(const struct net_device *dev, unsigned int stid,
2653 unsigned int queue, bool ipv6)
2654 {
2655 struct filter_entry *f;
2656 struct adapter *adap;
2657
2658 adap = netdev2adap(dev);
2659
2660 /* Adjust stid to correct filter index */
2661 stid -= adap->tids.sftid_base;
2662 stid += adap->tids.nftids;
2663
2664 f = &adap->tids.ftid_tab[stid];
2665 /* Unlock the filter */
2666 f->locked = 0;
2667
2668 return delete_filter(adap, stid);
2669 }
2670 EXPORT_SYMBOL(cxgb4_remove_server_filter);
2671
2672 static void cxgb_get_stats(struct net_device *dev,
2673 struct rtnl_link_stats64 *ns)
2674 {
2675 struct port_stats stats;
2676 struct port_info *p = netdev_priv(dev);
2677 struct adapter *adapter = p->adapter;
2678
2679 /* Block retrieving statistics during EEH error
2680 * recovery. Otherwise, the recovery might fail
2681 * and the PCI device will be removed permanently
2682 */
2683 spin_lock(&adapter->stats_lock);
2684 if (!netif_device_present(dev)) {
2685 spin_unlock(&adapter->stats_lock);
2686 return;
2687 }
2688 t4_get_port_stats_offset(adapter, p->tx_chan, &stats,
2689 &p->stats_base);
2690 spin_unlock(&adapter->stats_lock);
2691
2692 ns->tx_bytes = stats.tx_octets;
2693 ns->tx_packets = stats.tx_frames;
2694 ns->rx_bytes = stats.rx_octets;
2695 ns->rx_packets = stats.rx_frames;
2696 ns->multicast = stats.rx_mcast_frames;
2697
2698 /* detailed rx_errors */
2699 ns->rx_length_errors = stats.rx_jabber + stats.rx_too_long +
2700 stats.rx_runt;
2701 ns->rx_over_errors = 0;
2702 ns->rx_crc_errors = stats.rx_fcs_err;
2703 ns->rx_frame_errors = stats.rx_symbol_err;
2704 ns->rx_dropped = stats.rx_ovflow0 + stats.rx_ovflow1 +
2705 stats.rx_ovflow2 + stats.rx_ovflow3 +
2706 stats.rx_trunc0 + stats.rx_trunc1 +
2707 stats.rx_trunc2 + stats.rx_trunc3;
2708 ns->rx_missed_errors = 0;
2709
2710 /* detailed tx_errors */
2711 ns->tx_aborted_errors = 0;
2712 ns->tx_carrier_errors = 0;
2713 ns->tx_fifo_errors = 0;
2714 ns->tx_heartbeat_errors = 0;
2715 ns->tx_window_errors = 0;
2716
2717 ns->tx_errors = stats.tx_error_frames;
2718 ns->rx_errors = stats.rx_symbol_err + stats.rx_fcs_err +
2719 ns->rx_length_errors + stats.rx_len_err + ns->rx_fifo_errors;
2720 }
2721
2722 static int cxgb_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
2723 {
2724 unsigned int mbox;
2725 int ret = 0, prtad, devad;
2726 struct port_info *pi = netdev_priv(dev);
2727 struct adapter *adapter = pi->adapter;
2728 struct mii_ioctl_data *data = (struct mii_ioctl_data *)&req->ifr_data;
2729
2730 switch (cmd) {
2731 case SIOCGMIIPHY:
2732 if (pi->mdio_addr < 0)
2733 return -EOPNOTSUPP;
2734 data->phy_id = pi->mdio_addr;
2735 break;
2736 case SIOCGMIIREG:
2737 case SIOCSMIIREG:
2738 if (mdio_phy_id_is_c45(data->phy_id)) {
2739 prtad = mdio_phy_id_prtad(data->phy_id);
2740 devad = mdio_phy_id_devad(data->phy_id);
2741 } else if (data->phy_id < 32) {
2742 prtad = data->phy_id;
2743 devad = 0;
2744 data->reg_num &= 0x1f;
2745 } else
2746 return -EINVAL;
2747
2748 mbox = pi->adapter->pf;
2749 if (cmd == SIOCGMIIREG)
2750 ret = t4_mdio_rd(pi->adapter, mbox, prtad, devad,
2751 data->reg_num, &data->val_out);
2752 else
2753 ret = t4_mdio_wr(pi->adapter, mbox, prtad, devad,
2754 data->reg_num, data->val_in);
2755 break;
2756 case SIOCGHWTSTAMP:
2757 return copy_to_user(req->ifr_data, &pi->tstamp_config,
2758 sizeof(pi->tstamp_config)) ?
2759 -EFAULT : 0;
2760 case SIOCSHWTSTAMP:
2761 if (copy_from_user(&pi->tstamp_config, req->ifr_data,
2762 sizeof(pi->tstamp_config)))
2763 return -EFAULT;
2764
2765 if (!is_t4(adapter->params.chip)) {
2766 switch (pi->tstamp_config.tx_type) {
2767 case HWTSTAMP_TX_OFF:
2768 case HWTSTAMP_TX_ON:
2769 break;
2770 default:
2771 return -ERANGE;
2772 }
2773
2774 switch (pi->tstamp_config.rx_filter) {
2775 case HWTSTAMP_FILTER_NONE:
2776 pi->rxtstamp = false;
2777 break;
2778 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
2779 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
2780 cxgb4_ptprx_timestamping(pi, pi->port_id,
2781 PTP_TS_L4);
2782 break;
2783 case HWTSTAMP_FILTER_PTP_V2_EVENT:
2784 cxgb4_ptprx_timestamping(pi, pi->port_id,
2785 PTP_TS_L2_L4);
2786 break;
2787 case HWTSTAMP_FILTER_ALL:
2788 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
2789 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
2790 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
2791 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
2792 pi->rxtstamp = true;
2793 break;
2794 default:
2795 pi->tstamp_config.rx_filter =
2796 HWTSTAMP_FILTER_NONE;
2797 return -ERANGE;
2798 }
2799
2800 if ((pi->tstamp_config.tx_type == HWTSTAMP_TX_OFF) &&
2801 (pi->tstamp_config.rx_filter ==
2802 HWTSTAMP_FILTER_NONE)) {
2803 if (cxgb4_ptp_txtype(adapter, pi->port_id) >= 0)
2804 pi->ptp_enable = false;
2805 }
2806
2807 if (pi->tstamp_config.rx_filter !=
2808 HWTSTAMP_FILTER_NONE) {
2809 if (cxgb4_ptp_redirect_rx_packet(adapter,
2810 pi) >= 0)
2811 pi->ptp_enable = true;
2812 }
2813 } else {
2814 /* For T4 Adapters */
2815 switch (pi->tstamp_config.rx_filter) {
2816 case HWTSTAMP_FILTER_NONE:
2817 pi->rxtstamp = false;
2818 break;
2819 case HWTSTAMP_FILTER_ALL:
2820 pi->rxtstamp = true;
2821 break;
2822 default:
2823 pi->tstamp_config.rx_filter =
2824 HWTSTAMP_FILTER_NONE;
2825 return -ERANGE;
2826 }
2827 }
2828 return copy_to_user(req->ifr_data, &pi->tstamp_config,
2829 sizeof(pi->tstamp_config)) ?
2830 -EFAULT : 0;
2831 default:
2832 return -EOPNOTSUPP;
2833 }
2834 return ret;
2835 }
2836
2837 static void cxgb_set_rxmode(struct net_device *dev)
2838 {
2839 /* unfortunately we can't return errors to the stack */
2840 set_rxmode(dev, -1, false);
2841 }
2842
2843 static int cxgb_change_mtu(struct net_device *dev, int new_mtu)
2844 {
2845 int ret;
2846 struct port_info *pi = netdev_priv(dev);
2847
2848 ret = t4_set_rxmode(pi->adapter, pi->adapter->pf, pi->viid, new_mtu, -1,
2849 -1, -1, -1, true);
2850 if (!ret)
2851 dev->mtu = new_mtu;
2852 return ret;
2853 }
2854
2855 #ifdef CONFIG_PCI_IOV
2856 static int cxgb4_mgmt_open(struct net_device *dev)
2857 {
2858 /* Turn carrier off since we don't have to transmit anything on this
2859 * interface.
2860 */
2861 netif_carrier_off(dev);
2862 return 0;
2863 }
2864
2865 /* Fill MAC address that will be assigned by the FW */
2866 static void cxgb4_mgmt_fill_vf_station_mac_addr(struct adapter *adap)
2867 {
2868 u8 hw_addr[ETH_ALEN], macaddr[ETH_ALEN];
2869 unsigned int i, vf, nvfs;
2870 u16 a, b;
2871 int err;
2872 u8 *na;
2873
2874 adap->params.pci.vpd_cap_addr = pci_find_capability(adap->pdev,
2875 PCI_CAP_ID_VPD);
2876 err = t4_get_raw_vpd_params(adap, &adap->params.vpd);
2877 if (err)
2878 return;
2879
2880 na = adap->params.vpd.na;
2881 for (i = 0; i < ETH_ALEN; i++)
2882 hw_addr[i] = (hex2val(na[2 * i + 0]) * 16 +
2883 hex2val(na[2 * i + 1]));
2884
2885 a = (hw_addr[0] << 8) | hw_addr[1];
2886 b = (hw_addr[1] << 8) | hw_addr[2];
2887 a ^= b;
2888 a |= 0x0200; /* locally assigned Ethernet MAC address */
2889 a &= ~0x0100; /* not a multicast Ethernet MAC address */
2890 macaddr[0] = a >> 8;
2891 macaddr[1] = a & 0xff;
2892
2893 for (i = 2; i < 5; i++)
2894 macaddr[i] = hw_addr[i + 1];
2895
2896 for (vf = 0, nvfs = pci_sriov_get_totalvfs(adap->pdev);
2897 vf < nvfs; vf++) {
2898 macaddr[5] = adap->pf * nvfs + vf;
2899 ether_addr_copy(adap->vfinfo[vf].vf_mac_addr, macaddr);
2900 }
2901 }
2902
2903 static int cxgb4_mgmt_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
2904 {
2905 struct port_info *pi = netdev_priv(dev);
2906 struct adapter *adap = pi->adapter;
2907 int ret;
2908
2909 /* verify MAC addr is valid */
2910 if (!is_valid_ether_addr(mac)) {
2911 dev_err(pi->adapter->pdev_dev,
2912 "Invalid Ethernet address %pM for VF %d\n",
2913 mac, vf);
2914 return -EINVAL;
2915 }
2916
2917 dev_info(pi->adapter->pdev_dev,
2918 "Setting MAC %pM on VF %d\n", mac, vf);
2919 ret = t4_set_vf_mac_acl(adap, vf + 1, 1, mac);
2920 if (!ret)
2921 ether_addr_copy(adap->vfinfo[vf].vf_mac_addr, mac);
2922 return ret;
2923 }
2924
2925 static int cxgb4_mgmt_get_vf_config(struct net_device *dev,
2926 int vf, struct ifla_vf_info *ivi)
2927 {
2928 struct port_info *pi = netdev_priv(dev);
2929 struct adapter *adap = pi->adapter;
2930 struct vf_info *vfinfo;
2931
2932 if (vf >= adap->num_vfs)
2933 return -EINVAL;
2934 vfinfo = &adap->vfinfo[vf];
2935
2936 ivi->vf = vf;
2937 ivi->max_tx_rate = vfinfo->tx_rate;
2938 ivi->min_tx_rate = 0;
2939 ether_addr_copy(ivi->mac, vfinfo->vf_mac_addr);
2940 ivi->vlan = vfinfo->vlan;
2941 ivi->linkstate = vfinfo->link_state;
2942 return 0;
2943 }
2944
2945 static int cxgb4_mgmt_get_phys_port_id(struct net_device *dev,
2946 struct netdev_phys_item_id *ppid)
2947 {
2948 struct port_info *pi = netdev_priv(dev);
2949 unsigned int phy_port_id;
2950
2951 phy_port_id = pi->adapter->adap_idx * 10 + pi->port_id;
2952 ppid->id_len = sizeof(phy_port_id);
2953 memcpy(ppid->id, &phy_port_id, ppid->id_len);
2954 return 0;
2955 }
2956
2957 static int cxgb4_mgmt_set_vf_rate(struct net_device *dev, int vf,
2958 int min_tx_rate, int max_tx_rate)
2959 {
2960 struct port_info *pi = netdev_priv(dev);
2961 struct adapter *adap = pi->adapter;
2962 unsigned int link_ok, speed, mtu;
2963 u32 fw_pfvf, fw_class;
2964 int class_id = vf;
2965 int ret;
2966 u16 pktsize;
2967
2968 if (vf >= adap->num_vfs)
2969 return -EINVAL;
2970
2971 if (min_tx_rate) {
2972 dev_err(adap->pdev_dev,
2973 "Min tx rate (%d) (> 0) for VF %d is Invalid.\n",
2974 min_tx_rate, vf);
2975 return -EINVAL;
2976 }
2977
2978 if (max_tx_rate == 0) {
2979 /* unbind VF to to any Traffic Class */
2980 fw_pfvf =
2981 (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) |
2982 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_SCHEDCLASS_ETH));
2983 fw_class = 0xffffffff;
2984 ret = t4_set_params(adap, adap->mbox, adap->pf, vf + 1, 1,
2985 &fw_pfvf, &fw_class);
2986 if (ret) {
2987 dev_err(adap->pdev_dev,
2988 "Err %d in unbinding PF %d VF %d from TX Rate Limiting\n",
2989 ret, adap->pf, vf);
2990 return -EINVAL;
2991 }
2992 dev_info(adap->pdev_dev,
2993 "PF %d VF %d is unbound from TX Rate Limiting\n",
2994 adap->pf, vf);
2995 adap->vfinfo[vf].tx_rate = 0;
2996 return 0;
2997 }
2998
2999 ret = t4_get_link_params(pi, &link_ok, &speed, &mtu);
3000 if (ret != FW_SUCCESS) {
3001 dev_err(adap->pdev_dev,
3002 "Failed to get link information for VF %d\n", vf);
3003 return -EINVAL;
3004 }
3005
3006 if (!link_ok) {
3007 dev_err(adap->pdev_dev, "Link down for VF %d\n", vf);
3008 return -EINVAL;
3009 }
3010
3011 if (max_tx_rate > speed) {
3012 dev_err(adap->pdev_dev,
3013 "Max tx rate %d for VF %d can't be > link-speed %u",
3014 max_tx_rate, vf, speed);
3015 return -EINVAL;
3016 }
3017
3018 pktsize = mtu;
3019 /* subtract ethhdr size and 4 bytes crc since, f/w appends it */
3020 pktsize = pktsize - sizeof(struct ethhdr) - 4;
3021 /* subtract ipv4 hdr size, tcp hdr size to get typical IPv4 MSS size */
3022 pktsize = pktsize - sizeof(struct iphdr) - sizeof(struct tcphdr);
3023 /* configure Traffic Class for rate-limiting */
3024 ret = t4_sched_params(adap, SCHED_CLASS_TYPE_PACKET,
3025 SCHED_CLASS_LEVEL_CL_RL,
3026 SCHED_CLASS_MODE_CLASS,
3027 SCHED_CLASS_RATEUNIT_BITS,
3028 SCHED_CLASS_RATEMODE_ABS,
3029 pi->tx_chan, class_id, 0,
3030 max_tx_rate * 1000, 0, pktsize);
3031 if (ret) {
3032 dev_err(adap->pdev_dev, "Err %d for Traffic Class config\n",
3033 ret);
3034 return -EINVAL;
3035 }
3036 dev_info(adap->pdev_dev,
3037 "Class %d with MSS %u configured with rate %u\n",
3038 class_id, pktsize, max_tx_rate);
3039
3040 /* bind VF to configured Traffic Class */
3041 fw_pfvf = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) |
3042 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_SCHEDCLASS_ETH));
3043 fw_class = class_id;
3044 ret = t4_set_params(adap, adap->mbox, adap->pf, vf + 1, 1, &fw_pfvf,
3045 &fw_class);
3046 if (ret) {
3047 dev_err(adap->pdev_dev,
3048 "Err %d in binding PF %d VF %d to Traffic Class %d\n",
3049 ret, adap->pf, vf, class_id);
3050 return -EINVAL;
3051 }
3052 dev_info(adap->pdev_dev, "PF %d VF %d is bound to Class %d\n",
3053 adap->pf, vf, class_id);
3054 adap->vfinfo[vf].tx_rate = max_tx_rate;
3055 return 0;
3056 }
3057
3058 static int cxgb4_mgmt_set_vf_vlan(struct net_device *dev, int vf,
3059 u16 vlan, u8 qos, __be16 vlan_proto)
3060 {
3061 struct port_info *pi = netdev_priv(dev);
3062 struct adapter *adap = pi->adapter;
3063 int ret;
3064
3065 if (vf >= adap->num_vfs || vlan > 4095 || qos > 7)
3066 return -EINVAL;
3067
3068 if (vlan_proto != htons(ETH_P_8021Q) || qos != 0)
3069 return -EPROTONOSUPPORT;
3070
3071 ret = t4_set_vlan_acl(adap, adap->mbox, vf + 1, vlan);
3072 if (!ret) {
3073 adap->vfinfo[vf].vlan = vlan;
3074 return 0;
3075 }
3076
3077 dev_err(adap->pdev_dev, "Err %d %s VLAN ACL for PF/VF %d/%d\n",
3078 ret, (vlan ? "setting" : "clearing"), adap->pf, vf);
3079 return ret;
3080 }
3081
3082 static int cxgb4_mgmt_set_vf_link_state(struct net_device *dev, int vf,
3083 int link)
3084 {
3085 struct port_info *pi = netdev_priv(dev);
3086 struct adapter *adap = pi->adapter;
3087 u32 param, val;
3088 int ret = 0;
3089
3090 if (vf >= adap->num_vfs)
3091 return -EINVAL;
3092
3093 switch (link) {
3094 case IFLA_VF_LINK_STATE_AUTO:
3095 val = FW_VF_LINK_STATE_AUTO;
3096 break;
3097
3098 case IFLA_VF_LINK_STATE_ENABLE:
3099 val = FW_VF_LINK_STATE_ENABLE;
3100 break;
3101
3102 case IFLA_VF_LINK_STATE_DISABLE:
3103 val = FW_VF_LINK_STATE_DISABLE;
3104 break;
3105
3106 default:
3107 return -EINVAL;
3108 }
3109
3110 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) |
3111 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_LINK_STATE));
3112 ret = t4_set_params(adap, adap->mbox, adap->pf, vf + 1, 1,
3113 &param, &val);
3114 if (ret) {
3115 dev_err(adap->pdev_dev,
3116 "Error %d in setting PF %d VF %d link state\n",
3117 ret, adap->pf, vf);
3118 return -EINVAL;
3119 }
3120
3121 adap->vfinfo[vf].link_state = link;
3122 return ret;
3123 }
3124 #endif /* CONFIG_PCI_IOV */
3125
3126 static int cxgb_set_mac_addr(struct net_device *dev, void *p)
3127 {
3128 int ret;
3129 struct sockaddr *addr = p;
3130 struct port_info *pi = netdev_priv(dev);
3131
3132 if (!is_valid_ether_addr(addr->sa_data))
3133 return -EADDRNOTAVAIL;
3134
3135 ret = cxgb4_update_mac_filt(pi, pi->viid, &pi->xact_addr_filt,
3136 addr->sa_data, true, &pi->smt_idx);
3137 if (ret < 0)
3138 return ret;
3139
3140 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
3141 pi->xact_addr_filt = ret;
3142 return 0;
3143 }
3144
3145 #ifdef CONFIG_NET_POLL_CONTROLLER
3146 static void cxgb_netpoll(struct net_device *dev)
3147 {
3148 struct port_info *pi = netdev_priv(dev);
3149 struct adapter *adap = pi->adapter;
3150
3151 if (adap->flags & CXGB4_USING_MSIX) {
3152 int i;
3153 struct sge_eth_rxq *rx = &adap->sge.ethrxq[pi->first_qset];
3154
3155 for (i = pi->nqsets; i; i--, rx++)
3156 t4_sge_intr_msix(0, &rx->rspq);
3157 } else
3158 t4_intr_handler(adap)(0, adap);
3159 }
3160 #endif
3161
3162 static int cxgb_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
3163 {
3164 struct port_info *pi = netdev_priv(dev);
3165 struct adapter *adap = pi->adapter;
3166 struct ch_sched_queue qe = { 0 };
3167 struct ch_sched_params p = { 0 };
3168 struct sched_class *e;
3169 u32 req_rate;
3170 int err = 0;
3171
3172 if (!can_sched(dev))
3173 return -ENOTSUPP;
3174
3175 if (index < 0 || index > pi->nqsets - 1)
3176 return -EINVAL;
3177
3178 if (!(adap->flags & CXGB4_FULL_INIT_DONE)) {
3179 dev_err(adap->pdev_dev,
3180 "Failed to rate limit on queue %d. Link Down?\n",
3181 index);
3182 return -EINVAL;
3183 }
3184
3185 qe.queue = index;
3186 e = cxgb4_sched_queue_lookup(dev, &qe);
3187 if (e && e->info.u.params.level != SCHED_CLASS_LEVEL_CL_RL) {
3188 dev_err(adap->pdev_dev,
3189 "Queue %u already bound to class %u of type: %u\n",
3190 index, e->idx, e->info.u.params.level);
3191 return -EBUSY;
3192 }
3193
3194 /* Convert from Mbps to Kbps */
3195 req_rate = rate * 1000;
3196
3197 /* Max rate is 100 Gbps */
3198 if (req_rate > SCHED_MAX_RATE_KBPS) {
3199 dev_err(adap->pdev_dev,
3200 "Invalid rate %u Mbps, Max rate is %u Mbps\n",
3201 rate, SCHED_MAX_RATE_KBPS / 1000);
3202 return -ERANGE;
3203 }
3204
3205 /* First unbind the queue from any existing class */
3206 memset(&qe, 0, sizeof(qe));
3207 qe.queue = index;
3208 qe.class = SCHED_CLS_NONE;
3209
3210 err = cxgb4_sched_class_unbind(dev, (void *)(&qe), SCHED_QUEUE);
3211 if (err) {
3212 dev_err(adap->pdev_dev,
3213 "Unbinding Queue %d on port %d fail. Err: %d\n",
3214 index, pi->port_id, err);
3215 return err;
3216 }
3217
3218 /* Queue already unbound */
3219 if (!req_rate)
3220 return 0;
3221
3222 /* Fetch any available unused or matching scheduling class */
3223 p.type = SCHED_CLASS_TYPE_PACKET;
3224 p.u.params.level = SCHED_CLASS_LEVEL_CL_RL;
3225 p.u.params.mode = SCHED_CLASS_MODE_CLASS;
3226 p.u.params.rateunit = SCHED_CLASS_RATEUNIT_BITS;
3227 p.u.params.ratemode = SCHED_CLASS_RATEMODE_ABS;
3228 p.u.params.channel = pi->tx_chan;
3229 p.u.params.class = SCHED_CLS_NONE;
3230 p.u.params.minrate = 0;
3231 p.u.params.maxrate = req_rate;
3232 p.u.params.weight = 0;
3233 p.u.params.pktsize = dev->mtu;
3234
3235 e = cxgb4_sched_class_alloc(dev, &p);
3236 if (!e)
3237 return -ENOMEM;
3238
3239 /* Bind the queue to a scheduling class */
3240 memset(&qe, 0, sizeof(qe));
3241 qe.queue = index;
3242 qe.class = e->idx;
3243
3244 err = cxgb4_sched_class_bind(dev, (void *)(&qe), SCHED_QUEUE);
3245 if (err)
3246 dev_err(adap->pdev_dev,
3247 "Queue rate limiting failed. Err: %d\n", err);
3248 return err;
3249 }
3250
3251 static int cxgb_setup_tc_flower(struct net_device *dev,
3252 struct flow_cls_offload *cls_flower)
3253 {
3254 switch (cls_flower->command) {
3255 case FLOW_CLS_REPLACE:
3256 return cxgb4_tc_flower_replace(dev, cls_flower);
3257 case FLOW_CLS_DESTROY:
3258 return cxgb4_tc_flower_destroy(dev, cls_flower);
3259 case FLOW_CLS_STATS:
3260 return cxgb4_tc_flower_stats(dev, cls_flower);
3261 default:
3262 return -EOPNOTSUPP;
3263 }
3264 }
3265
3266 static int cxgb_setup_tc_cls_u32(struct net_device *dev,
3267 struct tc_cls_u32_offload *cls_u32)
3268 {
3269 switch (cls_u32->command) {
3270 case TC_CLSU32_NEW_KNODE:
3271 case TC_CLSU32_REPLACE_KNODE:
3272 return cxgb4_config_knode(dev, cls_u32);
3273 case TC_CLSU32_DELETE_KNODE:
3274 return cxgb4_delete_knode(dev, cls_u32);
3275 default:
3276 return -EOPNOTSUPP;
3277 }
3278 }
3279
3280 static int cxgb_setup_tc_matchall(struct net_device *dev,
3281 struct tc_cls_matchall_offload *cls_matchall,
3282 bool ingress)
3283 {
3284 struct adapter *adap = netdev2adap(dev);
3285
3286 if (!adap->tc_matchall)
3287 return -ENOMEM;
3288
3289 switch (cls_matchall->command) {
3290 case TC_CLSMATCHALL_REPLACE:
3291 return cxgb4_tc_matchall_replace(dev, cls_matchall, ingress);
3292 case TC_CLSMATCHALL_DESTROY:
3293 return cxgb4_tc_matchall_destroy(dev, cls_matchall, ingress);
3294 case TC_CLSMATCHALL_STATS:
3295 if (ingress)
3296 return cxgb4_tc_matchall_stats(dev, cls_matchall);
3297 break;
3298 default:
3299 break;
3300 }
3301
3302 return -EOPNOTSUPP;
3303 }
3304
3305 static int cxgb_setup_tc_block_ingress_cb(enum tc_setup_type type,
3306 void *type_data, void *cb_priv)
3307 {
3308 struct net_device *dev = cb_priv;
3309 struct port_info *pi = netdev2pinfo(dev);
3310 struct adapter *adap = netdev2adap(dev);
3311
3312 if (!(adap->flags & CXGB4_FULL_INIT_DONE)) {
3313 dev_err(adap->pdev_dev,
3314 "Failed to setup tc on port %d. Link Down?\n",
3315 pi->port_id);
3316 return -EINVAL;
3317 }
3318
3319 if (!tc_cls_can_offload_and_chain0(dev, type_data))
3320 return -EOPNOTSUPP;
3321
3322 switch (type) {
3323 case TC_SETUP_CLSU32:
3324 return cxgb_setup_tc_cls_u32(dev, type_data);
3325 case TC_SETUP_CLSFLOWER:
3326 return cxgb_setup_tc_flower(dev, type_data);
3327 case TC_SETUP_CLSMATCHALL:
3328 return cxgb_setup_tc_matchall(dev, type_data, true);
3329 default:
3330 return -EOPNOTSUPP;
3331 }
3332 }
3333
3334 static int cxgb_setup_tc_block_egress_cb(enum tc_setup_type type,
3335 void *type_data, void *cb_priv)
3336 {
3337 struct net_device *dev = cb_priv;
3338 struct port_info *pi = netdev2pinfo(dev);
3339 struct adapter *adap = netdev2adap(dev);
3340
3341 if (!(adap->flags & CXGB4_FULL_INIT_DONE)) {
3342 dev_err(adap->pdev_dev,
3343 "Failed to setup tc on port %d. Link Down?\n",
3344 pi->port_id);
3345 return -EINVAL;
3346 }
3347
3348 if (!tc_cls_can_offload_and_chain0(dev, type_data))
3349 return -EOPNOTSUPP;
3350
3351 switch (type) {
3352 case TC_SETUP_CLSMATCHALL:
3353 return cxgb_setup_tc_matchall(dev, type_data, false);
3354 default:
3355 break;
3356 }
3357
3358 return -EOPNOTSUPP;
3359 }
3360
3361 static int cxgb_setup_tc_mqprio(struct net_device *dev,
3362 struct tc_mqprio_qopt_offload *mqprio)
3363 {
3364 struct adapter *adap = netdev2adap(dev);
3365
3366 if (!is_ethofld(adap) || !adap->tc_mqprio)
3367 return -ENOMEM;
3368
3369 return cxgb4_setup_tc_mqprio(dev, mqprio);
3370 }
3371
3372 static LIST_HEAD(cxgb_block_cb_list);
3373
3374 static int cxgb_setup_tc_block(struct net_device *dev,
3375 struct flow_block_offload *f)
3376 {
3377 struct port_info *pi = netdev_priv(dev);
3378 flow_setup_cb_t *cb;
3379 bool ingress_only;
3380
3381 pi->tc_block_shared = f->block_shared;
3382 if (f->binder_type == FLOW_BLOCK_BINDER_TYPE_CLSACT_EGRESS) {
3383 cb = cxgb_setup_tc_block_egress_cb;
3384 ingress_only = false;
3385 } else {
3386 cb = cxgb_setup_tc_block_ingress_cb;
3387 ingress_only = true;
3388 }
3389
3390 return flow_block_cb_setup_simple(f, &cxgb_block_cb_list,
3391 cb, pi, dev, ingress_only);
3392 }
3393
3394 static int cxgb_setup_tc(struct net_device *dev, enum tc_setup_type type,
3395 void *type_data)
3396 {
3397 switch (type) {
3398 case TC_SETUP_QDISC_MQPRIO:
3399 return cxgb_setup_tc_mqprio(dev, type_data);
3400 case TC_SETUP_BLOCK:
3401 return cxgb_setup_tc_block(dev, type_data);
3402 default:
3403 return -EOPNOTSUPP;
3404 }
3405 }
3406
3407 static void cxgb_del_udp_tunnel(struct net_device *netdev,
3408 struct udp_tunnel_info *ti)
3409 {
3410 struct port_info *pi = netdev_priv(netdev);
3411 struct adapter *adapter = pi->adapter;
3412 unsigned int chip_ver = CHELSIO_CHIP_VERSION(adapter->params.chip);
3413 u8 match_all_mac[] = { 0, 0, 0, 0, 0, 0 };
3414 int ret = 0, i;
3415
3416 if (chip_ver < CHELSIO_T6)
3417 return;
3418
3419 switch (ti->type) {
3420 case UDP_TUNNEL_TYPE_VXLAN:
3421 if (!adapter->vxlan_port_cnt ||
3422 adapter->vxlan_port != ti->port)
3423 return; /* Invalid VxLAN destination port */
3424
3425 adapter->vxlan_port_cnt--;
3426 if (adapter->vxlan_port_cnt)
3427 return;
3428
3429 adapter->vxlan_port = 0;
3430 t4_write_reg(adapter, MPS_RX_VXLAN_TYPE_A, 0);
3431 break;
3432 case UDP_TUNNEL_TYPE_GENEVE:
3433 if (!adapter->geneve_port_cnt ||
3434 adapter->geneve_port != ti->port)
3435 return; /* Invalid GENEVE destination port */
3436
3437 adapter->geneve_port_cnt--;
3438 if (adapter->geneve_port_cnt)
3439 return;
3440
3441 adapter->geneve_port = 0;
3442 t4_write_reg(adapter, MPS_RX_GENEVE_TYPE_A, 0);
3443 break;
3444 default:
3445 return;
3446 }
3447
3448 /* Matchall mac entries can be deleted only after all tunnel ports
3449 * are brought down or removed.
3450 */
3451 if (!adapter->rawf_cnt)
3452 return;
3453 for_each_port(adapter, i) {
3454 pi = adap2pinfo(adapter, i);
3455 ret = t4_free_raw_mac_filt(adapter, pi->viid,
3456 match_all_mac, match_all_mac,
3457 adapter->rawf_start +
3458 pi->port_id,
3459 1, pi->port_id, false);
3460 if (ret < 0) {
3461 netdev_info(netdev, "Failed to free mac filter entry, for port %d\n",
3462 i);
3463 return;
3464 }
3465 }
3466 }
3467
3468 static void cxgb_add_udp_tunnel(struct net_device *netdev,
3469 struct udp_tunnel_info *ti)
3470 {
3471 struct port_info *pi = netdev_priv(netdev);
3472 struct adapter *adapter = pi->adapter;
3473 unsigned int chip_ver = CHELSIO_CHIP_VERSION(adapter->params.chip);
3474 u8 match_all_mac[] = { 0, 0, 0, 0, 0, 0 };
3475 int i, ret;
3476
3477 if (chip_ver < CHELSIO_T6 || !adapter->rawf_cnt)
3478 return;
3479
3480 switch (ti->type) {
3481 case UDP_TUNNEL_TYPE_VXLAN:
3482 /* Callback for adding vxlan port can be called with the same
3483 * port for both IPv4 and IPv6. We should not disable the
3484 * offloading when the same port for both protocols is added
3485 * and later one of them is removed.
3486 */
3487 if (adapter->vxlan_port_cnt &&
3488 adapter->vxlan_port == ti->port) {
3489 adapter->vxlan_port_cnt++;
3490 return;
3491 }
3492
3493 /* We will support only one VxLAN port */
3494 if (adapter->vxlan_port_cnt) {
3495 netdev_info(netdev, "UDP port %d already offloaded, not adding port %d\n",
3496 be16_to_cpu(adapter->vxlan_port),
3497 be16_to_cpu(ti->port));
3498 return;
3499 }
3500
3501 adapter->vxlan_port = ti->port;
3502 adapter->vxlan_port_cnt = 1;
3503
3504 t4_write_reg(adapter, MPS_RX_VXLAN_TYPE_A,
3505 VXLAN_V(be16_to_cpu(ti->port)) | VXLAN_EN_F);
3506 break;
3507 case UDP_TUNNEL_TYPE_GENEVE:
3508 if (adapter->geneve_port_cnt &&
3509 adapter->geneve_port == ti->port) {
3510 adapter->geneve_port_cnt++;
3511 return;
3512 }
3513
3514 /* We will support only one GENEVE port */
3515 if (adapter->geneve_port_cnt) {
3516 netdev_info(netdev, "UDP port %d already offloaded, not adding port %d\n",
3517 be16_to_cpu(adapter->geneve_port),
3518 be16_to_cpu(ti->port));
3519 return;
3520 }
3521
3522 adapter->geneve_port = ti->port;
3523 adapter->geneve_port_cnt = 1;
3524
3525 t4_write_reg(adapter, MPS_RX_GENEVE_TYPE_A,
3526 GENEVE_V(be16_to_cpu(ti->port)) | GENEVE_EN_F);
3527 break;
3528 default:
3529 return;
3530 }
3531
3532 /* Create a 'match all' mac filter entry for inner mac,
3533 * if raw mac interface is supported. Once the linux kernel provides
3534 * driver entry points for adding/deleting the inner mac addresses,
3535 * we will remove this 'match all' entry and fallback to adding
3536 * exact match filters.
3537 */
3538 for_each_port(adapter, i) {
3539 pi = adap2pinfo(adapter, i);
3540
3541 ret = t4_alloc_raw_mac_filt(adapter, pi->viid,
3542 match_all_mac,
3543 match_all_mac,
3544 adapter->rawf_start +
3545 pi->port_id,
3546 1, pi->port_id, false);
3547 if (ret < 0) {
3548 netdev_info(netdev, "Failed to allocate a mac filter entry, not adding port %d\n",
3549 be16_to_cpu(ti->port));
3550 cxgb_del_udp_tunnel(netdev, ti);
3551 return;
3552 }
3553 }
3554 }
3555
3556 static netdev_features_t cxgb_features_check(struct sk_buff *skb,
3557 struct net_device *dev,
3558 netdev_features_t features)
3559 {
3560 struct port_info *pi = netdev_priv(dev);
3561 struct adapter *adapter = pi->adapter;
3562
3563 if (CHELSIO_CHIP_VERSION(adapter->params.chip) < CHELSIO_T6)
3564 return features;
3565
3566 /* Check if hw supports offload for this packet */
3567 if (!skb->encapsulation || cxgb_encap_offload_supported(skb))
3568 return features;
3569
3570 /* Offload is not supported for this encapsulated packet */
3571 return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
3572 }
3573
3574 static netdev_features_t cxgb_fix_features(struct net_device *dev,
3575 netdev_features_t features)
3576 {
3577 /* Disable GRO, if RX_CSUM is disabled */
3578 if (!(features & NETIF_F_RXCSUM))
3579 features &= ~NETIF_F_GRO;
3580
3581 return features;
3582 }
3583
3584 static const struct net_device_ops cxgb4_netdev_ops = {
3585 .ndo_open = cxgb_open,
3586 .ndo_stop = cxgb_close,
3587 .ndo_start_xmit = t4_start_xmit,
3588 .ndo_select_queue = cxgb_select_queue,
3589 .ndo_get_stats64 = cxgb_get_stats,
3590 .ndo_set_rx_mode = cxgb_set_rxmode,
3591 .ndo_set_mac_address = cxgb_set_mac_addr,
3592 .ndo_set_features = cxgb_set_features,
3593 .ndo_validate_addr = eth_validate_addr,
3594 .ndo_do_ioctl = cxgb_ioctl,
3595 .ndo_change_mtu = cxgb_change_mtu,
3596 #ifdef CONFIG_NET_POLL_CONTROLLER
3597 .ndo_poll_controller = cxgb_netpoll,
3598 #endif
3599 #ifdef CONFIG_CHELSIO_T4_FCOE
3600 .ndo_fcoe_enable = cxgb_fcoe_enable,
3601 .ndo_fcoe_disable = cxgb_fcoe_disable,
3602 #endif /* CONFIG_CHELSIO_T4_FCOE */
3603 .ndo_set_tx_maxrate = cxgb_set_tx_maxrate,
3604 .ndo_setup_tc = cxgb_setup_tc,
3605 .ndo_udp_tunnel_add = cxgb_add_udp_tunnel,
3606 .ndo_udp_tunnel_del = cxgb_del_udp_tunnel,
3607 .ndo_features_check = cxgb_features_check,
3608 .ndo_fix_features = cxgb_fix_features,
3609 };
3610
3611 #ifdef CONFIG_PCI_IOV
3612 static const struct net_device_ops cxgb4_mgmt_netdev_ops = {
3613 .ndo_open = cxgb4_mgmt_open,
3614 .ndo_set_vf_mac = cxgb4_mgmt_set_vf_mac,
3615 .ndo_get_vf_config = cxgb4_mgmt_get_vf_config,
3616 .ndo_set_vf_rate = cxgb4_mgmt_set_vf_rate,
3617 .ndo_get_phys_port_id = cxgb4_mgmt_get_phys_port_id,
3618 .ndo_set_vf_vlan = cxgb4_mgmt_set_vf_vlan,
3619 .ndo_set_vf_link_state = cxgb4_mgmt_set_vf_link_state,
3620 };
3621 #endif
3622
3623 static void cxgb4_mgmt_get_drvinfo(struct net_device *dev,
3624 struct ethtool_drvinfo *info)
3625 {
3626 struct adapter *adapter = netdev2adap(dev);
3627
3628 strlcpy(info->driver, cxgb4_driver_name, sizeof(info->driver));
3629 strlcpy(info->version, cxgb4_driver_version,
3630 sizeof(info->version));
3631 strlcpy(info->bus_info, pci_name(adapter->pdev),
3632 sizeof(info->bus_info));
3633 }
3634
3635 static const struct ethtool_ops cxgb4_mgmt_ethtool_ops = {
3636 .get_drvinfo = cxgb4_mgmt_get_drvinfo,
3637 };
3638
3639 static void notify_fatal_err(struct work_struct *work)
3640 {
3641 struct adapter *adap;
3642
3643 adap = container_of(work, struct adapter, fatal_err_notify_task);
3644 notify_ulds(adap, CXGB4_STATE_FATAL_ERROR);
3645 }
3646
3647 void t4_fatal_err(struct adapter *adap)
3648 {
3649 int port;
3650
3651 if (pci_channel_offline(adap->pdev))
3652 return;
3653
3654 /* Disable the SGE since ULDs are going to free resources that
3655 * could be exposed to the adapter. RDMA MWs for example...
3656 */
3657 t4_shutdown_adapter(adap);
3658 for_each_port(adap, port) {
3659 struct net_device *dev = adap->port[port];
3660
3661 /* If we get here in very early initialization the network
3662 * devices may not have been set up yet.
3663 */
3664 if (!dev)
3665 continue;
3666
3667 netif_tx_stop_all_queues(dev);
3668 netif_carrier_off(dev);
3669 }
3670 dev_alert(adap->pdev_dev, "encountered fatal error, adapter stopped\n");
3671 queue_work(adap->workq, &adap->fatal_err_notify_task);
3672 }
3673
3674 static void setup_memwin(struct adapter *adap)
3675 {
3676 u32 nic_win_base = t4_get_util_window(adap);
3677
3678 t4_setup_memwin(adap, nic_win_base, MEMWIN_NIC);
3679 }
3680
3681 static void setup_memwin_rdma(struct adapter *adap)
3682 {
3683 if (adap->vres.ocq.size) {
3684 u32 start;
3685 unsigned int sz_kb;
3686
3687 start = t4_read_pcie_cfg4(adap, PCI_BASE_ADDRESS_2);
3688 start &= PCI_BASE_ADDRESS_MEM_MASK;
3689 start += OCQ_WIN_OFFSET(adap->pdev, &adap->vres);
3690 sz_kb = roundup_pow_of_two(adap->vres.ocq.size) >> 10;
3691 t4_write_reg(adap,
3692 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, 3),
3693 start | BIR_V(1) | WINDOW_V(ilog2(sz_kb)));
3694 t4_write_reg(adap,
3695 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, 3),
3696 adap->vres.ocq.start);
3697 t4_read_reg(adap,
3698 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, 3));
3699 }
3700 }
3701
3702 /* HMA Definitions */
3703
3704 /* The maximum number of address that can be send in a single FW cmd */
3705 #define HMA_MAX_ADDR_IN_CMD 5
3706
3707 #define HMA_PAGE_SIZE PAGE_SIZE
3708
3709 #define HMA_MAX_NO_FW_ADDRESS (16 << 10) /* FW supports 16K addresses */
3710
3711 #define HMA_PAGE_ORDER \
3712 ((HMA_PAGE_SIZE < HMA_MAX_NO_FW_ADDRESS) ? \
3713 ilog2(HMA_MAX_NO_FW_ADDRESS / HMA_PAGE_SIZE) : 0)
3714
3715 /* The minimum and maximum possible HMA sizes that can be specified in the FW
3716 * configuration(in units of MB).
3717 */
3718 #define HMA_MIN_TOTAL_SIZE 1
3719 #define HMA_MAX_TOTAL_SIZE \
3720 (((HMA_PAGE_SIZE << HMA_PAGE_ORDER) * \
3721 HMA_MAX_NO_FW_ADDRESS) >> 20)
3722
3723 static void adap_free_hma_mem(struct adapter *adapter)
3724 {
3725 struct scatterlist *iter;
3726 struct page *page;
3727 int i;
3728
3729 if (!adapter->hma.sgt)
3730 return;
3731
3732 if (adapter->hma.flags & HMA_DMA_MAPPED_FLAG) {
3733 dma_unmap_sg(adapter->pdev_dev, adapter->hma.sgt->sgl,
3734 adapter->hma.sgt->nents, PCI_DMA_BIDIRECTIONAL);
3735 adapter->hma.flags &= ~HMA_DMA_MAPPED_FLAG;
3736 }
3737
3738 for_each_sg(adapter->hma.sgt->sgl, iter,
3739 adapter->hma.sgt->orig_nents, i) {
3740 page = sg_page(iter);
3741 if (page)
3742 __free_pages(page, HMA_PAGE_ORDER);
3743 }
3744
3745 kfree(adapter->hma.phy_addr);
3746 sg_free_table(adapter->hma.sgt);
3747 kfree(adapter->hma.sgt);
3748 adapter->hma.sgt = NULL;
3749 }
3750
3751 static int adap_config_hma(struct adapter *adapter)
3752 {
3753 struct scatterlist *sgl, *iter;
3754 struct sg_table *sgt;
3755 struct page *newpage;
3756 unsigned int i, j, k;
3757 u32 param, hma_size;
3758 unsigned int ncmds;
3759 size_t page_size;
3760 u32 page_order;
3761 int node, ret;
3762
3763 /* HMA is supported only for T6+ cards.
3764 * Avoid initializing HMA in kdump kernels.
3765 */
3766 if (is_kdump_kernel() ||
3767 CHELSIO_CHIP_VERSION(adapter->params.chip) < CHELSIO_T6)
3768 return 0;
3769
3770 /* Get the HMA region size required by fw */
3771 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3772 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_HMA_SIZE));
3773 ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0,
3774 1, &param, &hma_size);
3775 /* An error means card has its own memory or HMA is not supported by
3776 * the firmware. Return without any errors.
3777 */
3778 if (ret || !hma_size)
3779 return 0;
3780
3781 if (hma_size < HMA_MIN_TOTAL_SIZE ||
3782 hma_size > HMA_MAX_TOTAL_SIZE) {
3783 dev_err(adapter->pdev_dev,
3784 "HMA size %uMB beyond bounds(%u-%lu)MB\n",
3785 hma_size, HMA_MIN_TOTAL_SIZE, HMA_MAX_TOTAL_SIZE);
3786 return -EINVAL;
3787 }
3788
3789 page_size = HMA_PAGE_SIZE;
3790 page_order = HMA_PAGE_ORDER;
3791 adapter->hma.sgt = kzalloc(sizeof(*adapter->hma.sgt), GFP_KERNEL);
3792 if (unlikely(!adapter->hma.sgt)) {
3793 dev_err(adapter->pdev_dev, "HMA SG table allocation failed\n");
3794 return -ENOMEM;
3795 }
3796 sgt = adapter->hma.sgt;
3797 /* FW returned value will be in MB's
3798 */
3799 sgt->orig_nents = (hma_size << 20) / (page_size << page_order);
3800 if (sg_alloc_table(sgt, sgt->orig_nents, GFP_KERNEL)) {
3801 dev_err(adapter->pdev_dev, "HMA SGL allocation failed\n");
3802 kfree(adapter->hma.sgt);
3803 adapter->hma.sgt = NULL;
3804 return -ENOMEM;
3805 }
3806
3807 sgl = adapter->hma.sgt->sgl;
3808 node = dev_to_node(adapter->pdev_dev);
3809 for_each_sg(sgl, iter, sgt->orig_nents, i) {
3810 newpage = alloc_pages_node(node, __GFP_NOWARN | GFP_KERNEL |
3811 __GFP_ZERO, page_order);
3812 if (!newpage) {
3813 dev_err(adapter->pdev_dev,
3814 "Not enough memory for HMA page allocation\n");
3815 ret = -ENOMEM;
3816 goto free_hma;
3817 }
3818 sg_set_page(iter, newpage, page_size << page_order, 0);
3819 }
3820
3821 sgt->nents = dma_map_sg(adapter->pdev_dev, sgl, sgt->orig_nents,
3822 DMA_BIDIRECTIONAL);
3823 if (!sgt->nents) {
3824 dev_err(adapter->pdev_dev,
3825 "Not enough memory for HMA DMA mapping");
3826 ret = -ENOMEM;
3827 goto free_hma;
3828 }
3829 adapter->hma.flags |= HMA_DMA_MAPPED_FLAG;
3830
3831 adapter->hma.phy_addr = kcalloc(sgt->nents, sizeof(dma_addr_t),
3832 GFP_KERNEL);
3833 if (unlikely(!adapter->hma.phy_addr))
3834 goto free_hma;
3835
3836 for_each_sg(sgl, iter, sgt->nents, i) {
3837 newpage = sg_page(iter);
3838 adapter->hma.phy_addr[i] = sg_dma_address(iter);
3839 }
3840
3841 ncmds = DIV_ROUND_UP(sgt->nents, HMA_MAX_ADDR_IN_CMD);
3842 /* Pass on the addresses to firmware */
3843 for (i = 0, k = 0; i < ncmds; i++, k += HMA_MAX_ADDR_IN_CMD) {
3844 struct fw_hma_cmd hma_cmd;
3845 u8 naddr = HMA_MAX_ADDR_IN_CMD;
3846 u8 soc = 0, eoc = 0;
3847 u8 hma_mode = 1; /* Presently we support only Page table mode */
3848
3849 soc = (i == 0) ? 1 : 0;
3850 eoc = (i == ncmds - 1) ? 1 : 0;
3851
3852 /* For last cmd, set naddr corresponding to remaining
3853 * addresses
3854 */
3855 if (i == ncmds - 1) {
3856 naddr = sgt->nents % HMA_MAX_ADDR_IN_CMD;
3857 naddr = naddr ? naddr : HMA_MAX_ADDR_IN_CMD;
3858 }
3859 memset(&hma_cmd, 0, sizeof(hma_cmd));
3860 hma_cmd.op_pkd = htonl(FW_CMD_OP_V(FW_HMA_CMD) |
3861 FW_CMD_REQUEST_F | FW_CMD_WRITE_F);
3862 hma_cmd.retval_len16 = htonl(FW_LEN16(hma_cmd));
3863
3864 hma_cmd.mode_to_pcie_params =
3865 htonl(FW_HMA_CMD_MODE_V(hma_mode) |
3866 FW_HMA_CMD_SOC_V(soc) | FW_HMA_CMD_EOC_V(eoc));
3867
3868 /* HMA cmd size specified in MB's */
3869 hma_cmd.naddr_size =
3870 htonl(FW_HMA_CMD_SIZE_V(hma_size) |
3871 FW_HMA_CMD_NADDR_V(naddr));
3872
3873 /* Total Page size specified in units of 4K */
3874 hma_cmd.addr_size_pkd =
3875 htonl(FW_HMA_CMD_ADDR_SIZE_V
3876 ((page_size << page_order) >> 12));
3877
3878 /* Fill the 5 addresses */
3879 for (j = 0; j < naddr; j++) {
3880 hma_cmd.phy_address[j] =
3881 cpu_to_be64(adapter->hma.phy_addr[j + k]);
3882 }
3883 ret = t4_wr_mbox(adapter, adapter->mbox, &hma_cmd,
3884 sizeof(hma_cmd), &hma_cmd);
3885 if (ret) {
3886 dev_err(adapter->pdev_dev,
3887 "HMA FW command failed with err %d\n", ret);
3888 goto free_hma;
3889 }
3890 }
3891
3892 if (!ret)
3893 dev_info(adapter->pdev_dev,
3894 "Reserved %uMB host memory for HMA\n", hma_size);
3895 return ret;
3896
3897 free_hma:
3898 adap_free_hma_mem(adapter);
3899 return ret;
3900 }
3901
3902 static int adap_init1(struct adapter *adap, struct fw_caps_config_cmd *c)
3903 {
3904 u32 v;
3905 int ret;
3906
3907 /* Now that we've successfully configured and initialized the adapter
3908 * can ask the Firmware what resources it has provisioned for us.
3909 */
3910 ret = t4_get_pfres(adap);
3911 if (ret) {
3912 dev_err(adap->pdev_dev,
3913 "Unable to retrieve resource provisioning information\n");
3914 return ret;
3915 }
3916
3917 /* get device capabilities */
3918 memset(c, 0, sizeof(*c));
3919 c->op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
3920 FW_CMD_REQUEST_F | FW_CMD_READ_F);
3921 c->cfvalid_to_len16 = htonl(FW_LEN16(*c));
3922 ret = t4_wr_mbox(adap, adap->mbox, c, sizeof(*c), c);
3923 if (ret < 0)
3924 return ret;
3925
3926 c->op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
3927 FW_CMD_REQUEST_F | FW_CMD_WRITE_F);
3928 ret = t4_wr_mbox(adap, adap->mbox, c, sizeof(*c), NULL);
3929 if (ret < 0)
3930 return ret;
3931
3932 ret = t4_config_glbl_rss(adap, adap->pf,
3933 FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL,
3934 FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_F |
3935 FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_F);
3936 if (ret < 0)
3937 return ret;
3938
3939 ret = t4_cfg_pfvf(adap, adap->mbox, adap->pf, 0, adap->sge.egr_sz, 64,
3940 MAX_INGQ, 0, 0, 4, 0xf, 0xf, 16, FW_CMD_CAP_PF,
3941 FW_CMD_CAP_PF);
3942 if (ret < 0)
3943 return ret;
3944
3945 t4_sge_init(adap);
3946
3947 /* tweak some settings */
3948 t4_write_reg(adap, TP_SHIFT_CNT_A, 0x64f8849);
3949 t4_write_reg(adap, ULP_RX_TDDP_PSZ_A, HPZ0_V(PAGE_SHIFT - 12));
3950 t4_write_reg(adap, TP_PIO_ADDR_A, TP_INGRESS_CONFIG_A);
3951 v = t4_read_reg(adap, TP_PIO_DATA_A);
3952 t4_write_reg(adap, TP_PIO_DATA_A, v & ~CSUM_HAS_PSEUDO_HDR_F);
3953
3954 /* first 4 Tx modulation queues point to consecutive Tx channels */
3955 adap->params.tp.tx_modq_map = 0xE4;
3956 t4_write_reg(adap, TP_TX_MOD_QUEUE_REQ_MAP_A,
3957 TX_MOD_QUEUE_REQ_MAP_V(adap->params.tp.tx_modq_map));
3958
3959 /* associate each Tx modulation queue with consecutive Tx channels */
3960 v = 0x84218421;
3961 t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
3962 &v, 1, TP_TX_SCHED_HDR_A);
3963 t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
3964 &v, 1, TP_TX_SCHED_FIFO_A);
3965 t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
3966 &v, 1, TP_TX_SCHED_PCMD_A);
3967
3968 #define T4_TX_MODQ_10G_WEIGHT_DEFAULT 16 /* in KB units */
3969 if (is_offload(adap)) {
3970 t4_write_reg(adap, TP_TX_MOD_QUEUE_WEIGHT0_A,
3971 TX_MODQ_WEIGHT0_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3972 TX_MODQ_WEIGHT1_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3973 TX_MODQ_WEIGHT2_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3974 TX_MODQ_WEIGHT3_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT));
3975 t4_write_reg(adap, TP_TX_MOD_CHANNEL_WEIGHT_A,
3976 TX_MODQ_WEIGHT0_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3977 TX_MODQ_WEIGHT1_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3978 TX_MODQ_WEIGHT2_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3979 TX_MODQ_WEIGHT3_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT));
3980 }
3981
3982 /* get basic stuff going */
3983 return t4_early_init(adap, adap->pf);
3984 }
3985
3986 /*
3987 * Max # of ATIDs. The absolute HW max is 16K but we keep it lower.
3988 */
3989 #define MAX_ATIDS 8192U
3990
3991 /*
3992 * Phase 0 of initialization: contact FW, obtain config, perform basic init.
3993 *
3994 * If the firmware we're dealing with has Configuration File support, then
3995 * we use that to perform all configuration
3996 */
3997
3998 /*
3999 * Tweak configuration based on module parameters, etc. Most of these have
4000 * defaults assigned to them by Firmware Configuration Files (if we're using
4001 * them) but need to be explicitly set if we're using hard-coded
4002 * initialization. But even in the case of using Firmware Configuration
4003 * Files, we'd like to expose the ability to change these via module
4004 * parameters so these are essentially common tweaks/settings for
4005 * Configuration Files and hard-coded initialization ...
4006 */
4007 static int adap_init0_tweaks(struct adapter *adapter)
4008 {
4009 /*
4010 * Fix up various Host-Dependent Parameters like Page Size, Cache
4011 * Line Size, etc. The firmware default is for a 4KB Page Size and
4012 * 64B Cache Line Size ...
4013 */
4014 t4_fixup_host_params(adapter, PAGE_SIZE, L1_CACHE_BYTES);
4015
4016 /*
4017 * Process module parameters which affect early initialization.
4018 */
4019 if (rx_dma_offset != 2 && rx_dma_offset != 0) {
4020 dev_err(&adapter->pdev->dev,
4021 "Ignoring illegal rx_dma_offset=%d, using 2\n",
4022 rx_dma_offset);
4023 rx_dma_offset = 2;
4024 }
4025 t4_set_reg_field(adapter, SGE_CONTROL_A,
4026 PKTSHIFT_V(PKTSHIFT_M),
4027 PKTSHIFT_V(rx_dma_offset));
4028
4029 /*
4030 * Don't include the "IP Pseudo Header" in CPL_RX_PKT checksums: Linux
4031 * adds the pseudo header itself.
4032 */
4033 t4_tp_wr_bits_indirect(adapter, TP_INGRESS_CONFIG_A,
4034 CSUM_HAS_PSEUDO_HDR_F, 0);
4035
4036 return 0;
4037 }
4038
4039 /* 10Gb/s-BT PHY Support. chip-external 10Gb/s-BT PHYs are complex chips
4040 * unto themselves and they contain their own firmware to perform their
4041 * tasks ...
4042 */
4043 static int phy_aq1202_version(const u8 *phy_fw_data,
4044 size_t phy_fw_size)
4045 {
4046 int offset;
4047
4048 /* At offset 0x8 you're looking for the primary image's
4049 * starting offset which is 3 Bytes wide
4050 *
4051 * At offset 0xa of the primary image, you look for the offset
4052 * of the DRAM segment which is 3 Bytes wide.
4053 *
4054 * The FW version is at offset 0x27e of the DRAM and is 2 Bytes
4055 * wide
4056 */
4057 #define be16(__p) (((__p)[0] << 8) | (__p)[1])
4058 #define le16(__p) ((__p)[0] | ((__p)[1] << 8))
4059 #define le24(__p) (le16(__p) | ((__p)[2] << 16))
4060
4061 offset = le24(phy_fw_data + 0x8) << 12;
4062 offset = le24(phy_fw_data + offset + 0xa);
4063 return be16(phy_fw_data + offset + 0x27e);
4064
4065 #undef be16
4066 #undef le16
4067 #undef le24
4068 }
4069
4070 static struct info_10gbt_phy_fw {
4071 unsigned int phy_fw_id; /* PCI Device ID */
4072 char *phy_fw_file; /* /lib/firmware/ PHY Firmware file */
4073 int (*phy_fw_version)(const u8 *phy_fw_data, size_t phy_fw_size);
4074 int phy_flash; /* Has FLASH for PHY Firmware */
4075 } phy_info_array[] = {
4076 {
4077 PHY_AQ1202_DEVICEID,
4078 PHY_AQ1202_FIRMWARE,
4079 phy_aq1202_version,
4080 1,
4081 },
4082 {
4083 PHY_BCM84834_DEVICEID,
4084 PHY_BCM84834_FIRMWARE,
4085 NULL,
4086 0,
4087 },
4088 { 0, NULL, NULL },
4089 };
4090
4091 static struct info_10gbt_phy_fw *find_phy_info(int devid)
4092 {
4093 int i;
4094
4095 for (i = 0; i < ARRAY_SIZE(phy_info_array); i++) {
4096 if (phy_info_array[i].phy_fw_id == devid)
4097 return &phy_info_array[i];
4098 }
4099 return NULL;
4100 }
4101
4102 /* Handle updating of chip-external 10Gb/s-BT PHY firmware. This needs to
4103 * happen after the FW_RESET_CMD but before the FW_INITIALIZE_CMD. On error
4104 * we return a negative error number. If we transfer new firmware we return 1
4105 * (from t4_load_phy_fw()). If we don't do anything we return 0.
4106 */
4107 static int adap_init0_phy(struct adapter *adap)
4108 {
4109 const struct firmware *phyf;
4110 int ret;
4111 struct info_10gbt_phy_fw *phy_info;
4112
4113 /* Use the device ID to determine which PHY file to flash.
4114 */
4115 phy_info = find_phy_info(adap->pdev->device);
4116 if (!phy_info) {
4117 dev_warn(adap->pdev_dev,
4118 "No PHY Firmware file found for this PHY\n");
4119 return -EOPNOTSUPP;
4120 }
4121
4122 /* If we have a T4 PHY firmware file under /lib/firmware/cxgb4/, then
4123 * use that. The adapter firmware provides us with a memory buffer
4124 * where we can load a PHY firmware file from the host if we want to
4125 * override the PHY firmware File in flash.
4126 */
4127 ret = request_firmware_direct(&phyf, phy_info->phy_fw_file,
4128 adap->pdev_dev);
4129 if (ret < 0) {
4130 /* For adapters without FLASH attached to PHY for their
4131 * firmware, it's obviously a fatal error if we can't get the
4132 * firmware to the adapter. For adapters with PHY firmware
4133 * FLASH storage, it's worth a warning if we can't find the
4134 * PHY Firmware but we'll neuter the error ...
4135 */
4136 dev_err(adap->pdev_dev, "unable to find PHY Firmware image "
4137 "/lib/firmware/%s, error %d\n",
4138 phy_info->phy_fw_file, -ret);
4139 if (phy_info->phy_flash) {
4140 int cur_phy_fw_ver = 0;
4141
4142 t4_phy_fw_ver(adap, &cur_phy_fw_ver);
4143 dev_warn(adap->pdev_dev, "continuing with, on-adapter "
4144 "FLASH copy, version %#x\n", cur_phy_fw_ver);
4145 ret = 0;
4146 }
4147
4148 return ret;
4149 }
4150
4151 /* Load PHY Firmware onto adapter.
4152 */
4153 ret = t4_load_phy_fw(adap, MEMWIN_NIC, &adap->win0_lock,
4154 phy_info->phy_fw_version,
4155 (u8 *)phyf->data, phyf->size);
4156 if (ret < 0)
4157 dev_err(adap->pdev_dev, "PHY Firmware transfer error %d\n",
4158 -ret);
4159 else if (ret > 0) {
4160 int new_phy_fw_ver = 0;
4161
4162 if (phy_info->phy_fw_version)
4163 new_phy_fw_ver = phy_info->phy_fw_version(phyf->data,
4164 phyf->size);
4165 dev_info(adap->pdev_dev, "Successfully transferred PHY "
4166 "Firmware /lib/firmware/%s, version %#x\n",
4167 phy_info->phy_fw_file, new_phy_fw_ver);
4168 }
4169
4170 release_firmware(phyf);
4171
4172 return ret;
4173 }
4174
4175 /*
4176 * Attempt to initialize the adapter via a Firmware Configuration File.
4177 */
4178 static int adap_init0_config(struct adapter *adapter, int reset)
4179 {
4180 char *fw_config_file, fw_config_file_path[256];
4181 u32 finiver, finicsum, cfcsum, param, val;
4182 struct fw_caps_config_cmd caps_cmd;
4183 unsigned long mtype = 0, maddr = 0;
4184 const struct firmware *cf;
4185 char *config_name = NULL;
4186 int config_issued = 0;
4187 int ret;
4188
4189 /*
4190 * Reset device if necessary.
4191 */
4192 if (reset) {
4193 ret = t4_fw_reset(adapter, adapter->mbox,
4194 PIORSTMODE_F | PIORST_F);
4195 if (ret < 0)
4196 goto bye;
4197 }
4198
4199 /* If this is a 10Gb/s-BT adapter make sure the chip-external
4200 * 10Gb/s-BT PHYs have up-to-date firmware. Note that this step needs
4201 * to be performed after any global adapter RESET above since some
4202 * PHYs only have local RAM copies of the PHY firmware.
4203 */
4204 if (is_10gbt_device(adapter->pdev->device)) {
4205 ret = adap_init0_phy(adapter);
4206 if (ret < 0)
4207 goto bye;
4208 }
4209 /*
4210 * If we have a T4 configuration file under /lib/firmware/cxgb4/,
4211 * then use that. Otherwise, use the configuration file stored
4212 * in the adapter flash ...
4213 */
4214 switch (CHELSIO_CHIP_VERSION(adapter->params.chip)) {
4215 case CHELSIO_T4:
4216 fw_config_file = FW4_CFNAME;
4217 break;
4218 case CHELSIO_T5:
4219 fw_config_file = FW5_CFNAME;
4220 break;
4221 case CHELSIO_T6:
4222 fw_config_file = FW6_CFNAME;
4223 break;
4224 default:
4225 dev_err(adapter->pdev_dev, "Device %d is not supported\n",
4226 adapter->pdev->device);
4227 ret = -EINVAL;
4228 goto bye;
4229 }
4230
4231 ret = request_firmware(&cf, fw_config_file, adapter->pdev_dev);
4232 if (ret < 0) {
4233 config_name = "On FLASH";
4234 mtype = FW_MEMTYPE_CF_FLASH;
4235 maddr = t4_flash_cfg_addr(adapter);
4236 } else {
4237 u32 params[7], val[7];
4238
4239 sprintf(fw_config_file_path,
4240 "/lib/firmware/%s", fw_config_file);
4241 config_name = fw_config_file_path;
4242
4243 if (cf->size >= FLASH_CFG_MAX_SIZE)
4244 ret = -ENOMEM;
4245 else {
4246 params[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
4247 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CF));
4248 ret = t4_query_params(adapter, adapter->mbox,
4249 adapter->pf, 0, 1, params, val);
4250 if (ret == 0) {
4251 /*
4252 * For t4_memory_rw() below addresses and
4253 * sizes have to be in terms of multiples of 4
4254 * bytes. So, if the Configuration File isn't
4255 * a multiple of 4 bytes in length we'll have
4256 * to write that out separately since we can't
4257 * guarantee that the bytes following the
4258 * residual byte in the buffer returned by
4259 * request_firmware() are zeroed out ...
4260 */
4261 size_t resid = cf->size & 0x3;
4262 size_t size = cf->size & ~0x3;
4263 __be32 *data = (__be32 *)cf->data;
4264
4265 mtype = FW_PARAMS_PARAM_Y_G(val[0]);
4266 maddr = FW_PARAMS_PARAM_Z_G(val[0]) << 16;
4267
4268 spin_lock(&adapter->win0_lock);
4269 ret = t4_memory_rw(adapter, 0, mtype, maddr,
4270 size, data, T4_MEMORY_WRITE);
4271 if (ret == 0 && resid != 0) {
4272 union {
4273 __be32 word;
4274 char buf[4];
4275 } last;
4276 int i;
4277
4278 last.word = data[size >> 2];
4279 for (i = resid; i < 4; i++)
4280 last.buf[i] = 0;
4281 ret = t4_memory_rw(adapter, 0, mtype,
4282 maddr + size,
4283 4, &last.word,
4284 T4_MEMORY_WRITE);
4285 }
4286 spin_unlock(&adapter->win0_lock);
4287 }
4288 }
4289
4290 release_firmware(cf);
4291 if (ret)
4292 goto bye;
4293 }
4294
4295 val = 0;
4296
4297 /* Ofld + Hash filter is supported. Older fw will fail this request and
4298 * it is fine.
4299 */
4300 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
4301 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_HASHFILTER_WITH_OFLD));
4302 ret = t4_set_params(adapter, adapter->mbox, adapter->pf, 0,
4303 1, &param, &val);
4304
4305 /* FW doesn't know about Hash filter + ofld support,
4306 * it's not a problem, don't return an error.
4307 */
4308 if (ret < 0) {
4309 dev_warn(adapter->pdev_dev,
4310 "Hash filter with ofld is not supported by FW\n");
4311 }
4312
4313 /*
4314 * Issue a Capability Configuration command to the firmware to get it
4315 * to parse the Configuration File. We don't use t4_fw_config_file()
4316 * because we want the ability to modify various features after we've
4317 * processed the configuration file ...
4318 */
4319 memset(&caps_cmd, 0, sizeof(caps_cmd));
4320 caps_cmd.op_to_write =
4321 htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
4322 FW_CMD_REQUEST_F |
4323 FW_CMD_READ_F);
4324 caps_cmd.cfvalid_to_len16 =
4325 htonl(FW_CAPS_CONFIG_CMD_CFVALID_F |
4326 FW_CAPS_CONFIG_CMD_MEMTYPE_CF_V(mtype) |
4327 FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_V(maddr >> 16) |
4328 FW_LEN16(caps_cmd));
4329 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
4330 &caps_cmd);
4331
4332 /* If the CAPS_CONFIG failed with an ENOENT (for a Firmware
4333 * Configuration File in FLASH), our last gasp effort is to use the
4334 * Firmware Configuration File which is embedded in the firmware. A
4335 * very few early versions of the firmware didn't have one embedded
4336 * but we can ignore those.
4337 */
4338 if (ret == -ENOENT) {
4339 memset(&caps_cmd, 0, sizeof(caps_cmd));
4340 caps_cmd.op_to_write =
4341 htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
4342 FW_CMD_REQUEST_F |
4343 FW_CMD_READ_F);
4344 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
4345 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd,
4346 sizeof(caps_cmd), &caps_cmd);
4347 config_name = "Firmware Default";
4348 }
4349
4350 config_issued = 1;
4351 if (ret < 0)
4352 goto bye;
4353
4354 finiver = ntohl(caps_cmd.finiver);
4355 finicsum = ntohl(caps_cmd.finicsum);
4356 cfcsum = ntohl(caps_cmd.cfcsum);
4357 if (finicsum != cfcsum)
4358 dev_warn(adapter->pdev_dev, "Configuration File checksum "\
4359 "mismatch: [fini] csum=%#x, computed csum=%#x\n",
4360 finicsum, cfcsum);
4361
4362 /*
4363 * And now tell the firmware to use the configuration we just loaded.
4364 */
4365 caps_cmd.op_to_write =
4366 htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
4367 FW_CMD_REQUEST_F |
4368 FW_CMD_WRITE_F);
4369 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
4370 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
4371 NULL);
4372 if (ret < 0)
4373 goto bye;
4374
4375 /*
4376 * Tweak configuration based on system architecture, module
4377 * parameters, etc.
4378 */
4379 ret = adap_init0_tweaks(adapter);
4380 if (ret < 0)
4381 goto bye;
4382
4383 /* We will proceed even if HMA init fails. */
4384 ret = adap_config_hma(adapter);
4385 if (ret)
4386 dev_err(adapter->pdev_dev,
4387 "HMA configuration failed with error %d\n", ret);
4388
4389 if (is_t6(adapter->params.chip)) {
4390 adap_config_hpfilter(adapter);
4391 ret = setup_ppod_edram(adapter);
4392 if (!ret)
4393 dev_info(adapter->pdev_dev, "Successfully enabled "
4394 "ppod edram feature\n");
4395 }
4396
4397 /*
4398 * And finally tell the firmware to initialize itself using the
4399 * parameters from the Configuration File.
4400 */
4401 ret = t4_fw_initialize(adapter, adapter->mbox);
4402 if (ret < 0)
4403 goto bye;
4404
4405 /* Emit Firmware Configuration File information and return
4406 * successfully.
4407 */
4408 dev_info(adapter->pdev_dev, "Successfully configured using Firmware "\
4409 "Configuration File \"%s\", version %#x, computed checksum %#x\n",
4410 config_name, finiver, cfcsum);
4411 return 0;
4412
4413 /*
4414 * Something bad happened. Return the error ... (If the "error"
4415 * is that there's no Configuration File on the adapter we don't
4416 * want to issue a warning since this is fairly common.)
4417 */
4418 bye:
4419 if (config_issued && ret != -ENOENT)
4420 dev_warn(adapter->pdev_dev, "\"%s\" configuration file error %d\n",
4421 config_name, -ret);
4422 return ret;
4423 }
4424
4425 static struct fw_info fw_info_array[] = {
4426 {
4427 .chip = CHELSIO_T4,
4428 .fs_name = FW4_CFNAME,
4429 .fw_mod_name = FW4_FNAME,
4430 .fw_hdr = {
4431 .chip = FW_HDR_CHIP_T4,
4432 .fw_ver = __cpu_to_be32(FW_VERSION(T4)),
4433 .intfver_nic = FW_INTFVER(T4, NIC),
4434 .intfver_vnic = FW_INTFVER(T4, VNIC),
4435 .intfver_ri = FW_INTFVER(T4, RI),
4436 .intfver_iscsi = FW_INTFVER(T4, ISCSI),
4437 .intfver_fcoe = FW_INTFVER(T4, FCOE),
4438 },
4439 }, {
4440 .chip = CHELSIO_T5,
4441 .fs_name = FW5_CFNAME,
4442 .fw_mod_name = FW5_FNAME,
4443 .fw_hdr = {
4444 .chip = FW_HDR_CHIP_T5,
4445 .fw_ver = __cpu_to_be32(FW_VERSION(T5)),
4446 .intfver_nic = FW_INTFVER(T5, NIC),
4447 .intfver_vnic = FW_INTFVER(T5, VNIC),
4448 .intfver_ri = FW_INTFVER(T5, RI),
4449 .intfver_iscsi = FW_INTFVER(T5, ISCSI),
4450 .intfver_fcoe = FW_INTFVER(T5, FCOE),
4451 },
4452 }, {
4453 .chip = CHELSIO_T6,
4454 .fs_name = FW6_CFNAME,
4455 .fw_mod_name = FW6_FNAME,
4456 .fw_hdr = {
4457 .chip = FW_HDR_CHIP_T6,
4458 .fw_ver = __cpu_to_be32(FW_VERSION(T6)),
4459 .intfver_nic = FW_INTFVER(T6, NIC),
4460 .intfver_vnic = FW_INTFVER(T6, VNIC),
4461 .intfver_ofld = FW_INTFVER(T6, OFLD),
4462 .intfver_ri = FW_INTFVER(T6, RI),
4463 .intfver_iscsipdu = FW_INTFVER(T6, ISCSIPDU),
4464 .intfver_iscsi = FW_INTFVER(T6, ISCSI),
4465 .intfver_fcoepdu = FW_INTFVER(T6, FCOEPDU),
4466 .intfver_fcoe = FW_INTFVER(T6, FCOE),
4467 },
4468 }
4469
4470 };
4471
4472 static struct fw_info *find_fw_info(int chip)
4473 {
4474 int i;
4475
4476 for (i = 0; i < ARRAY_SIZE(fw_info_array); i++) {
4477 if (fw_info_array[i].chip == chip)
4478 return &fw_info_array[i];
4479 }
4480 return NULL;
4481 }
4482
4483 /*
4484 * Phase 0 of initialization: contact FW, obtain config, perform basic init.
4485 */
4486 static int adap_init0(struct adapter *adap, int vpd_skip)
4487 {
4488 struct fw_caps_config_cmd caps_cmd;
4489 u32 params[7], val[7];
4490 enum dev_state state;
4491 u32 v, port_vec;
4492 int reset = 1;
4493 int ret;
4494
4495 /* Grab Firmware Device Log parameters as early as possible so we have
4496 * access to it for debugging, etc.
4497 */
4498 ret = t4_init_devlog_params(adap);
4499 if (ret < 0)
4500 return ret;
4501
4502 /* Contact FW, advertising Master capability */
4503 ret = t4_fw_hello(adap, adap->mbox, adap->mbox,
4504 is_kdump_kernel() ? MASTER_MUST : MASTER_MAY, &state);
4505 if (ret < 0) {
4506 dev_err(adap->pdev_dev, "could not connect to FW, error %d\n",
4507 ret);
4508 return ret;
4509 }
4510 if (ret == adap->mbox)
4511 adap->flags |= CXGB4_MASTER_PF;
4512
4513 /*
4514 * If we're the Master PF Driver and the device is uninitialized,
4515 * then let's consider upgrading the firmware ... (We always want
4516 * to check the firmware version number in order to A. get it for
4517 * later reporting and B. to warn if the currently loaded firmware
4518 * is excessively mismatched relative to the driver.)
4519 */
4520
4521 t4_get_version_info(adap);
4522 ret = t4_check_fw_version(adap);
4523 /* If firmware is too old (not supported by driver) force an update. */
4524 if (ret)
4525 state = DEV_STATE_UNINIT;
4526 if ((adap->flags & CXGB4_MASTER_PF) && state != DEV_STATE_INIT) {
4527 struct fw_info *fw_info;
4528 struct fw_hdr *card_fw;
4529 const struct firmware *fw;
4530 const u8 *fw_data = NULL;
4531 unsigned int fw_size = 0;
4532
4533 /* This is the firmware whose headers the driver was compiled
4534 * against
4535 */
4536 fw_info = find_fw_info(CHELSIO_CHIP_VERSION(adap->params.chip));
4537 if (fw_info == NULL) {
4538 dev_err(adap->pdev_dev,
4539 "unable to get firmware info for chip %d.\n",
4540 CHELSIO_CHIP_VERSION(adap->params.chip));
4541 return -EINVAL;
4542 }
4543
4544 /* allocate memory to read the header of the firmware on the
4545 * card
4546 */
4547 card_fw = kvzalloc(sizeof(*card_fw), GFP_KERNEL);
4548 if (!card_fw) {
4549 ret = -ENOMEM;
4550 goto bye;
4551 }
4552
4553 /* Get FW from from /lib/firmware/ */
4554 ret = request_firmware(&fw, fw_info->fw_mod_name,
4555 adap->pdev_dev);
4556 if (ret < 0) {
4557 dev_err(adap->pdev_dev,
4558 "unable to load firmware image %s, error %d\n",
4559 fw_info->fw_mod_name, ret);
4560 } else {
4561 fw_data = fw->data;
4562 fw_size = fw->size;
4563 }
4564
4565 /* upgrade FW logic */
4566 ret = t4_prep_fw(adap, fw_info, fw_data, fw_size, card_fw,
4567 state, &reset);
4568
4569 /* Cleaning up */
4570 release_firmware(fw);
4571 kvfree(card_fw);
4572
4573 if (ret < 0)
4574 goto bye;
4575 }
4576
4577 /* If the firmware is initialized already, emit a simply note to that
4578 * effect. Otherwise, it's time to try initializing the adapter.
4579 */
4580 if (state == DEV_STATE_INIT) {
4581 ret = adap_config_hma(adap);
4582 if (ret)
4583 dev_err(adap->pdev_dev,
4584 "HMA configuration failed with error %d\n",
4585 ret);
4586 dev_info(adap->pdev_dev, "Coming up as %s: "\
4587 "Adapter already initialized\n",
4588 adap->flags & CXGB4_MASTER_PF ? "MASTER" : "SLAVE");
4589 } else {
4590 dev_info(adap->pdev_dev, "Coming up as MASTER: "\
4591 "Initializing adapter\n");
4592
4593 /* Find out whether we're dealing with a version of the
4594 * firmware which has configuration file support.
4595 */
4596 params[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
4597 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CF));
4598 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1,
4599 params, val);
4600
4601 /* If the firmware doesn't support Configuration Files,
4602 * return an error.
4603 */
4604 if (ret < 0) {
4605 dev_err(adap->pdev_dev, "firmware doesn't support "
4606 "Firmware Configuration Files\n");
4607 goto bye;
4608 }
4609
4610 /* The firmware provides us with a memory buffer where we can
4611 * load a Configuration File from the host if we want to
4612 * override the Configuration File in flash.
4613 */
4614 ret = adap_init0_config(adap, reset);
4615 if (ret == -ENOENT) {
4616 dev_err(adap->pdev_dev, "no Configuration File "
4617 "present on adapter.\n");
4618 goto bye;
4619 }
4620 if (ret < 0) {
4621 dev_err(adap->pdev_dev, "could not initialize "
4622 "adapter, error %d\n", -ret);
4623 goto bye;
4624 }
4625 }
4626
4627 /* Now that we've successfully configured and initialized the adapter
4628 * (or found it already initialized), we can ask the Firmware what
4629 * resources it has provisioned for us.
4630 */
4631 ret = t4_get_pfres(adap);
4632 if (ret) {
4633 dev_err(adap->pdev_dev,
4634 "Unable to retrieve resource provisioning information\n");
4635 goto bye;
4636 }
4637
4638 /* Grab VPD parameters. This should be done after we establish a
4639 * connection to the firmware since some of the VPD parameters
4640 * (notably the Core Clock frequency) are retrieved via requests to
4641 * the firmware. On the other hand, we need these fairly early on
4642 * so we do this right after getting ahold of the firmware.
4643 *
4644 * We need to do this after initializing the adapter because someone
4645 * could have FLASHed a new VPD which won't be read by the firmware
4646 * until we do the RESET ...
4647 */
4648 if (!vpd_skip) {
4649 ret = t4_get_vpd_params(adap, &adap->params.vpd);
4650 if (ret < 0)
4651 goto bye;
4652 }
4653
4654 /* Find out what ports are available to us. Note that we need to do
4655 * this before calling adap_init0_no_config() since it needs nports
4656 * and portvec ...
4657 */
4658 v =
4659 FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
4660 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PORTVEC);
4661 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, &v, &port_vec);
4662 if (ret < 0)
4663 goto bye;
4664
4665 adap->params.nports = hweight32(port_vec);
4666 adap->params.portvec = port_vec;
4667
4668 /* Give the SGE code a chance to pull in anything that it needs ...
4669 * Note that this must be called after we retrieve our VPD parameters
4670 * in order to know how to convert core ticks to seconds, etc.
4671 */
4672 ret = t4_sge_init(adap);
4673 if (ret < 0)
4674 goto bye;
4675
4676 /* Grab the SGE Doorbell Queue Timer values. If successful, that
4677 * indicates that the Firmware and Hardware support this.
4678 */
4679 params[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
4680 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_DBQ_TIMERTICK));
4681 ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
4682 1, params, val);
4683
4684 if (!ret) {
4685 adap->sge.dbqtimer_tick = val[0];
4686 ret = t4_read_sge_dbqtimers(adap,
4687 ARRAY_SIZE(adap->sge.dbqtimer_val),
4688 adap->sge.dbqtimer_val);
4689 }
4690
4691 if (!ret)
4692 adap->flags |= CXGB4_SGE_DBQ_TIMER;
4693
4694 if (is_bypass_device(adap->pdev->device))
4695 adap->params.bypass = 1;
4696
4697 /*
4698 * Grab some of our basic fundamental operating parameters.
4699 */
4700 params[0] = FW_PARAM_PFVF(EQ_START);
4701 params[1] = FW_PARAM_PFVF(L2T_START);
4702 params[2] = FW_PARAM_PFVF(L2T_END);
4703 params[3] = FW_PARAM_PFVF(FILTER_START);
4704 params[4] = FW_PARAM_PFVF(FILTER_END);
4705 params[5] = FW_PARAM_PFVF(IQFLINT_START);
4706 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6, params, val);
4707 if (ret < 0)
4708 goto bye;
4709 adap->sge.egr_start = val[0];
4710 adap->l2t_start = val[1];
4711 adap->l2t_end = val[2];
4712 adap->tids.ftid_base = val[3];
4713 adap->tids.nftids = val[4] - val[3] + 1;
4714 adap->sge.ingr_start = val[5];
4715
4716 if (CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) {
4717 params[0] = FW_PARAM_PFVF(HPFILTER_START);
4718 params[1] = FW_PARAM_PFVF(HPFILTER_END);
4719 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2,
4720 params, val);
4721 if (ret < 0)
4722 goto bye;
4723
4724 adap->tids.hpftid_base = val[0];
4725 adap->tids.nhpftids = val[1] - val[0] + 1;
4726
4727 /* Read the raw mps entries. In T6, the last 2 tcam entries
4728 * are reserved for raw mac addresses (rawf = 2, one per port).
4729 */
4730 params[0] = FW_PARAM_PFVF(RAWF_START);
4731 params[1] = FW_PARAM_PFVF(RAWF_END);
4732 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2,
4733 params, val);
4734 if (ret == 0) {
4735 adap->rawf_start = val[0];
4736 adap->rawf_cnt = val[1] - val[0] + 1;
4737 }
4738
4739 adap->tids.tid_base =
4740 t4_read_reg(adap, LE_DB_ACTIVE_TABLE_START_INDEX_A);
4741 }
4742
4743 /* qids (ingress/egress) returned from firmware can be anywhere
4744 * in the range from EQ(IQFLINT)_START to EQ(IQFLINT)_END.
4745 * Hence driver needs to allocate memory for this range to
4746 * store the queue info. Get the highest IQFLINT/EQ index returned
4747 * in FW_EQ_*_CMD.alloc command.
4748 */
4749 params[0] = FW_PARAM_PFVF(EQ_END);
4750 params[1] = FW_PARAM_PFVF(IQFLINT_END);
4751 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val);
4752 if (ret < 0)
4753 goto bye;
4754 adap->sge.egr_sz = val[0] - adap->sge.egr_start + 1;
4755 adap->sge.ingr_sz = val[1] - adap->sge.ingr_start + 1;
4756
4757 adap->sge.egr_map = kcalloc(adap->sge.egr_sz,
4758 sizeof(*adap->sge.egr_map), GFP_KERNEL);
4759 if (!adap->sge.egr_map) {
4760 ret = -ENOMEM;
4761 goto bye;
4762 }
4763
4764 adap->sge.ingr_map = kcalloc(adap->sge.ingr_sz,
4765 sizeof(*adap->sge.ingr_map), GFP_KERNEL);
4766 if (!adap->sge.ingr_map) {
4767 ret = -ENOMEM;
4768 goto bye;
4769 }
4770
4771 /* Allocate the memory for the vaious egress queue bitmaps
4772 * ie starving_fl, txq_maperr and blocked_fl.
4773 */
4774 adap->sge.starving_fl = kcalloc(BITS_TO_LONGS(adap->sge.egr_sz),
4775 sizeof(long), GFP_KERNEL);
4776 if (!adap->sge.starving_fl) {
4777 ret = -ENOMEM;
4778 goto bye;
4779 }
4780
4781 adap->sge.txq_maperr = kcalloc(BITS_TO_LONGS(adap->sge.egr_sz),
4782 sizeof(long), GFP_KERNEL);
4783 if (!adap->sge.txq_maperr) {
4784 ret = -ENOMEM;
4785 goto bye;
4786 }
4787
4788 #ifdef CONFIG_DEBUG_FS
4789 adap->sge.blocked_fl = kcalloc(BITS_TO_LONGS(adap->sge.egr_sz),
4790 sizeof(long), GFP_KERNEL);
4791 if (!adap->sge.blocked_fl) {
4792 ret = -ENOMEM;
4793 goto bye;
4794 }
4795 #endif
4796
4797 params[0] = FW_PARAM_PFVF(CLIP_START);
4798 params[1] = FW_PARAM_PFVF(CLIP_END);
4799 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val);
4800 if (ret < 0)
4801 goto bye;
4802 adap->clipt_start = val[0];
4803 adap->clipt_end = val[1];
4804
4805 /* Get the supported number of traffic classes */
4806 params[0] = FW_PARAM_DEV(NUM_TM_CLASS);
4807 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, params, val);
4808 if (ret < 0) {
4809 /* We couldn't retrieve the number of Traffic Classes
4810 * supported by the hardware/firmware. So we hard
4811 * code it here.
4812 */
4813 adap->params.nsched_cls = is_t4(adap->params.chip) ? 15 : 16;
4814 } else {
4815 adap->params.nsched_cls = val[0];
4816 }
4817
4818 /* query params related to active filter region */
4819 params[0] = FW_PARAM_PFVF(ACTIVE_FILTER_START);
4820 params[1] = FW_PARAM_PFVF(ACTIVE_FILTER_END);
4821 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val);
4822 /* If Active filter size is set we enable establishing
4823 * offload connection through firmware work request
4824 */
4825 if ((val[0] != val[1]) && (ret >= 0)) {
4826 adap->flags |= CXGB4_FW_OFLD_CONN;
4827 adap->tids.aftid_base = val[0];
4828 adap->tids.aftid_end = val[1];
4829 }
4830
4831 /* If we're running on newer firmware, let it know that we're
4832 * prepared to deal with encapsulated CPL messages. Older
4833 * firmware won't understand this and we'll just get
4834 * unencapsulated messages ...
4835 */
4836 params[0] = FW_PARAM_PFVF(CPLFW4MSG_ENCAP);
4837 val[0] = 1;
4838 (void)t4_set_params(adap, adap->mbox, adap->pf, 0, 1, params, val);
4839
4840 /*
4841 * Find out whether we're allowed to use the T5+ ULPTX MEMWRITE DSGL
4842 * capability. Earlier versions of the firmware didn't have the
4843 * ULPTX_MEMWRITE_DSGL so we'll interpret a query failure as no
4844 * permission to use ULPTX MEMWRITE DSGL.
4845 */
4846 if (is_t4(adap->params.chip)) {
4847 adap->params.ulptx_memwrite_dsgl = false;
4848 } else {
4849 params[0] = FW_PARAM_DEV(ULPTX_MEMWRITE_DSGL);
4850 ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
4851 1, params, val);
4852 adap->params.ulptx_memwrite_dsgl = (ret == 0 && val[0] != 0);
4853 }
4854
4855 /* See if FW supports FW_RI_FR_NSMR_TPTE_WR work request */
4856 params[0] = FW_PARAM_DEV(RI_FR_NSMR_TPTE_WR);
4857 ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
4858 1, params, val);
4859 adap->params.fr_nsmr_tpte_wr_support = (ret == 0 && val[0] != 0);
4860
4861 /* See if FW supports FW_FILTER2 work request */
4862 if (is_t4(adap->params.chip)) {
4863 adap->params.filter2_wr_support = 0;
4864 } else {
4865 params[0] = FW_PARAM_DEV(FILTER2_WR);
4866 ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
4867 1, params, val);
4868 adap->params.filter2_wr_support = (ret == 0 && val[0] != 0);
4869 }
4870
4871 /* Check if FW supports returning vin and smt index.
4872 * If this is not supported, driver will interpret
4873 * these values from viid.
4874 */
4875 params[0] = FW_PARAM_DEV(OPAQUE_VIID_SMT_EXTN);
4876 ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
4877 1, params, val);
4878 adap->params.viid_smt_extn_support = (ret == 0 && val[0] != 0);
4879
4880 /*
4881 * Get device capabilities so we can determine what resources we need
4882 * to manage.
4883 */
4884 memset(&caps_cmd, 0, sizeof(caps_cmd));
4885 caps_cmd.op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
4886 FW_CMD_REQUEST_F | FW_CMD_READ_F);
4887 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
4888 ret = t4_wr_mbox(adap, adap->mbox, &caps_cmd, sizeof(caps_cmd),
4889 &caps_cmd);
4890 if (ret < 0)
4891 goto bye;
4892
4893 /* hash filter has some mandatory register settings to be tested and for
4894 * that it needs to test whether offload is enabled or not, hence
4895 * checking and setting it here.
4896 */
4897 if (caps_cmd.ofldcaps)
4898 adap->params.offload = 1;
4899
4900 if (caps_cmd.ofldcaps ||
4901 (caps_cmd.niccaps & htons(FW_CAPS_CONFIG_NIC_HASHFILTER)) ||
4902 (caps_cmd.niccaps & htons(FW_CAPS_CONFIG_NIC_ETHOFLD))) {
4903 /* query offload-related parameters */
4904 params[0] = FW_PARAM_DEV(NTID);
4905 params[1] = FW_PARAM_PFVF(SERVER_START);
4906 params[2] = FW_PARAM_PFVF(SERVER_END);
4907 params[3] = FW_PARAM_PFVF(TDDP_START);
4908 params[4] = FW_PARAM_PFVF(TDDP_END);
4909 params[5] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ);
4910 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6,
4911 params, val);
4912 if (ret < 0)
4913 goto bye;
4914 adap->tids.ntids = val[0];
4915 adap->tids.natids = min(adap->tids.ntids / 2, MAX_ATIDS);
4916 adap->tids.stid_base = val[1];
4917 adap->tids.nstids = val[2] - val[1] + 1;
4918 /*
4919 * Setup server filter region. Divide the available filter
4920 * region into two parts. Regular filters get 1/3rd and server
4921 * filters get 2/3rd part. This is only enabled if workarond
4922 * path is enabled.
4923 * 1. For regular filters.
4924 * 2. Server filter: This are special filters which are used
4925 * to redirect SYN packets to offload queue.
4926 */
4927 if (adap->flags & CXGB4_FW_OFLD_CONN && !is_bypass(adap)) {
4928 adap->tids.sftid_base = adap->tids.ftid_base +
4929 DIV_ROUND_UP(adap->tids.nftids, 3);
4930 adap->tids.nsftids = adap->tids.nftids -
4931 DIV_ROUND_UP(adap->tids.nftids, 3);
4932 adap->tids.nftids = adap->tids.sftid_base -
4933 adap->tids.ftid_base;
4934 }
4935 adap->vres.ddp.start = val[3];
4936 adap->vres.ddp.size = val[4] - val[3] + 1;
4937 adap->params.ofldq_wr_cred = val[5];
4938
4939 if (caps_cmd.niccaps & htons(FW_CAPS_CONFIG_NIC_HASHFILTER)) {
4940 init_hash_filter(adap);
4941 } else {
4942 adap->num_ofld_uld += 1;
4943 }
4944
4945 if (caps_cmd.niccaps & htons(FW_CAPS_CONFIG_NIC_ETHOFLD)) {
4946 params[0] = FW_PARAM_PFVF(ETHOFLD_START);
4947 params[1] = FW_PARAM_PFVF(ETHOFLD_END);
4948 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2,
4949 params, val);
4950 if (!ret) {
4951 adap->tids.eotid_base = val[0];
4952 adap->tids.neotids = min_t(u32, MAX_ATIDS,
4953 val[1] - val[0] + 1);
4954 adap->params.ethofld = 1;
4955 }
4956 }
4957 }
4958 if (caps_cmd.rdmacaps) {
4959 params[0] = FW_PARAM_PFVF(STAG_START);
4960 params[1] = FW_PARAM_PFVF(STAG_END);
4961 params[2] = FW_PARAM_PFVF(RQ_START);
4962 params[3] = FW_PARAM_PFVF(RQ_END);
4963 params[4] = FW_PARAM_PFVF(PBL_START);
4964 params[5] = FW_PARAM_PFVF(PBL_END);
4965 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6,
4966 params, val);
4967 if (ret < 0)
4968 goto bye;
4969 adap->vres.stag.start = val[0];
4970 adap->vres.stag.size = val[1] - val[0] + 1;
4971 adap->vres.rq.start = val[2];
4972 adap->vres.rq.size = val[3] - val[2] + 1;
4973 adap->vres.pbl.start = val[4];
4974 adap->vres.pbl.size = val[5] - val[4] + 1;
4975
4976 params[0] = FW_PARAM_PFVF(SRQ_START);
4977 params[1] = FW_PARAM_PFVF(SRQ_END);
4978 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2,
4979 params, val);
4980 if (!ret) {
4981 adap->vres.srq.start = val[0];
4982 adap->vres.srq.size = val[1] - val[0] + 1;
4983 }
4984 if (adap->vres.srq.size) {
4985 adap->srq = t4_init_srq(adap->vres.srq.size);
4986 if (!adap->srq)
4987 dev_warn(&adap->pdev->dev, "could not allocate SRQ, continuing\n");
4988 }
4989
4990 params[0] = FW_PARAM_PFVF(SQRQ_START);
4991 params[1] = FW_PARAM_PFVF(SQRQ_END);
4992 params[2] = FW_PARAM_PFVF(CQ_START);
4993 params[3] = FW_PARAM_PFVF(CQ_END);
4994 params[4] = FW_PARAM_PFVF(OCQ_START);
4995 params[5] = FW_PARAM_PFVF(OCQ_END);
4996 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6, params,
4997 val);
4998 if (ret < 0)
4999 goto bye;
5000 adap->vres.qp.start = val[0];
5001 adap->vres.qp.size = val[1] - val[0] + 1;
5002 adap->vres.cq.start = val[2];
5003 adap->vres.cq.size = val[3] - val[2] + 1;
5004 adap->vres.ocq.start = val[4];
5005 adap->vres.ocq.size = val[5] - val[4] + 1;
5006
5007 params[0] = FW_PARAM_DEV(MAXORDIRD_QP);
5008 params[1] = FW_PARAM_DEV(MAXIRD_ADAPTER);
5009 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params,
5010 val);
5011 if (ret < 0) {
5012 adap->params.max_ordird_qp = 8;
5013 adap->params.max_ird_adapter = 32 * adap->tids.ntids;
5014 ret = 0;
5015 } else {
5016 adap->params.max_ordird_qp = val[0];
5017 adap->params.max_ird_adapter = val[1];
5018 }
5019 dev_info(adap->pdev_dev,
5020 "max_ordird_qp %d max_ird_adapter %d\n",
5021 adap->params.max_ordird_qp,
5022 adap->params.max_ird_adapter);
5023
5024 /* Enable write_with_immediate if FW supports it */
5025 params[0] = FW_PARAM_DEV(RDMA_WRITE_WITH_IMM);
5026 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, params,
5027 val);
5028 adap->params.write_w_imm_support = (ret == 0 && val[0] != 0);
5029
5030 /* Enable write_cmpl if FW supports it */
5031 params[0] = FW_PARAM_DEV(RI_WRITE_CMPL_WR);
5032 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, params,
5033 val);
5034 adap->params.write_cmpl_support = (ret == 0 && val[0] != 0);
5035 adap->num_ofld_uld += 2;
5036 }
5037 if (caps_cmd.iscsicaps) {
5038 params[0] = FW_PARAM_PFVF(ISCSI_START);
5039 params[1] = FW_PARAM_PFVF(ISCSI_END);
5040 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2,
5041 params, val);
5042 if (ret < 0)
5043 goto bye;
5044 adap->vres.iscsi.start = val[0];
5045 adap->vres.iscsi.size = val[1] - val[0] + 1;
5046 if (is_t6(adap->params.chip)) {
5047 params[0] = FW_PARAM_PFVF(PPOD_EDRAM_START);
5048 params[1] = FW_PARAM_PFVF(PPOD_EDRAM_END);
5049 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2,
5050 params, val);
5051 if (!ret) {
5052 adap->vres.ppod_edram.start = val[0];
5053 adap->vres.ppod_edram.size =
5054 val[1] - val[0] + 1;
5055
5056 dev_info(adap->pdev_dev,
5057 "ppod edram start 0x%x end 0x%x size 0x%x\n",
5058 val[0], val[1],
5059 adap->vres.ppod_edram.size);
5060 }
5061 }
5062 /* LIO target and cxgb4i initiaitor */
5063 adap->num_ofld_uld += 2;
5064 }
5065 if (caps_cmd.cryptocaps) {
5066 if (ntohs(caps_cmd.cryptocaps) &
5067 FW_CAPS_CONFIG_CRYPTO_LOOKASIDE) {
5068 params[0] = FW_PARAM_PFVF(NCRYPTO_LOOKASIDE);
5069 ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
5070 2, params, val);
5071 if (ret < 0) {
5072 if (ret != -EINVAL)
5073 goto bye;
5074 } else {
5075 adap->vres.ncrypto_fc = val[0];
5076 }
5077 adap->num_ofld_uld += 1;
5078 }
5079 if (ntohs(caps_cmd.cryptocaps) &
5080 FW_CAPS_CONFIG_TLS_INLINE) {
5081 params[0] = FW_PARAM_PFVF(TLS_START);
5082 params[1] = FW_PARAM_PFVF(TLS_END);
5083 ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
5084 2, params, val);
5085 if (ret < 0)
5086 goto bye;
5087 adap->vres.key.start = val[0];
5088 adap->vres.key.size = val[1] - val[0] + 1;
5089 adap->num_uld += 1;
5090 }
5091 adap->params.crypto = ntohs(caps_cmd.cryptocaps);
5092 }
5093
5094 /* The MTU/MSS Table is initialized by now, so load their values. If
5095 * we're initializing the adapter, then we'll make any modifications
5096 * we want to the MTU/MSS Table and also initialize the congestion
5097 * parameters.
5098 */
5099 t4_read_mtu_tbl(adap, adap->params.mtus, NULL);
5100 if (state != DEV_STATE_INIT) {
5101 int i;
5102
5103 /* The default MTU Table contains values 1492 and 1500.
5104 * However, for TCP, it's better to have two values which are
5105 * a multiple of 8 +/- 4 bytes apart near this popular MTU.
5106 * This allows us to have a TCP Data Payload which is a
5107 * multiple of 8 regardless of what combination of TCP Options
5108 * are in use (always a multiple of 4 bytes) which is
5109 * important for performance reasons. For instance, if no
5110 * options are in use, then we have a 20-byte IP header and a
5111 * 20-byte TCP header. In this case, a 1500-byte MSS would
5112 * result in a TCP Data Payload of 1500 - 40 == 1460 bytes
5113 * which is not a multiple of 8. So using an MSS of 1488 in
5114 * this case results in a TCP Data Payload of 1448 bytes which
5115 * is a multiple of 8. On the other hand, if 12-byte TCP Time
5116 * Stamps have been negotiated, then an MTU of 1500 bytes
5117 * results in a TCP Data Payload of 1448 bytes which, as
5118 * above, is a multiple of 8 bytes ...
5119 */
5120 for (i = 0; i < NMTUS; i++)
5121 if (adap->params.mtus[i] == 1492) {
5122 adap->params.mtus[i] = 1488;
5123 break;
5124 }
5125
5126 t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd,
5127 adap->params.b_wnd);
5128 }
5129 t4_init_sge_params(adap);
5130 adap->flags |= CXGB4_FW_OK;
5131 t4_init_tp_params(adap, true);
5132 return 0;
5133
5134 /*
5135 * Something bad happened. If a command timed out or failed with EIO
5136 * FW does not operate within its spec or something catastrophic
5137 * happened to HW/FW, stop issuing commands.
5138 */
5139 bye:
5140 adap_free_hma_mem(adap);
5141 kfree(adap->sge.egr_map);
5142 kfree(adap->sge.ingr_map);
5143 kfree(adap->sge.starving_fl);
5144 kfree(adap->sge.txq_maperr);
5145 #ifdef CONFIG_DEBUG_FS
5146 kfree(adap->sge.blocked_fl);
5147 #endif
5148 if (ret != -ETIMEDOUT && ret != -EIO)
5149 t4_fw_bye(adap, adap->mbox);
5150 return ret;
5151 }
5152
5153 /* EEH callbacks */
5154
5155 static pci_ers_result_t eeh_err_detected(struct pci_dev *pdev,
5156 pci_channel_state_t state)
5157 {
5158 int i;
5159 struct adapter *adap = pci_get_drvdata(pdev);
5160
5161 if (!adap)
5162 goto out;
5163
5164 rtnl_lock();
5165 adap->flags &= ~CXGB4_FW_OK;
5166 notify_ulds(adap, CXGB4_STATE_START_RECOVERY);
5167 spin_lock(&adap->stats_lock);
5168 for_each_port(adap, i) {
5169 struct net_device *dev = adap->port[i];
5170 if (dev) {
5171 netif_device_detach(dev);
5172 netif_carrier_off(dev);
5173 }
5174 }
5175 spin_unlock(&adap->stats_lock);
5176 disable_interrupts(adap);
5177 if (adap->flags & CXGB4_FULL_INIT_DONE)
5178 cxgb_down(adap);
5179 rtnl_unlock();
5180 if ((adap->flags & CXGB4_DEV_ENABLED)) {
5181 pci_disable_device(pdev);
5182 adap->flags &= ~CXGB4_DEV_ENABLED;
5183 }
5184 out: return state == pci_channel_io_perm_failure ?
5185 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
5186 }
5187
5188 static pci_ers_result_t eeh_slot_reset(struct pci_dev *pdev)
5189 {
5190 int i, ret;
5191 struct fw_caps_config_cmd c;
5192 struct adapter *adap = pci_get_drvdata(pdev);
5193
5194 if (!adap) {
5195 pci_restore_state(pdev);
5196 pci_save_state(pdev);
5197 return PCI_ERS_RESULT_RECOVERED;
5198 }
5199
5200 if (!(adap->flags & CXGB4_DEV_ENABLED)) {
5201 if (pci_enable_device(pdev)) {
5202 dev_err(&pdev->dev, "Cannot reenable PCI "
5203 "device after reset\n");
5204 return PCI_ERS_RESULT_DISCONNECT;
5205 }
5206 adap->flags |= CXGB4_DEV_ENABLED;
5207 }
5208
5209 pci_set_master(pdev);
5210 pci_restore_state(pdev);
5211 pci_save_state(pdev);
5212
5213 if (t4_wait_dev_ready(adap->regs) < 0)
5214 return PCI_ERS_RESULT_DISCONNECT;
5215 if (t4_fw_hello(adap, adap->mbox, adap->pf, MASTER_MUST, NULL) < 0)
5216 return PCI_ERS_RESULT_DISCONNECT;
5217 adap->flags |= CXGB4_FW_OK;
5218 if (adap_init1(adap, &c))
5219 return PCI_ERS_RESULT_DISCONNECT;
5220
5221 for_each_port(adap, i) {
5222 struct port_info *pi = adap2pinfo(adap, i);
5223 u8 vivld = 0, vin = 0;
5224
5225 ret = t4_alloc_vi(adap, adap->mbox, pi->tx_chan, adap->pf, 0, 1,
5226 NULL, NULL, &vivld, &vin);
5227 if (ret < 0)
5228 return PCI_ERS_RESULT_DISCONNECT;
5229 pi->viid = ret;
5230 pi->xact_addr_filt = -1;
5231 /* If fw supports returning the VIN as part of FW_VI_CMD,
5232 * save the returned values.
5233 */
5234 if (adap->params.viid_smt_extn_support) {
5235 pi->vivld = vivld;
5236 pi->vin = vin;
5237 } else {
5238 /* Retrieve the values from VIID */
5239 pi->vivld = FW_VIID_VIVLD_G(pi->viid);
5240 pi->vin = FW_VIID_VIN_G(pi->viid);
5241 }
5242 }
5243
5244 t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd,
5245 adap->params.b_wnd);
5246 setup_memwin(adap);
5247 if (cxgb_up(adap))
5248 return PCI_ERS_RESULT_DISCONNECT;
5249 return PCI_ERS_RESULT_RECOVERED;
5250 }
5251
5252 static void eeh_resume(struct pci_dev *pdev)
5253 {
5254 int i;
5255 struct adapter *adap = pci_get_drvdata(pdev);
5256
5257 if (!adap)
5258 return;
5259
5260 rtnl_lock();
5261 for_each_port(adap, i) {
5262 struct net_device *dev = adap->port[i];
5263 if (dev) {
5264 if (netif_running(dev)) {
5265 link_start(dev);
5266 cxgb_set_rxmode(dev);
5267 }
5268 netif_device_attach(dev);
5269 }
5270 }
5271 rtnl_unlock();
5272 }
5273
5274 static void eeh_reset_prepare(struct pci_dev *pdev)
5275 {
5276 struct adapter *adapter = pci_get_drvdata(pdev);
5277 int i;
5278
5279 if (adapter->pf != 4)
5280 return;
5281
5282 adapter->flags &= ~CXGB4_FW_OK;
5283
5284 notify_ulds(adapter, CXGB4_STATE_DOWN);
5285
5286 for_each_port(adapter, i)
5287 if (adapter->port[i]->reg_state == NETREG_REGISTERED)
5288 cxgb_close(adapter->port[i]);
5289
5290 disable_interrupts(adapter);
5291 cxgb4_free_mps_ref_entries(adapter);
5292
5293 adap_free_hma_mem(adapter);
5294
5295 if (adapter->flags & CXGB4_FULL_INIT_DONE)
5296 cxgb_down(adapter);
5297 }
5298
5299 static void eeh_reset_done(struct pci_dev *pdev)
5300 {
5301 struct adapter *adapter = pci_get_drvdata(pdev);
5302 int err, i;
5303
5304 if (adapter->pf != 4)
5305 return;
5306
5307 err = t4_wait_dev_ready(adapter->regs);
5308 if (err < 0) {
5309 dev_err(adapter->pdev_dev,
5310 "Device not ready, err %d", err);
5311 return;
5312 }
5313
5314 setup_memwin(adapter);
5315
5316 err = adap_init0(adapter, 1);
5317 if (err) {
5318 dev_err(adapter->pdev_dev,
5319 "Adapter init failed, err %d", err);
5320 return;
5321 }
5322
5323 setup_memwin_rdma(adapter);
5324
5325 if (adapter->flags & CXGB4_FW_OK) {
5326 err = t4_port_init(adapter, adapter->pf, adapter->pf, 0);
5327 if (err) {
5328 dev_err(adapter->pdev_dev,
5329 "Port init failed, err %d", err);
5330 return;
5331 }
5332 }
5333
5334 err = cfg_queues(adapter);
5335 if (err) {
5336 dev_err(adapter->pdev_dev,
5337 "Config queues failed, err %d", err);
5338 return;
5339 }
5340
5341 cxgb4_init_mps_ref_entries(adapter);
5342
5343 err = setup_fw_sge_queues(adapter);
5344 if (err) {
5345 dev_err(adapter->pdev_dev,
5346 "FW sge queue allocation failed, err %d", err);
5347 return;
5348 }
5349
5350 for_each_port(adapter, i)
5351 if (adapter->port[i]->reg_state == NETREG_REGISTERED)
5352 cxgb_open(adapter->port[i]);
5353 }
5354
5355 static const struct pci_error_handlers cxgb4_eeh = {
5356 .error_detected = eeh_err_detected,
5357 .slot_reset = eeh_slot_reset,
5358 .resume = eeh_resume,
5359 .reset_prepare = eeh_reset_prepare,
5360 .reset_done = eeh_reset_done,
5361 };
5362
5363 /* Return true if the Link Configuration supports "High Speeds" (those greater
5364 * than 1Gb/s).
5365 */
5366 static inline bool is_x_10g_port(const struct link_config *lc)
5367 {
5368 unsigned int speeds, high_speeds;
5369
5370 speeds = FW_PORT_CAP32_SPEED_V(FW_PORT_CAP32_SPEED_G(lc->pcaps));
5371 high_speeds = speeds &
5372 ~(FW_PORT_CAP32_SPEED_100M | FW_PORT_CAP32_SPEED_1G);
5373
5374 return high_speeds != 0;
5375 }
5376
5377 /* Perform default configuration of DMA queues depending on the number and type
5378 * of ports we found and the number of available CPUs. Most settings can be
5379 * modified by the admin prior to actual use.
5380 */
5381 static int cfg_queues(struct adapter *adap)
5382 {
5383 u32 avail_qsets, avail_eth_qsets, avail_uld_qsets;
5384 u32 niqflint, neq, num_ulds;
5385 struct sge *s = &adap->sge;
5386 u32 i, n10g = 0, qidx = 0;
5387 #ifndef CONFIG_CHELSIO_T4_DCB
5388 int q10g = 0;
5389 #endif
5390
5391 /* Reduce memory usage in kdump environment, disable all offload. */
5392 if (is_kdump_kernel() || (is_uld(adap) && t4_uld_mem_alloc(adap))) {
5393 adap->params.offload = 0;
5394 adap->params.crypto = 0;
5395 adap->params.ethofld = 0;
5396 }
5397
5398 /* Calculate the number of Ethernet Queue Sets available based on
5399 * resources provisioned for us. We always have an Asynchronous
5400 * Firmware Event Ingress Queue. If we're operating in MSI or Legacy
5401 * IRQ Pin Interrupt mode, then we'll also have a Forwarded Interrupt
5402 * Ingress Queue. Meanwhile, we need two Egress Queues for each
5403 * Queue Set: one for the Free List and one for the Ethernet TX Queue.
5404 *
5405 * Note that we should also take into account all of the various
5406 * Offload Queues. But, in any situation where we're operating in
5407 * a Resource Constrained Provisioning environment, doing any Offload
5408 * at all is problematic ...
5409 */
5410 niqflint = adap->params.pfres.niqflint - 1;
5411 if (!(adap->flags & CXGB4_USING_MSIX))
5412 niqflint--;
5413 neq = adap->params.pfres.neq / 2;
5414 avail_qsets = min(niqflint, neq);
5415
5416 if (avail_qsets < adap->params.nports) {
5417 dev_err(adap->pdev_dev, "avail_eth_qsets=%d < nports=%d\n",
5418 avail_qsets, adap->params.nports);
5419 return -ENOMEM;
5420 }
5421
5422 /* Count the number of 10Gb/s or better ports */
5423 for_each_port(adap, i)
5424 n10g += is_x_10g_port(&adap2pinfo(adap, i)->link_cfg);
5425
5426 avail_eth_qsets = min_t(u32, avail_qsets, MAX_ETH_QSETS);
5427 #ifdef CONFIG_CHELSIO_T4_DCB
5428 /* For Data Center Bridging support we need to be able to support up
5429 * to 8 Traffic Priorities; each of which will be assigned to its
5430 * own TX Queue in order to prevent Head-Of-Line Blocking.
5431 */
5432 if (adap->params.nports * 8 > avail_eth_qsets) {
5433 dev_err(adap->pdev_dev, "DCB avail_eth_qsets=%d < %d!\n",
5434 avail_eth_qsets, adap->params.nports * 8);
5435 return -ENOMEM;
5436 }
5437
5438 for_each_port(adap, i) {
5439 struct port_info *pi = adap2pinfo(adap, i);
5440
5441 pi->first_qset = qidx;
5442 pi->nqsets = is_kdump_kernel() ? 1 : 8;
5443 qidx += pi->nqsets;
5444 }
5445 #else /* !CONFIG_CHELSIO_T4_DCB */
5446 /* We default to 1 queue per non-10G port and up to # of cores queues
5447 * per 10G port.
5448 */
5449 if (n10g)
5450 q10g = (avail_eth_qsets - (adap->params.nports - n10g)) / n10g;
5451 if (q10g > netif_get_num_default_rss_queues())
5452 q10g = netif_get_num_default_rss_queues();
5453
5454 if (is_kdump_kernel())
5455 q10g = 1;
5456
5457 for_each_port(adap, i) {
5458 struct port_info *pi = adap2pinfo(adap, i);
5459
5460 pi->first_qset = qidx;
5461 pi->nqsets = is_x_10g_port(&pi->link_cfg) ? q10g : 1;
5462 qidx += pi->nqsets;
5463 }
5464 #endif /* !CONFIG_CHELSIO_T4_DCB */
5465
5466 s->ethqsets = qidx;
5467 s->max_ethqsets = qidx; /* MSI-X may lower it later */
5468 avail_qsets -= qidx;
5469
5470 if (is_uld(adap)) {
5471 /* For offload we use 1 queue/channel if all ports are up to 1G,
5472 * otherwise we divide all available queues amongst the channels
5473 * capped by the number of available cores.
5474 */
5475 num_ulds = adap->num_uld + adap->num_ofld_uld;
5476 i = min_t(u32, MAX_OFLD_QSETS, num_online_cpus());
5477 avail_uld_qsets = roundup(i, adap->params.nports);
5478 if (avail_qsets < num_ulds * adap->params.nports) {
5479 adap->params.offload = 0;
5480 adap->params.crypto = 0;
5481 s->ofldqsets = 0;
5482 } else if (avail_qsets < num_ulds * avail_uld_qsets || !n10g) {
5483 s->ofldqsets = adap->params.nports;
5484 } else {
5485 s->ofldqsets = avail_uld_qsets;
5486 }
5487
5488 avail_qsets -= num_ulds * s->ofldqsets;
5489 }
5490
5491 /* ETHOFLD Queues used for QoS offload should follow same
5492 * allocation scheme as normal Ethernet Queues.
5493 */
5494 if (is_ethofld(adap)) {
5495 if (avail_qsets < s->max_ethqsets) {
5496 adap->params.ethofld = 0;
5497 s->eoqsets = 0;
5498 } else {
5499 s->eoqsets = s->max_ethqsets;
5500 }
5501 avail_qsets -= s->eoqsets;
5502 }
5503
5504 for (i = 0; i < ARRAY_SIZE(s->ethrxq); i++) {
5505 struct sge_eth_rxq *r = &s->ethrxq[i];
5506
5507 init_rspq(adap, &r->rspq, 5, 10, 1024, 64);
5508 r->fl.size = 72;
5509 }
5510
5511 for (i = 0; i < ARRAY_SIZE(s->ethtxq); i++)
5512 s->ethtxq[i].q.size = 1024;
5513
5514 for (i = 0; i < ARRAY_SIZE(s->ctrlq); i++)
5515 s->ctrlq[i].q.size = 512;
5516
5517 if (!is_t4(adap->params.chip))
5518 s->ptptxq.q.size = 8;
5519
5520 init_rspq(adap, &s->fw_evtq, 0, 1, 1024, 64);
5521 init_rspq(adap, &s->intrq, 0, 1, 512, 64);
5522
5523 return 0;
5524 }
5525
5526 /*
5527 * Reduce the number of Ethernet queues across all ports to at most n.
5528 * n provides at least one queue per port.
5529 */
5530 static void reduce_ethqs(struct adapter *adap, int n)
5531 {
5532 int i;
5533 struct port_info *pi;
5534
5535 while (n < adap->sge.ethqsets)
5536 for_each_port(adap, i) {
5537 pi = adap2pinfo(adap, i);
5538 if (pi->nqsets > 1) {
5539 pi->nqsets--;
5540 adap->sge.ethqsets--;
5541 if (adap->sge.ethqsets <= n)
5542 break;
5543 }
5544 }
5545
5546 n = 0;
5547 for_each_port(adap, i) {
5548 pi = adap2pinfo(adap, i);
5549 pi->first_qset = n;
5550 n += pi->nqsets;
5551 }
5552 }
5553
5554 static int alloc_msix_info(struct adapter *adap, u32 num_vec)
5555 {
5556 struct msix_info *msix_info;
5557
5558 msix_info = kcalloc(num_vec, sizeof(*msix_info), GFP_KERNEL);
5559 if (!msix_info)
5560 return -ENOMEM;
5561
5562 adap->msix_bmap.msix_bmap = kcalloc(BITS_TO_LONGS(num_vec),
5563 sizeof(long), GFP_KERNEL);
5564 if (!adap->msix_bmap.msix_bmap) {
5565 kfree(msix_info);
5566 return -ENOMEM;
5567 }
5568
5569 spin_lock_init(&adap->msix_bmap.lock);
5570 adap->msix_bmap.mapsize = num_vec;
5571
5572 adap->msix_info = msix_info;
5573 return 0;
5574 }
5575
5576 static void free_msix_info(struct adapter *adap)
5577 {
5578 kfree(adap->msix_bmap.msix_bmap);
5579 kfree(adap->msix_info);
5580 }
5581
5582 int cxgb4_get_msix_idx_from_bmap(struct adapter *adap)
5583 {
5584 struct msix_bmap *bmap = &adap->msix_bmap;
5585 unsigned int msix_idx;
5586 unsigned long flags;
5587
5588 spin_lock_irqsave(&bmap->lock, flags);
5589 msix_idx = find_first_zero_bit(bmap->msix_bmap, bmap->mapsize);
5590 if (msix_idx < bmap->mapsize) {
5591 __set_bit(msix_idx, bmap->msix_bmap);
5592 } else {
5593 spin_unlock_irqrestore(&bmap->lock, flags);
5594 return -ENOSPC;
5595 }
5596
5597 spin_unlock_irqrestore(&bmap->lock, flags);
5598 return msix_idx;
5599 }
5600
5601 void cxgb4_free_msix_idx_in_bmap(struct adapter *adap,
5602 unsigned int msix_idx)
5603 {
5604 struct msix_bmap *bmap = &adap->msix_bmap;
5605 unsigned long flags;
5606
5607 spin_lock_irqsave(&bmap->lock, flags);
5608 __clear_bit(msix_idx, bmap->msix_bmap);
5609 spin_unlock_irqrestore(&bmap->lock, flags);
5610 }
5611
5612 /* 2 MSI-X vectors needed for the FW queue and non-data interrupts */
5613 #define EXTRA_VECS 2
5614
5615 static int enable_msix(struct adapter *adap)
5616 {
5617 u32 eth_need, uld_need = 0, ethofld_need = 0;
5618 u32 ethqsets = 0, ofldqsets = 0, eoqsets = 0;
5619 u8 num_uld = 0, nchan = adap->params.nports;
5620 u32 i, want, need, num_vec;
5621 struct sge *s = &adap->sge;
5622 struct msix_entry *entries;
5623 struct port_info *pi;
5624 int allocated, ret;
5625
5626 want = s->max_ethqsets;
5627 #ifdef CONFIG_CHELSIO_T4_DCB
5628 /* For Data Center Bridging we need 8 Ethernet TX Priority Queues for
5629 * each port.
5630 */
5631 need = 8 * nchan;
5632 #else
5633 need = nchan;
5634 #endif
5635 eth_need = need;
5636 if (is_uld(adap)) {
5637 num_uld = adap->num_ofld_uld + adap->num_uld;
5638 want += num_uld * s->ofldqsets;
5639 uld_need = num_uld * nchan;
5640 need += uld_need;
5641 }
5642
5643 if (is_ethofld(adap)) {
5644 want += s->eoqsets;
5645 ethofld_need = eth_need;
5646 need += ethofld_need;
5647 }
5648
5649 want += EXTRA_VECS;
5650 need += EXTRA_VECS;
5651
5652 entries = kmalloc_array(want, sizeof(*entries), GFP_KERNEL);
5653 if (!entries)
5654 return -ENOMEM;
5655
5656 for (i = 0; i < want; i++)
5657 entries[i].entry = i;
5658
5659 allocated = pci_enable_msix_range(adap->pdev, entries, need, want);
5660 if (allocated < 0) {
5661 /* Disable offload and attempt to get vectors for NIC
5662 * only mode.
5663 */
5664 want = s->max_ethqsets + EXTRA_VECS;
5665 need = eth_need + EXTRA_VECS;
5666 allocated = pci_enable_msix_range(adap->pdev, entries,
5667 need, want);
5668 if (allocated < 0) {
5669 dev_info(adap->pdev_dev,
5670 "Disabling MSI-X due to insufficient MSI-X vectors\n");
5671 ret = allocated;
5672 goto out_free;
5673 }
5674
5675 dev_info(adap->pdev_dev,
5676 "Disabling offload due to insufficient MSI-X vectors\n");
5677 adap->params.offload = 0;
5678 adap->params.crypto = 0;
5679 adap->params.ethofld = 0;
5680 s->ofldqsets = 0;
5681 s->eoqsets = 0;
5682 uld_need = 0;
5683 ethofld_need = 0;
5684 }
5685
5686 num_vec = allocated;
5687 if (num_vec < want) {
5688 /* Distribute available vectors to the various queue groups.
5689 * Every group gets its minimum requirement and NIC gets top
5690 * priority for leftovers.
5691 */
5692 ethqsets = eth_need;
5693 if (is_uld(adap))
5694 ofldqsets = nchan;
5695 if (is_ethofld(adap))
5696 eoqsets = ethofld_need;
5697
5698 num_vec -= need;
5699 while (num_vec) {
5700 if (num_vec < eth_need + ethofld_need ||
5701 ethqsets > s->max_ethqsets)
5702 break;
5703
5704 for_each_port(adap, i) {
5705 pi = adap2pinfo(adap, i);
5706 if (pi->nqsets < 2)
5707 continue;
5708
5709 ethqsets++;
5710 num_vec--;
5711 if (ethofld_need) {
5712 eoqsets++;
5713 num_vec--;
5714 }
5715 }
5716 }
5717
5718 if (is_uld(adap)) {
5719 while (num_vec) {
5720 if (num_vec < uld_need ||
5721 ofldqsets > s->ofldqsets)
5722 break;
5723
5724 ofldqsets++;
5725 num_vec -= uld_need;
5726 }
5727 }
5728 } else {
5729 ethqsets = s->max_ethqsets;
5730 if (is_uld(adap))
5731 ofldqsets = s->ofldqsets;
5732 if (is_ethofld(adap))
5733 eoqsets = s->eoqsets;
5734 }
5735
5736 if (ethqsets < s->max_ethqsets) {
5737 s->max_ethqsets = ethqsets;
5738 reduce_ethqs(adap, ethqsets);
5739 }
5740
5741 if (is_uld(adap)) {
5742 s->ofldqsets = ofldqsets;
5743 s->nqs_per_uld = s->ofldqsets;
5744 }
5745
5746 if (is_ethofld(adap))
5747 s->eoqsets = eoqsets;
5748
5749 /* map for msix */
5750 ret = alloc_msix_info(adap, allocated);
5751 if (ret)
5752 goto out_disable_msix;
5753
5754 for (i = 0; i < allocated; i++) {
5755 adap->msix_info[i].vec = entries[i].vector;
5756 adap->msix_info[i].idx = i;
5757 }
5758
5759 dev_info(adap->pdev_dev,
5760 "%d MSI-X vectors allocated, nic %d eoqsets %d per uld %d\n",
5761 allocated, s->max_ethqsets, s->eoqsets, s->nqs_per_uld);
5762
5763 kfree(entries);
5764 return 0;
5765
5766 out_disable_msix:
5767 pci_disable_msix(adap->pdev);
5768
5769 out_free:
5770 kfree(entries);
5771 return ret;
5772 }
5773
5774 #undef EXTRA_VECS
5775
5776 static int init_rss(struct adapter *adap)
5777 {
5778 unsigned int i;
5779 int err;
5780
5781 err = t4_init_rss_mode(adap, adap->mbox);
5782 if (err)
5783 return err;
5784
5785 for_each_port(adap, i) {
5786 struct port_info *pi = adap2pinfo(adap, i);
5787
5788 pi->rss = kcalloc(pi->rss_size, sizeof(u16), GFP_KERNEL);
5789 if (!pi->rss)
5790 return -ENOMEM;
5791 }
5792 return 0;
5793 }
5794
5795 /* Dump basic information about the adapter */
5796 static void print_adapter_info(struct adapter *adapter)
5797 {
5798 /* Hardware/Firmware/etc. Version/Revision IDs */
5799 t4_dump_version_info(adapter);
5800
5801 /* Software/Hardware configuration */
5802 dev_info(adapter->pdev_dev, "Configuration: %sNIC %s, %s capable\n",
5803 is_offload(adapter) ? "R" : "",
5804 ((adapter->flags & CXGB4_USING_MSIX) ? "MSI-X" :
5805 (adapter->flags & CXGB4_USING_MSI) ? "MSI" : ""),
5806 is_offload(adapter) ? "Offload" : "non-Offload");
5807 }
5808
5809 static void print_port_info(const struct net_device *dev)
5810 {
5811 char buf[80];
5812 char *bufp = buf;
5813 const struct port_info *pi = netdev_priv(dev);
5814 const struct adapter *adap = pi->adapter;
5815
5816 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_100M)
5817 bufp += sprintf(bufp, "100M/");
5818 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_1G)
5819 bufp += sprintf(bufp, "1G/");
5820 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_10G)
5821 bufp += sprintf(bufp, "10G/");
5822 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_25G)
5823 bufp += sprintf(bufp, "25G/");
5824 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_40G)
5825 bufp += sprintf(bufp, "40G/");
5826 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_50G)
5827 bufp += sprintf(bufp, "50G/");
5828 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_100G)
5829 bufp += sprintf(bufp, "100G/");
5830 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_200G)
5831 bufp += sprintf(bufp, "200G/");
5832 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_400G)
5833 bufp += sprintf(bufp, "400G/");
5834 if (bufp != buf)
5835 --bufp;
5836 sprintf(bufp, "BASE-%s", t4_get_port_type_description(pi->port_type));
5837
5838 netdev_info(dev, "%s: Chelsio %s (%s) %s\n",
5839 dev->name, adap->params.vpd.id, adap->name, buf);
5840 }
5841
5842 /*
5843 * Free the following resources:
5844 * - memory used for tables
5845 * - MSI/MSI-X
5846 * - net devices
5847 * - resources FW is holding for us
5848 */
5849 static void free_some_resources(struct adapter *adapter)
5850 {
5851 unsigned int i;
5852
5853 kvfree(adapter->smt);
5854 kvfree(adapter->l2t);
5855 kvfree(adapter->srq);
5856 t4_cleanup_sched(adapter);
5857 kvfree(adapter->tids.tid_tab);
5858 cxgb4_cleanup_tc_matchall(adapter);
5859 cxgb4_cleanup_tc_mqprio(adapter);
5860 cxgb4_cleanup_tc_flower(adapter);
5861 cxgb4_cleanup_tc_u32(adapter);
5862 kfree(adapter->sge.egr_map);
5863 kfree(adapter->sge.ingr_map);
5864 kfree(adapter->sge.starving_fl);
5865 kfree(adapter->sge.txq_maperr);
5866 #ifdef CONFIG_DEBUG_FS
5867 kfree(adapter->sge.blocked_fl);
5868 #endif
5869 disable_msi(adapter);
5870
5871 for_each_port(adapter, i)
5872 if (adapter->port[i]) {
5873 struct port_info *pi = adap2pinfo(adapter, i);
5874
5875 if (pi->viid != 0)
5876 t4_free_vi(adapter, adapter->mbox, adapter->pf,
5877 0, pi->viid);
5878 kfree(adap2pinfo(adapter, i)->rss);
5879 free_netdev(adapter->port[i]);
5880 }
5881 if (adapter->flags & CXGB4_FW_OK)
5882 t4_fw_bye(adapter, adapter->pf);
5883 }
5884
5885 #define TSO_FLAGS (NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_TSO_ECN | \
5886 NETIF_F_GSO_UDP_L4)
5887 #define VLAN_FEAT (NETIF_F_SG | NETIF_F_IP_CSUM | TSO_FLAGS | \
5888 NETIF_F_GRO | NETIF_F_IPV6_CSUM | NETIF_F_HIGHDMA)
5889 #define SEGMENT_SIZE 128
5890
5891 static int t4_get_chip_type(struct adapter *adap, int ver)
5892 {
5893 u32 pl_rev = REV_G(t4_read_reg(adap, PL_REV_A));
5894
5895 switch (ver) {
5896 case CHELSIO_T4:
5897 return CHELSIO_CHIP_CODE(CHELSIO_T4, pl_rev);
5898 case CHELSIO_T5:
5899 return CHELSIO_CHIP_CODE(CHELSIO_T5, pl_rev);
5900 case CHELSIO_T6:
5901 return CHELSIO_CHIP_CODE(CHELSIO_T6, pl_rev);
5902 default:
5903 break;
5904 }
5905 return -EINVAL;
5906 }
5907
5908 #ifdef CONFIG_PCI_IOV
5909 static void cxgb4_mgmt_setup(struct net_device *dev)
5910 {
5911 dev->type = ARPHRD_NONE;
5912 dev->mtu = 0;
5913 dev->hard_header_len = 0;
5914 dev->addr_len = 0;
5915 dev->tx_queue_len = 0;
5916 dev->flags |= IFF_NOARP;
5917 dev->priv_flags |= IFF_NO_QUEUE;
5918
5919 /* Initialize the device structure. */
5920 dev->netdev_ops = &cxgb4_mgmt_netdev_ops;
5921 dev->ethtool_ops = &cxgb4_mgmt_ethtool_ops;
5922 }
5923
5924 static int cxgb4_iov_configure(struct pci_dev *pdev, int num_vfs)
5925 {
5926 struct adapter *adap = pci_get_drvdata(pdev);
5927 int err = 0;
5928 int current_vfs = pci_num_vf(pdev);
5929 u32 pcie_fw;
5930
5931 pcie_fw = readl(adap->regs + PCIE_FW_A);
5932 /* Check if fw is initialized */
5933 if (!(pcie_fw & PCIE_FW_INIT_F)) {
5934 dev_warn(&pdev->dev, "Device not initialized\n");
5935 return -EOPNOTSUPP;
5936 }
5937
5938 /* If any of the VF's is already assigned to Guest OS, then
5939 * SRIOV for the same cannot be modified
5940 */
5941 if (current_vfs && pci_vfs_assigned(pdev)) {
5942 dev_err(&pdev->dev,
5943 "Cannot modify SR-IOV while VFs are assigned\n");
5944 return current_vfs;
5945 }
5946 /* Note that the upper-level code ensures that we're never called with
5947 * a non-zero "num_vfs" when we already have VFs instantiated. But
5948 * it never hurts to code defensively.
5949 */
5950 if (num_vfs != 0 && current_vfs != 0)
5951 return -EBUSY;
5952
5953 /* Nothing to do for no change. */
5954 if (num_vfs == current_vfs)
5955 return num_vfs;
5956
5957 /* Disable SRIOV when zero is passed. */
5958 if (!num_vfs) {
5959 pci_disable_sriov(pdev);
5960 /* free VF Management Interface */
5961 unregister_netdev(adap->port[0]);
5962 free_netdev(adap->port[0]);
5963 adap->port[0] = NULL;
5964
5965 /* free VF resources */
5966 adap->num_vfs = 0;
5967 kfree(adap->vfinfo);
5968 adap->vfinfo = NULL;
5969 return 0;
5970 }
5971
5972 if (!current_vfs) {
5973 struct fw_pfvf_cmd port_cmd, port_rpl;
5974 struct net_device *netdev;
5975 unsigned int pmask, port;
5976 struct pci_dev *pbridge;
5977 struct port_info *pi;
5978 char name[IFNAMSIZ];
5979 u32 devcap2;
5980 u16 flags;
5981
5982 /* If we want to instantiate Virtual Functions, then our
5983 * parent bridge's PCI-E needs to support Alternative Routing
5984 * ID (ARI) because our VFs will show up at function offset 8
5985 * and above.
5986 */
5987 pbridge = pdev->bus->self;
5988 pcie_capability_read_word(pbridge, PCI_EXP_FLAGS, &flags);
5989 pcie_capability_read_dword(pbridge, PCI_EXP_DEVCAP2, &devcap2);
5990
5991 if ((flags & PCI_EXP_FLAGS_VERS) < 2 ||
5992 !(devcap2 & PCI_EXP_DEVCAP2_ARI)) {
5993 /* Our parent bridge does not support ARI so issue a
5994 * warning and skip instantiating the VFs. They
5995 * won't be reachable.
5996 */
5997 dev_warn(&pdev->dev, "Parent bridge %02x:%02x.%x doesn't support ARI; can't instantiate Virtual Functions\n",
5998 pbridge->bus->number, PCI_SLOT(pbridge->devfn),
5999 PCI_FUNC(pbridge->devfn));
6000 return -ENOTSUPP;
6001 }
6002 memset(&port_cmd, 0, sizeof(port_cmd));
6003 port_cmd.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PFVF_CMD) |
6004 FW_CMD_REQUEST_F |
6005 FW_CMD_READ_F |
6006 FW_PFVF_CMD_PFN_V(adap->pf) |
6007 FW_PFVF_CMD_VFN_V(0));
6008 port_cmd.retval_len16 = cpu_to_be32(FW_LEN16(port_cmd));
6009 err = t4_wr_mbox(adap, adap->mbox, &port_cmd, sizeof(port_cmd),
6010 &port_rpl);
6011 if (err)
6012 return err;
6013 pmask = FW_PFVF_CMD_PMASK_G(be32_to_cpu(port_rpl.type_to_neq));
6014 port = ffs(pmask) - 1;
6015 /* Allocate VF Management Interface. */
6016 snprintf(name, IFNAMSIZ, "mgmtpf%d,%d", adap->adap_idx,
6017 adap->pf);
6018 netdev = alloc_netdev(sizeof(struct port_info),
6019 name, NET_NAME_UNKNOWN, cxgb4_mgmt_setup);
6020 if (!netdev)
6021 return -ENOMEM;
6022
6023 pi = netdev_priv(netdev);
6024 pi->adapter = adap;
6025 pi->lport = port;
6026 pi->tx_chan = port;
6027 SET_NETDEV_DEV(netdev, &pdev->dev);
6028
6029 adap->port[0] = netdev;
6030 pi->port_id = 0;
6031
6032 err = register_netdev(adap->port[0]);
6033 if (err) {
6034 pr_info("Unable to register VF mgmt netdev %s\n", name);
6035 free_netdev(adap->port[0]);
6036 adap->port[0] = NULL;
6037 return err;
6038 }
6039 /* Allocate and set up VF Information. */
6040 adap->vfinfo = kcalloc(pci_sriov_get_totalvfs(pdev),
6041 sizeof(struct vf_info), GFP_KERNEL);
6042 if (!adap->vfinfo) {
6043 unregister_netdev(adap->port[0]);
6044 free_netdev(adap->port[0]);
6045 adap->port[0] = NULL;
6046 return -ENOMEM;
6047 }
6048 cxgb4_mgmt_fill_vf_station_mac_addr(adap);
6049 }
6050 /* Instantiate the requested number of VFs. */
6051 err = pci_enable_sriov(pdev, num_vfs);
6052 if (err) {
6053 pr_info("Unable to instantiate %d VFs\n", num_vfs);
6054 if (!current_vfs) {
6055 unregister_netdev(adap->port[0]);
6056 free_netdev(adap->port[0]);
6057 adap->port[0] = NULL;
6058 kfree(adap->vfinfo);
6059 adap->vfinfo = NULL;
6060 }
6061 return err;
6062 }
6063
6064 adap->num_vfs = num_vfs;
6065 return num_vfs;
6066 }
6067 #endif /* CONFIG_PCI_IOV */
6068
6069 static int init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
6070 {
6071 struct net_device *netdev;
6072 struct adapter *adapter;
6073 static int adap_idx = 1;
6074 int s_qpp, qpp, num_seg;
6075 struct port_info *pi;
6076 bool highdma = false;
6077 enum chip_type chip;
6078 void __iomem *regs;
6079 int func, chip_ver;
6080 u16 device_id;
6081 int i, err;
6082 u32 whoami;
6083
6084 printk_once(KERN_INFO "%s - version %s\n", DRV_DESC, DRV_VERSION);
6085
6086 err = pci_request_regions(pdev, KBUILD_MODNAME);
6087 if (err) {
6088 /* Just info, some other driver may have claimed the device. */
6089 dev_info(&pdev->dev, "cannot obtain PCI resources\n");
6090 return err;
6091 }
6092
6093 err = pci_enable_device(pdev);
6094 if (err) {
6095 dev_err(&pdev->dev, "cannot enable PCI device\n");
6096 goto out_release_regions;
6097 }
6098
6099 regs = pci_ioremap_bar(pdev, 0);
6100 if (!regs) {
6101 dev_err(&pdev->dev, "cannot map device registers\n");
6102 err = -ENOMEM;
6103 goto out_disable_device;
6104 }
6105
6106 adapter = kzalloc(sizeof(*adapter), GFP_KERNEL);
6107 if (!adapter) {
6108 err = -ENOMEM;
6109 goto out_unmap_bar0;
6110 }
6111
6112 adapter->regs = regs;
6113 err = t4_wait_dev_ready(regs);
6114 if (err < 0)
6115 goto out_free_adapter;
6116
6117 /* We control everything through one PF */
6118 whoami = t4_read_reg(adapter, PL_WHOAMI_A);
6119 pci_read_config_word(pdev, PCI_DEVICE_ID, &device_id);
6120 chip = t4_get_chip_type(adapter, CHELSIO_PCI_ID_VER(device_id));
6121 if ((int)chip < 0) {
6122 dev_err(&pdev->dev, "Device %d is not supported\n", device_id);
6123 err = chip;
6124 goto out_free_adapter;
6125 }
6126 chip_ver = CHELSIO_CHIP_VERSION(chip);
6127 func = chip_ver <= CHELSIO_T5 ?
6128 SOURCEPF_G(whoami) : T6_SOURCEPF_G(whoami);
6129
6130 adapter->pdev = pdev;
6131 adapter->pdev_dev = &pdev->dev;
6132 adapter->name = pci_name(pdev);
6133 adapter->mbox = func;
6134 adapter->pf = func;
6135 adapter->params.chip = chip;
6136 adapter->adap_idx = adap_idx;
6137 adapter->msg_enable = DFLT_MSG_ENABLE;
6138 adapter->mbox_log = kzalloc(sizeof(*adapter->mbox_log) +
6139 (sizeof(struct mbox_cmd) *
6140 T4_OS_LOG_MBOX_CMDS),
6141 GFP_KERNEL);
6142 if (!adapter->mbox_log) {
6143 err = -ENOMEM;
6144 goto out_free_adapter;
6145 }
6146 spin_lock_init(&adapter->mbox_lock);
6147 INIT_LIST_HEAD(&adapter->mlist.list);
6148 adapter->mbox_log->size = T4_OS_LOG_MBOX_CMDS;
6149 pci_set_drvdata(pdev, adapter);
6150
6151 if (func != ent->driver_data) {
6152 pci_disable_device(pdev);
6153 pci_save_state(pdev); /* to restore SR-IOV later */
6154 return 0;
6155 }
6156
6157 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
6158 highdma = true;
6159 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
6160 if (err) {
6161 dev_err(&pdev->dev, "unable to obtain 64-bit DMA for "
6162 "coherent allocations\n");
6163 goto out_free_adapter;
6164 }
6165 } else {
6166 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
6167 if (err) {
6168 dev_err(&pdev->dev, "no usable DMA configuration\n");
6169 goto out_free_adapter;
6170 }
6171 }
6172
6173 pci_enable_pcie_error_reporting(pdev);
6174 pci_set_master(pdev);
6175 pci_save_state(pdev);
6176 adap_idx++;
6177 adapter->workq = create_singlethread_workqueue("cxgb4");
6178 if (!adapter->workq) {
6179 err = -ENOMEM;
6180 goto out_free_adapter;
6181 }
6182
6183 /* PCI device has been enabled */
6184 adapter->flags |= CXGB4_DEV_ENABLED;
6185 memset(adapter->chan_map, 0xff, sizeof(adapter->chan_map));
6186
6187 /* If possible, we use PCIe Relaxed Ordering Attribute to deliver
6188 * Ingress Packet Data to Free List Buffers in order to allow for
6189 * chipset performance optimizations between the Root Complex and
6190 * Memory Controllers. (Messages to the associated Ingress Queue
6191 * notifying new Packet Placement in the Free Lists Buffers will be
6192 * send without the Relaxed Ordering Attribute thus guaranteeing that
6193 * all preceding PCIe Transaction Layer Packets will be processed
6194 * first.) But some Root Complexes have various issues with Upstream
6195 * Transaction Layer Packets with the Relaxed Ordering Attribute set.
6196 * The PCIe devices which under the Root Complexes will be cleared the
6197 * Relaxed Ordering bit in the configuration space, So we check our
6198 * PCIe configuration space to see if it's flagged with advice against
6199 * using Relaxed Ordering.
6200 */
6201 if (!pcie_relaxed_ordering_enabled(pdev))
6202 adapter->flags |= CXGB4_ROOT_NO_RELAXED_ORDERING;
6203
6204 spin_lock_init(&adapter->stats_lock);
6205 spin_lock_init(&adapter->tid_release_lock);
6206 spin_lock_init(&adapter->win0_lock);
6207
6208 INIT_WORK(&adapter->tid_release_task, process_tid_release_list);
6209 INIT_WORK(&adapter->db_full_task, process_db_full);
6210 INIT_WORK(&adapter->db_drop_task, process_db_drop);
6211 INIT_WORK(&adapter->fatal_err_notify_task, notify_fatal_err);
6212
6213 err = t4_prep_adapter(adapter);
6214 if (err)
6215 goto out_free_adapter;
6216
6217 if (is_kdump_kernel()) {
6218 /* Collect hardware state and append to /proc/vmcore */
6219 err = cxgb4_cudbg_vmcore_add_dump(adapter);
6220 if (err) {
6221 dev_warn(adapter->pdev_dev,
6222 "Fail collecting vmcore device dump, err: %d. Continuing\n",
6223 err);
6224 err = 0;
6225 }
6226 }
6227
6228 if (!is_t4(adapter->params.chip)) {
6229 s_qpp = (QUEUESPERPAGEPF0_S +
6230 (QUEUESPERPAGEPF1_S - QUEUESPERPAGEPF0_S) *
6231 adapter->pf);
6232 qpp = 1 << QUEUESPERPAGEPF0_G(t4_read_reg(adapter,
6233 SGE_EGRESS_QUEUES_PER_PAGE_PF_A) >> s_qpp);
6234 num_seg = PAGE_SIZE / SEGMENT_SIZE;
6235
6236 /* Each segment size is 128B. Write coalescing is enabled only
6237 * when SGE_EGRESS_QUEUES_PER_PAGE_PF reg value for the
6238 * queue is less no of segments that can be accommodated in
6239 * a page size.
6240 */
6241 if (qpp > num_seg) {
6242 dev_err(&pdev->dev,
6243 "Incorrect number of egress queues per page\n");
6244 err = -EINVAL;
6245 goto out_free_adapter;
6246 }
6247 adapter->bar2 = ioremap_wc(pci_resource_start(pdev, 2),
6248 pci_resource_len(pdev, 2));
6249 if (!adapter->bar2) {
6250 dev_err(&pdev->dev, "cannot map device bar2 region\n");
6251 err = -ENOMEM;
6252 goto out_free_adapter;
6253 }
6254 }
6255
6256 setup_memwin(adapter);
6257 err = adap_init0(adapter, 0);
6258 #ifdef CONFIG_DEBUG_FS
6259 bitmap_zero(adapter->sge.blocked_fl, adapter->sge.egr_sz);
6260 #endif
6261 setup_memwin_rdma(adapter);
6262 if (err)
6263 goto out_unmap_bar;
6264
6265 /* configure SGE_STAT_CFG_A to read WC stats */
6266 if (!is_t4(adapter->params.chip))
6267 t4_write_reg(adapter, SGE_STAT_CFG_A, STATSOURCE_T5_V(7) |
6268 (is_t5(adapter->params.chip) ? STATMODE_V(0) :
6269 T6_STATMODE_V(0)));
6270
6271 /* Initialize hash mac addr list */
6272 INIT_LIST_HEAD(&adapter->mac_hlist);
6273
6274 for_each_port(adapter, i) {
6275 /* For supporting MQPRIO Offload, need some extra
6276 * queues for each ETHOFLD TIDs. Keep it equal to
6277 * MAX_ATIDs for now. Once we connect to firmware
6278 * later and query the EOTID params, we'll come to
6279 * know the actual # of EOTIDs supported.
6280 */
6281 netdev = alloc_etherdev_mq(sizeof(struct port_info),
6282 MAX_ETH_QSETS + MAX_ATIDS);
6283 if (!netdev) {
6284 err = -ENOMEM;
6285 goto out_free_dev;
6286 }
6287
6288 SET_NETDEV_DEV(netdev, &pdev->dev);
6289
6290 adapter->port[i] = netdev;
6291 pi = netdev_priv(netdev);
6292 pi->adapter = adapter;
6293 pi->xact_addr_filt = -1;
6294 pi->port_id = i;
6295 netdev->irq = pdev->irq;
6296
6297 netdev->hw_features = NETIF_F_SG | TSO_FLAGS |
6298 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
6299 NETIF_F_RXCSUM | NETIF_F_RXHASH | NETIF_F_GRO |
6300 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |
6301 NETIF_F_HW_TC;
6302
6303 if (chip_ver > CHELSIO_T5) {
6304 netdev->hw_enc_features |= NETIF_F_IP_CSUM |
6305 NETIF_F_IPV6_CSUM |
6306 NETIF_F_RXCSUM |
6307 NETIF_F_GSO_UDP_TUNNEL |
6308 NETIF_F_GSO_UDP_TUNNEL_CSUM |
6309 NETIF_F_TSO | NETIF_F_TSO6;
6310
6311 netdev->hw_features |= NETIF_F_GSO_UDP_TUNNEL |
6312 NETIF_F_GSO_UDP_TUNNEL_CSUM |
6313 NETIF_F_HW_TLS_RECORD;
6314 }
6315
6316 if (highdma)
6317 netdev->hw_features |= NETIF_F_HIGHDMA;
6318 netdev->features |= netdev->hw_features;
6319 netdev->vlan_features = netdev->features & VLAN_FEAT;
6320
6321 netdev->priv_flags |= IFF_UNICAST_FLT;
6322
6323 /* MTU range: 81 - 9600 */
6324 netdev->min_mtu = 81; /* accommodate SACK */
6325 netdev->max_mtu = MAX_MTU;
6326
6327 netdev->netdev_ops = &cxgb4_netdev_ops;
6328 #ifdef CONFIG_CHELSIO_T4_DCB
6329 netdev->dcbnl_ops = &cxgb4_dcb_ops;
6330 cxgb4_dcb_state_init(netdev);
6331 cxgb4_dcb_version_init(netdev);
6332 #endif
6333 cxgb4_set_ethtool_ops(netdev);
6334 }
6335
6336 cxgb4_init_ethtool_dump(adapter);
6337
6338 pci_set_drvdata(pdev, adapter);
6339
6340 if (adapter->flags & CXGB4_FW_OK) {
6341 err = t4_port_init(adapter, func, func, 0);
6342 if (err)
6343 goto out_free_dev;
6344 } else if (adapter->params.nports == 1) {
6345 /* If we don't have a connection to the firmware -- possibly
6346 * because of an error -- grab the raw VPD parameters so we
6347 * can set the proper MAC Address on the debug network
6348 * interface that we've created.
6349 */
6350 u8 hw_addr[ETH_ALEN];
6351 u8 *na = adapter->params.vpd.na;
6352
6353 err = t4_get_raw_vpd_params(adapter, &adapter->params.vpd);
6354 if (!err) {
6355 for (i = 0; i < ETH_ALEN; i++)
6356 hw_addr[i] = (hex2val(na[2 * i + 0]) * 16 +
6357 hex2val(na[2 * i + 1]));
6358 t4_set_hw_addr(adapter, 0, hw_addr);
6359 }
6360 }
6361
6362 if (!(adapter->flags & CXGB4_FW_OK))
6363 goto fw_attach_fail;
6364
6365 /* Configure queues and allocate tables now, they can be needed as
6366 * soon as the first register_netdev completes.
6367 */
6368 err = cfg_queues(adapter);
6369 if (err)
6370 goto out_free_dev;
6371
6372 adapter->smt = t4_init_smt();
6373 if (!adapter->smt) {
6374 /* We tolerate a lack of SMT, giving up some functionality */
6375 dev_warn(&pdev->dev, "could not allocate SMT, continuing\n");
6376 }
6377
6378 adapter->l2t = t4_init_l2t(adapter->l2t_start, adapter->l2t_end);
6379 if (!adapter->l2t) {
6380 /* We tolerate a lack of L2T, giving up some functionality */
6381 dev_warn(&pdev->dev, "could not allocate L2T, continuing\n");
6382 adapter->params.offload = 0;
6383 }
6384
6385 #if IS_ENABLED(CONFIG_IPV6)
6386 if (chip_ver <= CHELSIO_T5 &&
6387 (!(t4_read_reg(adapter, LE_DB_CONFIG_A) & ASLIPCOMPEN_F))) {
6388 /* CLIP functionality is not present in hardware,
6389 * hence disable all offload features
6390 */
6391 dev_warn(&pdev->dev,
6392 "CLIP not enabled in hardware, continuing\n");
6393 adapter->params.offload = 0;
6394 } else {
6395 adapter->clipt = t4_init_clip_tbl(adapter->clipt_start,
6396 adapter->clipt_end);
6397 if (!adapter->clipt) {
6398 /* We tolerate a lack of clip_table, giving up
6399 * some functionality
6400 */
6401 dev_warn(&pdev->dev,
6402 "could not allocate Clip table, continuing\n");
6403 adapter->params.offload = 0;
6404 }
6405 }
6406 #endif
6407
6408 for_each_port(adapter, i) {
6409 pi = adap2pinfo(adapter, i);
6410 pi->sched_tbl = t4_init_sched(adapter->params.nsched_cls);
6411 if (!pi->sched_tbl)
6412 dev_warn(&pdev->dev,
6413 "could not activate scheduling on port %d\n",
6414 i);
6415 }
6416
6417 if (tid_init(&adapter->tids) < 0) {
6418 dev_warn(&pdev->dev, "could not allocate TID table, "
6419 "continuing\n");
6420 adapter->params.offload = 0;
6421 } else {
6422 adapter->tc_u32 = cxgb4_init_tc_u32(adapter);
6423 if (!adapter->tc_u32)
6424 dev_warn(&pdev->dev,
6425 "could not offload tc u32, continuing\n");
6426
6427 if (cxgb4_init_tc_flower(adapter))
6428 dev_warn(&pdev->dev,
6429 "could not offload tc flower, continuing\n");
6430
6431 if (cxgb4_init_tc_mqprio(adapter))
6432 dev_warn(&pdev->dev,
6433 "could not offload tc mqprio, continuing\n");
6434
6435 if (cxgb4_init_tc_matchall(adapter))
6436 dev_warn(&pdev->dev,
6437 "could not offload tc matchall, continuing\n");
6438 }
6439
6440 if (is_offload(adapter) || is_hashfilter(adapter)) {
6441 if (t4_read_reg(adapter, LE_DB_CONFIG_A) & HASHEN_F) {
6442 u32 hash_base, hash_reg;
6443
6444 if (chip_ver <= CHELSIO_T5) {
6445 hash_reg = LE_DB_TID_HASHBASE_A;
6446 hash_base = t4_read_reg(adapter, hash_reg);
6447 adapter->tids.hash_base = hash_base / 4;
6448 } else {
6449 hash_reg = T6_LE_DB_HASH_TID_BASE_A;
6450 hash_base = t4_read_reg(adapter, hash_reg);
6451 adapter->tids.hash_base = hash_base;
6452 }
6453 }
6454 }
6455
6456 /* See what interrupts we'll be using */
6457 if (msi > 1 && enable_msix(adapter) == 0)
6458 adapter->flags |= CXGB4_USING_MSIX;
6459 else if (msi > 0 && pci_enable_msi(pdev) == 0) {
6460 adapter->flags |= CXGB4_USING_MSI;
6461 if (msi > 1)
6462 free_msix_info(adapter);
6463 }
6464
6465 /* check for PCI Express bandwidth capabiltites */
6466 pcie_print_link_status(pdev);
6467
6468 cxgb4_init_mps_ref_entries(adapter);
6469
6470 err = init_rss(adapter);
6471 if (err)
6472 goto out_free_dev;
6473
6474 err = setup_non_data_intr(adapter);
6475 if (err) {
6476 dev_err(adapter->pdev_dev,
6477 "Non Data interrupt allocation failed, err: %d\n", err);
6478 goto out_free_dev;
6479 }
6480
6481 err = setup_fw_sge_queues(adapter);
6482 if (err) {
6483 dev_err(adapter->pdev_dev,
6484 "FW sge queue allocation failed, err %d", err);
6485 goto out_free_dev;
6486 }
6487
6488 fw_attach_fail:
6489 /*
6490 * The card is now ready to go. If any errors occur during device
6491 * registration we do not fail the whole card but rather proceed only
6492 * with the ports we manage to register successfully. However we must
6493 * register at least one net device.
6494 */
6495 for_each_port(adapter, i) {
6496 pi = adap2pinfo(adapter, i);
6497 adapter->port[i]->dev_port = pi->lport;
6498 netif_set_real_num_tx_queues(adapter->port[i], pi->nqsets);
6499 netif_set_real_num_rx_queues(adapter->port[i], pi->nqsets);
6500
6501 netif_carrier_off(adapter->port[i]);
6502
6503 err = register_netdev(adapter->port[i]);
6504 if (err)
6505 break;
6506 adapter->chan_map[pi->tx_chan] = i;
6507 print_port_info(adapter->port[i]);
6508 }
6509 if (i == 0) {
6510 dev_err(&pdev->dev, "could not register any net devices\n");
6511 goto out_free_dev;
6512 }
6513 if (err) {
6514 dev_warn(&pdev->dev, "only %d net devices registered\n", i);
6515 err = 0;
6516 }
6517
6518 if (cxgb4_debugfs_root) {
6519 adapter->debugfs_root = debugfs_create_dir(pci_name(pdev),
6520 cxgb4_debugfs_root);
6521 setup_debugfs(adapter);
6522 }
6523
6524 /* PCIe EEH recovery on powerpc platforms needs fundamental reset */
6525 pdev->needs_freset = 1;
6526
6527 if (is_uld(adapter)) {
6528 mutex_lock(&uld_mutex);
6529 list_add_tail(&adapter->list_node, &adapter_list);
6530 mutex_unlock(&uld_mutex);
6531 }
6532
6533 if (!is_t4(adapter->params.chip))
6534 cxgb4_ptp_init(adapter);
6535
6536 if (IS_REACHABLE(CONFIG_THERMAL) &&
6537 !is_t4(adapter->params.chip) && (adapter->flags & CXGB4_FW_OK))
6538 cxgb4_thermal_init(adapter);
6539
6540 print_adapter_info(adapter);
6541 return 0;
6542
6543 out_free_dev:
6544 t4_free_sge_resources(adapter);
6545 free_some_resources(adapter);
6546 if (adapter->flags & CXGB4_USING_MSIX)
6547 free_msix_info(adapter);
6548 if (adapter->num_uld || adapter->num_ofld_uld)
6549 t4_uld_mem_free(adapter);
6550 out_unmap_bar:
6551 if (!is_t4(adapter->params.chip))
6552 iounmap(adapter->bar2);
6553 out_free_adapter:
6554 if (adapter->workq)
6555 destroy_workqueue(adapter->workq);
6556
6557 kfree(adapter->mbox_log);
6558 kfree(adapter);
6559 out_unmap_bar0:
6560 iounmap(regs);
6561 out_disable_device:
6562 pci_disable_pcie_error_reporting(pdev);
6563 pci_disable_device(pdev);
6564 out_release_regions:
6565 pci_release_regions(pdev);
6566 return err;
6567 }
6568
6569 static void remove_one(struct pci_dev *pdev)
6570 {
6571 struct adapter *adapter = pci_get_drvdata(pdev);
6572 struct hash_mac_addr *entry, *tmp;
6573
6574 if (!adapter) {
6575 pci_release_regions(pdev);
6576 return;
6577 }
6578
6579 /* If we allocated filters, free up state associated with any
6580 * valid filters ...
6581 */
6582 clear_all_filters(adapter);
6583
6584 adapter->flags |= CXGB4_SHUTTING_DOWN;
6585
6586 if (adapter->pf == 4) {
6587 int i;
6588
6589 /* Tear down per-adapter Work Queue first since it can contain
6590 * references to our adapter data structure.
6591 */
6592 destroy_workqueue(adapter->workq);
6593
6594 if (is_uld(adapter)) {
6595 detach_ulds(adapter);
6596 t4_uld_clean_up(adapter);
6597 }
6598
6599 adap_free_hma_mem(adapter);
6600
6601 disable_interrupts(adapter);
6602
6603 cxgb4_free_mps_ref_entries(adapter);
6604
6605 for_each_port(adapter, i)
6606 if (adapter->port[i]->reg_state == NETREG_REGISTERED)
6607 unregister_netdev(adapter->port[i]);
6608
6609 debugfs_remove_recursive(adapter->debugfs_root);
6610
6611 if (!is_t4(adapter->params.chip))
6612 cxgb4_ptp_stop(adapter);
6613 if (IS_REACHABLE(CONFIG_THERMAL))
6614 cxgb4_thermal_remove(adapter);
6615
6616 if (adapter->flags & CXGB4_FULL_INIT_DONE)
6617 cxgb_down(adapter);
6618
6619 if (adapter->flags & CXGB4_USING_MSIX)
6620 free_msix_info(adapter);
6621 if (adapter->num_uld || adapter->num_ofld_uld)
6622 t4_uld_mem_free(adapter);
6623 free_some_resources(adapter);
6624 list_for_each_entry_safe(entry, tmp, &adapter->mac_hlist,
6625 list) {
6626 list_del(&entry->list);
6627 kfree(entry);
6628 }
6629
6630 #if IS_ENABLED(CONFIG_IPV6)
6631 t4_cleanup_clip_tbl(adapter);
6632 #endif
6633 if (!is_t4(adapter->params.chip))
6634 iounmap(adapter->bar2);
6635 }
6636 #ifdef CONFIG_PCI_IOV
6637 else {
6638 cxgb4_iov_configure(adapter->pdev, 0);
6639 }
6640 #endif
6641 iounmap(adapter->regs);
6642 pci_disable_pcie_error_reporting(pdev);
6643 if ((adapter->flags & CXGB4_DEV_ENABLED)) {
6644 pci_disable_device(pdev);
6645 adapter->flags &= ~CXGB4_DEV_ENABLED;
6646 }
6647 pci_release_regions(pdev);
6648 kfree(adapter->mbox_log);
6649 synchronize_rcu();
6650 kfree(adapter);
6651 }
6652
6653 /* "Shutdown" quiesces the device, stopping Ingress Packet and Interrupt
6654 * delivery. This is essentially a stripped down version of the PCI remove()
6655 * function where we do the minimal amount of work necessary to shutdown any
6656 * further activity.
6657 */
6658 static void shutdown_one(struct pci_dev *pdev)
6659 {
6660 struct adapter *adapter = pci_get_drvdata(pdev);
6661
6662 /* As with remove_one() above (see extended comment), we only want do
6663 * do cleanup on PCI Devices which went all the way through init_one()
6664 * ...
6665 */
6666 if (!adapter) {
6667 pci_release_regions(pdev);
6668 return;
6669 }
6670
6671 adapter->flags |= CXGB4_SHUTTING_DOWN;
6672
6673 if (adapter->pf == 4) {
6674 int i;
6675
6676 for_each_port(adapter, i)
6677 if (adapter->port[i]->reg_state == NETREG_REGISTERED)
6678 cxgb_close(adapter->port[i]);
6679
6680 if (is_uld(adapter)) {
6681 detach_ulds(adapter);
6682 t4_uld_clean_up(adapter);
6683 }
6684
6685 disable_interrupts(adapter);
6686 disable_msi(adapter);
6687
6688 t4_sge_stop(adapter);
6689 if (adapter->flags & CXGB4_FW_OK)
6690 t4_fw_bye(adapter, adapter->mbox);
6691 }
6692 }
6693
6694 static struct pci_driver cxgb4_driver = {
6695 .name = KBUILD_MODNAME,
6696 .id_table = cxgb4_pci_tbl,
6697 .probe = init_one,
6698 .remove = remove_one,
6699 .shutdown = shutdown_one,
6700 #ifdef CONFIG_PCI_IOV
6701 .sriov_configure = cxgb4_iov_configure,
6702 #endif
6703 .err_handler = &cxgb4_eeh,
6704 };
6705
6706 static int __init cxgb4_init_module(void)
6707 {
6708 int ret;
6709
6710 cxgb4_debugfs_root = debugfs_create_dir(KBUILD_MODNAME, NULL);
6711
6712 ret = pci_register_driver(&cxgb4_driver);
6713 if (ret < 0)
6714 goto err_pci;
6715
6716 #if IS_ENABLED(CONFIG_IPV6)
6717 if (!inet6addr_registered) {
6718 ret = register_inet6addr_notifier(&cxgb4_inet6addr_notifier);
6719 if (ret)
6720 pci_unregister_driver(&cxgb4_driver);
6721 else
6722 inet6addr_registered = true;
6723 }
6724 #endif
6725
6726 if (ret == 0)
6727 return ret;
6728
6729 err_pci:
6730 debugfs_remove(cxgb4_debugfs_root);
6731
6732 return ret;
6733 }
6734
6735 static void __exit cxgb4_cleanup_module(void)
6736 {
6737 #if IS_ENABLED(CONFIG_IPV6)
6738 if (inet6addr_registered) {
6739 unregister_inet6addr_notifier(&cxgb4_inet6addr_notifier);
6740 inet6addr_registered = false;
6741 }
6742 #endif
6743 pci_unregister_driver(&cxgb4_driver);
6744 debugfs_remove(cxgb4_debugfs_root); /* NULL ok */
6745 }
6746
6747 module_init(cxgb4_init_module);
6748 module_exit(cxgb4_cleanup_module);
Linux with added FPC-III support