1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * EP93xx ethernet network device driver
4 * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
5 * Dedicated to Marija Kulikova.
8 #define pr_fmt(fmt) KBUILD_MODNAME ":%s: " fmt, __func__
10 #include <linux/dma-mapping.h>
11 #include <linux/module.h>
12 #include <linux/kernel.h>
13 #include <linux/netdevice.h>
14 #include <linux/mii.h>
15 #include <linux/etherdevice.h>
16 #include <linux/ethtool.h>
17 #include <linux/interrupt.h>
18 #include <linux/moduleparam.h>
19 #include <linux/platform_device.h>
20 #include <linux/delay.h>
22 #include <linux/slab.h>
24 #include <linux/platform_data/eth-ep93xx.h>
26 #define DRV_MODULE_NAME "ep93xx-eth"
27 #define DRV_MODULE_VERSION "0.1"
29 #define RX_QUEUE_ENTRIES 64
30 #define TX_QUEUE_ENTRIES 8
32 #define MAX_PKT_SIZE 2044
33 #define PKT_BUF_SIZE 2048
35 #define REG_RXCTL 0x0000
36 #define REG_RXCTL_DEFAULT 0x00073800
37 #define REG_TXCTL 0x0004
38 #define REG_TXCTL_ENABLE 0x00000001
39 #define REG_MIICMD 0x0010
40 #define REG_MIICMD_READ 0x00008000
41 #define REG_MIICMD_WRITE 0x00004000
42 #define REG_MIIDATA 0x0014
43 #define REG_MIISTS 0x0018
44 #define REG_MIISTS_BUSY 0x00000001
45 #define REG_SELFCTL 0x0020
46 #define REG_SELFCTL_RESET 0x00000001
47 #define REG_INTEN 0x0024
48 #define REG_INTEN_TX 0x00000008
49 #define REG_INTEN_RX 0x00000007
50 #define REG_INTSTSP 0x0028
51 #define REG_INTSTS_TX 0x00000008
52 #define REG_INTSTS_RX 0x00000004
53 #define REG_INTSTSC 0x002c
54 #define REG_AFP 0x004c
55 #define REG_INDAD0 0x0050
56 #define REG_INDAD1 0x0051
57 #define REG_INDAD2 0x0052
58 #define REG_INDAD3 0x0053
59 #define REG_INDAD4 0x0054
60 #define REG_INDAD5 0x0055
61 #define REG_GIINTMSK 0x0064
62 #define REG_GIINTMSK_ENABLE 0x00008000
63 #define REG_BMCTL 0x0080
64 #define REG_BMCTL_ENABLE_TX 0x00000100
65 #define REG_BMCTL_ENABLE_RX 0x00000001
66 #define REG_BMSTS 0x0084
67 #define REG_BMSTS_RX_ACTIVE 0x00000008
68 #define REG_RXDQBADD 0x0090
69 #define REG_RXDQBLEN 0x0094
70 #define REG_RXDCURADD 0x0098
71 #define REG_RXDENQ 0x009c
72 #define REG_RXSTSQBADD 0x00a0
73 #define REG_RXSTSQBLEN 0x00a4
74 #define REG_RXSTSQCURADD 0x00a8
75 #define REG_RXSTSENQ 0x00ac
76 #define REG_TXDQBADD 0x00b0
77 #define REG_TXDQBLEN 0x00b4
78 #define REG_TXDQCURADD 0x00b8
79 #define REG_TXDENQ 0x00bc
80 #define REG_TXSTSQBADD 0x00c0
81 #define REG_TXSTSQBLEN 0x00c4
82 #define REG_TXSTSQCURADD 0x00c8
83 #define REG_MAXFRMLEN 0x00e8
91 #define RDESC1_NSOF 0x80000000
92 #define RDESC1_BUFFER_INDEX 0x7fff0000
93 #define RDESC1_BUFFER_LENGTH 0x0000ffff
101 #define RSTAT0_RFP 0x80000000
102 #define RSTAT0_RWE 0x40000000
103 #define RSTAT0_EOF 0x20000000
104 #define RSTAT0_EOB 0x10000000
105 #define RSTAT0_AM 0x00c00000
106 #define RSTAT0_RX_ERR 0x00200000
107 #define RSTAT0_OE 0x00100000
108 #define RSTAT0_FE 0x00080000
109 #define RSTAT0_RUNT 0x00040000
110 #define RSTAT0_EDATA 0x00020000
111 #define RSTAT0_CRCE 0x00010000
112 #define RSTAT0_CRCI 0x00008000
113 #define RSTAT0_HTI 0x00003f00
114 #define RSTAT1_RFP 0x80000000
115 #define RSTAT1_BUFFER_INDEX 0x7fff0000
116 #define RSTAT1_FRAME_LENGTH 0x0000ffff
124 #define TDESC1_EOF 0x80000000
125 #define TDESC1_BUFFER_INDEX 0x7fff0000
126 #define TDESC1_BUFFER_ABORT 0x00008000
127 #define TDESC1_BUFFER_LENGTH 0x00000fff
134 #define TSTAT0_TXFP 0x80000000
135 #define TSTAT0_TXWE 0x40000000
136 #define TSTAT0_FA 0x20000000
137 #define TSTAT0_LCRS 0x10000000
138 #define TSTAT0_OW 0x04000000
139 #define TSTAT0_TXU 0x02000000
140 #define TSTAT0_ECOLL 0x01000000
141 #define TSTAT0_NCOLL 0x001f0000
142 #define TSTAT0_BUFFER_INDEX 0x00007fff
146 struct ep93xx_rdesc rdesc
[RX_QUEUE_ENTRIES
];
147 struct ep93xx_tdesc tdesc
[TX_QUEUE_ENTRIES
];
148 struct ep93xx_rstat rstat
[RX_QUEUE_ENTRIES
];
149 struct ep93xx_tstat tstat
[TX_QUEUE_ENTRIES
];
154 struct resource
*res
;
155 void __iomem
*base_addr
;
158 struct ep93xx_descs
*descs
;
159 dma_addr_t descs_dma_addr
;
161 void *rx_buf
[RX_QUEUE_ENTRIES
];
162 void *tx_buf
[TX_QUEUE_ENTRIES
];
165 unsigned int rx_pointer
;
166 unsigned int tx_clean_pointer
;
167 unsigned int tx_pointer
;
168 spinlock_t tx_pending_lock
;
169 unsigned int tx_pending
;
171 struct net_device
*dev
;
172 struct napi_struct napi
;
174 struct mii_if_info mii
;
178 #define rdb(ep, off) __raw_readb((ep)->base_addr + (off))
179 #define rdw(ep, off) __raw_readw((ep)->base_addr + (off))
180 #define rdl(ep, off) __raw_readl((ep)->base_addr + (off))
181 #define wrb(ep, off, val) __raw_writeb((val), (ep)->base_addr + (off))
182 #define wrw(ep, off, val) __raw_writew((val), (ep)->base_addr + (off))
183 #define wrl(ep, off, val) __raw_writel((val), (ep)->base_addr + (off))
185 static int ep93xx_mdio_read(struct net_device
*dev
, int phy_id
, int reg
)
187 struct ep93xx_priv
*ep
= netdev_priv(dev
);
191 wrl(ep
, REG_MIICMD
, REG_MIICMD_READ
| (phy_id
<< 5) | reg
);
193 for (i
= 0; i
< 10; i
++) {
194 if ((rdl(ep
, REG_MIISTS
) & REG_MIISTS_BUSY
) == 0)
200 pr_info("mdio read timed out\n");
203 data
= rdl(ep
, REG_MIIDATA
);
209 static void ep93xx_mdio_write(struct net_device
*dev
, int phy_id
, int reg
, int data
)
211 struct ep93xx_priv
*ep
= netdev_priv(dev
);
214 wrl(ep
, REG_MIIDATA
, data
);
215 wrl(ep
, REG_MIICMD
, REG_MIICMD_WRITE
| (phy_id
<< 5) | reg
);
217 for (i
= 0; i
< 10; i
++) {
218 if ((rdl(ep
, REG_MIISTS
) & REG_MIISTS_BUSY
) == 0)
224 pr_info("mdio write timed out\n");
227 static int ep93xx_rx(struct net_device
*dev
, int budget
)
229 struct ep93xx_priv
*ep
= netdev_priv(dev
);
232 while (processed
< budget
) {
234 struct ep93xx_rstat
*rstat
;
240 entry
= ep
->rx_pointer
;
241 rstat
= ep
->descs
->rstat
+ entry
;
243 rstat0
= rstat
->rstat0
;
244 rstat1
= rstat
->rstat1
;
245 if (!(rstat0
& RSTAT0_RFP
) || !(rstat1
& RSTAT1_RFP
))
251 if (!(rstat0
& RSTAT0_EOF
))
252 pr_crit("not end-of-frame %.8x %.8x\n", rstat0
, rstat1
);
253 if (!(rstat0
& RSTAT0_EOB
))
254 pr_crit("not end-of-buffer %.8x %.8x\n", rstat0
, rstat1
);
255 if ((rstat1
& RSTAT1_BUFFER_INDEX
) >> 16 != entry
)
256 pr_crit("entry mismatch %.8x %.8x\n", rstat0
, rstat1
);
258 if (!(rstat0
& RSTAT0_RWE
)) {
259 dev
->stats
.rx_errors
++;
260 if (rstat0
& RSTAT0_OE
)
261 dev
->stats
.rx_fifo_errors
++;
262 if (rstat0
& RSTAT0_FE
)
263 dev
->stats
.rx_frame_errors
++;
264 if (rstat0
& (RSTAT0_RUNT
| RSTAT0_EDATA
))
265 dev
->stats
.rx_length_errors
++;
266 if (rstat0
& RSTAT0_CRCE
)
267 dev
->stats
.rx_crc_errors
++;
271 length
= rstat1
& RSTAT1_FRAME_LENGTH
;
272 if (length
> MAX_PKT_SIZE
) {
273 pr_notice("invalid length %.8x %.8x\n", rstat0
, rstat1
);
278 if (rstat0
& RSTAT0_CRCI
)
281 skb
= netdev_alloc_skb(dev
, length
+ 2);
282 if (likely(skb
!= NULL
)) {
283 struct ep93xx_rdesc
*rxd
= &ep
->descs
->rdesc
[entry
];
285 dma_sync_single_for_cpu(dev
->dev
.parent
, rxd
->buf_addr
,
286 length
, DMA_FROM_DEVICE
);
287 skb_copy_to_linear_data(skb
, ep
->rx_buf
[entry
], length
);
288 dma_sync_single_for_device(dev
->dev
.parent
,
289 rxd
->buf_addr
, length
,
291 skb_put(skb
, length
);
292 skb
->protocol
= eth_type_trans(skb
, dev
);
294 napi_gro_receive(&ep
->napi
, skb
);
296 dev
->stats
.rx_packets
++;
297 dev
->stats
.rx_bytes
+= length
;
299 dev
->stats
.rx_dropped
++;
303 ep
->rx_pointer
= (entry
+ 1) & (RX_QUEUE_ENTRIES
- 1);
310 static int ep93xx_poll(struct napi_struct
*napi
, int budget
)
312 struct ep93xx_priv
*ep
= container_of(napi
, struct ep93xx_priv
, napi
);
313 struct net_device
*dev
= ep
->dev
;
316 rx
= ep93xx_rx(dev
, budget
);
317 if (rx
< budget
&& napi_complete_done(napi
, rx
)) {
318 spin_lock_irq(&ep
->rx_lock
);
319 wrl(ep
, REG_INTEN
, REG_INTEN_TX
| REG_INTEN_RX
);
320 spin_unlock_irq(&ep
->rx_lock
);
324 wrw(ep
, REG_RXDENQ
, rx
);
325 wrw(ep
, REG_RXSTSENQ
, rx
);
331 static netdev_tx_t
ep93xx_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
333 struct ep93xx_priv
*ep
= netdev_priv(dev
);
334 struct ep93xx_tdesc
*txd
;
337 if (unlikely(skb
->len
> MAX_PKT_SIZE
)) {
338 dev
->stats
.tx_dropped
++;
343 entry
= ep
->tx_pointer
;
344 ep
->tx_pointer
= (ep
->tx_pointer
+ 1) & (TX_QUEUE_ENTRIES
- 1);
346 txd
= &ep
->descs
->tdesc
[entry
];
348 txd
->tdesc1
= TDESC1_EOF
| (entry
<< 16) | (skb
->len
& 0xfff);
349 dma_sync_single_for_cpu(dev
->dev
.parent
, txd
->buf_addr
, skb
->len
,
351 skb_copy_and_csum_dev(skb
, ep
->tx_buf
[entry
]);
352 dma_sync_single_for_device(dev
->dev
.parent
, txd
->buf_addr
, skb
->len
,
356 spin_lock_irq(&ep
->tx_pending_lock
);
358 if (ep
->tx_pending
== TX_QUEUE_ENTRIES
)
359 netif_stop_queue(dev
);
360 spin_unlock_irq(&ep
->tx_pending_lock
);
362 wrl(ep
, REG_TXDENQ
, 1);
367 static void ep93xx_tx_complete(struct net_device
*dev
)
369 struct ep93xx_priv
*ep
= netdev_priv(dev
);
374 spin_lock(&ep
->tx_pending_lock
);
377 struct ep93xx_tstat
*tstat
;
380 entry
= ep
->tx_clean_pointer
;
381 tstat
= ep
->descs
->tstat
+ entry
;
383 tstat0
= tstat
->tstat0
;
384 if (!(tstat0
& TSTAT0_TXFP
))
389 if (tstat0
& TSTAT0_FA
)
390 pr_crit("frame aborted %.8x\n", tstat0
);
391 if ((tstat0
& TSTAT0_BUFFER_INDEX
) != entry
)
392 pr_crit("entry mismatch %.8x\n", tstat0
);
394 if (tstat0
& TSTAT0_TXWE
) {
395 int length
= ep
->descs
->tdesc
[entry
].tdesc1
& 0xfff;
397 dev
->stats
.tx_packets
++;
398 dev
->stats
.tx_bytes
+= length
;
400 dev
->stats
.tx_errors
++;
403 if (tstat0
& TSTAT0_OW
)
404 dev
->stats
.tx_window_errors
++;
405 if (tstat0
& TSTAT0_TXU
)
406 dev
->stats
.tx_fifo_errors
++;
407 dev
->stats
.collisions
+= (tstat0
>> 16) & 0x1f;
409 ep
->tx_clean_pointer
= (entry
+ 1) & (TX_QUEUE_ENTRIES
- 1);
410 if (ep
->tx_pending
== TX_QUEUE_ENTRIES
)
414 spin_unlock(&ep
->tx_pending_lock
);
417 netif_wake_queue(dev
);
420 static irqreturn_t
ep93xx_irq(int irq
, void *dev_id
)
422 struct net_device
*dev
= dev_id
;
423 struct ep93xx_priv
*ep
= netdev_priv(dev
);
426 status
= rdl(ep
, REG_INTSTSC
);
430 if (status
& REG_INTSTS_RX
) {
431 spin_lock(&ep
->rx_lock
);
432 if (likely(napi_schedule_prep(&ep
->napi
))) {
433 wrl(ep
, REG_INTEN
, REG_INTEN_TX
);
434 __napi_schedule(&ep
->napi
);
436 spin_unlock(&ep
->rx_lock
);
439 if (status
& REG_INTSTS_TX
)
440 ep93xx_tx_complete(dev
);
445 static void ep93xx_free_buffers(struct ep93xx_priv
*ep
)
447 struct device
*dev
= ep
->dev
->dev
.parent
;
453 for (i
= 0; i
< RX_QUEUE_ENTRIES
; i
++) {
456 d
= ep
->descs
->rdesc
[i
].buf_addr
;
458 dma_unmap_single(dev
, d
, PKT_BUF_SIZE
, DMA_FROM_DEVICE
);
460 kfree(ep
->rx_buf
[i
]);
463 for (i
= 0; i
< TX_QUEUE_ENTRIES
; i
++) {
466 d
= ep
->descs
->tdesc
[i
].buf_addr
;
468 dma_unmap_single(dev
, d
, PKT_BUF_SIZE
, DMA_TO_DEVICE
);
470 kfree(ep
->tx_buf
[i
]);
473 dma_free_coherent(dev
, sizeof(struct ep93xx_descs
), ep
->descs
,
478 static int ep93xx_alloc_buffers(struct ep93xx_priv
*ep
)
480 struct device
*dev
= ep
->dev
->dev
.parent
;
483 ep
->descs
= dma_alloc_coherent(dev
, sizeof(struct ep93xx_descs
),
484 &ep
->descs_dma_addr
, GFP_KERNEL
);
485 if (ep
->descs
== NULL
)
488 for (i
= 0; i
< RX_QUEUE_ENTRIES
; i
++) {
492 buf
= kmalloc(PKT_BUF_SIZE
, GFP_KERNEL
);
496 d
= dma_map_single(dev
, buf
, PKT_BUF_SIZE
, DMA_FROM_DEVICE
);
497 if (dma_mapping_error(dev
, d
)) {
503 ep
->descs
->rdesc
[i
].buf_addr
= d
;
504 ep
->descs
->rdesc
[i
].rdesc1
= (i
<< 16) | PKT_BUF_SIZE
;
507 for (i
= 0; i
< TX_QUEUE_ENTRIES
; i
++) {
511 buf
= kmalloc(PKT_BUF_SIZE
, GFP_KERNEL
);
515 d
= dma_map_single(dev
, buf
, PKT_BUF_SIZE
, DMA_TO_DEVICE
);
516 if (dma_mapping_error(dev
, d
)) {
522 ep
->descs
->tdesc
[i
].buf_addr
= d
;
528 ep93xx_free_buffers(ep
);
532 static int ep93xx_start_hw(struct net_device
*dev
)
534 struct ep93xx_priv
*ep
= netdev_priv(dev
);
538 wrl(ep
, REG_SELFCTL
, REG_SELFCTL_RESET
);
539 for (i
= 0; i
< 10; i
++) {
540 if ((rdl(ep
, REG_SELFCTL
) & REG_SELFCTL_RESET
) == 0)
546 pr_crit("hw failed to reset\n");
550 wrl(ep
, REG_SELFCTL
, ((ep
->mdc_divisor
- 1) << 9));
552 /* Does the PHY support preamble suppress? */
553 if ((ep93xx_mdio_read(dev
, ep
->mii
.phy_id
, MII_BMSR
) & 0x0040) != 0)
554 wrl(ep
, REG_SELFCTL
, ((ep
->mdc_divisor
- 1) << 9) | (1 << 8));
556 /* Receive descriptor ring. */
557 addr
= ep
->descs_dma_addr
+ offsetof(struct ep93xx_descs
, rdesc
);
558 wrl(ep
, REG_RXDQBADD
, addr
);
559 wrl(ep
, REG_RXDCURADD
, addr
);
560 wrw(ep
, REG_RXDQBLEN
, RX_QUEUE_ENTRIES
* sizeof(struct ep93xx_rdesc
));
562 /* Receive status ring. */
563 addr
= ep
->descs_dma_addr
+ offsetof(struct ep93xx_descs
, rstat
);
564 wrl(ep
, REG_RXSTSQBADD
, addr
);
565 wrl(ep
, REG_RXSTSQCURADD
, addr
);
566 wrw(ep
, REG_RXSTSQBLEN
, RX_QUEUE_ENTRIES
* sizeof(struct ep93xx_rstat
));
568 /* Transmit descriptor ring. */
569 addr
= ep
->descs_dma_addr
+ offsetof(struct ep93xx_descs
, tdesc
);
570 wrl(ep
, REG_TXDQBADD
, addr
);
571 wrl(ep
, REG_TXDQCURADD
, addr
);
572 wrw(ep
, REG_TXDQBLEN
, TX_QUEUE_ENTRIES
* sizeof(struct ep93xx_tdesc
));
574 /* Transmit status ring. */
575 addr
= ep
->descs_dma_addr
+ offsetof(struct ep93xx_descs
, tstat
);
576 wrl(ep
, REG_TXSTSQBADD
, addr
);
577 wrl(ep
, REG_TXSTSQCURADD
, addr
);
578 wrw(ep
, REG_TXSTSQBLEN
, TX_QUEUE_ENTRIES
* sizeof(struct ep93xx_tstat
));
580 wrl(ep
, REG_BMCTL
, REG_BMCTL_ENABLE_TX
| REG_BMCTL_ENABLE_RX
);
581 wrl(ep
, REG_INTEN
, REG_INTEN_TX
| REG_INTEN_RX
);
582 wrl(ep
, REG_GIINTMSK
, 0);
584 for (i
= 0; i
< 10; i
++) {
585 if ((rdl(ep
, REG_BMSTS
) & REG_BMSTS_RX_ACTIVE
) != 0)
591 pr_crit("hw failed to start\n");
595 wrl(ep
, REG_RXDENQ
, RX_QUEUE_ENTRIES
);
596 wrl(ep
, REG_RXSTSENQ
, RX_QUEUE_ENTRIES
);
598 wrb(ep
, REG_INDAD0
, dev
->dev_addr
[0]);
599 wrb(ep
, REG_INDAD1
, dev
->dev_addr
[1]);
600 wrb(ep
, REG_INDAD2
, dev
->dev_addr
[2]);
601 wrb(ep
, REG_INDAD3
, dev
->dev_addr
[3]);
602 wrb(ep
, REG_INDAD4
, dev
->dev_addr
[4]);
603 wrb(ep
, REG_INDAD5
, dev
->dev_addr
[5]);
606 wrl(ep
, REG_MAXFRMLEN
, (MAX_PKT_SIZE
<< 16) | MAX_PKT_SIZE
);
608 wrl(ep
, REG_RXCTL
, REG_RXCTL_DEFAULT
);
609 wrl(ep
, REG_TXCTL
, REG_TXCTL_ENABLE
);
614 static void ep93xx_stop_hw(struct net_device
*dev
)
616 struct ep93xx_priv
*ep
= netdev_priv(dev
);
619 wrl(ep
, REG_SELFCTL
, REG_SELFCTL_RESET
);
620 for (i
= 0; i
< 10; i
++) {
621 if ((rdl(ep
, REG_SELFCTL
) & REG_SELFCTL_RESET
) == 0)
627 pr_crit("hw failed to reset\n");
630 static int ep93xx_open(struct net_device
*dev
)
632 struct ep93xx_priv
*ep
= netdev_priv(dev
);
635 if (ep93xx_alloc_buffers(ep
))
638 napi_enable(&ep
->napi
);
640 if (ep93xx_start_hw(dev
)) {
641 napi_disable(&ep
->napi
);
642 ep93xx_free_buffers(ep
);
646 spin_lock_init(&ep
->rx_lock
);
648 ep
->tx_clean_pointer
= 0;
650 spin_lock_init(&ep
->tx_pending_lock
);
653 err
= request_irq(ep
->irq
, ep93xx_irq
, IRQF_SHARED
, dev
->name
, dev
);
655 napi_disable(&ep
->napi
);
657 ep93xx_free_buffers(ep
);
661 wrl(ep
, REG_GIINTMSK
, REG_GIINTMSK_ENABLE
);
663 netif_start_queue(dev
);
668 static int ep93xx_close(struct net_device
*dev
)
670 struct ep93xx_priv
*ep
= netdev_priv(dev
);
672 napi_disable(&ep
->napi
);
673 netif_stop_queue(dev
);
675 wrl(ep
, REG_GIINTMSK
, 0);
676 free_irq(ep
->irq
, dev
);
678 ep93xx_free_buffers(ep
);
683 static int ep93xx_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
685 struct ep93xx_priv
*ep
= netdev_priv(dev
);
686 struct mii_ioctl_data
*data
= if_mii(ifr
);
688 return generic_mii_ioctl(&ep
->mii
, data
, cmd
, NULL
);
691 static void ep93xx_get_drvinfo(struct net_device
*dev
, struct ethtool_drvinfo
*info
)
693 strlcpy(info
->driver
, DRV_MODULE_NAME
, sizeof(info
->driver
));
694 strlcpy(info
->version
, DRV_MODULE_VERSION
, sizeof(info
->version
));
697 static int ep93xx_get_link_ksettings(struct net_device
*dev
,
698 struct ethtool_link_ksettings
*cmd
)
700 struct ep93xx_priv
*ep
= netdev_priv(dev
);
702 mii_ethtool_get_link_ksettings(&ep
->mii
, cmd
);
707 static int ep93xx_set_link_ksettings(struct net_device
*dev
,
708 const struct ethtool_link_ksettings
*cmd
)
710 struct ep93xx_priv
*ep
= netdev_priv(dev
);
711 return mii_ethtool_set_link_ksettings(&ep
->mii
, cmd
);
714 static int ep93xx_nway_reset(struct net_device
*dev
)
716 struct ep93xx_priv
*ep
= netdev_priv(dev
);
717 return mii_nway_restart(&ep
->mii
);
720 static u32
ep93xx_get_link(struct net_device
*dev
)
722 struct ep93xx_priv
*ep
= netdev_priv(dev
);
723 return mii_link_ok(&ep
->mii
);
726 static const struct ethtool_ops ep93xx_ethtool_ops
= {
727 .get_drvinfo
= ep93xx_get_drvinfo
,
728 .nway_reset
= ep93xx_nway_reset
,
729 .get_link
= ep93xx_get_link
,
730 .get_link_ksettings
= ep93xx_get_link_ksettings
,
731 .set_link_ksettings
= ep93xx_set_link_ksettings
,
734 static const struct net_device_ops ep93xx_netdev_ops
= {
735 .ndo_open
= ep93xx_open
,
736 .ndo_stop
= ep93xx_close
,
737 .ndo_start_xmit
= ep93xx_xmit
,
738 .ndo_do_ioctl
= ep93xx_ioctl
,
739 .ndo_validate_addr
= eth_validate_addr
,
740 .ndo_set_mac_address
= eth_mac_addr
,
743 static struct net_device
*ep93xx_dev_alloc(struct ep93xx_eth_data
*data
)
745 struct net_device
*dev
;
747 dev
= alloc_etherdev(sizeof(struct ep93xx_priv
));
751 memcpy(dev
->dev_addr
, data
->dev_addr
, ETH_ALEN
);
753 dev
->ethtool_ops
= &ep93xx_ethtool_ops
;
754 dev
->netdev_ops
= &ep93xx_netdev_ops
;
756 dev
->features
|= NETIF_F_SG
| NETIF_F_HW_CSUM
;
762 static int ep93xx_eth_remove(struct platform_device
*pdev
)
764 struct net_device
*dev
;
765 struct ep93xx_priv
*ep
;
766 struct resource
*mem
;
768 dev
= platform_get_drvdata(pdev
);
772 ep
= netdev_priv(dev
);
774 /* @@@ Force down. */
775 unregister_netdev(dev
);
776 ep93xx_free_buffers(ep
);
778 if (ep
->base_addr
!= NULL
)
779 iounmap(ep
->base_addr
);
781 if (ep
->res
!= NULL
) {
782 mem
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
783 release_mem_region(mem
->start
, resource_size(mem
));
791 static int ep93xx_eth_probe(struct platform_device
*pdev
)
793 struct ep93xx_eth_data
*data
;
794 struct net_device
*dev
;
795 struct ep93xx_priv
*ep
;
796 struct resource
*mem
;
802 data
= dev_get_platdata(&pdev
->dev
);
804 mem
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
805 irq
= platform_get_irq(pdev
, 0);
809 dev
= ep93xx_dev_alloc(data
);
814 ep
= netdev_priv(dev
);
816 SET_NETDEV_DEV(dev
, &pdev
->dev
);
817 netif_napi_add(dev
, &ep
->napi
, ep93xx_poll
, 64);
819 platform_set_drvdata(pdev
, dev
);
821 ep
->res
= request_mem_region(mem
->start
, resource_size(mem
),
822 dev_name(&pdev
->dev
));
823 if (ep
->res
== NULL
) {
824 dev_err(&pdev
->dev
, "Could not reserve memory region\n");
829 ep
->base_addr
= ioremap(mem
->start
, resource_size(mem
));
830 if (ep
->base_addr
== NULL
) {
831 dev_err(&pdev
->dev
, "Failed to ioremap ethernet registers\n");
837 ep
->mii
.phy_id
= data
->phy_id
;
838 ep
->mii
.phy_id_mask
= 0x1f;
839 ep
->mii
.reg_num_mask
= 0x1f;
841 ep
->mii
.mdio_read
= ep93xx_mdio_read
;
842 ep
->mii
.mdio_write
= ep93xx_mdio_write
;
843 ep
->mdc_divisor
= 40; /* Max HCLK 100 MHz, min MDIO clk 2.5 MHz. */
845 if (is_zero_ether_addr(dev
->dev_addr
))
846 eth_hw_addr_random(dev
);
848 err
= register_netdev(dev
);
850 dev_err(&pdev
->dev
, "Failed to register netdev\n");
854 printk(KERN_INFO
"%s: ep93xx on-chip ethernet, IRQ %d, %pM\n",
855 dev
->name
, ep
->irq
, dev
->dev_addr
);
860 ep93xx_eth_remove(pdev
);
865 static struct platform_driver ep93xx_eth_driver
= {
866 .probe
= ep93xx_eth_probe
,
867 .remove
= ep93xx_eth_remove
,
869 .name
= "ep93xx-eth",
873 module_platform_driver(ep93xx_eth_driver
);
875 MODULE_LICENSE("GPL");
876 MODULE_ALIAS("platform:ep93xx-eth");