?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
treewide: remove redundant IS_ERR() before error code check
[linux/fpc-iii.git] / drivers / net / ethernet / cortina / gemini.c
blobf30fa8e6ef80b38fe3a5b24ae0e0674f783f6fb4
1 // SPDX-License-Identifier: GPL-2.0
2 /* Ethernet device driver for Cortina Systems Gemini SoC
3 * Also known as the StorLink SL3512 and SL3516 (SL351x) or Lepus
4 * Net Engine and Gigabit Ethernet MAC (GMAC)
5 * This hardware contains a TCP Offload Engine (TOE) but currently the
6 * driver does not make use of it.
7 *
8 * Authors:
9 * Linus Walleij <linus.walleij@linaro.org>
10 * Tobias Waldvogel <tobias.waldvogel@gmail.com> (OpenWRT)
11 * Michał Mirosław <mirq-linux@rere.qmqm.pl>
12 * Paulius Zaleckas <paulius.zaleckas@gmail.com>
13 * Giuseppe De Robertis <Giuseppe.DeRobertis@ba.infn.it>
14 * Gary Chen & Ch Hsu Storlink Semiconductor
15 */
16 #include <linux/kernel.h>
17 #include <linux/init.h>
18 #include <linux/module.h>
19 #include <linux/platform_device.h>
20 #include <linux/spinlock.h>
21 #include <linux/slab.h>
22 #include <linux/dma-mapping.h>
23 #include <linux/cache.h>
24 #include <linux/interrupt.h>
25 #include <linux/reset.h>
26 #include <linux/clk.h>
27 #include <linux/of.h>
28 #include <linux/of_mdio.h>
29 #include <linux/of_net.h>
30 #include <linux/of_platform.h>
31 #include <linux/etherdevice.h>
32 #include <linux/if_vlan.h>
33 #include <linux/skbuff.h>
34 #include <linux/phy.h>
35 #include <linux/crc32.h>
36 #include <linux/ethtool.h>
37 #include <linux/tcp.h>
38 #include <linux/u64_stats_sync.h>
39
40 #include <linux/in.h>
41 #include <linux/ip.h>
42 #include <linux/ipv6.h>
43
44 #include "gemini.h"
45
46 #define DRV_NAME "gmac-gemini"
47 #define DRV_VERSION "1.0"
48
49 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
50 static int debug = -1;
51 module_param(debug, int, 0);
52 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
53
54 #define HSIZE_8 0x00
55 #define HSIZE_16 0x01
56 #define HSIZE_32 0x02
57
58 #define HBURST_SINGLE 0x00
59 #define HBURST_INCR 0x01
60 #define HBURST_INCR4 0x02
61 #define HBURST_INCR8 0x03
62
63 #define HPROT_DATA_CACHE BIT(0)
64 #define HPROT_PRIVILIGED BIT(1)
65 #define HPROT_BUFFERABLE BIT(2)
66 #define HPROT_CACHABLE BIT(3)
67
68 #define DEFAULT_RX_COALESCE_NSECS 0
69 #define DEFAULT_GMAC_RXQ_ORDER 9
70 #define DEFAULT_GMAC_TXQ_ORDER 8
71 #define DEFAULT_RX_BUF_ORDER 11
72 #define DEFAULT_NAPI_WEIGHT 64
73 #define TX_MAX_FRAGS 16
74 #define TX_QUEUE_NUM 1 /* max: 6 */
75 #define RX_MAX_ALLOC_ORDER 2
76
77 #define GMAC0_IRQ0_2 (GMAC0_TXDERR_INT_BIT | GMAC0_TXPERR_INT_BIT | \
78 GMAC0_RXDERR_INT_BIT | GMAC0_RXPERR_INT_BIT)
79 #define GMAC0_IRQ0_TXQ0_INTS (GMAC0_SWTQ00_EOF_INT_BIT | \
80 GMAC0_SWTQ00_FIN_INT_BIT)
81 #define GMAC0_IRQ4_8 (GMAC0_MIB_INT_BIT | GMAC0_RX_OVERRUN_INT_BIT)
82
83 #define GMAC_OFFLOAD_FEATURES (NETIF_F_SG | NETIF_F_IP_CSUM | \
84 NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM | \
85 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6)
86
87 /**
88 * struct gmac_queue_page - page buffer per-page info
89 */
90 struct gmac_queue_page {
91 struct page *page;
92 dma_addr_t mapping;
93 };
94
95 struct gmac_txq {
96 struct gmac_txdesc *ring;
97 struct sk_buff **skb;
98 unsigned int cptr;
99 unsigned int noirq_packets;
100 };
101
102 struct gemini_ethernet;
103
104 struct gemini_ethernet_port {
105 u8 id; /* 0 or 1 */
106
107 struct gemini_ethernet *geth;
108 struct net_device *netdev;
109 struct device *dev;
110 void __iomem *dma_base;
111 void __iomem *gmac_base;
112 struct clk *pclk;
113 struct reset_control *reset;
114 int irq;
115 __le32 mac_addr[3];
116
117 void __iomem *rxq_rwptr;
118 struct gmac_rxdesc *rxq_ring;
119 unsigned int rxq_order;
120
121 struct napi_struct napi;
122 struct hrtimer rx_coalesce_timer;
123 unsigned int rx_coalesce_nsecs;
124 unsigned int freeq_refill;
125 struct gmac_txq txq[TX_QUEUE_NUM];
126 unsigned int txq_order;
127 unsigned int irq_every_tx_packets;
128
129 dma_addr_t rxq_dma_base;
130 dma_addr_t txq_dma_base;
131
132 unsigned int msg_enable;
133 spinlock_t config_lock; /* Locks config register */
134
135 struct u64_stats_sync tx_stats_syncp;
136 struct u64_stats_sync rx_stats_syncp;
137 struct u64_stats_sync ir_stats_syncp;
138
139 struct rtnl_link_stats64 stats;
140 u64 hw_stats[RX_STATS_NUM];
141 u64 rx_stats[RX_STATUS_NUM];
142 u64 rx_csum_stats[RX_CHKSUM_NUM];
143 u64 rx_napi_exits;
144 u64 tx_frag_stats[TX_MAX_FRAGS];
145 u64 tx_frags_linearized;
146 u64 tx_hw_csummed;
147 };
148
149 struct gemini_ethernet {
150 struct device *dev;
151 void __iomem *base;
152 struct gemini_ethernet_port *port0;
153 struct gemini_ethernet_port *port1;
154 bool initialized;
155
156 spinlock_t irq_lock; /* Locks IRQ-related registers */
157 unsigned int freeq_order;
158 unsigned int freeq_frag_order;
159 struct gmac_rxdesc *freeq_ring;
160 dma_addr_t freeq_dma_base;
161 struct gmac_queue_page *freeq_pages;
162 unsigned int num_freeq_pages;
163 spinlock_t freeq_lock; /* Locks queue from reentrance */
164 };
165
166 #define GMAC_STATS_NUM ( \
167 RX_STATS_NUM + RX_STATUS_NUM + RX_CHKSUM_NUM + 1 + \
168 TX_MAX_FRAGS + 2)
169
170 static const char gmac_stats_strings[GMAC_STATS_NUM][ETH_GSTRING_LEN] = {
171 "GMAC_IN_DISCARDS",
172 "GMAC_IN_ERRORS",
173 "GMAC_IN_MCAST",
174 "GMAC_IN_BCAST",
175 "GMAC_IN_MAC1",
176 "GMAC_IN_MAC2",
177 "RX_STATUS_GOOD_FRAME",
178 "RX_STATUS_TOO_LONG_GOOD_CRC",
179 "RX_STATUS_RUNT_FRAME",
180 "RX_STATUS_SFD_NOT_FOUND",
181 "RX_STATUS_CRC_ERROR",
182 "RX_STATUS_TOO_LONG_BAD_CRC",
183 "RX_STATUS_ALIGNMENT_ERROR",
184 "RX_STATUS_TOO_LONG_BAD_ALIGN",
185 "RX_STATUS_RX_ERR",
186 "RX_STATUS_DA_FILTERED",
187 "RX_STATUS_BUFFER_FULL",
188 "RX_STATUS_11",
189 "RX_STATUS_12",
190 "RX_STATUS_13",
191 "RX_STATUS_14",
192 "RX_STATUS_15",
193 "RX_CHKSUM_IP_UDP_TCP_OK",
194 "RX_CHKSUM_IP_OK_ONLY",
195 "RX_CHKSUM_NONE",
196 "RX_CHKSUM_3",
197 "RX_CHKSUM_IP_ERR_UNKNOWN",
198 "RX_CHKSUM_IP_ERR",
199 "RX_CHKSUM_TCP_UDP_ERR",
200 "RX_CHKSUM_7",
201 "RX_NAPI_EXITS",
202 "TX_FRAGS[1]",
203 "TX_FRAGS[2]",
204 "TX_FRAGS[3]",
205 "TX_FRAGS[4]",
206 "TX_FRAGS[5]",
207 "TX_FRAGS[6]",
208 "TX_FRAGS[7]",
209 "TX_FRAGS[8]",
210 "TX_FRAGS[9]",
211 "TX_FRAGS[10]",
212 "TX_FRAGS[11]",
213 "TX_FRAGS[12]",
214 "TX_FRAGS[13]",
215 "TX_FRAGS[14]",
216 "TX_FRAGS[15]",
217 "TX_FRAGS[16+]",
218 "TX_FRAGS_LINEARIZED",
219 "TX_HW_CSUMMED",
220 };
221
222 static void gmac_dump_dma_state(struct net_device *netdev);
223
224 static void gmac_update_config0_reg(struct net_device *netdev,
225 u32 val, u32 vmask)
226 {
227 struct gemini_ethernet_port *port = netdev_priv(netdev);
228 unsigned long flags;
229 u32 reg;
230
231 spin_lock_irqsave(&port->config_lock, flags);
232
233 reg = readl(port->gmac_base + GMAC_CONFIG0);
234 reg = (reg & ~vmask) | val;
235 writel(reg, port->gmac_base + GMAC_CONFIG0);
236
237 spin_unlock_irqrestore(&port->config_lock, flags);
238 }
239
240 static void gmac_enable_tx_rx(struct net_device *netdev)
241 {
242 struct gemini_ethernet_port *port = netdev_priv(netdev);
243 unsigned long flags;
244 u32 reg;
245
246 spin_lock_irqsave(&port->config_lock, flags);
247
248 reg = readl(port->gmac_base + GMAC_CONFIG0);
249 reg &= ~CONFIG0_TX_RX_DISABLE;
250 writel(reg, port->gmac_base + GMAC_CONFIG0);
251
252 spin_unlock_irqrestore(&port->config_lock, flags);
253 }
254
255 static void gmac_disable_tx_rx(struct net_device *netdev)
256 {
257 struct gemini_ethernet_port *port = netdev_priv(netdev);
258 unsigned long flags;
259 u32 val;
260
261 spin_lock_irqsave(&port->config_lock, flags);
262
263 val = readl(port->gmac_base + GMAC_CONFIG0);
264 val |= CONFIG0_TX_RX_DISABLE;
265 writel(val, port->gmac_base + GMAC_CONFIG0);
266
267 spin_unlock_irqrestore(&port->config_lock, flags);
268
269 mdelay(10); /* let GMAC consume packet */
270 }
271
272 static void gmac_set_flow_control(struct net_device *netdev, bool tx, bool rx)
273 {
274 struct gemini_ethernet_port *port = netdev_priv(netdev);
275 unsigned long flags;
276 u32 val;
277
278 spin_lock_irqsave(&port->config_lock, flags);
279
280 val = readl(port->gmac_base + GMAC_CONFIG0);
281 val &= ~CONFIG0_FLOW_CTL;
282 if (tx)
283 val |= CONFIG0_FLOW_TX;
284 if (rx)
285 val |= CONFIG0_FLOW_RX;
286 writel(val, port->gmac_base + GMAC_CONFIG0);
287
288 spin_unlock_irqrestore(&port->config_lock, flags);
289 }
290
291 static void gmac_speed_set(struct net_device *netdev)
292 {
293 struct gemini_ethernet_port *port = netdev_priv(netdev);
294 struct phy_device *phydev = netdev->phydev;
295 union gmac_status status, old_status;
296 int pause_tx = 0;
297 int pause_rx = 0;
298
299 status.bits32 = readl(port->gmac_base + GMAC_STATUS);
300 old_status.bits32 = status.bits32;
301 status.bits.link = phydev->link;
302 status.bits.duplex = phydev->duplex;
303
304 switch (phydev->speed) {
305 case 1000:
306 status.bits.speed = GMAC_SPEED_1000;
307 if (phydev->interface == PHY_INTERFACE_MODE_RGMII)
308 status.bits.mii_rmii = GMAC_PHY_RGMII_1000;
309 netdev_dbg(netdev, "connect %s to RGMII @ 1Gbit\n",
310 phydev_name(phydev));
311 break;
312 case 100:
313 status.bits.speed = GMAC_SPEED_100;
314 if (phydev->interface == PHY_INTERFACE_MODE_RGMII)
315 status.bits.mii_rmii = GMAC_PHY_RGMII_100_10;
316 netdev_dbg(netdev, "connect %s to RGMII @ 100 Mbit\n",
317 phydev_name(phydev));
318 break;
319 case 10:
320 status.bits.speed = GMAC_SPEED_10;
321 if (phydev->interface == PHY_INTERFACE_MODE_RGMII)
322 status.bits.mii_rmii = GMAC_PHY_RGMII_100_10;
323 netdev_dbg(netdev, "connect %s to RGMII @ 10 Mbit\n",
324 phydev_name(phydev));
325 break;
326 default:
327 netdev_warn(netdev, "Unsupported PHY speed (%d) on %s\n",
328 phydev->speed, phydev_name(phydev));
329 }
330
331 if (phydev->duplex == DUPLEX_FULL) {
332 u16 lcladv = phy_read(phydev, MII_ADVERTISE);
333 u16 rmtadv = phy_read(phydev, MII_LPA);
334 u8 cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
335
336 if (cap & FLOW_CTRL_RX)
337 pause_rx = 1;
338 if (cap & FLOW_CTRL_TX)
339 pause_tx = 1;
340 }
341
342 gmac_set_flow_control(netdev, pause_tx, pause_rx);
343
344 if (old_status.bits32 == status.bits32)
345 return;
346
347 if (netif_msg_link(port)) {
348 phy_print_status(phydev);
349 netdev_info(netdev, "link flow control: %s\n",
350 phydev->pause
351 ? (phydev->asym_pause ? "tx" : "both")
352 : (phydev->asym_pause ? "rx" : "none")
353 );
354 }
355
356 gmac_disable_tx_rx(netdev);
357 writel(status.bits32, port->gmac_base + GMAC_STATUS);
358 gmac_enable_tx_rx(netdev);
359 }
360
361 static int gmac_setup_phy(struct net_device *netdev)
362 {
363 struct gemini_ethernet_port *port = netdev_priv(netdev);
364 union gmac_status status = { .bits32 = 0 };
365 struct device *dev = port->dev;
366 struct phy_device *phy;
367
368 phy = of_phy_get_and_connect(netdev,
369 dev->of_node,
370 gmac_speed_set);
371 if (!phy)
372 return -ENODEV;
373 netdev->phydev = phy;
374
375 phy_set_max_speed(phy, SPEED_1000);
376 phy_support_asym_pause(phy);
377
378 /* set PHY interface type */
379 switch (phy->interface) {
380 case PHY_INTERFACE_MODE_MII:
381 netdev_dbg(netdev,
382 "MII: set GMAC0 to GMII mode, GMAC1 disabled\n");
383 status.bits.mii_rmii = GMAC_PHY_MII;
384 break;
385 case PHY_INTERFACE_MODE_GMII:
386 netdev_dbg(netdev,
387 "GMII: set GMAC0 to GMII mode, GMAC1 disabled\n");
388 status.bits.mii_rmii = GMAC_PHY_GMII;
389 break;
390 case PHY_INTERFACE_MODE_RGMII:
391 netdev_dbg(netdev,
392 "RGMII: set GMAC0 and GMAC1 to MII/RGMII mode\n");
393 status.bits.mii_rmii = GMAC_PHY_RGMII_100_10;
394 break;
395 default:
396 netdev_err(netdev, "Unsupported MII interface\n");
397 phy_disconnect(phy);
398 netdev->phydev = NULL;
399 return -EINVAL;
400 }
401 writel(status.bits32, port->gmac_base + GMAC_STATUS);
402
403 if (netif_msg_link(port))
404 phy_attached_info(phy);
405
406 return 0;
407 }
408
409 /* The maximum frame length is not logically enumerated in the
410 * hardware, so we do a table lookup to find the applicable max
411 * frame length.
412 */
413 struct gmac_max_framelen {
414 unsigned int max_l3_len;
415 u8 val;
416 };
417
418 static const struct gmac_max_framelen gmac_maxlens[] = {
419 {
420 .max_l3_len = 1518,
421 .val = CONFIG0_MAXLEN_1518,
422 },
423 {
424 .max_l3_len = 1522,
425 .val = CONFIG0_MAXLEN_1522,
426 },
427 {
428 .max_l3_len = 1536,
429 .val = CONFIG0_MAXLEN_1536,
430 },
431 {
432 .max_l3_len = 1542,
433 .val = CONFIG0_MAXLEN_1542,
434 },
435 {
436 .max_l3_len = 9212,
437 .val = CONFIG0_MAXLEN_9k,
438 },
439 {
440 .max_l3_len = 10236,
441 .val = CONFIG0_MAXLEN_10k,
442 },
443 };
444
445 static int gmac_pick_rx_max_len(unsigned int max_l3_len)
446 {
447 const struct gmac_max_framelen *maxlen;
448 int maxtot;
449 int i;
450
451 maxtot = max_l3_len + ETH_HLEN + VLAN_HLEN;
452
453 for (i = 0; i < ARRAY_SIZE(gmac_maxlens); i++) {
454 maxlen = &gmac_maxlens[i];
455 if (maxtot <= maxlen->max_l3_len)
456 return maxlen->val;
457 }
458
459 return -1;
460 }
461
462 static int gmac_init(struct net_device *netdev)
463 {
464 struct gemini_ethernet_port *port = netdev_priv(netdev);
465 union gmac_config0 config0 = { .bits = {
466 .dis_tx = 1,
467 .dis_rx = 1,
468 .ipv4_rx_chksum = 1,
469 .ipv6_rx_chksum = 1,
470 .rx_err_detect = 1,
471 .rgmm_edge = 1,
472 .port0_chk_hwq = 1,
473 .port1_chk_hwq = 1,
474 .port0_chk_toeq = 1,
475 .port1_chk_toeq = 1,
476 .port0_chk_classq = 1,
477 .port1_chk_classq = 1,
478 } };
479 union gmac_ahb_weight ahb_weight = { .bits = {
480 .rx_weight = 1,
481 .tx_weight = 1,
482 .hash_weight = 1,
483 .pre_req = 0x1f,
484 .tq_dv_threshold = 0,
485 } };
486 union gmac_tx_wcr0 hw_weigh = { .bits = {
487 .hw_tq3 = 1,
488 .hw_tq2 = 1,
489 .hw_tq1 = 1,
490 .hw_tq0 = 1,
491 } };
492 union gmac_tx_wcr1 sw_weigh = { .bits = {
493 .sw_tq5 = 1,
494 .sw_tq4 = 1,
495 .sw_tq3 = 1,
496 .sw_tq2 = 1,
497 .sw_tq1 = 1,
498 .sw_tq0 = 1,
499 } };
500 union gmac_config1 config1 = { .bits = {
501 .set_threshold = 16,
502 .rel_threshold = 24,
503 } };
504 union gmac_config2 config2 = { .bits = {
505 .set_threshold = 16,
506 .rel_threshold = 32,
507 } };
508 union gmac_config3 config3 = { .bits = {
509 .set_threshold = 0,
510 .rel_threshold = 0,
511 } };
512 union gmac_config0 tmp;
513 u32 val;
514
515 config0.bits.max_len = gmac_pick_rx_max_len(netdev->mtu);
516 tmp.bits32 = readl(port->gmac_base + GMAC_CONFIG0);
517 config0.bits.reserved = tmp.bits.reserved;
518 writel(config0.bits32, port->gmac_base + GMAC_CONFIG0);
519 writel(config1.bits32, port->gmac_base + GMAC_CONFIG1);
520 writel(config2.bits32, port->gmac_base + GMAC_CONFIG2);
521 writel(config3.bits32, port->gmac_base + GMAC_CONFIG3);
522
523 val = readl(port->dma_base + GMAC_AHB_WEIGHT_REG);
524 writel(ahb_weight.bits32, port->dma_base + GMAC_AHB_WEIGHT_REG);
525
526 writel(hw_weigh.bits32,
527 port->dma_base + GMAC_TX_WEIGHTING_CTRL_0_REG);
528 writel(sw_weigh.bits32,
529 port->dma_base + GMAC_TX_WEIGHTING_CTRL_1_REG);
530
531 port->rxq_order = DEFAULT_GMAC_RXQ_ORDER;
532 port->txq_order = DEFAULT_GMAC_TXQ_ORDER;
533 port->rx_coalesce_nsecs = DEFAULT_RX_COALESCE_NSECS;
534
535 /* Mark every quarter of the queue a packet for interrupt
536 * in order to be able to wake up the queue if it was stopped
537 */
538 port->irq_every_tx_packets = 1 << (port->txq_order - 2);
539
540 return 0;
541 }
542
543 static void gmac_uninit(struct net_device *netdev)
544 {
545 if (netdev->phydev)
546 phy_disconnect(netdev->phydev);
547 }
548
549 static int gmac_setup_txqs(struct net_device *netdev)
550 {
551 struct gemini_ethernet_port *port = netdev_priv(netdev);
552 unsigned int n_txq = netdev->num_tx_queues;
553 struct gemini_ethernet *geth = port->geth;
554 size_t entries = 1 << port->txq_order;
555 struct gmac_txq *txq = port->txq;
556 struct gmac_txdesc *desc_ring;
557 size_t len = n_txq * entries;
558 struct sk_buff **skb_tab;
559 void __iomem *rwptr_reg;
560 unsigned int r;
561 int i;
562
563 rwptr_reg = port->dma_base + GMAC_SW_TX_QUEUE0_PTR_REG;
564
565 skb_tab = kcalloc(len, sizeof(*skb_tab), GFP_KERNEL);
566 if (!skb_tab)
567 return -ENOMEM;
568
569 desc_ring = dma_alloc_coherent(geth->dev, len * sizeof(*desc_ring),
570 &port->txq_dma_base, GFP_KERNEL);
571
572 if (!desc_ring) {
573 kfree(skb_tab);
574 return -ENOMEM;
575 }
576
577 if (port->txq_dma_base & ~DMA_Q_BASE_MASK) {
578 dev_warn(geth->dev, "TX queue base is not aligned\n");
579 dma_free_coherent(geth->dev, len * sizeof(*desc_ring),
580 desc_ring, port->txq_dma_base);
581 kfree(skb_tab);
582 return -ENOMEM;
583 }
584
585 writel(port->txq_dma_base | port->txq_order,
586 port->dma_base + GMAC_SW_TX_QUEUE_BASE_REG);
587
588 for (i = 0; i < n_txq; i++) {
589 txq->ring = desc_ring;
590 txq->skb = skb_tab;
591 txq->noirq_packets = 0;
592
593 r = readw(rwptr_reg);
594 rwptr_reg += 2;
595 writew(r, rwptr_reg);
596 rwptr_reg += 2;
597 txq->cptr = r;
598
599 txq++;
600 desc_ring += entries;
601 skb_tab += entries;
602 }
603
604 return 0;
605 }
606
607 static void gmac_clean_txq(struct net_device *netdev, struct gmac_txq *txq,
608 unsigned int r)
609 {
610 struct gemini_ethernet_port *port = netdev_priv(netdev);
611 unsigned int m = (1 << port->txq_order) - 1;
612 struct gemini_ethernet *geth = port->geth;
613 unsigned int c = txq->cptr;
614 union gmac_txdesc_0 word0;
615 union gmac_txdesc_1 word1;
616 unsigned int hwchksum = 0;
617 unsigned long bytes = 0;
618 struct gmac_txdesc *txd;
619 unsigned short nfrags;
620 unsigned int errs = 0;
621 unsigned int pkts = 0;
622 unsigned int word3;
623 dma_addr_t mapping;
624
625 if (c == r)
626 return;
627
628 while (c != r) {
629 txd = txq->ring + c;
630 word0 = txd->word0;
631 word1 = txd->word1;
632 mapping = txd->word2.buf_adr;
633 word3 = txd->word3.bits32;
634
635 dma_unmap_single(geth->dev, mapping,
636 word0.bits.buffer_size, DMA_TO_DEVICE);
637
638 if (word3 & EOF_BIT)
639 dev_kfree_skb(txq->skb[c]);
640
641 c++;
642 c &= m;
643
644 if (!(word3 & SOF_BIT))
645 continue;
646
647 if (!word0.bits.status_tx_ok) {
648 errs++;
649 continue;
650 }
651
652 pkts++;
653 bytes += txd->word1.bits.byte_count;
654
655 if (word1.bits32 & TSS_CHECKUM_ENABLE)
656 hwchksum++;
657
658 nfrags = word0.bits.desc_count - 1;
659 if (nfrags) {
660 if (nfrags >= TX_MAX_FRAGS)
661 nfrags = TX_MAX_FRAGS - 1;
662
663 u64_stats_update_begin(&port->tx_stats_syncp);
664 port->tx_frag_stats[nfrags]++;
665 u64_stats_update_end(&port->tx_stats_syncp);
666 }
667 }
668
669 u64_stats_update_begin(&port->ir_stats_syncp);
670 port->stats.tx_errors += errs;
671 port->stats.tx_packets += pkts;
672 port->stats.tx_bytes += bytes;
673 port->tx_hw_csummed += hwchksum;
674 u64_stats_update_end(&port->ir_stats_syncp);
675
676 txq->cptr = c;
677 }
678
679 static void gmac_cleanup_txqs(struct net_device *netdev)
680 {
681 struct gemini_ethernet_port *port = netdev_priv(netdev);
682 unsigned int n_txq = netdev->num_tx_queues;
683 struct gemini_ethernet *geth = port->geth;
684 void __iomem *rwptr_reg;
685 unsigned int r, i;
686
687 rwptr_reg = port->dma_base + GMAC_SW_TX_QUEUE0_PTR_REG;
688
689 for (i = 0; i < n_txq; i++) {
690 r = readw(rwptr_reg);
691 rwptr_reg += 2;
692 writew(r, rwptr_reg);
693 rwptr_reg += 2;
694
695 gmac_clean_txq(netdev, port->txq + i, r);
696 }
697 writel(0, port->dma_base + GMAC_SW_TX_QUEUE_BASE_REG);
698
699 kfree(port->txq->skb);
700 dma_free_coherent(geth->dev,
701 n_txq * sizeof(*port->txq->ring) << port->txq_order,
702 port->txq->ring, port->txq_dma_base);
703 }
704
705 static int gmac_setup_rxq(struct net_device *netdev)
706 {
707 struct gemini_ethernet_port *port = netdev_priv(netdev);
708 struct gemini_ethernet *geth = port->geth;
709 struct nontoe_qhdr __iomem *qhdr;
710
711 qhdr = geth->base + TOE_DEFAULT_Q_HDR_BASE(netdev->dev_id);
712 port->rxq_rwptr = &qhdr->word1;
713
714 /* Remap a slew of memory to use for the RX queue */
715 port->rxq_ring = dma_alloc_coherent(geth->dev,
716 sizeof(*port->rxq_ring) << port->rxq_order,
717 &port->rxq_dma_base, GFP_KERNEL);
718 if (!port->rxq_ring)
719 return -ENOMEM;
720 if (port->rxq_dma_base & ~NONTOE_QHDR0_BASE_MASK) {
721 dev_warn(geth->dev, "RX queue base is not aligned\n");
722 return -ENOMEM;
723 }
724
725 writel(port->rxq_dma_base | port->rxq_order, &qhdr->word0);
726 writel(0, port->rxq_rwptr);
727 return 0;
728 }
729
730 static struct gmac_queue_page *
731 gmac_get_queue_page(struct gemini_ethernet *geth,
732 struct gemini_ethernet_port *port,
733 dma_addr_t addr)
734 {
735 struct gmac_queue_page *gpage;
736 dma_addr_t mapping;
737 int i;
738
739 /* Only look for even pages */
740 mapping = addr & PAGE_MASK;
741
742 if (!geth->freeq_pages) {
743 dev_err(geth->dev, "try to get page with no page list\n");
744 return NULL;
745 }
746
747 /* Look up a ring buffer page from virtual mapping */
748 for (i = 0; i < geth->num_freeq_pages; i++) {
749 gpage = &geth->freeq_pages[i];
750 if (gpage->mapping == mapping)
751 return gpage;
752 }
753
754 return NULL;
755 }
756
757 static void gmac_cleanup_rxq(struct net_device *netdev)
758 {
759 struct gemini_ethernet_port *port = netdev_priv(netdev);
760 struct gemini_ethernet *geth = port->geth;
761 struct gmac_rxdesc *rxd = port->rxq_ring;
762 static struct gmac_queue_page *gpage;
763 struct nontoe_qhdr __iomem *qhdr;
764 void __iomem *dma_reg;
765 void __iomem *ptr_reg;
766 dma_addr_t mapping;
767 union dma_rwptr rw;
768 unsigned int r, w;
769
770 qhdr = geth->base +
771 TOE_DEFAULT_Q_HDR_BASE(netdev->dev_id);
772 dma_reg = &qhdr->word0;
773 ptr_reg = &qhdr->word1;
774
775 rw.bits32 = readl(ptr_reg);
776 r = rw.bits.rptr;
777 w = rw.bits.wptr;
778 writew(r, ptr_reg + 2);
779
780 writel(0, dma_reg);
781
782 /* Loop from read pointer to write pointer of the RX queue
783 * and free up all pages by the queue.
784 */
785 while (r != w) {
786 mapping = rxd[r].word2.buf_adr;
787 r++;
788 r &= ((1 << port->rxq_order) - 1);
789
790 if (!mapping)
791 continue;
792
793 /* Freeq pointers are one page off */
794 gpage = gmac_get_queue_page(geth, port, mapping + PAGE_SIZE);
795 if (!gpage) {
796 dev_err(geth->dev, "could not find page\n");
797 continue;
798 }
799 /* Release the RX queue reference to the page */
800 put_page(gpage->page);
801 }
802
803 dma_free_coherent(geth->dev, sizeof(*port->rxq_ring) << port->rxq_order,
804 port->rxq_ring, port->rxq_dma_base);
805 }
806
807 static struct page *geth_freeq_alloc_map_page(struct gemini_ethernet *geth,
808 int pn)
809 {
810 struct gmac_rxdesc *freeq_entry;
811 struct gmac_queue_page *gpage;
812 unsigned int fpp_order;
813 unsigned int frag_len;
814 dma_addr_t mapping;
815 struct page *page;
816 int i;
817
818 /* First allocate and DMA map a single page */
819 page = alloc_page(GFP_ATOMIC);
820 if (!page)
821 return NULL;
822
823 mapping = dma_map_single(geth->dev, page_address(page),
824 PAGE_SIZE, DMA_FROM_DEVICE);
825 if (dma_mapping_error(geth->dev, mapping)) {
826 put_page(page);
827 return NULL;
828 }
829
830 /* The assign the page mapping (physical address) to the buffer address
831 * in the hardware queue. PAGE_SHIFT on ARM is 12 (1 page is 4096 bytes,
832 * 4k), and the default RX frag order is 11 (fragments are up 20 2048
833 * bytes, 2k) so fpp_order (fragments per page order) is default 1. Thus
834 * each page normally needs two entries in the queue.
835 */
836 frag_len = 1 << geth->freeq_frag_order; /* Usually 2048 */
837 fpp_order = PAGE_SHIFT - geth->freeq_frag_order;
838 freeq_entry = geth->freeq_ring + (pn << fpp_order);
839 dev_dbg(geth->dev, "allocate page %d fragment length %d fragments per page %d, freeq entry %p\n",
840 pn, frag_len, (1 << fpp_order), freeq_entry);
841 for (i = (1 << fpp_order); i > 0; i--) {
842 freeq_entry->word2.buf_adr = mapping;
843 freeq_entry++;
844 mapping += frag_len;
845 }
846
847 /* If the freeq entry already has a page mapped, then unmap it. */
848 gpage = &geth->freeq_pages[pn];
849 if (gpage->page) {
850 mapping = geth->freeq_ring[pn << fpp_order].word2.buf_adr;
851 dma_unmap_single(geth->dev, mapping, frag_len, DMA_FROM_DEVICE);
852 /* This should be the last reference to the page so it gets
853 * released
854 */
855 put_page(gpage->page);
856 }
857
858 /* Then put our new mapping into the page table */
859 dev_dbg(geth->dev, "page %d, DMA addr: %08x, page %p\n",
860 pn, (unsigned int)mapping, page);
861 gpage->mapping = mapping;
862 gpage->page = page;
863
864 return page;
865 }
866
867 /**
868 * geth_fill_freeq() - Fill the freeq with empty fragments to use
869 * @geth: the ethernet adapter
870 * @refill: whether to reset the queue by filling in all freeq entries or
871 * just refill it, usually the interrupt to refill the queue happens when
872 * the queue is half empty.
873 */
874 static unsigned int geth_fill_freeq(struct gemini_ethernet *geth, bool refill)
875 {
876 unsigned int fpp_order = PAGE_SHIFT - geth->freeq_frag_order;
877 unsigned int count = 0;
878 unsigned int pn, epn;
879 unsigned long flags;
880 union dma_rwptr rw;
881 unsigned int m_pn;
882
883 /* Mask for page */
884 m_pn = (1 << (geth->freeq_order - fpp_order)) - 1;
885
886 spin_lock_irqsave(&geth->freeq_lock, flags);
887
888 rw.bits32 = readl(geth->base + GLOBAL_SWFQ_RWPTR_REG);
889 pn = (refill ? rw.bits.wptr : rw.bits.rptr) >> fpp_order;
890 epn = (rw.bits.rptr >> fpp_order) - 1;
891 epn &= m_pn;
892
893 /* Loop over the freeq ring buffer entries */
894 while (pn != epn) {
895 struct gmac_queue_page *gpage;
896 struct page *page;
897
898 gpage = &geth->freeq_pages[pn];
899 page = gpage->page;
900
901 dev_dbg(geth->dev, "fill entry %d page ref count %d add %d refs\n",
902 pn, page_ref_count(page), 1 << fpp_order);
903
904 if (page_ref_count(page) > 1) {
905 unsigned int fl = (pn - epn) & m_pn;
906
907 if (fl > 64 >> fpp_order)
908 break;
909
910 page = geth_freeq_alloc_map_page(geth, pn);
911 if (!page)
912 break;
913 }
914
915 /* Add one reference per fragment in the page */
916 page_ref_add(page, 1 << fpp_order);
917 count += 1 << fpp_order;
918 pn++;
919 pn &= m_pn;
920 }
921
922 writew(pn << fpp_order, geth->base + GLOBAL_SWFQ_RWPTR_REG + 2);
923
924 spin_unlock_irqrestore(&geth->freeq_lock, flags);
925
926 return count;
927 }
928
929 static int geth_setup_freeq(struct gemini_ethernet *geth)
930 {
931 unsigned int fpp_order = PAGE_SHIFT - geth->freeq_frag_order;
932 unsigned int frag_len = 1 << geth->freeq_frag_order;
933 unsigned int len = 1 << geth->freeq_order;
934 unsigned int pages = len >> fpp_order;
935 union queue_threshold qt;
936 union dma_skb_size skbsz;
937 unsigned int filled;
938 unsigned int pn;
939
940 geth->freeq_ring = dma_alloc_coherent(geth->dev,
941 sizeof(*geth->freeq_ring) << geth->freeq_order,
942 &geth->freeq_dma_base, GFP_KERNEL);
943 if (!geth->freeq_ring)
944 return -ENOMEM;
945 if (geth->freeq_dma_base & ~DMA_Q_BASE_MASK) {
946 dev_warn(geth->dev, "queue ring base is not aligned\n");
947 goto err_freeq;
948 }
949
950 /* Allocate a mapping to page look-up index */
951 geth->freeq_pages = kcalloc(pages, sizeof(*geth->freeq_pages),
952 GFP_KERNEL);
953 if (!geth->freeq_pages)
954 goto err_freeq;
955 geth->num_freeq_pages = pages;
956
957 dev_info(geth->dev, "allocate %d pages for queue\n", pages);
958 for (pn = 0; pn < pages; pn++)
959 if (!geth_freeq_alloc_map_page(geth, pn))
960 goto err_freeq_alloc;
961
962 filled = geth_fill_freeq(geth, false);
963 if (!filled)
964 goto err_freeq_alloc;
965
966 qt.bits32 = readl(geth->base + GLOBAL_QUEUE_THRESHOLD_REG);
967 qt.bits.swfq_empty = 32;
968 writel(qt.bits32, geth->base + GLOBAL_QUEUE_THRESHOLD_REG);
969
970 skbsz.bits.sw_skb_size = 1 << geth->freeq_frag_order;
971 writel(skbsz.bits32, geth->base + GLOBAL_DMA_SKB_SIZE_REG);
972 writel(geth->freeq_dma_base | geth->freeq_order,
973 geth->base + GLOBAL_SW_FREEQ_BASE_SIZE_REG);
974
975 return 0;
976
977 err_freeq_alloc:
978 while (pn > 0) {
979 struct gmac_queue_page *gpage;
980 dma_addr_t mapping;
981
982 --pn;
983 mapping = geth->freeq_ring[pn << fpp_order].word2.buf_adr;
984 dma_unmap_single(geth->dev, mapping, frag_len, DMA_FROM_DEVICE);
985 gpage = &geth->freeq_pages[pn];
986 put_page(gpage->page);
987 }
988
989 kfree(geth->freeq_pages);
990 err_freeq:
991 dma_free_coherent(geth->dev,
992 sizeof(*geth->freeq_ring) << geth->freeq_order,
993 geth->freeq_ring, geth->freeq_dma_base);
994 geth->freeq_ring = NULL;
995 return -ENOMEM;
996 }
997
998 /**
999 * geth_cleanup_freeq() - cleanup the DMA mappings and free the queue
1000 * @geth: the Gemini global ethernet state
1001 */
1002 static void geth_cleanup_freeq(struct gemini_ethernet *geth)
1003 {
1004 unsigned int fpp_order = PAGE_SHIFT - geth->freeq_frag_order;
1005 unsigned int frag_len = 1 << geth->freeq_frag_order;
1006 unsigned int len = 1 << geth->freeq_order;
1007 unsigned int pages = len >> fpp_order;
1008 unsigned int pn;
1009
1010 writew(readw(geth->base + GLOBAL_SWFQ_RWPTR_REG),
1011 geth->base + GLOBAL_SWFQ_RWPTR_REG + 2);
1012 writel(0, geth->base + GLOBAL_SW_FREEQ_BASE_SIZE_REG);
1013
1014 for (pn = 0; pn < pages; pn++) {
1015 struct gmac_queue_page *gpage;
1016 dma_addr_t mapping;
1017
1018 mapping = geth->freeq_ring[pn << fpp_order].word2.buf_adr;
1019 dma_unmap_single(geth->dev, mapping, frag_len, DMA_FROM_DEVICE);
1020
1021 gpage = &geth->freeq_pages[pn];
1022 while (page_ref_count(gpage->page) > 0)
1023 put_page(gpage->page);
1024 }
1025
1026 kfree(geth->freeq_pages);
1027
1028 dma_free_coherent(geth->dev,
1029 sizeof(*geth->freeq_ring) << geth->freeq_order,
1030 geth->freeq_ring, geth->freeq_dma_base);
1031 }
1032
1033 /**
1034 * geth_resize_freeq() - resize the software queue depth
1035 * @port: the port requesting the change
1036 *
1037 * This gets called at least once during probe() so the device queue gets
1038 * "resized" from the hardware defaults. Since both ports/net devices share
1039 * the same hardware queue, some synchronization between the ports is
1040 * needed.
1041 */
1042 static int geth_resize_freeq(struct gemini_ethernet_port *port)
1043 {
1044 struct gemini_ethernet *geth = port->geth;
1045 struct net_device *netdev = port->netdev;
1046 struct gemini_ethernet_port *other_port;
1047 struct net_device *other_netdev;
1048 unsigned int new_size = 0;
1049 unsigned int new_order;
1050 unsigned long flags;
1051 u32 en;
1052 int ret;
1053
1054 if (netdev->dev_id == 0)
1055 other_netdev = geth->port1->netdev;
1056 else
1057 other_netdev = geth->port0->netdev;
1058
1059 if (other_netdev && netif_running(other_netdev))
1060 return -EBUSY;
1061
1062 new_size = 1 << (port->rxq_order + 1);
1063 netdev_dbg(netdev, "port %d size: %d order %d\n",
1064 netdev->dev_id,
1065 new_size,
1066 port->rxq_order);
1067 if (other_netdev) {
1068 other_port = netdev_priv(other_netdev);
1069 new_size += 1 << (other_port->rxq_order + 1);
1070 netdev_dbg(other_netdev, "port %d size: %d order %d\n",
1071 other_netdev->dev_id,
1072 (1 << (other_port->rxq_order + 1)),
1073 other_port->rxq_order);
1074 }
1075
1076 new_order = min(15, ilog2(new_size - 1) + 1);
1077 dev_dbg(geth->dev, "set shared queue to size %d order %d\n",
1078 new_size, new_order);
1079 if (geth->freeq_order == new_order)
1080 return 0;
1081
1082 spin_lock_irqsave(&geth->irq_lock, flags);
1083
1084 /* Disable the software queue IRQs */
1085 en = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG);
1086 en &= ~SWFQ_EMPTY_INT_BIT;
1087 writel(en, geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG);
1088 spin_unlock_irqrestore(&geth->irq_lock, flags);
1089
1090 /* Drop the old queue */
1091 if (geth->freeq_ring)
1092 geth_cleanup_freeq(geth);
1093
1094 /* Allocate a new queue with the desired order */
1095 geth->freeq_order = new_order;
1096 ret = geth_setup_freeq(geth);
1097
1098 /* Restart the interrupts - NOTE if this is the first resize
1099 * after probe(), this is where the interrupts get turned on
1100 * in the first place.
1101 */
1102 spin_lock_irqsave(&geth->irq_lock, flags);
1103 en |= SWFQ_EMPTY_INT_BIT;
1104 writel(en, geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG);
1105 spin_unlock_irqrestore(&geth->irq_lock, flags);
1106
1107 return ret;
1108 }
1109
1110 static void gmac_tx_irq_enable(struct net_device *netdev,
1111 unsigned int txq, int en)
1112 {
1113 struct gemini_ethernet_port *port = netdev_priv(netdev);
1114 struct gemini_ethernet *geth = port->geth;
1115 u32 val, mask;
1116
1117 netdev_dbg(netdev, "%s device %d\n", __func__, netdev->dev_id);
1118
1119 mask = GMAC0_IRQ0_TXQ0_INTS << (6 * netdev->dev_id + txq);
1120
1121 if (en)
1122 writel(mask, geth->base + GLOBAL_INTERRUPT_STATUS_0_REG);
1123
1124 val = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_0_REG);
1125 val = en ? val | mask : val & ~mask;
1126 writel(val, geth->base + GLOBAL_INTERRUPT_ENABLE_0_REG);
1127 }
1128
1129 static void gmac_tx_irq(struct net_device *netdev, unsigned int txq_num)
1130 {
1131 struct netdev_queue *ntxq = netdev_get_tx_queue(netdev, txq_num);
1132
1133 gmac_tx_irq_enable(netdev, txq_num, 0);
1134 netif_tx_wake_queue(ntxq);
1135 }
1136
1137 static int gmac_map_tx_bufs(struct net_device *netdev, struct sk_buff *skb,
1138 struct gmac_txq *txq, unsigned short *desc)
1139 {
1140 struct gemini_ethernet_port *port = netdev_priv(netdev);
1141 struct skb_shared_info *skb_si = skb_shinfo(skb);
1142 unsigned short m = (1 << port->txq_order) - 1;
1143 short frag, last_frag = skb_si->nr_frags - 1;
1144 struct gemini_ethernet *geth = port->geth;
1145 unsigned int word1, word3, buflen;
1146 unsigned short w = *desc;
1147 struct gmac_txdesc *txd;
1148 skb_frag_t *skb_frag;
1149 dma_addr_t mapping;
1150 unsigned short mtu;
1151 void *buffer;
1152
1153 mtu = ETH_HLEN;
1154 mtu += netdev->mtu;
1155 if (skb->protocol == htons(ETH_P_8021Q))
1156 mtu += VLAN_HLEN;
1157
1158 word1 = skb->len;
1159 word3 = SOF_BIT;
1160
1161 if (word1 > mtu) {
1162 word1 |= TSS_MTU_ENABLE_BIT;
1163 word3 |= mtu;
1164 }
1165
1166 if (skb->ip_summed != CHECKSUM_NONE) {
1167 int tcp = 0;
1168
1169 if (skb->protocol == htons(ETH_P_IP)) {
1170 word1 |= TSS_IP_CHKSUM_BIT;
1171 tcp = ip_hdr(skb)->protocol == IPPROTO_TCP;
1172 } else { /* IPv6 */
1173 word1 |= TSS_IPV6_ENABLE_BIT;
1174 tcp = ipv6_hdr(skb)->nexthdr == IPPROTO_TCP;
1175 }
1176
1177 word1 |= tcp ? TSS_TCP_CHKSUM_BIT : TSS_UDP_CHKSUM_BIT;
1178 }
1179
1180 frag = -1;
1181 while (frag <= last_frag) {
1182 if (frag == -1) {
1183 buffer = skb->data;
1184 buflen = skb_headlen(skb);
1185 } else {
1186 skb_frag = skb_si->frags + frag;
1187 buffer = skb_frag_address(skb_frag);
1188 buflen = skb_frag_size(skb_frag);
1189 }
1190
1191 if (frag == last_frag) {
1192 word3 |= EOF_BIT;
1193 txq->skb[w] = skb;
1194 }
1195
1196 mapping = dma_map_single(geth->dev, buffer, buflen,
1197 DMA_TO_DEVICE);
1198 if (dma_mapping_error(geth->dev, mapping))
1199 goto map_error;
1200
1201 txd = txq->ring + w;
1202 txd->word0.bits32 = buflen;
1203 txd->word1.bits32 = word1;
1204 txd->word2.buf_adr = mapping;
1205 txd->word3.bits32 = word3;
1206
1207 word3 &= MTU_SIZE_BIT_MASK;
1208 w++;
1209 w &= m;
1210 frag++;
1211 }
1212
1213 *desc = w;
1214 return 0;
1215
1216 map_error:
1217 while (w != *desc) {
1218 w--;
1219 w &= m;
1220
1221 dma_unmap_page(geth->dev, txq->ring[w].word2.buf_adr,
1222 txq->ring[w].word0.bits.buffer_size,
1223 DMA_TO_DEVICE);
1224 }
1225 return -ENOMEM;
1226 }
1227
1228 static int gmac_start_xmit(struct sk_buff *skb, struct net_device *netdev)
1229 {
1230 struct gemini_ethernet_port *port = netdev_priv(netdev);
1231 unsigned short m = (1 << port->txq_order) - 1;
1232 struct netdev_queue *ntxq;
1233 unsigned short r, w, d;
1234 void __iomem *ptr_reg;
1235 struct gmac_txq *txq;
1236 int txq_num, nfrags;
1237 union dma_rwptr rw;
1238
1239 if (skb->len >= 0x10000)
1240 goto out_drop_free;
1241
1242 txq_num = skb_get_queue_mapping(skb);
1243 ptr_reg = port->dma_base + GMAC_SW_TX_QUEUE_PTR_REG(txq_num);
1244 txq = &port->txq[txq_num];
1245 ntxq = netdev_get_tx_queue(netdev, txq_num);
1246 nfrags = skb_shinfo(skb)->nr_frags;
1247
1248 rw.bits32 = readl(ptr_reg);
1249 r = rw.bits.rptr;
1250 w = rw.bits.wptr;
1251
1252 d = txq->cptr - w - 1;
1253 d &= m;
1254
1255 if (d < nfrags + 2) {
1256 gmac_clean_txq(netdev, txq, r);
1257 d = txq->cptr - w - 1;
1258 d &= m;
1259
1260 if (d < nfrags + 2) {
1261 netif_tx_stop_queue(ntxq);
1262
1263 d = txq->cptr + nfrags + 16;
1264 d &= m;
1265 txq->ring[d].word3.bits.eofie = 1;
1266 gmac_tx_irq_enable(netdev, txq_num, 1);
1267
1268 u64_stats_update_begin(&port->tx_stats_syncp);
1269 netdev->stats.tx_fifo_errors++;
1270 u64_stats_update_end(&port->tx_stats_syncp);
1271 return NETDEV_TX_BUSY;
1272 }
1273 }
1274
1275 if (gmac_map_tx_bufs(netdev, skb, txq, &w)) {
1276 if (skb_linearize(skb))
1277 goto out_drop;
1278
1279 u64_stats_update_begin(&port->tx_stats_syncp);
1280 port->tx_frags_linearized++;
1281 u64_stats_update_end(&port->tx_stats_syncp);
1282
1283 if (gmac_map_tx_bufs(netdev, skb, txq, &w))
1284 goto out_drop_free;
1285 }
1286
1287 writew(w, ptr_reg + 2);
1288
1289 gmac_clean_txq(netdev, txq, r);
1290 return NETDEV_TX_OK;
1291
1292 out_drop_free:
1293 dev_kfree_skb(skb);
1294 out_drop:
1295 u64_stats_update_begin(&port->tx_stats_syncp);
1296 port->stats.tx_dropped++;
1297 u64_stats_update_end(&port->tx_stats_syncp);
1298 return NETDEV_TX_OK;
1299 }
1300
1301 static void gmac_tx_timeout(struct net_device *netdev, unsigned int txqueue)
1302 {
1303 netdev_err(netdev, "Tx timeout\n");
1304 gmac_dump_dma_state(netdev);
1305 }
1306
1307 static void gmac_enable_irq(struct net_device *netdev, int enable)
1308 {
1309 struct gemini_ethernet_port *port = netdev_priv(netdev);
1310 struct gemini_ethernet *geth = port->geth;
1311 unsigned long flags;
1312 u32 val, mask;
1313
1314 netdev_dbg(netdev, "%s device %d %s\n", __func__,
1315 netdev->dev_id, enable ? "enable" : "disable");
1316 spin_lock_irqsave(&geth->irq_lock, flags);
1317
1318 mask = GMAC0_IRQ0_2 << (netdev->dev_id * 2);
1319 val = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_0_REG);
1320 val = enable ? (val | mask) : (val & ~mask);
1321 writel(val, geth->base + GLOBAL_INTERRUPT_ENABLE_0_REG);
1322
1323 mask = DEFAULT_Q0_INT_BIT << netdev->dev_id;
1324 val = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_1_REG);
1325 val = enable ? (val | mask) : (val & ~mask);
1326 writel(val, geth->base + GLOBAL_INTERRUPT_ENABLE_1_REG);
1327
1328 mask = GMAC0_IRQ4_8 << (netdev->dev_id * 8);
1329 val = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG);
1330 val = enable ? (val | mask) : (val & ~mask);
1331 writel(val, geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG);
1332
1333 spin_unlock_irqrestore(&geth->irq_lock, flags);
1334 }
1335
1336 static void gmac_enable_rx_irq(struct net_device *netdev, int enable)
1337 {
1338 struct gemini_ethernet_port *port = netdev_priv(netdev);
1339 struct gemini_ethernet *geth = port->geth;
1340 unsigned long flags;
1341 u32 val, mask;
1342
1343 netdev_dbg(netdev, "%s device %d %s\n", __func__, netdev->dev_id,
1344 enable ? "enable" : "disable");
1345 spin_lock_irqsave(&geth->irq_lock, flags);
1346 mask = DEFAULT_Q0_INT_BIT << netdev->dev_id;
1347
1348 val = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_1_REG);
1349 val = enable ? (val | mask) : (val & ~mask);
1350 writel(val, geth->base + GLOBAL_INTERRUPT_ENABLE_1_REG);
1351
1352 spin_unlock_irqrestore(&geth->irq_lock, flags);
1353 }
1354
1355 static struct sk_buff *gmac_skb_if_good_frame(struct gemini_ethernet_port *port,
1356 union gmac_rxdesc_0 word0,
1357 unsigned int frame_len)
1358 {
1359 unsigned int rx_csum = word0.bits.chksum_status;
1360 unsigned int rx_status = word0.bits.status;
1361 struct sk_buff *skb = NULL;
1362
1363 port->rx_stats[rx_status]++;
1364 port->rx_csum_stats[rx_csum]++;
1365
1366 if (word0.bits.derr || word0.bits.perr ||
1367 rx_status || frame_len < ETH_ZLEN ||
1368 rx_csum >= RX_CHKSUM_IP_ERR_UNKNOWN) {
1369 port->stats.rx_errors++;
1370
1371 if (frame_len < ETH_ZLEN || RX_ERROR_LENGTH(rx_status))
1372 port->stats.rx_length_errors++;
1373 if (RX_ERROR_OVER(rx_status))
1374 port->stats.rx_over_errors++;
1375 if (RX_ERROR_CRC(rx_status))
1376 port->stats.rx_crc_errors++;
1377 if (RX_ERROR_FRAME(rx_status))
1378 port->stats.rx_frame_errors++;
1379 return NULL;
1380 }
1381
1382 skb = napi_get_frags(&port->napi);
1383 if (!skb)
1384 goto update_exit;
1385
1386 if (rx_csum == RX_CHKSUM_IP_UDP_TCP_OK)
1387 skb->ip_summed = CHECKSUM_UNNECESSARY;
1388
1389 update_exit:
1390 port->stats.rx_bytes += frame_len;
1391 port->stats.rx_packets++;
1392 return skb;
1393 }
1394
1395 static unsigned int gmac_rx(struct net_device *netdev, unsigned int budget)
1396 {
1397 struct gemini_ethernet_port *port = netdev_priv(netdev);
1398 unsigned short m = (1 << port->rxq_order) - 1;
1399 struct gemini_ethernet *geth = port->geth;
1400 void __iomem *ptr_reg = port->rxq_rwptr;
1401 unsigned int frame_len, frag_len;
1402 struct gmac_rxdesc *rx = NULL;
1403 struct gmac_queue_page *gpage;
1404 static struct sk_buff *skb;
1405 union gmac_rxdesc_0 word0;
1406 union gmac_rxdesc_1 word1;
1407 union gmac_rxdesc_3 word3;
1408 struct page *page = NULL;
1409 unsigned int page_offs;
1410 unsigned short r, w;
1411 union dma_rwptr rw;
1412 dma_addr_t mapping;
1413 int frag_nr = 0;
1414
1415 rw.bits32 = readl(ptr_reg);
1416 /* Reset interrupt as all packages until here are taken into account */
1417 writel(DEFAULT_Q0_INT_BIT << netdev->dev_id,
1418 geth->base + GLOBAL_INTERRUPT_STATUS_1_REG);
1419 r = rw.bits.rptr;
1420 w = rw.bits.wptr;
1421
1422 while (budget && w != r) {
1423 rx = port->rxq_ring + r;
1424 word0 = rx->word0;
1425 word1 = rx->word1;
1426 mapping = rx->word2.buf_adr;
1427 word3 = rx->word3;
1428
1429 r++;
1430 r &= m;
1431
1432 frag_len = word0.bits.buffer_size;
1433 frame_len = word1.bits.byte_count;
1434 page_offs = mapping & ~PAGE_MASK;
1435
1436 if (!mapping) {
1437 netdev_err(netdev,
1438 "rxq[%u]: HW BUG: zero DMA desc\n", r);
1439 goto err_drop;
1440 }
1441
1442 /* Freeq pointers are one page off */
1443 gpage = gmac_get_queue_page(geth, port, mapping + PAGE_SIZE);
1444 if (!gpage) {
1445 dev_err(geth->dev, "could not find mapping\n");
1446 continue;
1447 }
1448 page = gpage->page;
1449
1450 if (word3.bits32 & SOF_BIT) {
1451 if (skb) {
1452 napi_free_frags(&port->napi);
1453 port->stats.rx_dropped++;
1454 }
1455
1456 skb = gmac_skb_if_good_frame(port, word0, frame_len);
1457 if (!skb)
1458 goto err_drop;
1459
1460 page_offs += NET_IP_ALIGN;
1461 frag_len -= NET_IP_ALIGN;
1462 frag_nr = 0;
1463
1464 } else if (!skb) {
1465 put_page(page);
1466 continue;
1467 }
1468
1469 if (word3.bits32 & EOF_BIT)
1470 frag_len = frame_len - skb->len;
1471
1472 /* append page frag to skb */
1473 if (frag_nr == MAX_SKB_FRAGS)
1474 goto err_drop;
1475
1476 if (frag_len == 0)
1477 netdev_err(netdev, "Received fragment with len = 0\n");
1478
1479 skb_fill_page_desc(skb, frag_nr, page, page_offs, frag_len);
1480 skb->len += frag_len;
1481 skb->data_len += frag_len;
1482 skb->truesize += frag_len;
1483 frag_nr++;
1484
1485 if (word3.bits32 & EOF_BIT) {
1486 napi_gro_frags(&port->napi);
1487 skb = NULL;
1488 --budget;
1489 }
1490 continue;
1491
1492 err_drop:
1493 if (skb) {
1494 napi_free_frags(&port->napi);
1495 skb = NULL;
1496 }
1497
1498 if (mapping)
1499 put_page(page);
1500
1501 port->stats.rx_dropped++;
1502 }
1503
1504 writew(r, ptr_reg);
1505 return budget;
1506 }
1507
1508 static int gmac_napi_poll(struct napi_struct *napi, int budget)
1509 {
1510 struct gemini_ethernet_port *port = netdev_priv(napi->dev);
1511 struct gemini_ethernet *geth = port->geth;
1512 unsigned int freeq_threshold;
1513 unsigned int received;
1514
1515 freeq_threshold = 1 << (geth->freeq_order - 1);
1516 u64_stats_update_begin(&port->rx_stats_syncp);
1517
1518 received = gmac_rx(napi->dev, budget);
1519 if (received < budget) {
1520 napi_gro_flush(napi, false);
1521 napi_complete_done(napi, received);
1522 gmac_enable_rx_irq(napi->dev, 1);
1523 ++port->rx_napi_exits;
1524 }
1525
1526 port->freeq_refill += (budget - received);
1527 if (port->freeq_refill > freeq_threshold) {
1528 port->freeq_refill -= freeq_threshold;
1529 geth_fill_freeq(geth, true);
1530 }
1531
1532 u64_stats_update_end(&port->rx_stats_syncp);
1533 return received;
1534 }
1535
1536 static void gmac_dump_dma_state(struct net_device *netdev)
1537 {
1538 struct gemini_ethernet_port *port = netdev_priv(netdev);
1539 struct gemini_ethernet *geth = port->geth;
1540 void __iomem *ptr_reg;
1541 u32 reg[5];
1542
1543 /* Interrupt status */
1544 reg[0] = readl(geth->base + GLOBAL_INTERRUPT_STATUS_0_REG);
1545 reg[1] = readl(geth->base + GLOBAL_INTERRUPT_STATUS_1_REG);
1546 reg[2] = readl(geth->base + GLOBAL_INTERRUPT_STATUS_2_REG);
1547 reg[3] = readl(geth->base + GLOBAL_INTERRUPT_STATUS_3_REG);
1548 reg[4] = readl(geth->base + GLOBAL_INTERRUPT_STATUS_4_REG);
1549 netdev_err(netdev, "IRQ status: 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n",
1550 reg[0], reg[1], reg[2], reg[3], reg[4]);
1551
1552 /* Interrupt enable */
1553 reg[0] = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_0_REG);
1554 reg[1] = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_1_REG);
1555 reg[2] = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_2_REG);
1556 reg[3] = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_3_REG);
1557 reg[4] = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG);
1558 netdev_err(netdev, "IRQ enable: 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n",
1559 reg[0], reg[1], reg[2], reg[3], reg[4]);
1560
1561 /* RX DMA status */
1562 reg[0] = readl(port->dma_base + GMAC_DMA_RX_FIRST_DESC_REG);
1563 reg[1] = readl(port->dma_base + GMAC_DMA_RX_CURR_DESC_REG);
1564 reg[2] = GET_RPTR(port->rxq_rwptr);
1565 reg[3] = GET_WPTR(port->rxq_rwptr);
1566 netdev_err(netdev, "RX DMA regs: 0x%08x 0x%08x, ptr: %u %u\n",
1567 reg[0], reg[1], reg[2], reg[3]);
1568
1569 reg[0] = readl(port->dma_base + GMAC_DMA_RX_DESC_WORD0_REG);
1570 reg[1] = readl(port->dma_base + GMAC_DMA_RX_DESC_WORD1_REG);
1571 reg[2] = readl(port->dma_base + GMAC_DMA_RX_DESC_WORD2_REG);
1572 reg[3] = readl(port->dma_base + GMAC_DMA_RX_DESC_WORD3_REG);
1573 netdev_err(netdev, "RX DMA descriptor: 0x%08x 0x%08x 0x%08x 0x%08x\n",
1574 reg[0], reg[1], reg[2], reg[3]);
1575
1576 /* TX DMA status */
1577 ptr_reg = port->dma_base + GMAC_SW_TX_QUEUE0_PTR_REG;
1578
1579 reg[0] = readl(port->dma_base + GMAC_DMA_TX_FIRST_DESC_REG);
1580 reg[1] = readl(port->dma_base + GMAC_DMA_TX_CURR_DESC_REG);
1581 reg[2] = GET_RPTR(ptr_reg);
1582 reg[3] = GET_WPTR(ptr_reg);
1583 netdev_err(netdev, "TX DMA regs: 0x%08x 0x%08x, ptr: %u %u\n",
1584 reg[0], reg[1], reg[2], reg[3]);
1585
1586 reg[0] = readl(port->dma_base + GMAC_DMA_TX_DESC_WORD0_REG);
1587 reg[1] = readl(port->dma_base + GMAC_DMA_TX_DESC_WORD1_REG);
1588 reg[2] = readl(port->dma_base + GMAC_DMA_TX_DESC_WORD2_REG);
1589 reg[3] = readl(port->dma_base + GMAC_DMA_TX_DESC_WORD3_REG);
1590 netdev_err(netdev, "TX DMA descriptor: 0x%08x 0x%08x 0x%08x 0x%08x\n",
1591 reg[0], reg[1], reg[2], reg[3]);
1592
1593 /* FREE queues status */
1594 ptr_reg = geth->base + GLOBAL_SWFQ_RWPTR_REG;
1595
1596 reg[0] = GET_RPTR(ptr_reg);
1597 reg[1] = GET_WPTR(ptr_reg);
1598
1599 ptr_reg = geth->base + GLOBAL_HWFQ_RWPTR_REG;
1600
1601 reg[2] = GET_RPTR(ptr_reg);
1602 reg[3] = GET_WPTR(ptr_reg);
1603 netdev_err(netdev, "FQ SW ptr: %u %u, HW ptr: %u %u\n",
1604 reg[0], reg[1], reg[2], reg[3]);
1605 }
1606
1607 static void gmac_update_hw_stats(struct net_device *netdev)
1608 {
1609 struct gemini_ethernet_port *port = netdev_priv(netdev);
1610 unsigned int rx_discards, rx_mcast, rx_bcast;
1611 struct gemini_ethernet *geth = port->geth;
1612 unsigned long flags;
1613
1614 spin_lock_irqsave(&geth->irq_lock, flags);
1615 u64_stats_update_begin(&port->ir_stats_syncp);
1616
1617 rx_discards = readl(port->gmac_base + GMAC_IN_DISCARDS);
1618 port->hw_stats[0] += rx_discards;
1619 port->hw_stats[1] += readl(port->gmac_base + GMAC_IN_ERRORS);
1620 rx_mcast = readl(port->gmac_base + GMAC_IN_MCAST);
1621 port->hw_stats[2] += rx_mcast;
1622 rx_bcast = readl(port->gmac_base + GMAC_IN_BCAST);
1623 port->hw_stats[3] += rx_bcast;
1624 port->hw_stats[4] += readl(port->gmac_base + GMAC_IN_MAC1);
1625 port->hw_stats[5] += readl(port->gmac_base + GMAC_IN_MAC2);
1626
1627 port->stats.rx_missed_errors += rx_discards;
1628 port->stats.multicast += rx_mcast;
1629 port->stats.multicast += rx_bcast;
1630
1631 writel(GMAC0_MIB_INT_BIT << (netdev->dev_id * 8),
1632 geth->base + GLOBAL_INTERRUPT_STATUS_4_REG);
1633
1634 u64_stats_update_end(&port->ir_stats_syncp);
1635 spin_unlock_irqrestore(&geth->irq_lock, flags);
1636 }
1637
1638 /**
1639 * gmac_get_intr_flags() - get interrupt status flags for a port from
1640 * @netdev: the net device for the port to get flags from
1641 * @i: the interrupt status register 0..4
1642 */
1643 static u32 gmac_get_intr_flags(struct net_device *netdev, int i)
1644 {
1645 struct gemini_ethernet_port *port = netdev_priv(netdev);
1646 struct gemini_ethernet *geth = port->geth;
1647 void __iomem *irqif_reg, *irqen_reg;
1648 unsigned int offs, val;
1649
1650 /* Calculate the offset using the stride of the status registers */
1651 offs = i * (GLOBAL_INTERRUPT_STATUS_1_REG -
1652 GLOBAL_INTERRUPT_STATUS_0_REG);
1653
1654 irqif_reg = geth->base + GLOBAL_INTERRUPT_STATUS_0_REG + offs;
1655 irqen_reg = geth->base + GLOBAL_INTERRUPT_ENABLE_0_REG + offs;
1656
1657 val = readl(irqif_reg) & readl(irqen_reg);
1658 return val;
1659 }
1660
1661 static enum hrtimer_restart gmac_coalesce_delay_expired(struct hrtimer *timer)
1662 {
1663 struct gemini_ethernet_port *port =
1664 container_of(timer, struct gemini_ethernet_port,
1665 rx_coalesce_timer);
1666
1667 napi_schedule(&port->napi);
1668 return HRTIMER_NORESTART;
1669 }
1670
1671 static irqreturn_t gmac_irq(int irq, void *data)
1672 {
1673 struct gemini_ethernet_port *port;
1674 struct net_device *netdev = data;
1675 struct gemini_ethernet *geth;
1676 u32 val, orr = 0;
1677
1678 port = netdev_priv(netdev);
1679 geth = port->geth;
1680
1681 val = gmac_get_intr_flags(netdev, 0);
1682 orr |= val;
1683
1684 if (val & (GMAC0_IRQ0_2 << (netdev->dev_id * 2))) {
1685 /* Oh, crap */
1686 netdev_err(netdev, "hw failure/sw bug\n");
1687 gmac_dump_dma_state(netdev);
1688
1689 /* don't know how to recover, just reduce losses */
1690 gmac_enable_irq(netdev, 0);
1691 return IRQ_HANDLED;
1692 }
1693
1694 if (val & (GMAC0_IRQ0_TXQ0_INTS << (netdev->dev_id * 6)))
1695 gmac_tx_irq(netdev, 0);
1696
1697 val = gmac_get_intr_flags(netdev, 1);
1698 orr |= val;
1699
1700 if (val & (DEFAULT_Q0_INT_BIT << netdev->dev_id)) {
1701 gmac_enable_rx_irq(netdev, 0);
1702
1703 if (!port->rx_coalesce_nsecs) {
1704 napi_schedule(&port->napi);
1705 } else {
1706 ktime_t ktime;
1707
1708 ktime = ktime_set(0, port->rx_coalesce_nsecs);
1709 hrtimer_start(&port->rx_coalesce_timer, ktime,
1710 HRTIMER_MODE_REL);
1711 }
1712 }
1713
1714 val = gmac_get_intr_flags(netdev, 4);
1715 orr |= val;
1716
1717 if (val & (GMAC0_MIB_INT_BIT << (netdev->dev_id * 8)))
1718 gmac_update_hw_stats(netdev);
1719
1720 if (val & (GMAC0_RX_OVERRUN_INT_BIT << (netdev->dev_id * 8))) {
1721 writel(GMAC0_RXDERR_INT_BIT << (netdev->dev_id * 8),
1722 geth->base + GLOBAL_INTERRUPT_STATUS_4_REG);
1723
1724 spin_lock(&geth->irq_lock);
1725 u64_stats_update_begin(&port->ir_stats_syncp);
1726 ++port->stats.rx_fifo_errors;
1727 u64_stats_update_end(&port->ir_stats_syncp);
1728 spin_unlock(&geth->irq_lock);
1729 }
1730
1731 return orr ? IRQ_HANDLED : IRQ_NONE;
1732 }
1733
1734 static void gmac_start_dma(struct gemini_ethernet_port *port)
1735 {
1736 void __iomem *dma_ctrl_reg = port->dma_base + GMAC_DMA_CTRL_REG;
1737 union gmac_dma_ctrl dma_ctrl;
1738
1739 dma_ctrl.bits32 = readl(dma_ctrl_reg);
1740 dma_ctrl.bits.rd_enable = 1;
1741 dma_ctrl.bits.td_enable = 1;
1742 dma_ctrl.bits.loopback = 0;
1743 dma_ctrl.bits.drop_small_ack = 0;
1744 dma_ctrl.bits.rd_insert_bytes = NET_IP_ALIGN;
1745 dma_ctrl.bits.rd_prot = HPROT_DATA_CACHE | HPROT_PRIVILIGED;
1746 dma_ctrl.bits.rd_burst_size = HBURST_INCR8;
1747 dma_ctrl.bits.rd_bus = HSIZE_8;
1748 dma_ctrl.bits.td_prot = HPROT_DATA_CACHE;
1749 dma_ctrl.bits.td_burst_size = HBURST_INCR8;
1750 dma_ctrl.bits.td_bus = HSIZE_8;
1751
1752 writel(dma_ctrl.bits32, dma_ctrl_reg);
1753 }
1754
1755 static void gmac_stop_dma(struct gemini_ethernet_port *port)
1756 {
1757 void __iomem *dma_ctrl_reg = port->dma_base + GMAC_DMA_CTRL_REG;
1758 union gmac_dma_ctrl dma_ctrl;
1759
1760 dma_ctrl.bits32 = readl(dma_ctrl_reg);
1761 dma_ctrl.bits.rd_enable = 0;
1762 dma_ctrl.bits.td_enable = 0;
1763 writel(dma_ctrl.bits32, dma_ctrl_reg);
1764 }
1765
1766 static int gmac_open(struct net_device *netdev)
1767 {
1768 struct gemini_ethernet_port *port = netdev_priv(netdev);
1769 int err;
1770
1771 if (!netdev->phydev) {
1772 err = gmac_setup_phy(netdev);
1773 if (err) {
1774 netif_err(port, ifup, netdev,
1775 "PHY init failed: %d\n", err);
1776 return err;
1777 }
1778 }
1779
1780 err = request_irq(netdev->irq, gmac_irq,
1781 IRQF_SHARED, netdev->name, netdev);
1782 if (err) {
1783 netdev_err(netdev, "no IRQ\n");
1784 return err;
1785 }
1786
1787 netif_carrier_off(netdev);
1788 phy_start(netdev->phydev);
1789
1790 err = geth_resize_freeq(port);
1791 /* It's fine if it's just busy, the other port has set up
1792 * the freeq in that case.
1793 */
1794 if (err && (err != -EBUSY)) {
1795 netdev_err(netdev, "could not resize freeq\n");
1796 goto err_stop_phy;
1797 }
1798
1799 err = gmac_setup_rxq(netdev);
1800 if (err) {
1801 netdev_err(netdev, "could not setup RXQ\n");
1802 goto err_stop_phy;
1803 }
1804
1805 err = gmac_setup_txqs(netdev);
1806 if (err) {
1807 netdev_err(netdev, "could not setup TXQs\n");
1808 gmac_cleanup_rxq(netdev);
1809 goto err_stop_phy;
1810 }
1811
1812 napi_enable(&port->napi);
1813
1814 gmac_start_dma(port);
1815 gmac_enable_irq(netdev, 1);
1816 gmac_enable_tx_rx(netdev);
1817 netif_tx_start_all_queues(netdev);
1818
1819 hrtimer_init(&port->rx_coalesce_timer, CLOCK_MONOTONIC,
1820 HRTIMER_MODE_REL);
1821 port->rx_coalesce_timer.function = &gmac_coalesce_delay_expired;
1822
1823 netdev_dbg(netdev, "opened\n");
1824
1825 return 0;
1826
1827 err_stop_phy:
1828 phy_stop(netdev->phydev);
1829 free_irq(netdev->irq, netdev);
1830 return err;
1831 }
1832
1833 static int gmac_stop(struct net_device *netdev)
1834 {
1835 struct gemini_ethernet_port *port = netdev_priv(netdev);
1836
1837 hrtimer_cancel(&port->rx_coalesce_timer);
1838 netif_tx_stop_all_queues(netdev);
1839 gmac_disable_tx_rx(netdev);
1840 gmac_stop_dma(port);
1841 napi_disable(&port->napi);
1842
1843 gmac_enable_irq(netdev, 0);
1844 gmac_cleanup_rxq(netdev);
1845 gmac_cleanup_txqs(netdev);
1846
1847 phy_stop(netdev->phydev);
1848 free_irq(netdev->irq, netdev);
1849
1850 gmac_update_hw_stats(netdev);
1851 return 0;
1852 }
1853
1854 static void gmac_set_rx_mode(struct net_device *netdev)
1855 {
1856 struct gemini_ethernet_port *port = netdev_priv(netdev);
1857 union gmac_rx_fltr filter = { .bits = {
1858 .broadcast = 1,
1859 .multicast = 1,
1860 .unicast = 1,
1861 } };
1862 struct netdev_hw_addr *ha;
1863 unsigned int bit_nr;
1864 u32 mc_filter[2];
1865
1866 mc_filter[1] = 0;
1867 mc_filter[0] = 0;
1868
1869 if (netdev->flags & IFF_PROMISC) {
1870 filter.bits.error = 1;
1871 filter.bits.promiscuous = 1;
1872 mc_filter[1] = ~0;
1873 mc_filter[0] = ~0;
1874 } else if (netdev->flags & IFF_ALLMULTI) {
1875 mc_filter[1] = ~0;
1876 mc_filter[0] = ~0;
1877 } else {
1878 netdev_for_each_mc_addr(ha, netdev) {
1879 bit_nr = ~crc32_le(~0, ha->addr, ETH_ALEN) & 0x3f;
1880 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 0x1f);
1881 }
1882 }
1883
1884 writel(mc_filter[0], port->gmac_base + GMAC_MCAST_FIL0);
1885 writel(mc_filter[1], port->gmac_base + GMAC_MCAST_FIL1);
1886 writel(filter.bits32, port->gmac_base + GMAC_RX_FLTR);
1887 }
1888
1889 static void gmac_write_mac_address(struct net_device *netdev)
1890 {
1891 struct gemini_ethernet_port *port = netdev_priv(netdev);
1892 __le32 addr[3];
1893
1894 memset(addr, 0, sizeof(addr));
1895 memcpy(addr, netdev->dev_addr, ETH_ALEN);
1896
1897 writel(le32_to_cpu(addr[0]), port->gmac_base + GMAC_STA_ADD0);
1898 writel(le32_to_cpu(addr[1]), port->gmac_base + GMAC_STA_ADD1);
1899 writel(le32_to_cpu(addr[2]), port->gmac_base + GMAC_STA_ADD2);
1900 }
1901
1902 static int gmac_set_mac_address(struct net_device *netdev, void *addr)
1903 {
1904 struct sockaddr *sa = addr;
1905
1906 memcpy(netdev->dev_addr, sa->sa_data, ETH_ALEN);
1907 gmac_write_mac_address(netdev);
1908
1909 return 0;
1910 }
1911
1912 static void gmac_clear_hw_stats(struct net_device *netdev)
1913 {
1914 struct gemini_ethernet_port *port = netdev_priv(netdev);
1915
1916 readl(port->gmac_base + GMAC_IN_DISCARDS);
1917 readl(port->gmac_base + GMAC_IN_ERRORS);
1918 readl(port->gmac_base + GMAC_IN_MCAST);
1919 readl(port->gmac_base + GMAC_IN_BCAST);
1920 readl(port->gmac_base + GMAC_IN_MAC1);
1921 readl(port->gmac_base + GMAC_IN_MAC2);
1922 }
1923
1924 static void gmac_get_stats64(struct net_device *netdev,
1925 struct rtnl_link_stats64 *stats)
1926 {
1927 struct gemini_ethernet_port *port = netdev_priv(netdev);
1928 unsigned int start;
1929
1930 gmac_update_hw_stats(netdev);
1931
1932 /* Racing with RX NAPI */
1933 do {
1934 start = u64_stats_fetch_begin(&port->rx_stats_syncp);
1935
1936 stats->rx_packets = port->stats.rx_packets;
1937 stats->rx_bytes = port->stats.rx_bytes;
1938 stats->rx_errors = port->stats.rx_errors;
1939 stats->rx_dropped = port->stats.rx_dropped;
1940
1941 stats->rx_length_errors = port->stats.rx_length_errors;
1942 stats->rx_over_errors = port->stats.rx_over_errors;
1943 stats->rx_crc_errors = port->stats.rx_crc_errors;
1944 stats->rx_frame_errors = port->stats.rx_frame_errors;
1945
1946 } while (u64_stats_fetch_retry(&port->rx_stats_syncp, start));
1947
1948 /* Racing with MIB and TX completion interrupts */
1949 do {
1950 start = u64_stats_fetch_begin(&port->ir_stats_syncp);
1951
1952 stats->tx_errors = port->stats.tx_errors;
1953 stats->tx_packets = port->stats.tx_packets;
1954 stats->tx_bytes = port->stats.tx_bytes;
1955
1956 stats->multicast = port->stats.multicast;
1957 stats->rx_missed_errors = port->stats.rx_missed_errors;
1958 stats->rx_fifo_errors = port->stats.rx_fifo_errors;
1959
1960 } while (u64_stats_fetch_retry(&port->ir_stats_syncp, start));
1961
1962 /* Racing with hard_start_xmit */
1963 do {
1964 start = u64_stats_fetch_begin(&port->tx_stats_syncp);
1965
1966 stats->tx_dropped = port->stats.tx_dropped;
1967
1968 } while (u64_stats_fetch_retry(&port->tx_stats_syncp, start));
1969
1970 stats->rx_dropped += stats->rx_missed_errors;
1971 }
1972
1973 static int gmac_change_mtu(struct net_device *netdev, int new_mtu)
1974 {
1975 int max_len = gmac_pick_rx_max_len(new_mtu);
1976
1977 if (max_len < 0)
1978 return -EINVAL;
1979
1980 gmac_disable_tx_rx(netdev);
1981
1982 netdev->mtu = new_mtu;
1983 gmac_update_config0_reg(netdev, max_len << CONFIG0_MAXLEN_SHIFT,
1984 CONFIG0_MAXLEN_MASK);
1985
1986 netdev_update_features(netdev);
1987
1988 gmac_enable_tx_rx(netdev);
1989
1990 return 0;
1991 }
1992
1993 static netdev_features_t gmac_fix_features(struct net_device *netdev,
1994 netdev_features_t features)
1995 {
1996 if (netdev->mtu + ETH_HLEN + VLAN_HLEN > MTU_SIZE_BIT_MASK)
1997 features &= ~GMAC_OFFLOAD_FEATURES;
1998
1999 return features;
2000 }
2001
2002 static int gmac_set_features(struct net_device *netdev,
2003 netdev_features_t features)
2004 {
2005 struct gemini_ethernet_port *port = netdev_priv(netdev);
2006 int enable = features & NETIF_F_RXCSUM;
2007 unsigned long flags;
2008 u32 reg;
2009
2010 spin_lock_irqsave(&port->config_lock, flags);
2011
2012 reg = readl(port->gmac_base + GMAC_CONFIG0);
2013 reg = enable ? reg | CONFIG0_RX_CHKSUM : reg & ~CONFIG0_RX_CHKSUM;
2014 writel(reg, port->gmac_base + GMAC_CONFIG0);
2015
2016 spin_unlock_irqrestore(&port->config_lock, flags);
2017 return 0;
2018 }
2019
2020 static int gmac_get_sset_count(struct net_device *netdev, int sset)
2021 {
2022 return sset == ETH_SS_STATS ? GMAC_STATS_NUM : 0;
2023 }
2024
2025 static void gmac_get_strings(struct net_device *netdev, u32 stringset, u8 *data)
2026 {
2027 if (stringset != ETH_SS_STATS)
2028 return;
2029
2030 memcpy(data, gmac_stats_strings, sizeof(gmac_stats_strings));
2031 }
2032
2033 static void gmac_get_ethtool_stats(struct net_device *netdev,
2034 struct ethtool_stats *estats, u64 *values)
2035 {
2036 struct gemini_ethernet_port *port = netdev_priv(netdev);
2037 unsigned int start;
2038 u64 *p;
2039 int i;
2040
2041 gmac_update_hw_stats(netdev);
2042
2043 /* Racing with MIB interrupt */
2044 do {
2045 p = values;
2046 start = u64_stats_fetch_begin(&port->ir_stats_syncp);
2047
2048 for (i = 0; i < RX_STATS_NUM; i++)
2049 *p++ = port->hw_stats[i];
2050
2051 } while (u64_stats_fetch_retry(&port->ir_stats_syncp, start));
2052 values = p;
2053
2054 /* Racing with RX NAPI */
2055 do {
2056 p = values;
2057 start = u64_stats_fetch_begin(&port->rx_stats_syncp);
2058
2059 for (i = 0; i < RX_STATUS_NUM; i++)
2060 *p++ = port->rx_stats[i];
2061 for (i = 0; i < RX_CHKSUM_NUM; i++)
2062 *p++ = port->rx_csum_stats[i];
2063 *p++ = port->rx_napi_exits;
2064
2065 } while (u64_stats_fetch_retry(&port->rx_stats_syncp, start));
2066 values = p;
2067
2068 /* Racing with TX start_xmit */
2069 do {
2070 p = values;
2071 start = u64_stats_fetch_begin(&port->tx_stats_syncp);
2072
2073 for (i = 0; i < TX_MAX_FRAGS; i++) {
2074 *values++ = port->tx_frag_stats[i];
2075 port->tx_frag_stats[i] = 0;
2076 }
2077 *values++ = port->tx_frags_linearized;
2078 *values++ = port->tx_hw_csummed;
2079
2080 } while (u64_stats_fetch_retry(&port->tx_stats_syncp, start));
2081 }
2082
2083 static int gmac_get_ksettings(struct net_device *netdev,
2084 struct ethtool_link_ksettings *cmd)
2085 {
2086 if (!netdev->phydev)
2087 return -ENXIO;
2088 phy_ethtool_ksettings_get(netdev->phydev, cmd);
2089
2090 return 0;
2091 }
2092
2093 static int gmac_set_ksettings(struct net_device *netdev,
2094 const struct ethtool_link_ksettings *cmd)
2095 {
2096 if (!netdev->phydev)
2097 return -ENXIO;
2098 return phy_ethtool_ksettings_set(netdev->phydev, cmd);
2099 }
2100
2101 static int gmac_nway_reset(struct net_device *netdev)
2102 {
2103 if (!netdev->phydev)
2104 return -ENXIO;
2105 return phy_start_aneg(netdev->phydev);
2106 }
2107
2108 static void gmac_get_pauseparam(struct net_device *netdev,
2109 struct ethtool_pauseparam *pparam)
2110 {
2111 struct gemini_ethernet_port *port = netdev_priv(netdev);
2112 union gmac_config0 config0;
2113
2114 config0.bits32 = readl(port->gmac_base + GMAC_CONFIG0);
2115
2116 pparam->rx_pause = config0.bits.rx_fc_en;
2117 pparam->tx_pause = config0.bits.tx_fc_en;
2118 pparam->autoneg = true;
2119 }
2120
2121 static void gmac_get_ringparam(struct net_device *netdev,
2122 struct ethtool_ringparam *rp)
2123 {
2124 struct gemini_ethernet_port *port = netdev_priv(netdev);
2125 union gmac_config0 config0;
2126
2127 config0.bits32 = readl(port->gmac_base + GMAC_CONFIG0);
2128
2129 rp->rx_max_pending = 1 << 15;
2130 rp->rx_mini_max_pending = 0;
2131 rp->rx_jumbo_max_pending = 0;
2132 rp->tx_max_pending = 1 << 15;
2133
2134 rp->rx_pending = 1 << port->rxq_order;
2135 rp->rx_mini_pending = 0;
2136 rp->rx_jumbo_pending = 0;
2137 rp->tx_pending = 1 << port->txq_order;
2138 }
2139
2140 static int gmac_set_ringparam(struct net_device *netdev,
2141 struct ethtool_ringparam *rp)
2142 {
2143 struct gemini_ethernet_port *port = netdev_priv(netdev);
2144 int err = 0;
2145
2146 if (netif_running(netdev))
2147 return -EBUSY;
2148
2149 if (rp->rx_pending) {
2150 port->rxq_order = min(15, ilog2(rp->rx_pending - 1) + 1);
2151 err = geth_resize_freeq(port);
2152 }
2153 if (rp->tx_pending) {
2154 port->txq_order = min(15, ilog2(rp->tx_pending - 1) + 1);
2155 port->irq_every_tx_packets = 1 << (port->txq_order - 2);
2156 }
2157
2158 return err;
2159 }
2160
2161 static int gmac_get_coalesce(struct net_device *netdev,
2162 struct ethtool_coalesce *ecmd)
2163 {
2164 struct gemini_ethernet_port *port = netdev_priv(netdev);
2165
2166 ecmd->rx_max_coalesced_frames = 1;
2167 ecmd->tx_max_coalesced_frames = port->irq_every_tx_packets;
2168 ecmd->rx_coalesce_usecs = port->rx_coalesce_nsecs / 1000;
2169
2170 return 0;
2171 }
2172
2173 static int gmac_set_coalesce(struct net_device *netdev,
2174 struct ethtool_coalesce *ecmd)
2175 {
2176 struct gemini_ethernet_port *port = netdev_priv(netdev);
2177
2178 if (ecmd->tx_max_coalesced_frames < 1)
2179 return -EINVAL;
2180 if (ecmd->tx_max_coalesced_frames >= 1 << port->txq_order)
2181 return -EINVAL;
2182
2183 port->irq_every_tx_packets = ecmd->tx_max_coalesced_frames;
2184 port->rx_coalesce_nsecs = ecmd->rx_coalesce_usecs * 1000;
2185
2186 return 0;
2187 }
2188
2189 static u32 gmac_get_msglevel(struct net_device *netdev)
2190 {
2191 struct gemini_ethernet_port *port = netdev_priv(netdev);
2192
2193 return port->msg_enable;
2194 }
2195
2196 static void gmac_set_msglevel(struct net_device *netdev, u32 level)
2197 {
2198 struct gemini_ethernet_port *port = netdev_priv(netdev);
2199
2200 port->msg_enable = level;
2201 }
2202
2203 static void gmac_get_drvinfo(struct net_device *netdev,
2204 struct ethtool_drvinfo *info)
2205 {
2206 strcpy(info->driver, DRV_NAME);
2207 strcpy(info->version, DRV_VERSION);
2208 strcpy(info->bus_info, netdev->dev_id ? "1" : "0");
2209 }
2210
2211 static const struct net_device_ops gmac_351x_ops = {
2212 .ndo_init = gmac_init,
2213 .ndo_uninit = gmac_uninit,
2214 .ndo_open = gmac_open,
2215 .ndo_stop = gmac_stop,
2216 .ndo_start_xmit = gmac_start_xmit,
2217 .ndo_tx_timeout = gmac_tx_timeout,
2218 .ndo_set_rx_mode = gmac_set_rx_mode,
2219 .ndo_set_mac_address = gmac_set_mac_address,
2220 .ndo_get_stats64 = gmac_get_stats64,
2221 .ndo_change_mtu = gmac_change_mtu,
2222 .ndo_fix_features = gmac_fix_features,
2223 .ndo_set_features = gmac_set_features,
2224 };
2225
2226 static const struct ethtool_ops gmac_351x_ethtool_ops = {
2227 .get_sset_count = gmac_get_sset_count,
2228 .get_strings = gmac_get_strings,
2229 .get_ethtool_stats = gmac_get_ethtool_stats,
2230 .get_link = ethtool_op_get_link,
2231 .get_link_ksettings = gmac_get_ksettings,
2232 .set_link_ksettings = gmac_set_ksettings,
2233 .nway_reset = gmac_nway_reset,
2234 .get_pauseparam = gmac_get_pauseparam,
2235 .get_ringparam = gmac_get_ringparam,
2236 .set_ringparam = gmac_set_ringparam,
2237 .get_coalesce = gmac_get_coalesce,
2238 .set_coalesce = gmac_set_coalesce,
2239 .get_msglevel = gmac_get_msglevel,
2240 .set_msglevel = gmac_set_msglevel,
2241 .get_drvinfo = gmac_get_drvinfo,
2242 };
2243
2244 static irqreturn_t gemini_port_irq_thread(int irq, void *data)
2245 {
2246 unsigned long irqmask = SWFQ_EMPTY_INT_BIT;
2247 struct gemini_ethernet_port *port = data;
2248 struct gemini_ethernet *geth;
2249 unsigned long flags;
2250
2251 geth = port->geth;
2252 /* The queue is half empty so refill it */
2253 geth_fill_freeq(geth, true);
2254
2255 spin_lock_irqsave(&geth->irq_lock, flags);
2256 /* ACK queue interrupt */
2257 writel(irqmask, geth->base + GLOBAL_INTERRUPT_STATUS_4_REG);
2258 /* Enable queue interrupt again */
2259 irqmask |= readl(geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG);
2260 writel(irqmask, geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG);
2261 spin_unlock_irqrestore(&geth->irq_lock, flags);
2262
2263 return IRQ_HANDLED;
2264 }
2265
2266 static irqreturn_t gemini_port_irq(int irq, void *data)
2267 {
2268 struct gemini_ethernet_port *port = data;
2269 struct gemini_ethernet *geth;
2270 irqreturn_t ret = IRQ_NONE;
2271 u32 val, en;
2272
2273 geth = port->geth;
2274 spin_lock(&geth->irq_lock);
2275
2276 val = readl(geth->base + GLOBAL_INTERRUPT_STATUS_4_REG);
2277 en = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG);
2278
2279 if (val & en & SWFQ_EMPTY_INT_BIT) {
2280 /* Disable the queue empty interrupt while we work on
2281 * processing the queue. Also disable overrun interrupts
2282 * as there is not much we can do about it here.
2283 */
2284 en &= ~(SWFQ_EMPTY_INT_BIT | GMAC0_RX_OVERRUN_INT_BIT
2285 | GMAC1_RX_OVERRUN_INT_BIT);
2286 writel(en, geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG);
2287 ret = IRQ_WAKE_THREAD;
2288 }
2289
2290 spin_unlock(&geth->irq_lock);
2291
2292 return ret;
2293 }
2294
2295 static void gemini_port_remove(struct gemini_ethernet_port *port)
2296 {
2297 if (port->netdev)
2298 unregister_netdev(port->netdev);
2299 clk_disable_unprepare(port->pclk);
2300 geth_cleanup_freeq(port->geth);
2301 }
2302
2303 static void gemini_ethernet_init(struct gemini_ethernet *geth)
2304 {
2305 /* Only do this once both ports are online */
2306 if (geth->initialized)
2307 return;
2308 if (geth->port0 && geth->port1)
2309 geth->initialized = true;
2310 else
2311 return;
2312
2313 writel(0, geth->base + GLOBAL_INTERRUPT_ENABLE_0_REG);
2314 writel(0, geth->base + GLOBAL_INTERRUPT_ENABLE_1_REG);
2315 writel(0, geth->base + GLOBAL_INTERRUPT_ENABLE_2_REG);
2316 writel(0, geth->base + GLOBAL_INTERRUPT_ENABLE_3_REG);
2317 writel(0, geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG);
2318
2319 /* Interrupt config:
2320 *
2321 * GMAC0 intr bits ------> int0 ----> eth0
2322 * GMAC1 intr bits ------> int1 ----> eth1
2323 * TOE intr -------------> int1 ----> eth1
2324 * Classification Intr --> int0 ----> eth0
2325 * Default Q0 -----------> int0 ----> eth0
2326 * Default Q1 -----------> int1 ----> eth1
2327 * FreeQ intr -----------> int1 ----> eth1
2328 */
2329 writel(0xCCFC0FC0, geth->base + GLOBAL_INTERRUPT_SELECT_0_REG);
2330 writel(0x00F00002, geth->base + GLOBAL_INTERRUPT_SELECT_1_REG);
2331 writel(0xFFFFFFFF, geth->base + GLOBAL_INTERRUPT_SELECT_2_REG);
2332 writel(0xFFFFFFFF, geth->base + GLOBAL_INTERRUPT_SELECT_3_REG);
2333 writel(0xFF000003, geth->base + GLOBAL_INTERRUPT_SELECT_4_REG);
2334
2335 /* edge-triggered interrupts packed to level-triggered one... */
2336 writel(~0, geth->base + GLOBAL_INTERRUPT_STATUS_0_REG);
2337 writel(~0, geth->base + GLOBAL_INTERRUPT_STATUS_1_REG);
2338 writel(~0, geth->base + GLOBAL_INTERRUPT_STATUS_2_REG);
2339 writel(~0, geth->base + GLOBAL_INTERRUPT_STATUS_3_REG);
2340 writel(~0, geth->base + GLOBAL_INTERRUPT_STATUS_4_REG);
2341
2342 /* Set up queue */
2343 writel(0, geth->base + GLOBAL_SW_FREEQ_BASE_SIZE_REG);
2344 writel(0, geth->base + GLOBAL_HW_FREEQ_BASE_SIZE_REG);
2345 writel(0, geth->base + GLOBAL_SWFQ_RWPTR_REG);
2346 writel(0, geth->base + GLOBAL_HWFQ_RWPTR_REG);
2347
2348 geth->freeq_frag_order = DEFAULT_RX_BUF_ORDER;
2349 /* This makes the queue resize on probe() so that we
2350 * set up and enable the queue IRQ. FIXME: fragile.
2351 */
2352 geth->freeq_order = 1;
2353 }
2354
2355 static void gemini_port_save_mac_addr(struct gemini_ethernet_port *port)
2356 {
2357 port->mac_addr[0] =
2358 cpu_to_le32(readl(port->gmac_base + GMAC_STA_ADD0));
2359 port->mac_addr[1] =
2360 cpu_to_le32(readl(port->gmac_base + GMAC_STA_ADD1));
2361 port->mac_addr[2] =
2362 cpu_to_le32(readl(port->gmac_base + GMAC_STA_ADD2));
2363 }
2364
2365 static int gemini_ethernet_port_probe(struct platform_device *pdev)
2366 {
2367 char *port_names[2] = { "ethernet0", "ethernet1" };
2368 struct gemini_ethernet_port *port;
2369 struct device *dev = &pdev->dev;
2370 struct gemini_ethernet *geth;
2371 struct net_device *netdev;
2372 struct resource *gmacres;
2373 struct resource *dmares;
2374 struct device *parent;
2375 unsigned int id;
2376 int irq;
2377 int ret;
2378
2379 parent = dev->parent;
2380 geth = dev_get_drvdata(parent);
2381
2382 if (!strcmp(dev_name(dev), "60008000.ethernet-port"))
2383 id = 0;
2384 else if (!strcmp(dev_name(dev), "6000c000.ethernet-port"))
2385 id = 1;
2386 else
2387 return -ENODEV;
2388
2389 dev_info(dev, "probe %s ID %d\n", dev_name(dev), id);
2390
2391 netdev = alloc_etherdev_mq(sizeof(*port), TX_QUEUE_NUM);
2392 if (!netdev) {
2393 dev_err(dev, "Can't allocate ethernet device #%d\n", id);
2394 return -ENOMEM;
2395 }
2396
2397 port = netdev_priv(netdev);
2398 SET_NETDEV_DEV(netdev, dev);
2399 port->netdev = netdev;
2400 port->id = id;
2401 port->geth = geth;
2402 port->dev = dev;
2403 port->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
2404
2405 /* DMA memory */
2406 dmares = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2407 if (!dmares) {
2408 dev_err(dev, "no DMA resource\n");
2409 return -ENODEV;
2410 }
2411 port->dma_base = devm_ioremap_resource(dev, dmares);
2412 if (IS_ERR(port->dma_base))
2413 return PTR_ERR(port->dma_base);
2414
2415 /* GMAC config memory */
2416 gmacres = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2417 if (!gmacres) {
2418 dev_err(dev, "no GMAC resource\n");
2419 return -ENODEV;
2420 }
2421 port->gmac_base = devm_ioremap_resource(dev, gmacres);
2422 if (IS_ERR(port->gmac_base))
2423 return PTR_ERR(port->gmac_base);
2424
2425 /* Interrupt */
2426 irq = platform_get_irq(pdev, 0);
2427 if (irq <= 0)
2428 return irq ? irq : -ENODEV;
2429 port->irq = irq;
2430
2431 /* Clock the port */
2432 port->pclk = devm_clk_get(dev, "PCLK");
2433 if (IS_ERR(port->pclk)) {
2434 dev_err(dev, "no PCLK\n");
2435 return PTR_ERR(port->pclk);
2436 }
2437 ret = clk_prepare_enable(port->pclk);
2438 if (ret)
2439 return ret;
2440
2441 /* Maybe there is a nice ethernet address we should use */
2442 gemini_port_save_mac_addr(port);
2443
2444 /* Reset the port */
2445 port->reset = devm_reset_control_get_exclusive(dev, NULL);
2446 if (IS_ERR(port->reset)) {
2447 dev_err(dev, "no reset\n");
2448 return PTR_ERR(port->reset);
2449 }
2450 reset_control_reset(port->reset);
2451 usleep_range(100, 500);
2452
2453 /* Assign pointer in the main state container */
2454 if (!id)
2455 geth->port0 = port;
2456 else
2457 geth->port1 = port;
2458
2459 /* This will just be done once both ports are up and reset */
2460 gemini_ethernet_init(geth);
2461
2462 platform_set_drvdata(pdev, port);
2463
2464 /* Set up and register the netdev */
2465 netdev->dev_id = port->id;
2466 netdev->irq = irq;
2467 netdev->netdev_ops = &gmac_351x_ops;
2468 netdev->ethtool_ops = &gmac_351x_ethtool_ops;
2469
2470 spin_lock_init(&port->config_lock);
2471 gmac_clear_hw_stats(netdev);
2472
2473 netdev->hw_features = GMAC_OFFLOAD_FEATURES;
2474 netdev->features |= GMAC_OFFLOAD_FEATURES | NETIF_F_GRO;
2475 /* We can handle jumbo frames up to 10236 bytes so, let's accept
2476 * payloads of 10236 bytes minus VLAN and ethernet header
2477 */
2478 netdev->min_mtu = ETH_MIN_MTU;
2479 netdev->max_mtu = 10236 - VLAN_ETH_HLEN;
2480
2481 port->freeq_refill = 0;
2482 netif_napi_add(netdev, &port->napi, gmac_napi_poll,
2483 DEFAULT_NAPI_WEIGHT);
2484
2485 if (is_valid_ether_addr((void *)port->mac_addr)) {
2486 memcpy(netdev->dev_addr, port->mac_addr, ETH_ALEN);
2487 } else {
2488 dev_dbg(dev, "ethernet address 0x%08x%08x%08x invalid\n",
2489 port->mac_addr[0], port->mac_addr[1],
2490 port->mac_addr[2]);
2491 dev_info(dev, "using a random ethernet address\n");
2492 eth_random_addr(netdev->dev_addr);
2493 }
2494 gmac_write_mac_address(netdev);
2495
2496 ret = devm_request_threaded_irq(port->dev,
2497 port->irq,
2498 gemini_port_irq,
2499 gemini_port_irq_thread,
2500 IRQF_SHARED,
2501 port_names[port->id],
2502 port);
2503 if (ret)
2504 return ret;
2505
2506 ret = register_netdev(netdev);
2507 if (!ret) {
2508 netdev_info(netdev,
2509 "irq %d, DMA @ 0x%pap, GMAC @ 0x%pap\n",
2510 port->irq, &dmares->start,
2511 &gmacres->start);
2512 ret = gmac_setup_phy(netdev);
2513 if (ret)
2514 netdev_info(netdev,
2515 "PHY init failed, deferring to ifup time\n");
2516 return 0;
2517 }
2518
2519 port->netdev = NULL;
2520 free_netdev(netdev);
2521 return ret;
2522 }
2523
2524 static int gemini_ethernet_port_remove(struct platform_device *pdev)
2525 {
2526 struct gemini_ethernet_port *port = platform_get_drvdata(pdev);
2527
2528 gemini_port_remove(port);
2529 free_netdev(port->netdev);
2530 return 0;
2531 }
2532
2533 static const struct of_device_id gemini_ethernet_port_of_match[] = {
2534 {
2535 .compatible = "cortina,gemini-ethernet-port",
2536 },
2537 {},
2538 };
2539 MODULE_DEVICE_TABLE(of, gemini_ethernet_port_of_match);
2540
2541 static struct platform_driver gemini_ethernet_port_driver = {
2542 .driver = {
2543 .name = "gemini-ethernet-port",
2544 .of_match_table = of_match_ptr(gemini_ethernet_port_of_match),
2545 },
2546 .probe = gemini_ethernet_port_probe,
2547 .remove = gemini_ethernet_port_remove,
2548 };
2549
2550 static int gemini_ethernet_probe(struct platform_device *pdev)
2551 {
2552 struct device *dev = &pdev->dev;
2553 struct gemini_ethernet *geth;
2554 unsigned int retry = 5;
2555 struct resource *res;
2556 u32 val;
2557
2558 /* Global registers */
2559 geth = devm_kzalloc(dev, sizeof(*geth), GFP_KERNEL);
2560 if (!geth)
2561 return -ENOMEM;
2562 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2563 if (!res)
2564 return -ENODEV;
2565 geth->base = devm_ioremap_resource(dev, res);
2566 if (IS_ERR(geth->base))
2567 return PTR_ERR(geth->base);
2568 geth->dev = dev;
2569
2570 /* Wait for ports to stabilize */
2571 do {
2572 udelay(2);
2573 val = readl(geth->base + GLOBAL_TOE_VERSION_REG);
2574 barrier();
2575 } while (!val && --retry);
2576 if (!retry) {
2577 dev_err(dev, "failed to reset ethernet\n");
2578 return -EIO;
2579 }
2580 dev_info(dev, "Ethernet device ID: 0x%03x, revision 0x%01x\n",
2581 (val >> 4) & 0xFFFU, val & 0xFU);
2582
2583 spin_lock_init(&geth->irq_lock);
2584 spin_lock_init(&geth->freeq_lock);
2585
2586 /* The children will use this */
2587 platform_set_drvdata(pdev, geth);
2588
2589 /* Spawn child devices for the two ports */
2590 return devm_of_platform_populate(dev);
2591 }
2592
2593 static int gemini_ethernet_remove(struct platform_device *pdev)
2594 {
2595 struct gemini_ethernet *geth = platform_get_drvdata(pdev);
2596
2597 geth_cleanup_freeq(geth);
2598 geth->initialized = false;
2599
2600 return 0;
2601 }
2602
2603 static const struct of_device_id gemini_ethernet_of_match[] = {
2604 {
2605 .compatible = "cortina,gemini-ethernet",
2606 },
2607 {},
2608 };
2609 MODULE_DEVICE_TABLE(of, gemini_ethernet_of_match);
2610
2611 static struct platform_driver gemini_ethernet_driver = {
2612 .driver = {
2613 .name = DRV_NAME,
2614 .of_match_table = of_match_ptr(gemini_ethernet_of_match),
2615 },
2616 .probe = gemini_ethernet_probe,
2617 .remove = gemini_ethernet_remove,
2618 };
2619
2620 static int __init gemini_ethernet_module_init(void)
2621 {
2622 int ret;
2623
2624 ret = platform_driver_register(&gemini_ethernet_port_driver);
2625 if (ret)
2626 return ret;
2627
2628 ret = platform_driver_register(&gemini_ethernet_driver);
2629 if (ret) {
2630 platform_driver_unregister(&gemini_ethernet_port_driver);
2631 return ret;
2632 }
2633
2634 return 0;
2635 }
2636 module_init(gemini_ethernet_module_init);
2637
2638 static void __exit gemini_ethernet_module_exit(void)
2639 {
2640 platform_driver_unregister(&gemini_ethernet_driver);
2641 platform_driver_unregister(&gemini_ethernet_port_driver);
2642 }
2643 module_exit(gemini_ethernet_module_exit);
2644
2645 MODULE_AUTHOR("Linus Walleij <linus.walleij@linaro.org>");
2646 MODULE_DESCRIPTION("StorLink SL351x (Gemini) ethernet driver");
2647 MODULE_LICENSE("GPL");
2648 MODULE_ALIAS("platform:" DRV_NAME);
Linux with added FPC-III support