drivers/net/ethernet/huawei/hinic/hinic_port.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * Huawei HiNIC PCI Express Linux driver
   4  * Copyright(c) 2017 Huawei Technologies Co., Ltd
   5  */
   6
   7 #ifndef HINIC_PORT_H
   8 #define HINIC_PORT_H
   9
  10 #include <linux/types.h>
  11 #include <linux/etherdevice.h>
  12 #include <linux/bitops.h>
  13
  14 #include "hinic_dev.h"
  15
  16 #define HINIC_RSS_KEY_SIZE      40
  17 #define HINIC_RSS_INDIR_SIZE    256
  18 #define HINIC_PORT_STATS_VERSION        0
  19 #define HINIC_FW_VERSION_NAME   16
  20 #define HINIC_COMPILE_TIME_LEN  20
  21 #define HINIC_MGMT_VERSION_MAX_LEN      32
  22
  23 struct hinic_version_info {
  24         u8 status;
  25         u8 version;
  26         u8 rsvd[6];
  27
  28         u8 ver[HINIC_FW_VERSION_NAME];
  29         u8 time[HINIC_COMPILE_TIME_LEN];
  30 };
  31
  32 enum hinic_rx_mode {
  33         HINIC_RX_MODE_UC        = BIT(0),
  34         HINIC_RX_MODE_MC        = BIT(1),
  35         HINIC_RX_MODE_BC        = BIT(2),
  36         HINIC_RX_MODE_MC_ALL    = BIT(3),
  37         HINIC_RX_MODE_PROMISC   = BIT(4),
  38 };
  39
  40 enum hinic_port_link_state {
  41         HINIC_LINK_STATE_DOWN,
  42         HINIC_LINK_STATE_UP,
  43 };
  44
  45 enum hinic_port_state {
  46         HINIC_PORT_DISABLE      = 0,
  47         HINIC_PORT_ENABLE       = 3,
  48 };
  49
  50 enum hinic_func_port_state {
  51         HINIC_FUNC_PORT_DISABLE = 0,
  52         HINIC_FUNC_PORT_ENABLE  = 2,
  53 };
  54
  55 enum hinic_autoneg_cap {
  56         HINIC_AUTONEG_UNSUPPORTED,
  57         HINIC_AUTONEG_SUPPORTED,
  58 };
  59
  60 enum hinic_autoneg_state {
  61         HINIC_AUTONEG_DISABLED,
  62         HINIC_AUTONEG_ACTIVE,
  63 };
  64
  65 enum hinic_duplex {
  66         HINIC_DUPLEX_HALF,
  67         HINIC_DUPLEX_FULL,
  68 };
  69
  70 enum hinic_speed {
  71         HINIC_SPEED_10MB_LINK = 0,
  72         HINIC_SPEED_100MB_LINK,
  73         HINIC_SPEED_1000MB_LINK,
  74         HINIC_SPEED_10GB_LINK,
  75         HINIC_SPEED_25GB_LINK,
  76         HINIC_SPEED_40GB_LINK,
  77         HINIC_SPEED_100GB_LINK,
  78
  79         HINIC_SPEED_UNKNOWN = 0xFF,
  80 };
  81
  82 enum hinic_tso_state {
  83         HINIC_TSO_DISABLE = 0,
  84         HINIC_TSO_ENABLE  = 1,
  85 };
  86
  87 struct hinic_port_mac_cmd {
  88         u8              status;
  89         u8              version;
  90         u8              rsvd0[6];
  91
  92         u16             func_idx;
  93         u16             vlan_id;
  94         u16             rsvd1;
  95         unsigned char   mac[ETH_ALEN];
  96 };
  97
  98 struct hinic_port_mtu_cmd {
  99         u8      status;
 100         u8      version;
 101         u8      rsvd0[6];
 102
 103         u16     func_idx;
 104         u16     rsvd1;
 105         u32     mtu;
 106 };
 107
 108 struct hinic_port_vlan_cmd {
 109         u8      status;
 110         u8      version;
 111         u8      rsvd0[6];
 112
 113         u16     func_idx;
 114         u16     vlan_id;
 115 };
 116
 117 struct hinic_port_rx_mode_cmd {
 118         u8      status;
 119         u8      version;
 120         u8      rsvd0[6];
 121
 122         u16     func_idx;
 123         u16     rsvd;
 124         u32     rx_mode;
 125 };
 126
 127 struct hinic_port_link_cmd {
 128         u8      status;
 129         u8      version;
 130         u8      rsvd0[6];
 131
 132         u16     func_idx;
 133         u8      state;
 134         u8      rsvd1;
 135 };
 136
 137 struct hinic_port_state_cmd {
 138         u8      status;
 139         u8      version;
 140         u8      rsvd0[6];
 141
 142         u8      state;
 143         u8      rsvd1[3];
 144 };
 145
 146 struct hinic_port_link_status {
 147         u8      status;
 148         u8      version;
 149         u8      rsvd0[6];
 150
 151         u16     rsvd1;
 152         u8      link;
 153         u8      rsvd2;
 154 };
 155
 156 struct hinic_port_func_state_cmd {
 157         u8      status;
 158         u8      version;
 159         u8      rsvd0[6];
 160
 161         u16     func_idx;
 162         u16     rsvd1;
 163         u8      state;
 164         u8      rsvd2[3];
 165 };
 166
 167 struct hinic_port_cap {
 168         u8      status;
 169         u8      version;
 170         u8      rsvd0[6];
 171
 172         u16     func_idx;
 173         u16     rsvd1;
 174         u8      port_type;
 175         u8      autoneg_cap;
 176         u8      autoneg_state;
 177         u8      duplex;
 178         u8      speed;
 179         u8      rsvd2[3];
 180 };
 181
 182 struct hinic_tso_config {
 183         u8      status;
 184         u8      version;
 185         u8      rsvd0[6];
 186
 187         u16     func_id;
 188         u16     rsvd1;
 189         u8      tso_en;
 190         u8      resv2[3];
 191 };
 192
 193 struct hinic_checksum_offload {
 194         u8      status;
 195         u8      version;
 196         u8      rsvd0[6];
 197
 198         u16     func_id;
 199         u16     rsvd1;
 200         u32     rx_csum_offload;
 201 };
 202
 203 struct hinic_rq_num {
 204         u8      status;
 205         u8      version;
 206         u8      rsvd0[6];
 207
 208         u16     func_id;
 209         u16     rsvd1[33];
 210         u32     num_rqs;
 211         u32     rq_depth;
 212 };
 213
 214 struct hinic_lro_config {
 215         u8      status;
 216         u8      version;
 217         u8      rsvd0[6];
 218
 219         u16     func_id;
 220         u16     rsvd1;
 221         u8      lro_ipv4_en;
 222         u8      lro_ipv6_en;
 223         u8      lro_max_wqe_num;
 224         u8      resv2[13];
 225 };
 226
 227 struct hinic_lro_timer {
 228         u8      status;
 229         u8      version;
 230         u8      rsvd0[6];
 231
 232         u8      type;   /* 0: set timer value, 1: get timer value */
 233         u8      enable; /* when set lro time, enable should be 1 */
 234         u16     rsvd1;
 235         u32     timer;
 236 };
 237
 238 struct hinic_vlan_cfg {
 239         u8      status;
 240         u8      version;
 241         u8      rsvd0[6];
 242
 243         u16     func_id;
 244         u8      vlan_rx_offload;
 245         u8      rsvd1[5];
 246 };
 247
 248 struct hinic_rss_template_mgmt {
 249         u8      status;
 250         u8      version;
 251         u8      rsvd0[6];
 252
 253         u16     func_id;
 254         u8      cmd;
 255         u8      template_id;
 256         u8      rsvd1[4];
 257 };
 258
 259 struct hinic_rss_template_key {
 260         u8      status;
 261         u8      version;
 262         u8      rsvd0[6];
 263
 264         u16     func_id;
 265         u8      template_id;
 266         u8      rsvd1;
 267         u8      key[HINIC_RSS_KEY_SIZE];
 268 };
 269
 270 struct hinic_rss_context_tbl {
 271         u32 group_index;
 272         u32 offset;
 273         u32 size;
 274         u32 rsvd;
 275         u32 ctx;
 276 };
 277
 278 struct hinic_rss_context_table {
 279         u8      status;
 280         u8      version;
 281         u8      rsvd0[6];
 282
 283         u16     func_id;
 284         u8      template_id;
 285         u8      rsvd1;
 286         u32     context;
 287 };
 288
 289 struct hinic_rss_indirect_tbl {
 290         u32 group_index;
 291         u32 offset;
 292         u32 size;
 293         u32 rsvd;
 294         u8 entry[HINIC_RSS_INDIR_SIZE];
 295 };
 296
 297 struct hinic_rss_indir_table {
 298         u8      status;
 299         u8      version;
 300         u8      rsvd0[6];
 301
 302         u16     func_id;
 303         u8      template_id;
 304         u8      rsvd1;
 305         u8      indir[HINIC_RSS_INDIR_SIZE];
 306 };
 307
 308 struct hinic_rss_key {
 309         u8      status;
 310         u8      version;
 311         u8      rsvd0[6];
 312
 313         u16     func_id;
 314         u8      template_id;
 315         u8      rsvd1;
 316         u8      key[HINIC_RSS_KEY_SIZE];
 317 };
 318
 319 struct hinic_rss_engine_type {
 320         u8      status;
 321         u8      version;
 322         u8      rsvd0[6];
 323
 324         u16     func_id;
 325         u8      template_id;
 326         u8      hash_engine;
 327         u8      rsvd1[4];
 328 };
 329
 330 struct hinic_rss_config {
 331         u8      status;
 332         u8      version;
 333         u8      rsvd0[6];
 334
 335         u16     func_id;
 336         u8      rss_en;
 337         u8      template_id;
 338         u8      rq_priority_number;
 339         u8      rsvd1[11];
 340 };
 341
 342 struct hinic_stats {
 343         char name[ETH_GSTRING_LEN];
 344         u32 size;
 345         int offset;
 346 };
 347
 348 struct hinic_vport_stats {
 349         u64 tx_unicast_pkts_vport;
 350         u64 tx_unicast_bytes_vport;
 351         u64 tx_multicast_pkts_vport;
 352         u64 tx_multicast_bytes_vport;
 353         u64 tx_broadcast_pkts_vport;
 354         u64 tx_broadcast_bytes_vport;
 355
 356         u64 rx_unicast_pkts_vport;
 357         u64 rx_unicast_bytes_vport;
 358         u64 rx_multicast_pkts_vport;
 359         u64 rx_multicast_bytes_vport;
 360         u64 rx_broadcast_pkts_vport;
 361         u64 rx_broadcast_bytes_vport;
 362
 363         u64 tx_discard_vport;
 364         u64 rx_discard_vport;
 365         u64 tx_err_vport;
 366         u64 rx_err_vport;
 367 };
 368
 369 struct hinic_phy_port_stats {
 370         u64 mac_rx_total_pkt_num;
 371         u64 mac_rx_total_oct_num;
 372         u64 mac_rx_bad_pkt_num;
 373         u64 mac_rx_bad_oct_num;
 374         u64 mac_rx_good_pkt_num;
 375         u64 mac_rx_good_oct_num;
 376         u64 mac_rx_uni_pkt_num;
 377         u64 mac_rx_multi_pkt_num;
 378         u64 mac_rx_broad_pkt_num;
 379
 380         u64 mac_tx_total_pkt_num;
 381         u64 mac_tx_total_oct_num;
 382         u64 mac_tx_bad_pkt_num;
 383         u64 mac_tx_bad_oct_num;
 384         u64 mac_tx_good_pkt_num;
 385         u64 mac_tx_good_oct_num;
 386         u64 mac_tx_uni_pkt_num;
 387         u64 mac_tx_multi_pkt_num;
 388         u64 mac_tx_broad_pkt_num;
 389
 390         u64 mac_rx_fragment_pkt_num;
 391         u64 mac_rx_undersize_pkt_num;
 392         u64 mac_rx_undermin_pkt_num;
 393         u64 mac_rx_64_oct_pkt_num;
 394         u64 mac_rx_65_127_oct_pkt_num;
 395         u64 mac_rx_128_255_oct_pkt_num;
 396         u64 mac_rx_256_511_oct_pkt_num;
 397         u64 mac_rx_512_1023_oct_pkt_num;
 398         u64 mac_rx_1024_1518_oct_pkt_num;
 399         u64 mac_rx_1519_2047_oct_pkt_num;
 400         u64 mac_rx_2048_4095_oct_pkt_num;
 401         u64 mac_rx_4096_8191_oct_pkt_num;
 402         u64 mac_rx_8192_9216_oct_pkt_num;
 403         u64 mac_rx_9217_12287_oct_pkt_num;
 404         u64 mac_rx_12288_16383_oct_pkt_num;
 405         u64 mac_rx_1519_max_bad_pkt_num;
 406         u64 mac_rx_1519_max_good_pkt_num;
 407         u64 mac_rx_oversize_pkt_num;
 408         u64 mac_rx_jabber_pkt_num;
 409
 410         u64 mac_rx_pause_num;
 411         u64 mac_rx_pfc_pkt_num;
 412         u64 mac_rx_pfc_pri0_pkt_num;
 413         u64 mac_rx_pfc_pri1_pkt_num;
 414         u64 mac_rx_pfc_pri2_pkt_num;
 415         u64 mac_rx_pfc_pri3_pkt_num;
 416         u64 mac_rx_pfc_pri4_pkt_num;
 417         u64 mac_rx_pfc_pri5_pkt_num;
 418         u64 mac_rx_pfc_pri6_pkt_num;
 419         u64 mac_rx_pfc_pri7_pkt_num;
 420         u64 mac_rx_control_pkt_num;
 421         u64 mac_rx_y1731_pkt_num;
 422         u64 mac_rx_sym_err_pkt_num;
 423         u64 mac_rx_fcs_err_pkt_num;
 424         u64 mac_rx_send_app_good_pkt_num;
 425         u64 mac_rx_send_app_bad_pkt_num;
 426
 427         u64 mac_tx_fragment_pkt_num;
 428         u64 mac_tx_undersize_pkt_num;
 429         u64 mac_tx_undermin_pkt_num;
 430         u64 mac_tx_64_oct_pkt_num;
 431         u64 mac_tx_65_127_oct_pkt_num;
 432         u64 mac_tx_128_255_oct_pkt_num;
 433         u64 mac_tx_256_511_oct_pkt_num;
 434         u64 mac_tx_512_1023_oct_pkt_num;
 435         u64 mac_tx_1024_1518_oct_pkt_num;
 436         u64 mac_tx_1519_2047_oct_pkt_num;
 437         u64 mac_tx_2048_4095_oct_pkt_num;
 438         u64 mac_tx_4096_8191_oct_pkt_num;
 439         u64 mac_tx_8192_9216_oct_pkt_num;
 440         u64 mac_tx_9217_12287_oct_pkt_num;
 441         u64 mac_tx_12288_16383_oct_pkt_num;
 442         u64 mac_tx_1519_max_bad_pkt_num;
 443         u64 mac_tx_1519_max_good_pkt_num;
 444         u64 mac_tx_oversize_pkt_num;
 445         u64 mac_tx_jabber_pkt_num;
 446
 447         u64 mac_tx_pause_num;
 448         u64 mac_tx_pfc_pkt_num;
 449         u64 mac_tx_pfc_pri0_pkt_num;
 450         u64 mac_tx_pfc_pri1_pkt_num;
 451         u64 mac_tx_pfc_pri2_pkt_num;
 452         u64 mac_tx_pfc_pri3_pkt_num;
 453         u64 mac_tx_pfc_pri4_pkt_num;
 454         u64 mac_tx_pfc_pri5_pkt_num;
 455         u64 mac_tx_pfc_pri6_pkt_num;
 456         u64 mac_tx_pfc_pri7_pkt_num;
 457         u64 mac_tx_control_pkt_num;
 458         u64 mac_tx_y1731_pkt_num;
 459         u64 mac_tx_1588_pkt_num;
 460         u64 mac_tx_err_all_pkt_num;
 461         u64 mac_tx_from_app_good_pkt_num;
 462         u64 mac_tx_from_app_bad_pkt_num;
 463
 464         u64 mac_rx_higig2_ext_pkt_num;
 465         u64 mac_rx_higig2_message_pkt_num;
 466         u64 mac_rx_higig2_error_pkt_num;
 467         u64 mac_rx_higig2_cpu_ctrl_pkt_num;
 468         u64 mac_rx_higig2_unicast_pkt_num;
 469         u64 mac_rx_higig2_broadcast_pkt_num;
 470         u64 mac_rx_higig2_l2_multicast_pkt_num;
 471         u64 mac_rx_higig2_l3_multicast_pkt_num;
 472
 473         u64 mac_tx_higig2_message_pkt_num;
 474         u64 mac_tx_higig2_ext_pkt_num;
 475         u64 mac_tx_higig2_cpu_ctrl_pkt_num;
 476         u64 mac_tx_higig2_unicast_pkt_num;
 477         u64 mac_tx_higig2_broadcast_pkt_num;
 478         u64 mac_tx_higig2_l2_multicast_pkt_num;
 479         u64 mac_tx_higig2_l3_multicast_pkt_num;
 480 };
 481
 482 struct hinic_port_stats_info {
 483         u8      status;
 484         u8      version;
 485         u8      rsvd0[6];
 486
 487         u16     func_id;
 488         u16     rsvd1;
 489         u32     stats_version;
 490         u32     stats_size;
 491 };
 492
 493 struct hinic_port_stats {
 494         u8 status;
 495         u8 version;
 496         u8 rsvd[6];
 497
 498         struct hinic_phy_port_stats stats;
 499 };
 500
 501 struct hinic_cmd_vport_stats {
 502         u8 status;
 503         u8 version;
 504         u8 rsvd0[6];
 505
 506         struct hinic_vport_stats stats;
 507 };
 508
 509 int hinic_port_add_mac(struct hinic_dev *nic_dev, const u8 *addr,
 510                        u16 vlan_id);
 511
 512 int hinic_port_del_mac(struct hinic_dev *nic_dev, const u8 *addr,
 513                        u16 vlan_id);
 514
 515 int hinic_port_get_mac(struct hinic_dev *nic_dev, u8 *addr);
 516
 517 int hinic_port_set_mtu(struct hinic_dev *nic_dev, int new_mtu);
 518
 519 int hinic_port_add_vlan(struct hinic_dev *nic_dev, u16 vlan_id);
 520
 521 int hinic_port_del_vlan(struct hinic_dev *nic_dev, u16 vlan_id);
 522
 523 int hinic_port_set_rx_mode(struct hinic_dev *nic_dev, u32 rx_mode);
 524
 525 int hinic_port_link_state(struct hinic_dev *nic_dev,
 526                           enum hinic_port_link_state *link_state);
 527
 528 int hinic_port_set_state(struct hinic_dev *nic_dev,
 529                          enum hinic_port_state state);
 530
 531 int hinic_port_set_func_state(struct hinic_dev *nic_dev,
 532                               enum hinic_func_port_state state);
 533
 534 int hinic_port_get_cap(struct hinic_dev *nic_dev,
 535                        struct hinic_port_cap *port_cap);
 536
 537 int hinic_set_max_qnum(struct hinic_dev *nic_dev, u8 num_rqs);
 538
 539 int hinic_port_set_tso(struct hinic_dev *nic_dev, enum hinic_tso_state state);
 540
 541 int hinic_set_rx_csum_offload(struct hinic_dev *nic_dev, u32 en);
 542
 543 int hinic_set_rx_lro_state(struct hinic_dev *nic_dev, u8 lro_en,
 544                            u32 lro_timer, u32 wqe_num);
 545
 546 int hinic_set_rss_type(struct hinic_dev *nic_dev, u32 tmpl_idx,
 547                        struct hinic_rss_type rss_type);
 548
 549 int hinic_rss_set_indir_tbl(struct hinic_dev *nic_dev, u32 tmpl_idx,
 550                             const u32 *indir_table);
 551
 552 int hinic_rss_set_template_tbl(struct hinic_dev *nic_dev, u32 template_id,
 553                                const u8 *temp);
 554
 555 int hinic_rss_set_hash_engine(struct hinic_dev *nic_dev, u8 template_id,
 556                               u8 type);
 557
 558 int hinic_rss_cfg(struct hinic_dev *nic_dev, u8 rss_en, u8 template_id);
 559
 560 int hinic_rss_template_alloc(struct hinic_dev *nic_dev, u8 *tmpl_idx);
 561
 562 int hinic_rss_template_free(struct hinic_dev *nic_dev, u8 tmpl_idx);
 563
 564 void hinic_set_ethtool_ops(struct net_device *netdev);
 565
 566 int hinic_get_rss_type(struct hinic_dev *nic_dev, u32 tmpl_idx,
 567                        struct hinic_rss_type *rss_type);
 568
 569 int hinic_rss_get_indir_tbl(struct hinic_dev *nic_dev, u32 tmpl_idx,
 570                             u32 *indir_table);
 571
 572 int hinic_rss_get_template_tbl(struct hinic_dev *nic_dev, u32 tmpl_idx,
 573                                u8 *temp);
 574
 575 int hinic_rss_get_hash_engine(struct hinic_dev *nic_dev, u8 tmpl_idx,
 576                               u8 *type);
 577
 578 int hinic_get_phy_port_stats(struct hinic_dev *nic_dev,
 579                              struct hinic_phy_port_stats *stats);
 580
 581 int hinic_get_vport_stats(struct hinic_dev *nic_dev,
 582                           struct hinic_vport_stats *stats);
 583
 584 int hinic_set_rx_vlan_offload(struct hinic_dev *nic_dev, u8 en);
 585
 586 int hinic_get_mgmt_version(struct hinic_dev *nic_dev, u8 *mgmt_ver);
 587
 588 #endif