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treewide: remove redundant IS_ERR() before error code check
[linux/fpc-iii.git] / drivers / net / ethernet / microchip / encx24j600.c
blob39925e4bf2ecb4a8d8304c2b36b90a3fd80a2b60
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /**
3 * Microchip ENCX24J600 ethernet driver
4 *
5 * Copyright (C) 2015 Gridpoint
6 * Author: Jon Ringle <jringle@gridpoint.com>
7 */
8
9 #include <linux/device.h>
10 #include <linux/errno.h>
11 #include <linux/etherdevice.h>
12 #include <linux/ethtool.h>
13 #include <linux/interrupt.h>
14 #include <linux/kernel.h>
15 #include <linux/module.h>
16 #include <linux/netdevice.h>
17 #include <linux/regmap.h>
18 #include <linux/skbuff.h>
19 #include <linux/spi/spi.h>
20
21 #include "encx24j600_hw.h"
22
23 #define DRV_NAME "encx24j600"
24 #define DRV_VERSION "1.0"
25
26 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
27 static int debug = -1;
28 module_param(debug, int, 0000);
29 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
30
31 /* SRAM memory layout:
32 *
33 * 0x0000-0x05ff TX buffers 1.5KB (1*1536) reside in the GP area in SRAM
34 * 0x0600-0x5fff RX buffers 22.5KB (15*1536) reside in the RX area in SRAM
35 */
36 #define ENC_TX_BUF_START 0x0000U
37 #define ENC_RX_BUF_START 0x0600U
38 #define ENC_RX_BUF_END 0x5fffU
39 #define ENC_SRAM_SIZE 0x6000U
40
41 enum {
42 RXFILTER_NORMAL,
43 RXFILTER_MULTI,
44 RXFILTER_PROMISC
45 };
46
47 struct encx24j600_priv {
48 struct net_device *ndev;
49 struct mutex lock; /* device access lock */
50 struct encx24j600_context ctx;
51 struct sk_buff *tx_skb;
52 struct task_struct *kworker_task;
53 struct kthread_worker kworker;
54 struct kthread_work tx_work;
55 struct kthread_work setrx_work;
56 u16 next_packet;
57 bool hw_enabled;
58 bool full_duplex;
59 bool autoneg;
60 u16 speed;
61 int rxfilter;
62 u32 msg_enable;
63 };
64
65 static void dump_packet(const char *msg, int len, const char *data)
66 {
67 pr_debug(DRV_NAME ": %s - packet len:%d\n", msg, len);
68 print_hex_dump_bytes("pk data: ", DUMP_PREFIX_OFFSET, data, len);
69 }
70
71 static void encx24j600_dump_rsv(struct encx24j600_priv *priv, const char *msg,
72 struct rsv *rsv)
73 {
74 struct net_device *dev = priv->ndev;
75
76 netdev_info(dev, "RX packet Len:%d\n", rsv->len);
77 netdev_dbg(dev, "%s - NextPk: 0x%04x\n", msg,
78 rsv->next_packet);
79 netdev_dbg(dev, "RxOK: %d, DribbleNibble: %d\n",
80 RSV_GETBIT(rsv->rxstat, RSV_RXOK),
81 RSV_GETBIT(rsv->rxstat, RSV_DRIBBLENIBBLE));
82 netdev_dbg(dev, "CRCErr:%d, LenChkErr: %d, LenOutOfRange: %d\n",
83 RSV_GETBIT(rsv->rxstat, RSV_CRCERROR),
84 RSV_GETBIT(rsv->rxstat, RSV_LENCHECKERR),
85 RSV_GETBIT(rsv->rxstat, RSV_LENOUTOFRANGE));
86 netdev_dbg(dev, "Multicast: %d, Broadcast: %d, LongDropEvent: %d, CarrierEvent: %d\n",
87 RSV_GETBIT(rsv->rxstat, RSV_RXMULTICAST),
88 RSV_GETBIT(rsv->rxstat, RSV_RXBROADCAST),
89 RSV_GETBIT(rsv->rxstat, RSV_RXLONGEVDROPEV),
90 RSV_GETBIT(rsv->rxstat, RSV_CARRIEREV));
91 netdev_dbg(dev, "ControlFrame: %d, PauseFrame: %d, UnknownOp: %d, VLanTagFrame: %d\n",
92 RSV_GETBIT(rsv->rxstat, RSV_RXCONTROLFRAME),
93 RSV_GETBIT(rsv->rxstat, RSV_RXPAUSEFRAME),
94 RSV_GETBIT(rsv->rxstat, RSV_RXUNKNOWNOPCODE),
95 RSV_GETBIT(rsv->rxstat, RSV_RXTYPEVLAN));
96 }
97
98 static u16 encx24j600_read_reg(struct encx24j600_priv *priv, u8 reg)
99 {
100 struct net_device *dev = priv->ndev;
101 unsigned int val = 0;
102 int ret = regmap_read(priv->ctx.regmap, reg, &val);
103
104 if (unlikely(ret))
105 netif_err(priv, drv, dev, "%s: error %d reading reg %02x\n",
106 __func__, ret, reg);
107 return val;
108 }
109
110 static void encx24j600_write_reg(struct encx24j600_priv *priv, u8 reg, u16 val)
111 {
112 struct net_device *dev = priv->ndev;
113 int ret = regmap_write(priv->ctx.regmap, reg, val);
114
115 if (unlikely(ret))
116 netif_err(priv, drv, dev, "%s: error %d writing reg %02x=%04x\n",
117 __func__, ret, reg, val);
118 }
119
120 static void encx24j600_update_reg(struct encx24j600_priv *priv, u8 reg,
121 u16 mask, u16 val)
122 {
123 struct net_device *dev = priv->ndev;
124 int ret = regmap_update_bits(priv->ctx.regmap, reg, mask, val);
125
126 if (unlikely(ret))
127 netif_err(priv, drv, dev, "%s: error %d updating reg %02x=%04x~%04x\n",
128 __func__, ret, reg, val, mask);
129 }
130
131 static u16 encx24j600_read_phy(struct encx24j600_priv *priv, u8 reg)
132 {
133 struct net_device *dev = priv->ndev;
134 unsigned int val = 0;
135 int ret = regmap_read(priv->ctx.phymap, reg, &val);
136
137 if (unlikely(ret))
138 netif_err(priv, drv, dev, "%s: error %d reading %02x\n",
139 __func__, ret, reg);
140 return val;
141 }
142
143 static void encx24j600_write_phy(struct encx24j600_priv *priv, u8 reg, u16 val)
144 {
145 struct net_device *dev = priv->ndev;
146 int ret = regmap_write(priv->ctx.phymap, reg, val);
147
148 if (unlikely(ret))
149 netif_err(priv, drv, dev, "%s: error %d writing reg %02x=%04x\n",
150 __func__, ret, reg, val);
151 }
152
153 static void encx24j600_clr_bits(struct encx24j600_priv *priv, u8 reg, u16 mask)
154 {
155 encx24j600_update_reg(priv, reg, mask, 0);
156 }
157
158 static void encx24j600_set_bits(struct encx24j600_priv *priv, u8 reg, u16 mask)
159 {
160 encx24j600_update_reg(priv, reg, mask, mask);
161 }
162
163 static void encx24j600_cmd(struct encx24j600_priv *priv, u8 cmd)
164 {
165 struct net_device *dev = priv->ndev;
166 int ret = regmap_write(priv->ctx.regmap, cmd, 0);
167
168 if (unlikely(ret))
169 netif_err(priv, drv, dev, "%s: error %d with cmd %02x\n",
170 __func__, ret, cmd);
171 }
172
173 static int encx24j600_raw_read(struct encx24j600_priv *priv, u8 reg, u8 *data,
174 size_t count)
175 {
176 int ret;
177
178 mutex_lock(&priv->ctx.mutex);
179 ret = regmap_encx24j600_spi_read(&priv->ctx, reg, data, count);
180 mutex_unlock(&priv->ctx.mutex);
181
182 return ret;
183 }
184
185 static int encx24j600_raw_write(struct encx24j600_priv *priv, u8 reg,
186 const u8 *data, size_t count)
187 {
188 int ret;
189
190 mutex_lock(&priv->ctx.mutex);
191 ret = regmap_encx24j600_spi_write(&priv->ctx, reg, data, count);
192 mutex_unlock(&priv->ctx.mutex);
193
194 return ret;
195 }
196
197 static void encx24j600_update_phcon1(struct encx24j600_priv *priv)
198 {
199 u16 phcon1 = encx24j600_read_phy(priv, PHCON1);
200
201 if (priv->autoneg == AUTONEG_ENABLE) {
202 phcon1 |= ANEN | RENEG;
203 } else {
204 phcon1 &= ~ANEN;
205 if (priv->speed == SPEED_100)
206 phcon1 |= SPD100;
207 else
208 phcon1 &= ~SPD100;
209
210 if (priv->full_duplex)
211 phcon1 |= PFULDPX;
212 else
213 phcon1 &= ~PFULDPX;
214 }
215 encx24j600_write_phy(priv, PHCON1, phcon1);
216 }
217
218 /* Waits for autonegotiation to complete. */
219 static int encx24j600_wait_for_autoneg(struct encx24j600_priv *priv)
220 {
221 struct net_device *dev = priv->ndev;
222 unsigned long timeout = jiffies + msecs_to_jiffies(2000);
223 u16 phstat1;
224 u16 estat;
225 int ret = 0;
226
227 phstat1 = encx24j600_read_phy(priv, PHSTAT1);
228 while ((phstat1 & ANDONE) == 0) {
229 if (time_after(jiffies, timeout)) {
230 u16 phstat3;
231
232 netif_notice(priv, drv, dev, "timeout waiting for autoneg done\n");
233
234 priv->autoneg = AUTONEG_DISABLE;
235 phstat3 = encx24j600_read_phy(priv, PHSTAT3);
236 priv->speed = (phstat3 & PHY3SPD100)
237 ? SPEED_100 : SPEED_10;
238 priv->full_duplex = (phstat3 & PHY3DPX) ? 1 : 0;
239 encx24j600_update_phcon1(priv);
240 netif_notice(priv, drv, dev, "Using parallel detection: %s/%s",
241 priv->speed == SPEED_100 ? "100" : "10",
242 priv->full_duplex ? "Full" : "Half");
243
244 return -ETIMEDOUT;
245 }
246 cpu_relax();
247 phstat1 = encx24j600_read_phy(priv, PHSTAT1);
248 }
249
250 estat = encx24j600_read_reg(priv, ESTAT);
251 if (estat & PHYDPX) {
252 encx24j600_set_bits(priv, MACON2, FULDPX);
253 encx24j600_write_reg(priv, MABBIPG, 0x15);
254 } else {
255 encx24j600_clr_bits(priv, MACON2, FULDPX);
256 encx24j600_write_reg(priv, MABBIPG, 0x12);
257 /* Max retransmittions attempt */
258 encx24j600_write_reg(priv, MACLCON, 0x370f);
259 }
260
261 return ret;
262 }
263
264 /* Access the PHY to determine link status */
265 static void encx24j600_check_link_status(struct encx24j600_priv *priv)
266 {
267 struct net_device *dev = priv->ndev;
268 u16 estat;
269
270 estat = encx24j600_read_reg(priv, ESTAT);
271
272 if (estat & PHYLNK) {
273 if (priv->autoneg == AUTONEG_ENABLE)
274 encx24j600_wait_for_autoneg(priv);
275
276 netif_carrier_on(dev);
277 netif_info(priv, ifup, dev, "link up\n");
278 } else {
279 netif_info(priv, ifdown, dev, "link down\n");
280
281 /* Re-enable autoneg since we won't know what we might be
282 * connected to when the link is brought back up again.
283 */
284 priv->autoneg = AUTONEG_ENABLE;
285 priv->full_duplex = true;
286 priv->speed = SPEED_100;
287 netif_carrier_off(dev);
288 }
289 }
290
291 static void encx24j600_int_link_handler(struct encx24j600_priv *priv)
292 {
293 struct net_device *dev = priv->ndev;
294
295 netif_dbg(priv, intr, dev, "%s", __func__);
296 encx24j600_check_link_status(priv);
297 encx24j600_clr_bits(priv, EIR, LINKIF);
298 }
299
300 static void encx24j600_tx_complete(struct encx24j600_priv *priv, bool err)
301 {
302 struct net_device *dev = priv->ndev;
303
304 if (!priv->tx_skb) {
305 BUG();
306 return;
307 }
308
309 mutex_lock(&priv->lock);
310
311 if (err)
312 dev->stats.tx_errors++;
313 else
314 dev->stats.tx_packets++;
315
316 dev->stats.tx_bytes += priv->tx_skb->len;
317
318 encx24j600_clr_bits(priv, EIR, TXIF | TXABTIF);
319
320 netif_dbg(priv, tx_done, dev, "TX Done%s\n", err ? ": Err" : "");
321
322 dev_kfree_skb(priv->tx_skb);
323 priv->tx_skb = NULL;
324
325 netif_wake_queue(dev);
326
327 mutex_unlock(&priv->lock);
328 }
329
330 static int encx24j600_receive_packet(struct encx24j600_priv *priv,
331 struct rsv *rsv)
332 {
333 struct net_device *dev = priv->ndev;
334 struct sk_buff *skb = netdev_alloc_skb(dev, rsv->len + NET_IP_ALIGN);
335
336 if (!skb) {
337 pr_err_ratelimited("RX: OOM: packet dropped\n");
338 dev->stats.rx_dropped++;
339 return -ENOMEM;
340 }
341 skb_reserve(skb, NET_IP_ALIGN);
342 encx24j600_raw_read(priv, RRXDATA, skb_put(skb, rsv->len), rsv->len);
343
344 if (netif_msg_pktdata(priv))
345 dump_packet("RX", skb->len, skb->data);
346
347 skb->dev = dev;
348 skb->protocol = eth_type_trans(skb, dev);
349 skb->ip_summed = CHECKSUM_COMPLETE;
350
351 /* Maintain stats */
352 dev->stats.rx_packets++;
353 dev->stats.rx_bytes += rsv->len;
354
355 netif_rx(skb);
356
357 return 0;
358 }
359
360 static void encx24j600_rx_packets(struct encx24j600_priv *priv, u8 packet_count)
361 {
362 struct net_device *dev = priv->ndev;
363
364 while (packet_count--) {
365 struct rsv rsv;
366 u16 newrxtail;
367
368 encx24j600_write_reg(priv, ERXRDPT, priv->next_packet);
369 encx24j600_raw_read(priv, RRXDATA, (u8 *)&rsv, sizeof(rsv));
370
371 if (netif_msg_rx_status(priv))
372 encx24j600_dump_rsv(priv, __func__, &rsv);
373
374 if (!RSV_GETBIT(rsv.rxstat, RSV_RXOK) ||
375 (rsv.len > MAX_FRAMELEN)) {
376 netif_err(priv, rx_err, dev, "RX Error %04x\n",
377 rsv.rxstat);
378 dev->stats.rx_errors++;
379
380 if (RSV_GETBIT(rsv.rxstat, RSV_CRCERROR))
381 dev->stats.rx_crc_errors++;
382 if (RSV_GETBIT(rsv.rxstat, RSV_LENCHECKERR))
383 dev->stats.rx_frame_errors++;
384 if (rsv.len > MAX_FRAMELEN)
385 dev->stats.rx_over_errors++;
386 } else {
387 encx24j600_receive_packet(priv, &rsv);
388 }
389
390 priv->next_packet = rsv.next_packet;
391
392 newrxtail = priv->next_packet - 2;
393 if (newrxtail == ENC_RX_BUF_START)
394 newrxtail = SRAM_SIZE - 2;
395
396 encx24j600_cmd(priv, SETPKTDEC);
397 encx24j600_write_reg(priv, ERXTAIL, newrxtail);
398 }
399 }
400
401 static irqreturn_t encx24j600_isr(int irq, void *dev_id)
402 {
403 struct encx24j600_priv *priv = dev_id;
404 struct net_device *dev = priv->ndev;
405 int eir;
406
407 /* Clear interrupts */
408 encx24j600_cmd(priv, CLREIE);
409
410 eir = encx24j600_read_reg(priv, EIR);
411
412 if (eir & LINKIF)
413 encx24j600_int_link_handler(priv);
414
415 if (eir & TXIF)
416 encx24j600_tx_complete(priv, false);
417
418 if (eir & TXABTIF)
419 encx24j600_tx_complete(priv, true);
420
421 if (eir & RXABTIF) {
422 if (eir & PCFULIF) {
423 /* Packet counter is full */
424 netif_err(priv, rx_err, dev, "Packet counter full\n");
425 }
426 dev->stats.rx_dropped++;
427 encx24j600_clr_bits(priv, EIR, RXABTIF);
428 }
429
430 if (eir & PKTIF) {
431 u8 packet_count;
432
433 mutex_lock(&priv->lock);
434
435 packet_count = encx24j600_read_reg(priv, ESTAT) & 0xff;
436 while (packet_count) {
437 encx24j600_rx_packets(priv, packet_count);
438 packet_count = encx24j600_read_reg(priv, ESTAT) & 0xff;
439 }
440
441 mutex_unlock(&priv->lock);
442 }
443
444 /* Enable interrupts */
445 encx24j600_cmd(priv, SETEIE);
446
447 return IRQ_HANDLED;
448 }
449
450 static int encx24j600_soft_reset(struct encx24j600_priv *priv)
451 {
452 int ret = 0;
453 int timeout;
454 u16 eudast;
455
456 /* Write and verify a test value to EUDAST */
457 regcache_cache_bypass(priv->ctx.regmap, true);
458 timeout = 10;
459 do {
460 encx24j600_write_reg(priv, EUDAST, EUDAST_TEST_VAL);
461 eudast = encx24j600_read_reg(priv, EUDAST);
462 usleep_range(25, 100);
463 } while ((eudast != EUDAST_TEST_VAL) && --timeout);
464 regcache_cache_bypass(priv->ctx.regmap, false);
465
466 if (timeout == 0) {
467 ret = -ETIMEDOUT;
468 goto err_out;
469 }
470
471 /* Wait for CLKRDY to become set */
472 timeout = 10;
473 while (!(encx24j600_read_reg(priv, ESTAT) & CLKRDY) && --timeout)
474 usleep_range(25, 100);
475
476 if (timeout == 0) {
477 ret = -ETIMEDOUT;
478 goto err_out;
479 }
480
481 /* Issue a System Reset command */
482 encx24j600_cmd(priv, SETETHRST);
483 usleep_range(25, 100);
484
485 /* Confirm that EUDAST has 0000h after system reset */
486 if (encx24j600_read_reg(priv, EUDAST) != 0) {
487 ret = -EINVAL;
488 goto err_out;
489 }
490
491 /* Wait for PHY register and status bits to become available */
492 usleep_range(256, 1000);
493
494 err_out:
495 return ret;
496 }
497
498 static int encx24j600_hw_reset(struct encx24j600_priv *priv)
499 {
500 int ret;
501
502 mutex_lock(&priv->lock);
503 ret = encx24j600_soft_reset(priv);
504 mutex_unlock(&priv->lock);
505
506 return ret;
507 }
508
509 static void encx24j600_reset_hw_tx(struct encx24j600_priv *priv)
510 {
511 encx24j600_set_bits(priv, ECON2, TXRST);
512 encx24j600_clr_bits(priv, ECON2, TXRST);
513 }
514
515 static void encx24j600_hw_init_tx(struct encx24j600_priv *priv)
516 {
517 /* Reset TX */
518 encx24j600_reset_hw_tx(priv);
519
520 /* Clear the TXIF flag if were previously set */
521 encx24j600_clr_bits(priv, EIR, TXIF | TXABTIF);
522
523 /* Write the Tx Buffer pointer */
524 encx24j600_write_reg(priv, EGPWRPT, ENC_TX_BUF_START);
525 }
526
527 static void encx24j600_hw_init_rx(struct encx24j600_priv *priv)
528 {
529 encx24j600_cmd(priv, DISABLERX);
530
531 /* Set up RX packet start address in the SRAM */
532 encx24j600_write_reg(priv, ERXST, ENC_RX_BUF_START);
533
534 /* Preload the RX Data pointer to the beginning of the RX area */
535 encx24j600_write_reg(priv, ERXRDPT, ENC_RX_BUF_START);
536
537 priv->next_packet = ENC_RX_BUF_START;
538
539 /* Set up RX end address in the SRAM */
540 encx24j600_write_reg(priv, ERXTAIL, ENC_SRAM_SIZE - 2);
541
542 /* Reset the user data pointers */
543 encx24j600_write_reg(priv, EUDAST, ENC_SRAM_SIZE);
544 encx24j600_write_reg(priv, EUDAND, ENC_SRAM_SIZE + 1);
545
546 /* Set Max Frame length */
547 encx24j600_write_reg(priv, MAMXFL, MAX_FRAMELEN);
548 }
549
550 static void encx24j600_dump_config(struct encx24j600_priv *priv,
551 const char *msg)
552 {
553 pr_info(DRV_NAME ": %s\n", msg);
554
555 /* CHIP configuration */
556 pr_info(DRV_NAME " ECON1: %04X\n", encx24j600_read_reg(priv, ECON1));
557 pr_info(DRV_NAME " ECON2: %04X\n", encx24j600_read_reg(priv, ECON2));
558 pr_info(DRV_NAME " ERXFCON: %04X\n", encx24j600_read_reg(priv,
559 ERXFCON));
560 pr_info(DRV_NAME " ESTAT: %04X\n", encx24j600_read_reg(priv, ESTAT));
561 pr_info(DRV_NAME " EIR: %04X\n", encx24j600_read_reg(priv, EIR));
562 pr_info(DRV_NAME " EIDLED: %04X\n", encx24j600_read_reg(priv, EIDLED));
563
564 /* MAC layer configuration */
565 pr_info(DRV_NAME " MACON1: %04X\n", encx24j600_read_reg(priv, MACON1));
566 pr_info(DRV_NAME " MACON2: %04X\n", encx24j600_read_reg(priv, MACON2));
567 pr_info(DRV_NAME " MAIPG: %04X\n", encx24j600_read_reg(priv, MAIPG));
568 pr_info(DRV_NAME " MACLCON: %04X\n", encx24j600_read_reg(priv,
569 MACLCON));
570 pr_info(DRV_NAME " MABBIPG: %04X\n", encx24j600_read_reg(priv,
571 MABBIPG));
572
573 /* PHY configuation */
574 pr_info(DRV_NAME " PHCON1: %04X\n", encx24j600_read_phy(priv, PHCON1));
575 pr_info(DRV_NAME " PHCON2: %04X\n", encx24j600_read_phy(priv, PHCON2));
576 pr_info(DRV_NAME " PHANA: %04X\n", encx24j600_read_phy(priv, PHANA));
577 pr_info(DRV_NAME " PHANLPA: %04X\n", encx24j600_read_phy(priv,
578 PHANLPA));
579 pr_info(DRV_NAME " PHANE: %04X\n", encx24j600_read_phy(priv, PHANE));
580 pr_info(DRV_NAME " PHSTAT1: %04X\n", encx24j600_read_phy(priv,
581 PHSTAT1));
582 pr_info(DRV_NAME " PHSTAT2: %04X\n", encx24j600_read_phy(priv,
583 PHSTAT2));
584 pr_info(DRV_NAME " PHSTAT3: %04X\n", encx24j600_read_phy(priv,
585 PHSTAT3));
586 }
587
588 static void encx24j600_set_rxfilter_mode(struct encx24j600_priv *priv)
589 {
590 switch (priv->rxfilter) {
591 case RXFILTER_PROMISC:
592 encx24j600_set_bits(priv, MACON1, PASSALL);
593 encx24j600_write_reg(priv, ERXFCON, UCEN | MCEN | NOTMEEN);
594 break;
595 case RXFILTER_MULTI:
596 encx24j600_clr_bits(priv, MACON1, PASSALL);
597 encx24j600_write_reg(priv, ERXFCON, UCEN | CRCEN | BCEN | MCEN);
598 break;
599 case RXFILTER_NORMAL:
600 default:
601 encx24j600_clr_bits(priv, MACON1, PASSALL);
602 encx24j600_write_reg(priv, ERXFCON, UCEN | CRCEN | BCEN);
603 break;
604 }
605 }
606
607 static int encx24j600_hw_init(struct encx24j600_priv *priv)
608 {
609 int ret = 0;
610 u16 macon2;
611
612 priv->hw_enabled = false;
613
614 /* PHY Leds: link status,
615 * LEDA: Link State + collision events
616 * LEDB: Link State + transmit/receive events
617 */
618 encx24j600_update_reg(priv, EIDLED, 0xff00, 0xcb00);
619
620 /* Loopback disabled */
621 encx24j600_write_reg(priv, MACON1, 0x9);
622
623 /* interpacket gap value */
624 encx24j600_write_reg(priv, MAIPG, 0x0c12);
625
626 /* Write the auto negotiation pattern */
627 encx24j600_write_phy(priv, PHANA, PHANA_DEFAULT);
628
629 encx24j600_update_phcon1(priv);
630 encx24j600_check_link_status(priv);
631
632 macon2 = MACON2_RSV1 | TXCRCEN | PADCFG0 | PADCFG2 | MACON2_DEFER;
633 if ((priv->autoneg == AUTONEG_DISABLE) && priv->full_duplex)
634 macon2 |= FULDPX;
635
636 encx24j600_set_bits(priv, MACON2, macon2);
637
638 priv->rxfilter = RXFILTER_NORMAL;
639 encx24j600_set_rxfilter_mode(priv);
640
641 /* Program the Maximum frame length */
642 encx24j600_write_reg(priv, MAMXFL, MAX_FRAMELEN);
643
644 /* Init Tx pointers */
645 encx24j600_hw_init_tx(priv);
646
647 /* Init Rx pointers */
648 encx24j600_hw_init_rx(priv);
649
650 if (netif_msg_hw(priv))
651 encx24j600_dump_config(priv, "Hw is initialized");
652
653 return ret;
654 }
655
656 static void encx24j600_hw_enable(struct encx24j600_priv *priv)
657 {
658 /* Clear the interrupt flags in case was set */
659 encx24j600_clr_bits(priv, EIR, (PCFULIF | RXABTIF | TXABTIF | TXIF |
660 PKTIF | LINKIF));
661
662 /* Enable the interrupts */
663 encx24j600_write_reg(priv, EIE, (PCFULIE | RXABTIE | TXABTIE | TXIE |
664 PKTIE | LINKIE | INTIE));
665
666 /* Enable RX */
667 encx24j600_cmd(priv, ENABLERX);
668
669 priv->hw_enabled = true;
670 }
671
672 static void encx24j600_hw_disable(struct encx24j600_priv *priv)
673 {
674 /* Disable all interrupts */
675 encx24j600_write_reg(priv, EIE, 0);
676
677 /* Disable RX */
678 encx24j600_cmd(priv, DISABLERX);
679
680 priv->hw_enabled = false;
681 }
682
683 static int encx24j600_setlink(struct net_device *dev, u8 autoneg, u16 speed,
684 u8 duplex)
685 {
686 struct encx24j600_priv *priv = netdev_priv(dev);
687 int ret = 0;
688
689 if (!priv->hw_enabled) {
690 /* link is in low power mode now; duplex setting
691 * will take effect on next encx24j600_hw_init()
692 */
693 if (speed == SPEED_10 || speed == SPEED_100) {
694 priv->autoneg = (autoneg == AUTONEG_ENABLE);
695 priv->full_duplex = (duplex == DUPLEX_FULL);
696 priv->speed = (speed == SPEED_100);
697 } else {
698 netif_warn(priv, link, dev, "unsupported link speed setting\n");
699 /*speeds other than SPEED_10 and SPEED_100 */
700 /*are not supported by chip */
701 ret = -EOPNOTSUPP;
702 }
703 } else {
704 netif_warn(priv, link, dev, "Warning: hw must be disabled to set link mode\n");
705 ret = -EBUSY;
706 }
707 return ret;
708 }
709
710 static void encx24j600_hw_get_macaddr(struct encx24j600_priv *priv,
711 unsigned char *ethaddr)
712 {
713 unsigned short val;
714
715 val = encx24j600_read_reg(priv, MAADR1);
716
717 ethaddr[0] = val & 0x00ff;
718 ethaddr[1] = (val & 0xff00) >> 8;
719
720 val = encx24j600_read_reg(priv, MAADR2);
721
722 ethaddr[2] = val & 0x00ffU;
723 ethaddr[3] = (val & 0xff00U) >> 8;
724
725 val = encx24j600_read_reg(priv, MAADR3);
726
727 ethaddr[4] = val & 0x00ffU;
728 ethaddr[5] = (val & 0xff00U) >> 8;
729 }
730
731 /* Program the hardware MAC address from dev->dev_addr.*/
732 static int encx24j600_set_hw_macaddr(struct net_device *dev)
733 {
734 struct encx24j600_priv *priv = netdev_priv(dev);
735
736 if (priv->hw_enabled) {
737 netif_info(priv, drv, dev, "Hardware must be disabled to set Mac address\n");
738 return -EBUSY;
739 }
740
741 mutex_lock(&priv->lock);
742
743 netif_info(priv, drv, dev, "%s: Setting MAC address to %pM\n",
744 dev->name, dev->dev_addr);
745
746 encx24j600_write_reg(priv, MAADR3, (dev->dev_addr[4] |
747 dev->dev_addr[5] << 8));
748 encx24j600_write_reg(priv, MAADR2, (dev->dev_addr[2] |
749 dev->dev_addr[3] << 8));
750 encx24j600_write_reg(priv, MAADR1, (dev->dev_addr[0] |
751 dev->dev_addr[1] << 8));
752
753 mutex_unlock(&priv->lock);
754
755 return 0;
756 }
757
758 /* Store the new hardware address in dev->dev_addr, and update the MAC.*/
759 static int encx24j600_set_mac_address(struct net_device *dev, void *addr)
760 {
761 struct sockaddr *address = addr;
762
763 if (netif_running(dev))
764 return -EBUSY;
765 if (!is_valid_ether_addr(address->sa_data))
766 return -EADDRNOTAVAIL;
767
768 memcpy(dev->dev_addr, address->sa_data, dev->addr_len);
769 return encx24j600_set_hw_macaddr(dev);
770 }
771
772 static int encx24j600_open(struct net_device *dev)
773 {
774 struct encx24j600_priv *priv = netdev_priv(dev);
775
776 int ret = request_threaded_irq(priv->ctx.spi->irq, NULL, encx24j600_isr,
777 IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
778 DRV_NAME, priv);
779 if (unlikely(ret < 0)) {
780 netdev_err(dev, "request irq %d failed (ret = %d)\n",
781 priv->ctx.spi->irq, ret);
782 return ret;
783 }
784
785 encx24j600_hw_disable(priv);
786 encx24j600_hw_init(priv);
787 encx24j600_hw_enable(priv);
788 netif_start_queue(dev);
789
790 return 0;
791 }
792
793 static int encx24j600_stop(struct net_device *dev)
794 {
795 struct encx24j600_priv *priv = netdev_priv(dev);
796
797 netif_stop_queue(dev);
798 free_irq(priv->ctx.spi->irq, priv);
799 return 0;
800 }
801
802 static void encx24j600_setrx_proc(struct kthread_work *ws)
803 {
804 struct encx24j600_priv *priv =
805 container_of(ws, struct encx24j600_priv, setrx_work);
806
807 mutex_lock(&priv->lock);
808 encx24j600_set_rxfilter_mode(priv);
809 mutex_unlock(&priv->lock);
810 }
811
812 static void encx24j600_set_multicast_list(struct net_device *dev)
813 {
814 struct encx24j600_priv *priv = netdev_priv(dev);
815 int oldfilter = priv->rxfilter;
816
817 if (dev->flags & IFF_PROMISC) {
818 netif_dbg(priv, link, dev, "promiscuous mode\n");
819 priv->rxfilter = RXFILTER_PROMISC;
820 } else if ((dev->flags & IFF_ALLMULTI) || !netdev_mc_empty(dev)) {
821 netif_dbg(priv, link, dev, "%smulticast mode\n",
822 (dev->flags & IFF_ALLMULTI) ? "all-" : "");
823 priv->rxfilter = RXFILTER_MULTI;
824 } else {
825 netif_dbg(priv, link, dev, "normal mode\n");
826 priv->rxfilter = RXFILTER_NORMAL;
827 }
828
829 if (oldfilter != priv->rxfilter)
830 kthread_queue_work(&priv->kworker, &priv->setrx_work);
831 }
832
833 static void encx24j600_hw_tx(struct encx24j600_priv *priv)
834 {
835 struct net_device *dev = priv->ndev;
836
837 netif_info(priv, tx_queued, dev, "TX Packet Len:%d\n",
838 priv->tx_skb->len);
839
840 if (netif_msg_pktdata(priv))
841 dump_packet("TX", priv->tx_skb->len, priv->tx_skb->data);
842
843 if (encx24j600_read_reg(priv, EIR) & TXABTIF)
844 /* Last transmition aborted due to error. Reset TX interface */
845 encx24j600_reset_hw_tx(priv);
846
847 /* Clear the TXIF flag if were previously set */
848 encx24j600_clr_bits(priv, EIR, TXIF);
849
850 /* Set the data pointer to the TX buffer address in the SRAM */
851 encx24j600_write_reg(priv, EGPWRPT, ENC_TX_BUF_START);
852
853 /* Copy the packet into the SRAM */
854 encx24j600_raw_write(priv, WGPDATA, (u8 *)priv->tx_skb->data,
855 priv->tx_skb->len);
856
857 /* Program the Tx buffer start pointer */
858 encx24j600_write_reg(priv, ETXST, ENC_TX_BUF_START);
859
860 /* Program the packet length */
861 encx24j600_write_reg(priv, ETXLEN, priv->tx_skb->len);
862
863 /* Start the transmission */
864 encx24j600_cmd(priv, SETTXRTS);
865 }
866
867 static void encx24j600_tx_proc(struct kthread_work *ws)
868 {
869 struct encx24j600_priv *priv =
870 container_of(ws, struct encx24j600_priv, tx_work);
871
872 mutex_lock(&priv->lock);
873 encx24j600_hw_tx(priv);
874 mutex_unlock(&priv->lock);
875 }
876
877 static netdev_tx_t encx24j600_tx(struct sk_buff *skb, struct net_device *dev)
878 {
879 struct encx24j600_priv *priv = netdev_priv(dev);
880
881 netif_stop_queue(dev);
882
883 /* save the timestamp */
884 netif_trans_update(dev);
885
886 /* Remember the skb for deferred processing */
887 priv->tx_skb = skb;
888
889 kthread_queue_work(&priv->kworker, &priv->tx_work);
890
891 return NETDEV_TX_OK;
892 }
893
894 /* Deal with a transmit timeout */
895 static void encx24j600_tx_timeout(struct net_device *dev, unsigned int txqueue)
896 {
897 struct encx24j600_priv *priv = netdev_priv(dev);
898
899 netif_err(priv, tx_err, dev, "TX timeout at %ld, latency %ld\n",
900 jiffies, jiffies - dev_trans_start(dev));
901
902 dev->stats.tx_errors++;
903 netif_wake_queue(dev);
904 }
905
906 static int encx24j600_get_regs_len(struct net_device *dev)
907 {
908 return SFR_REG_COUNT;
909 }
910
911 static void encx24j600_get_regs(struct net_device *dev,
912 struct ethtool_regs *regs, void *p)
913 {
914 struct encx24j600_priv *priv = netdev_priv(dev);
915 u16 *buff = p;
916 u8 reg;
917
918 regs->version = 1;
919 mutex_lock(&priv->lock);
920 for (reg = 0; reg < SFR_REG_COUNT; reg += 2) {
921 unsigned int val = 0;
922 /* ignore errors for unreadable registers */
923 regmap_read(priv->ctx.regmap, reg, &val);
924 buff[reg] = val & 0xffff;
925 }
926 mutex_unlock(&priv->lock);
927 }
928
929 static void encx24j600_get_drvinfo(struct net_device *dev,
930 struct ethtool_drvinfo *info)
931 {
932 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
933 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
934 strlcpy(info->bus_info, dev_name(dev->dev.parent),
935 sizeof(info->bus_info));
936 }
937
938 static int encx24j600_get_link_ksettings(struct net_device *dev,
939 struct ethtool_link_ksettings *cmd)
940 {
941 struct encx24j600_priv *priv = netdev_priv(dev);
942 u32 supported;
943
944 supported = SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
945 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
946 SUPPORTED_Autoneg | SUPPORTED_TP;
947
948 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
949 supported);
950
951 cmd->base.speed = priv->speed;
952 cmd->base.duplex = priv->full_duplex ? DUPLEX_FULL : DUPLEX_HALF;
953 cmd->base.port = PORT_TP;
954 cmd->base.autoneg = priv->autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE;
955
956 return 0;
957 }
958
959 static int
960 encx24j600_set_link_ksettings(struct net_device *dev,
961 const struct ethtool_link_ksettings *cmd)
962 {
963 return encx24j600_setlink(dev, cmd->base.autoneg,
964 cmd->base.speed, cmd->base.duplex);
965 }
966
967 static u32 encx24j600_get_msglevel(struct net_device *dev)
968 {
969 struct encx24j600_priv *priv = netdev_priv(dev);
970
971 return priv->msg_enable;
972 }
973
974 static void encx24j600_set_msglevel(struct net_device *dev, u32 val)
975 {
976 struct encx24j600_priv *priv = netdev_priv(dev);
977
978 priv->msg_enable = val;
979 }
980
981 static const struct ethtool_ops encx24j600_ethtool_ops = {
982 .get_drvinfo = encx24j600_get_drvinfo,
983 .get_msglevel = encx24j600_get_msglevel,
984 .set_msglevel = encx24j600_set_msglevel,
985 .get_regs_len = encx24j600_get_regs_len,
986 .get_regs = encx24j600_get_regs,
987 .get_link_ksettings = encx24j600_get_link_ksettings,
988 .set_link_ksettings = encx24j600_set_link_ksettings,
989 };
990
991 static const struct net_device_ops encx24j600_netdev_ops = {
992 .ndo_open = encx24j600_open,
993 .ndo_stop = encx24j600_stop,
994 .ndo_start_xmit = encx24j600_tx,
995 .ndo_set_rx_mode = encx24j600_set_multicast_list,
996 .ndo_set_mac_address = encx24j600_set_mac_address,
997 .ndo_tx_timeout = encx24j600_tx_timeout,
998 .ndo_validate_addr = eth_validate_addr,
999 };
1000
1001 static int encx24j600_spi_probe(struct spi_device *spi)
1002 {
1003 int ret;
1004
1005 struct net_device *ndev;
1006 struct encx24j600_priv *priv;
1007 u16 eidled;
1008
1009 ndev = alloc_etherdev(sizeof(struct encx24j600_priv));
1010
1011 if (!ndev) {
1012 ret = -ENOMEM;
1013 goto error_out;
1014 }
1015
1016 priv = netdev_priv(ndev);
1017 spi_set_drvdata(spi, priv);
1018 dev_set_drvdata(&spi->dev, priv);
1019 SET_NETDEV_DEV(ndev, &spi->dev);
1020
1021 priv->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
1022 priv->ndev = ndev;
1023
1024 /* Default configuration PHY configuration */
1025 priv->full_duplex = true;
1026 priv->autoneg = AUTONEG_ENABLE;
1027 priv->speed = SPEED_100;
1028
1029 priv->ctx.spi = spi;
1030 devm_regmap_init_encx24j600(&spi->dev, &priv->ctx);
1031 ndev->irq = spi->irq;
1032 ndev->netdev_ops = &encx24j600_netdev_ops;
1033
1034 mutex_init(&priv->lock);
1035
1036 /* Reset device and check if it is connected */
1037 if (encx24j600_hw_reset(priv)) {
1038 netif_err(priv, probe, ndev,
1039 DRV_NAME ": Chip is not detected\n");
1040 ret = -EIO;
1041 goto out_free;
1042 }
1043
1044 /* Initialize the device HW to the consistent state */
1045 if (encx24j600_hw_init(priv)) {
1046 netif_err(priv, probe, ndev,
1047 DRV_NAME ": HW initialization error\n");
1048 ret = -EIO;
1049 goto out_free;
1050 }
1051
1052 kthread_init_worker(&priv->kworker);
1053 kthread_init_work(&priv->tx_work, encx24j600_tx_proc);
1054 kthread_init_work(&priv->setrx_work, encx24j600_setrx_proc);
1055
1056 priv->kworker_task = kthread_run(kthread_worker_fn, &priv->kworker,
1057 "encx24j600");
1058
1059 if (IS_ERR(priv->kworker_task)) {
1060 ret = PTR_ERR(priv->kworker_task);
1061 goto out_free;
1062 }
1063
1064 /* Get the MAC address from the chip */
1065 encx24j600_hw_get_macaddr(priv, ndev->dev_addr);
1066
1067 ndev->ethtool_ops = &encx24j600_ethtool_ops;
1068
1069 ret = register_netdev(ndev);
1070 if (unlikely(ret)) {
1071 netif_err(priv, probe, ndev, "Error %d initializing card encx24j600 card\n",
1072 ret);
1073 goto out_free;
1074 }
1075
1076 eidled = encx24j600_read_reg(priv, EIDLED);
1077 if (((eidled & DEVID_MASK) >> DEVID_SHIFT) != ENCX24J600_DEV_ID) {
1078 ret = -EINVAL;
1079 goto out_unregister;
1080 }
1081
1082 netif_info(priv, probe, ndev, "Silicon rev ID: 0x%02x\n",
1083 (eidled & REVID_MASK) >> REVID_SHIFT);
1084
1085 netif_info(priv, drv, priv->ndev, "MAC address %pM\n", ndev->dev_addr);
1086
1087 return ret;
1088
1089 out_unregister:
1090 unregister_netdev(priv->ndev);
1091 out_free:
1092 free_netdev(ndev);
1093
1094 error_out:
1095 return ret;
1096 }
1097
1098 static int encx24j600_spi_remove(struct spi_device *spi)
1099 {
1100 struct encx24j600_priv *priv = dev_get_drvdata(&spi->dev);
1101
1102 unregister_netdev(priv->ndev);
1103
1104 free_netdev(priv->ndev);
1105
1106 return 0;
1107 }
1108
1109 static const struct spi_device_id encx24j600_spi_id_table[] = {
1110 { .name = "encx24j600" },
1111 { /* sentinel */ }
1112 };
1113 MODULE_DEVICE_TABLE(spi, encx24j600_spi_id_table);
1114
1115 static struct spi_driver encx24j600_spi_net_driver = {
1116 .driver = {
1117 .name = DRV_NAME,
1118 .owner = THIS_MODULE,
1119 .bus = &spi_bus_type,
1120 },
1121 .probe = encx24j600_spi_probe,
1122 .remove = encx24j600_spi_remove,
1123 .id_table = encx24j600_spi_id_table,
1124 };
1125
1126 static int __init encx24j600_init(void)
1127 {
1128 return spi_register_driver(&encx24j600_spi_net_driver);
1129 }
1130 module_init(encx24j600_init);
1131
1132 static void encx24j600_exit(void)
1133 {
1134 spi_unregister_driver(&encx24j600_spi_net_driver);
1135 }
1136 module_exit(encx24j600_exit);
1137
1138 MODULE_DESCRIPTION(DRV_NAME " ethernet driver");
1139 MODULE_AUTHOR("Jon Ringle <jringle@gridpoint.com>");
1140 MODULE_LICENSE("GPL");
1141 MODULE_ALIAS("spi:" DRV_NAME);
Linux with added FPC-III support